JP7356340B2 - gate drive circuit - Google Patents

Description

The present invention relates to a gate drive circuit for driving a power semiconductor switch such as an IGBT (Insulated Gate Bipolar Transistor) module. In particular, it relates to protection of collector-emitter withstand voltage of IGBT.

<Background>
The present invention relates to a technology for driving a high-power semiconductor switch typified by an IGBT. Semiconductor switches such as IGBTs switch large currents of several 100s to several 1000s of amperes and high voltages of several 100s to 1000V or more, so if a semiconductor switch such as an IGBT is destroyed, the impact will be large and will even affect the surroundings of the semiconductor switch. Extends. That is, not only the IGBT itself but also the control circuit around it may be destroyed, leading to a risk of failure of the entire system circuit.
Therefore, various protection measures have been adopted to protect semiconductor switches such as IGBTs from destruction. Semiconductors have maximum ratings for current, voltage, power, and temperature, and if these maximum ratings are exceeded even momentarily, the semiconductor switch may be damaged.
The present invention relates to a technique for using a semiconductor switch such as an IGBT with a collector-emitter voltage within the maximum rating value.

<Conventional protection measures>
When a semiconductor switch such as an IGBT is repeatedly turned on and off, when the IGBT is in a saturated state, the current flowing to its collector terminal accumulates electromagnetic energy in the inductance component of the wiring and load connected to the IGBT's collector terminal. . Thereafter, when the IGBT is turned off, the accumulated electromagnetic energy is generated as a surge voltage between the collector and emitter of the IGBT. This surge voltage E _S is expressed by the following equation (1A), where L is the inductance component of the wiring and load, and I(t) is the current flowing through the collector terminal.

サージ電圧Ｅ_Ｓは、インダクタンス成分の値が大きいほど、また、電流の変化率が大きいほど高い電圧となる。このサージ電圧Ｅ_Ｓの電圧が、ＩＧＢＴの最大定格を超えると、ＩＧＢＴを破壊する。そこで、サージ電圧Ｅ_Ｓを最大定格未満に抑え込むために、サージ電圧Ｅ_Ｓが最大定格を超える前に、サージ電圧Ｅ_Ｓを低減する措置を講じる必要がある。

The surge voltage _ES increases as the value of the inductance component increases and as the rate of change of the current increases. If this surge voltage _ES exceeds the maximum rating of the IGBT, the IGBT will be destroyed. Therefore, in order to suppress the surge voltage E _S to less than the maximum rating, it is necessary to take measures to reduce the surge voltage E _S before the surge voltage E _S exceeds the maximum rating.

Conventionally, a snubber circuit as shown in FIG. 6 has been used as a method for reducing this surge voltage _ES . A control signal output by a drive circuit (not shown) is supplied to the gate terminal of the IGBT 10, and the ON/OFF state of the IGBT 10 is controlled. A load 12 is connected between the collector terminal of the IGBT 10 and a high voltage power system, and power supplied to the load 12 is controlled by the ON/OFF state of the IGBT 10. The _snubber circuit 14 is configured by connecting a parallel circuit of a capacitor CS and a resistor R _S , and a diode D _S in series (see FIG. 6). This snubber circuit 14 is connected between the high voltage power system and the collector terminal of the IGBT 10.
The snubber circuit 14 shown in FIG _. 6 stores a part of the surge voltage E _S in a capacitor C S via a diode D _S , converts it into heat using a resistor R _S , and consumes it to reduce the surge voltage E _S. It is a typical circuit.

More recently, a method called an active clamp method is sometimes adopted. A diagram of the principle of this method is shown in FIG. Also in FIG. 7, similarly to FIG. 6, a load 12 is provided between the collector terminal of the IGBT 10 and the high voltage power system. An active clamp circuit 16 is connected between the collector terminal and gate terminal of the IGBT 10. The active clamp circuit 16 is a series circuit including a diode D1, a constant voltage diode _DZ , and a limiting resistor _RZ . Note that the constant voltage diode _DZ may have a configuration in which a plurality of constant voltage diodes are connected in series (see FIG. 7).
In this method, when the voltage between the collector and emitter of the IGBT10 exceeds the Zener voltage of the constant voltage diode _DZ , the constant voltage diode _DZ becomes conductive, and the conduction current flows into the gate terminal of the IGBT10 through the limiting resistor _RZ . This is the way to do it. This provides the effect of easing the turn-off operation of the IGBT 10.
When the turn-off operation is relaxed, the rate of decrease of the collector current decreases, and the surge voltage _ES tends to decrease according to the above equation (1). Furthermore, when the constant voltage diode _DZ becomes conductive, the collector-emitter voltage is clamped and does not exceed the Zener voltage of the constant voltage diode _DZ . By combining these effects, the collector-emitter voltage of the IGBT 10 can be used within the maximum rating.

Prior Patent Technology For example, a conventional active clamp circuit is disclosed in Patent Document 1 (Japanese Patent No. 4230190), which will be described later. In particular, when a plurality of constant voltage elements are connected in series to form a protection circuit, a technique has been disclosed for detecting that a short-circuit failure has occurred in any of the constant voltage elements.

Patent No. 4230190

However, the conventional method described above has the following problems.
In the method using the _snubber circuit shown in Fig. 6, the energy of the generated surge voltage E _S does not decrease as it is, but is consumed within the snubber circuit (that is, in the resistor R _S ), so heat generation may be a problem. Furthermore, a steep current flows through the diode _DS of the snubber circuit as the IGBT turns ON/OFF. Therefore, the diode _DS may also become a source of noise.

Furthermore, in the active clamp method shown in FIG. 7, heat generation in the constant voltage diode _DZ may pose a problem due to the same cause as in the snubber circuit.

Further, if an excessive current flows through the constant voltage diode _DZ due to an internal resistance component, there is a possibility that the voltage regulator diode DZ will deviate from the clamp level. As a countermeasure against this, it is possible to set the Zener voltage low, but there is a problem in that setting the Zener voltage low lowers the voltage that can be applied to the IGBT. Therefore, there are design problems such as the need to increase the withstand voltage of the IGBT in order to satisfy the required circuit specifications.

The present invention was made in view of the problems of heat generation and noise generation, and its purpose is to provide a gate drive circuit equipped with an active clamp circuit that can protect between the collector and emitter of an IGBT. Therefore, it is an object of the present invention to provide a gate drive circuit for an IGBT in which heat generation of a constant voltage diode is further suppressed and generation of noise is also reduced.

(1) In order to solve the above problems, the present invention provides a gate drive circuit for driving a power semiconductor element, wherein when the power semiconductor element is turned off, the collector-emitter voltage of the power semiconductor element is maintained at a predetermined level. an active clamp circuit that clamps the collector-emitter voltage of the power semiconductor element at the predetermined voltage when the voltage reaches the predetermined voltage, and supplies a predetermined current to the gate terminal of the power semiconductor element; The circuit includes a voltage regulator diode having one end connected to a collector terminal of the power semiconductor element, an impedance circuit connected between the other end of the voltage regulator diode and a negative power supply, and a voltage regulator diode and the voltage regulator diode. An output terminal connected to the connection point with the impedance circuit and connected to the gate terminal of the power semiconductor element, one end connected to the connection point between the voltage regulator diode and the impedance circuit, and the other end connected to the negative power supply. a first switch and a first resistor connected in series for extracting charge from the gate terminal of the power semiconductor element based on an external open/close signal when the power semiconductor element is turned off; A pullout circuit, one end of which is connected to a connection point between the constant voltage diode and the impedance circuit, and the other end of which is connected to a negative power supply, and when the power semiconductor element is turned off, the power semiconductor element is A second extraction circuit consisting of a series circuit of a second switch and a second resistor for extracting charge from the gate terminal of the element, and a voltage at a connection point between the constant voltage diode and the impedance circuit, the power semiconductor element a detection circuit that calculates a rate of change in the collector voltage of and outputs a switch open signal when the rate of change exceeds a predetermined threshold, and when the second switch receives the switch open signal, A gate drive circuit characterized in that by changing from a conductive state to a non-conductive state, a resistance value for extracting the gate charge of the power semiconductor element is increased, thereby extracting the gate charge while alleviating turn-off of the power semiconductor element. It is.

(2) The present invention also provides the gate drive circuit according to (1), in which the active clamp circuit is arranged so that a surge voltage generated when turning off the power semiconductor switching element is applied to the power semiconductor switching element IGBT. When the collector-emitter voltage reaches or is close to the maximum rated voltage, the collector-emitter voltage is clamped at that voltage, and at the same time, a current is supplied to the self-gating gate to reduce the surge voltage. This gate drive circuit is characterized by being an active clamp circuit that prevents destruction.

(3) The present invention also provides the gate drive circuit according to (1) or (2), in which the constant voltage diode has a parallel capacitance parasitic to the constant voltage diode, and the impedance circuit includes at least This is a gate drive circuit characterized by including a parallel circuit of a resistor and a capacitor.

(4) The present invention also provides a gate drive circuit according to any one of (1) to (3), in which there are n-1 types of n-th gate drive circuits from a second extraction circuit to an n-th extraction circuit. an extraction circuit, and n-1 types of n-th detection circuits from a second detection circuit to an n-th detection circuit, where n is a natural number of 3 or more, and the n-th extraction circuit is configured to an nth switch and an nth resistor connected to a connection point between the diode and the impedance circuit, and for extracting charge from the gate terminal of the power semiconductor element based on the opening/closing signal when the power semiconductor element is turned off; The n-th detection circuit is composed of a series circuit, and the n-th detection circuit determines a rate of change in the collector voltage of the power semiconductor element based on the voltage at the connection point between the constant voltage diode and the impedance circuit, and the n-th detection circuit calculates a rate of change in the collector voltage of the power semiconductor element, and determines whether the rate of change is a predetermined n-th detection circuit. When the threshold value of is exceeded, an n-th switch open signal is output,
When the n-th switch receives the n-th switch open signal, the n-th switch changes from a conductive state to a non-conductive state, thereby increasing the resistance value for extracting the gate charge of the power semiconductor element, and increasing the resistance value for extracting the gate charge of the power semiconductor element. This is a gate drive circuit characterized by extracting gate charge while alleviating turn-off.

According to the present invention, it is possible to provide a gate drive circuit for driving an IGBT that generates less heat and generates less noise.

FIG. 3 is a circuit diagram of a gate drive circuit in the first embodiment. This is an equivalent circuit that approximates a circuit portion consisting of a constant voltage diode ZD1, a resistor R4, and an impedance circuit Z1. FIG. 3 is a circuit diagram of a gate drive circuit in Embodiment 2. FIG. FIG. 3 is a circuit diagram of a gate drive circuit in a specific example. 2 is a graph showing experimental data obtained through experiments on specific examples. 1 is an example of a circuit diagram of a conventional snubber circuit. 1 is an example of a conventional active clamp circuit diagram.

Hereinafter, preferred embodiments of the present invention will be described based on the drawings.
1. Embodiment 1
FIG. 1 shows a circuit diagram showing a characteristic configuration of a gate drive circuit 100 according to this embodiment. The gate drive circuit 100 according to this embodiment is characterized by including a predictive active clamp circuit 102. The gate drive circuit 100 may also include a driver semiconductor element for driving the gate, a power supply circuit, and the like, but these components are not shown in FIG. 1 because they are the same as conventional ones.
The load ZL104 is a load driven by the IGBT 106, and is provided between the power line and the collector terminal of the IGBT 106. The IGBT 106 is an IGBT 106 to be driven by the gate drive circuit 100, and a control signal from the gate drive circuit 100 is supplied to its gate terminal. Note that the load ZL104 and the IGBT 106 (to be driven) are not included in the configuration of the gate drive circuit 100.
Here, the IGBT corresponds to a preferred example of the power semiconductor device in the claims.

As shown in FIG. 1, the characteristic configuration of this embodiment is a predictive active clamp circuit 102. This predictive active clamp circuit is characterized by adding a circuit to the conventional active clamp circuit to open the SW of the gate pullout circuit according to the rate of increase between the collector and the emitter. A control signal is supplied from the output terminal 102a of the active clamp circuit 102 to the gate terminal of the IGBT 106. Further, the detection terminal 102b of the active clamp circuit 102 and the collector terminal of the IGBT 106 are connected.

The detection terminal 102b is connected to an anode terminal of a diode D1 that prevents current from flowing backward, and a cathode terminal of the diode D1 is connected to a cathode terminal of a constant voltage diode ZD1. The anode terminal of the constant voltage diode ZD1 is connected to an impedance circuit Z1 via a resistor R4 (see FIG. 1). Further, the other end of the impedance circuit Z1 is connected to a negative power supply Vee.
Note that the constant voltage diode ZD1 can be represented by an equivalent circuit as shown in FIG. 1 using an ideal constant voltage diode _VZ exhibiting constant voltage characteristics and a parallel capacitance _CZ existing between both terminals thereof.
Here, the predictive active clamp circuit 102 corresponds to a preferred example of the active clamp circuit in the claims. Further, the constant voltage diode ZD1 corresponds to a preferred example of the constant voltage diode in the claims. The parallel capacitance _CZ of the constant voltage diode ZD1 corresponds to a preferred example of the parallel capacitance in the claims. In this embodiment, a parasitic parallel capacitance _CZ is used in consideration of component cost and mounting area, but a separate capacitor may be connected in parallel with the constant voltage diode _VZ . The same applies to the parallel capacitance _CZ in FIG. 4, which will be described later. The capacitor in this case also corresponds to a preferred example of the parallel capacitance in the claims.
Further, the impedance circuit Z1 corresponds to a preferred example of the impedance circuit in the claims. The output terminal 102a (and 202a and 302a described later) corresponds to a preferred example of an output terminal in the claims.

The switch SW1 and the switch SW2 are switches for extracting the gate charge of the IGBT 106.
A series circuit of switch SW1 and resistor R1 is connected between the gate terminal of IGBT 106 and negative power supply Vee. When the switch SW1 is closed (ON), the resistor R1 is connected to the negative power supply Vee to discharge the gate charge of the IGBT 106.
This series circuit of the switch SW1 and the resistor R1 corresponds to a preferred example of the first extraction circuit in the claims. The switch SW1 corresponds to a preferred example of the first switch in the claims. The resistor R1 corresponds to a preferred example of the first resistor in the claims.
Similarly, a series circuit of switch SW2 and resistor R2 is connected between the gate terminal of IGBT 106 and negative power supply Vee. When the switch SW2 is closed (ON), the resistor R2 is connected to the negative power supply Vee, and the gate charge of the IGBT 106 is discharged.
This series circuit of switch SW2 and resistor R2 corresponds to a preferred example of the second extraction circuit in the claims. The switch SW2 corresponds to a preferred example of the second switch in the claims. The resistor R2 corresponds to a preferred example of the second resistor in the claims.

In principle, the switches SW1 and SW2 are opened and closed using open/close signals that are signals from a predetermined control circuit (not shown). When turning off the IGBT 106, a close (ON) opening/closing signal is sent from the control circuit to the switch SW1 and the switch SW2, and both switches are closed (ON). In this text, the open/close signal indicates "open" when it is low and "closed" when it is high, but it may be reversed depending on the polarity of the switch element used (P channel, N channel). Good too.
Moreover, in FIG. 1, impedance circuit Z2 is a termination impedance circuit of the gate of IGBT106.
The anode terminal of the diode D2 is connected to the connection point between the resistor R4 and the impedance circuit Z1. The cathode terminal of the diode D2 is connected to the output terminal 102. That is, the terminal of the resistor R1 on the opposite side of the switch SW1 is connected to the anode terminal of the diode D2. Similarly, the terminal of the resistor R2 on the opposite side of the switch SW2 is also connected to the anode terminal of the diode D2 (see FIG. 1). This diode D2 is also a diode that prevents reverse flow of current, similar to the diode D1.

The detection circuit DET2 is a detection circuit that monitors the voltage (voltage between terminals) generated in the impedance circuit Z1. The detection circuit DET2 opens the switch SW2 so that when the voltage between the terminals of the impedance circuit Z1 is higher than a preset threshold value (positive predetermined value), the switch SW2 is opened (OFF) regardless of the opening/closing signal from the control circuit. An open signal is supplied to switch SW2. When the switch SW2 receives the SW2 open signal instructing to open the switch SW2, the switch SW2 opens the switch (OFF: non-conducting state) regardless of the value of the open/close signal from the control circuit.
The resistor R4 connected between the anode terminal of the constant voltage diode ZD1 and the impedance circuit Z1 is a limiting resistor, and when the collector voltage of the IGBT 106 increases and the constant voltage diode ZD1 becomes conductive, the gate terminal of the IGBT 106 This limits the current flowing into the circuit.
Here, the detection circuit DET2 corresponds to a preferred example of the detection circuit in the claims. The SW2 open signal corresponds to a preferred example of the switch open signal in the claims.

In order to turn off the IGBT 106, an open/close signal is sent from the control circuit to the switch SW1 and the switch SW2, and when both switches are closed (ON), the gate charge of the IGBT 106 becomes the combined resistance value of the resistor R1 and the resistor R2 (R1R2/ (R1+R2)). In this formula for the combined resistance value, R1 and R2 represent the resistance value of the resistor R1 and the resistance value of the resistor R2, respectively.
In this way, when the gate charge of the IGBT 106 is extracted, the IGBT 106 attempts to turn off. As a result, the collector current of the IGBT 106 rapidly decreases, and the collector voltage of the IGBT 106 starts to rise according to equation (3) described below. If the load ZL of the IGBT 106 is a constant value, the rate of increase in the collector voltage of the IGBT 106 is considered to be approximately proportional to the rate of decrease in the collector current.

Impedance circuit Z1 provides impedance for measuring the rate of increase in the collector voltage of IGBT 106. Assume that this impedance circuit Z1 is, for example, a parallel circuit of a resistor R _d and a capacitor C _d . Furthermore, the mechanism for measuring the rate of increase can be simplified and equivalent as shown in FIG. FIG. 2 shows an equivalent circuit that approximates a circuit portion consisting of a constant voltage diode ZD1, a resistor R4, and an impedance circuit Z1 in the predictive active clamp circuit 102 of FIG.
As shown in FIG. 2, the constant voltage diode ZD1 can be approximated by a capacitor _CZ in a non-conducting state, as shown in FIG. Furthermore, if the resistor R4 has a sufficiently small value, it can be omitted. Further, as described above, the impedance circuit Z1 can be approximated by a parallel circuit of a resistor R _d and a capacitor C _d .

と、インピーダンス回路Ｚ１の端子間電圧Ｖ_１との関係は、次の式（２）で表される。

ここで、ｔは時間を表す。さて、ｔ≪Ｒ_ｄ（Ｃ_Ｚ＋Ｃ_ｄ）の場合は、Ｖ_１はほぼ「０」と等しくなり、検出回路ＤＥＴ２は動作しない。検出回路ＤＥＴ２の閾値は正の電圧値であるので、ほぼ０Ｖの電圧は閾値を超えないからである。すなわち、Ｒ_ｄ（Ｃ_Ｚ＋Ｃ_ｄ）の値を調整することにより、パルス幅の短いノイズを除去できることを意味する。つまり、ｔ≫Ｒ_ｄ（Ｃ_Ｚ＋Ｃ_ｄ）の時間帯においては、端子間電圧Ｖ_１は、下記の式（３Ａ）で表され、インピーダンス回路Ｚ１の端子間電圧Ｖ_１は、コレクタ電圧Ｖ_ＣＥ（ｔ）の上昇率に比例する値となる。

インピーダンス回路Ｚ１の端子間電圧Ｖ_１の値が高いことは、ＩＧＢＴ１０６のコレクタ電流の減少率が大きいことを意味する。すなわち、ＩＧＢＴ１０６のゲート電荷の引き抜き量が大きすぎることを意味する。 As a result of such approximation, the terminal-to-terminal voltage of the impedance circuit Z1 of the circuit shown in FIG. 2 can be expressed by V ₁ in FIG. 2, that is, the connection point between the impedance circuit Z1 and the constant voltage diode ZD1. The detection circuit DET2 can detect the inter-terminal voltage from this _V1 and the negative power supply Vee. As a result of this approximation, the rate of increase in the collector voltage V _CE (t) of the IGBT 106 is

The relationship between the voltage _V1 between the terminals of the impedance circuit Z1 and the voltage V1 between the terminals of the impedance circuit Z1 is expressed by the following equation (2).

Here, t represents time. Now, in the case of t<<R _d (C _Z +C _d ), V ₁ becomes approximately equal to "0" and the detection circuit DET2 does not operate. This is because the threshold of the detection circuit DET2 is a positive voltage value, so a voltage of approximately 0V does not exceed the threshold. That is, it means that noise with a short pulse width can be removed by adjusting the value of R _d (C _Z +C _d ). In other words, in the time period t≫R _d (C _Z +C _d ), the inter-terminal voltage V ₁ is expressed by the following formula (3A), and the inter-terminal voltage V ₁ of the impedance circuit Z1 is the collector voltage V _CE The value is proportional to the rate of increase in (t).

A high value of the inter-terminal voltage _V1 of the impedance circuit Z1 means that the rate of decrease in the collector current of the IGBT 106 is large. That is, it means that the amount of gate charge extracted from the IGBT 106 is too large.

Find in advance the value of the terminal voltage V ₁ that can be predicted to result in an excessively large rate of decrease in the collector current, resulting in a high rate of voltage increase in the collector voltage V _CE (t), which will eventually exceed the maximum rating of the IGBT 106. You can leave it there. A feature of the first embodiment is that this predicted value is set in advance as the threshold value of the detection circuit DET2 as the limit value of the inter-terminal voltage _V1 .
If the threshold value is set in the detection circuit DET2 in this way, when the threshold value is reached, the detection circuit DET2 operates (detects that the terminal voltage _V1 exceeds the threshold value), and the SW open signal is activated. Output. The switch SW2 receives the SW open signal, becomes open (OFF), and the value of the gate charge extraction resistance of the IGBT 106 can be changed from (R1R2/(R1+R2)) to R1. In other words, the value of the pull-out resistance can be increased.

This operation increases the combined resistance value of the resistance values for gate charge extraction, reduces the amount of gate charge extraction from the IGBT 106, and reduces the surge voltage according to the above equation (3A).
In the example shown in FIG. 1, the resistor R1 and the resistor R1 are equivalently connected in parallel, but they may be configured to be connected in series. In this case, one end of a resistor series circuit of resistors R1 and R2 connected in series is connected to the output terminal 102a, a switch SW1 is connected between the other end and Vee, and the connection point of the resistors R1 and R2 is connected to the output terminal 102a. A switch SW2 may be connected between the switch SW2 and the switch SW2 so that the combined resistance value can be adjusted by switching the switch.
By appropriately selecting the limit value of the voltage V ₁ between the terminals of the impedance circuit Z1 in this way, the IGBT 106 can be protected without the constant voltage diode ZD1 becoming conductive due to a surge voltage. Even if the constant voltage diode ZD1 becomes conductive, the conduction current value and time width of the constant voltage diode ZD1 can be reduced, so that heat generation of the constant voltage diode ZD1 can be suppressed. Furthermore, since a steep rise in the collector voltage V _CE (t) of the IGBT 106 and a steep decrease in the collector current of the IGBT 106 can be alleviated in advance, it is also effective in reducing the noise accompanying them.

2. Embodiment 2
In the second embodiment, an example in which two detection circuits DET are provided will be described.
In the first embodiment, an example has been described in which the detection circuit DET2 is provided and the resistance value for extracting the gate charge is changed. It is considered that this detection circuit DET can be controlled more precisely by providing a plurality of detection circuits DET with different threshold values.
Therefore, in the second embodiment, a circuit example will be described in which a detection circuit DET3 is provided in addition to the detection circuit DET2 of FIG. 1 described in the first embodiment. FIG. 3 shows a circuit including the detection circuit DET2 and the detection circuit DET3 in this manner.
Specifically, the circuit example shown in FIG. 3 has a configuration in which a detection circuit DET3, a switch SW3, and a resistor R3 are added to the circuit shown in FIG. 1 described in the first embodiment, and other components are added. The configuration is exactly the same as in FIG.

The switch SW3, like the switches SW1 and SW2, is a switch for drawing out the gate charge of the IGBT 106. Similarly to the switch SW1, etc., the switch SW3 is a switch that performs opening/closing operations based on an opening/closing signal from a control circuit (not shown). be.
A series circuit of switch SW3 and resistor R3 is connected between the gate terminal of IGBT 106 and negative power supply Vee. When the switch SW3 is closed (ON), the resistor R3 is connected to the negative power supply Vee and discharges the gate charge of the IGBT 106. This operation itself is similar to the switches SW1 and SW2 described above.
The resistor R3 is a resistor for discharging gate charges, and has the same meaning as the resistors R1 and R2.
The series circuit of switch SW3 and resistor R3 corresponds to a preferred example of the n-th extraction circuit in the claims (in the case of n=3). The switch SW3 corresponds to a preferred example of the n-th switch (in the case of n=3) in the claims. The resistor R3 corresponds to a preferable example of the n-th resistor (in the case of n=3) in the claims.

The detection circuit DET3 is a circuit similar to the detection circuit DET2, and differs only in the threshold value as described later.
This detection circuit DET3 also detects the inter-terminal voltage V1 of the impedance circuit Z1, and outputs a SW open signal if it exceeds a preset threshold. When the switch SW3 receives the SW3 open signal, which is an instruction to open the switch SW3, the switch SW3 becomes open and disconnects the resistor R3 from the negative power supply Vee. In this way, the detection circuit DET3 is the same circuit as the detection circuit DET2 except that the threshold value is different.
This detection circuit DET3 corresponds to a preferred example of the n-th detection circuit in the claims (in the case of n=3). The SW3 open signal corresponds to a preferred example of the n-th switch open signal in the claims.

Similar to the first embodiment, in order to turn off the IGBT 106, the control circuit sends an open/close signal to the switch SW3 in addition to the switches SW1 and SW2, thereby closing all the switches. The switch SW3 also transitions to the ON state (closed).
In this state, the gate charge of the IGBT 106 is extracted through the combined resistance value (1/((1/R1)+(1/R2)+(1/R3))) of the resistor R1, the resistor R2, and the resistor R3. In this formula for the combined resistance value, R1, R2, and R3 represent the resistance value of the resistor R1, the resistance value of the resistor R2, and the resistance value of the resistor R3, respectively.

In this way, when the gate charge of the IGBT 106 is extracted, the IGBT 106 starts to turn off, and the collector current of the IGBT 106 rapidly decreases. As a result, as described above, the collector voltage of the IGBT 106 starts to rise according to the above equation (3A). If the load ZL104 of the IGBT 106 is a constant value, the rate of increase in the collector voltage of the IGBT 106 is considered to be approximately proportional to the rate of decrease in the collector current.

Moreover, as already explained, the voltage V ₁ between the terminals of the impedance circuit Z1 has a value proportional to the rate of increase of the collector voltage V _CE (t). Therefore, the value of the inter-terminal voltage V ₁ that can be predicted to exceed the maximum rated value of the IGBT 106 is determined in advance if the rate of decrease in the collector current is too large, resulting in a high rate of voltage increase in the collector voltage V _CE (t). You can ask for it.
At this time, in order to prevent the maximum rated value from being exceeded, it is preferable to set a threshold value smaller than the predicted value of the inter-terminal voltage _V1 in the detection circuit DET2.
On the other hand, if the voltage increase rate of the collector voltage V _CE (t) is high, it may be necessary to further increase the value of the gate charge extraction resistor.

Therefore, if a voltage larger than the predicted inter-terminal voltage _V1 is set as the threshold of the detection circuit DET3, it is sufficient to increase the value of the gate charge extraction resistor by simply disconnecting the resistor R2 using the detection circuit DET2. Even if this is not possible, the resistance value can be further increased.
In the second embodiment, as described above, a slightly smaller threshold value is set for the detection circuit DET2, the resistor R2 is disconnected early, and the value of the resistor for drawing out the gate charge is increased early.
Furthermore, a slightly larger threshold value is set for the detection circuit DET3, and when the voltage increase rate of the collector voltage V _CE (t) is extremely high, the resistor R3 is also disconnected in addition to the resistor R2. As a result, only R1 is used as the resistor for extracting gate charges, and the value of the resistor for extracting gate charges can be further increased.
In the example shown in FIG. 3, the resistors R1, R2, and R3 are equivalently connected in parallel, but they may be connected in series. In this case, one end of a resistor series circuit of resistors R1, R2, and R3 connected in series is connected to the output terminal 202a, a switch SW1 is connected between the other end and Vee, and the connection point of the resistors R1 and R2 is connected to the output terminal 202a. It is also possible to configure a configuration in which a switch SW2 is connected between and Vee, and a switch SW3 is connected between the connection point of resistors R2 and R3 and Vee, so that the combined resistance value can be adjusted by switching the switches. good.

Since the predictive active clamp circuit 202 of the gate drive circuit 200 in FIG. 3 described in the second embodiment includes two types of detection circuits in this way, it is more precise than the circuit in FIG. 1 of the first embodiment. control can be executed.

3. Illustrative Embodiment FIG. 4 shows a circuit diagram of a gate drive circuit 300 including an illustrative predictive active clamp circuit 302. Referring to FIG. The actual gate drive circuit 300 includes various circuits such as a power supply circuit and a driver element in addition to the predictive active clamp circuit 302 of FIG. 4.
Similar to FIGS. 1 and 3, the active clamp circuit 302 is a part surrounded by a solid line, and its output terminal 302a is connected to the gate terminal of the IGBT 106 to be driven. Further, the load 104 is connected between the IGBT 106 and the power line, and the power supply is controlled by the IGBT 106, as in FIGS. 1 and 3. The active clamp circuit 302 is provided with a detection terminal 302b, and this detection terminal 302b is connected to the collector terminal of the IGBT 106.

In FIG. 4, Vee is the negative power supply of the gate drive circuit 300, and Vdc is the positive power supply, as described above.
The active clamp circuit 300 is provided with three types of input terminals IN1, IN2, and IN3.
A switching signal is input to the input terminal IN1 (and IN2, IN3) from an external control circuit. When the open/close signal input to the input terminal IN1 (and IN2, IN3) is low, the transistor Q4 is turned on and the IGBT 106 is turned on. When the open/close signals input to the input terminals IN2 and IN3 (and IN1) are high, the transistors Q2 and Q3 are turned on and the IGBT 106 is turned off.

In this embodiment, the switching signals applied to IN1, IN2, and IN3 are in-phase signals, but depending on the polarity of the switch element used, the polarity of the switching signal applied to IN2, IN3 can be changed to IN1. The opening/closing signal may be reversed.

When the open/close signal input to the input terminal IN1 (and IN2, IN3) becomes low, the transistor Q4 turns on and supplies current from Vdc to the gate terminal of the IGBT 106 connected to the output terminal 302a via the resistor R7. . As a result, the IGBT 106 is turned ON.
The transistor Q4 is a high-side switch of the gate drive circuit 300, but is omitted and not shown in FIGS. 1 and 3 described above.

On the other hand, when the control signals input to input terminals IN2 and IN3 (and IN1) become high, transistor Q4 turns OFF and transistors Q2 and Q3 turn ON, draining the gate charge of IGBT 106 through resistor R5 and resistor R6. Pull it out. As a result, the IGBT 106 is turned off.

Note that the transistor Q2 corresponds to the switch SW2 in FIG. 1 (FIG. 3), and the transistor Q3 corresponds to the switch SW1 in FIG. 1 (FIG. 3). Further, the resistor R4 in FIG. 4 corresponds to the current detection impedance circuit Z1 in FIG. 1. Further, ZD1 to ZD6 in FIG. 4 are diodes corresponding to the constant voltage diode ZD1 in FIG. Further, _CZ in FIG. 4 corresponds to the parallel capacitance _CZ in FIG.

Further, the transistor Q1 in FIG. 4 corresponds to the detection circuit DET2 in FIG. 1, and its threshold voltage corresponds to the threshold voltage _VQ1TH between the gate and source of the transistor Q1. When the transistor Q1 turns on, the transistor Q2 turns off regardless of the signal state of the control signal input to the input terminal IN3.
That is, when the voltage between the terminals of the resistor R4 reaches the threshold voltage _VQ1TH , the transistor Q1 is turned on. When transistor Q1 turns on, transistor Q2 turns off. In other words, the switch corresponding to switch SW2 is turned OFF (non-conducting). Therefore, the only circuit that extracts the gate charge of the IGBT 106 is the series circuit of the resistor R6 and the transistor Q3, so that the charge is extracted more gently and the surge voltage generated at the collector terminal of the IGBT 106 can be reduced.

The resistor R3 is a resistor for adjusting the relative ratio of the effects of the novel effect of this embodiment and the effect of the conventional active clamp circuit system. The conventional active clamp circuit system is a system in which the current of the constant voltage diode ZD1 directly flows into the gate terminal of the IGBT 106.

Here, the novel effects of this embodiment are as follows:
- The combined resistance value of the resistance values for gate charge extraction increases, the amount of gate charge extraction from the IGBT 106 decreases, and the surge voltage is reduced according to equation (3A).
- Heat generation of the constant voltage diode ZD1 can be suppressed.
- Since the steep decrease in collector current can be alleviated, the accompanying noise can be reduced.
etc.
In addition, the effects of the conventional active clamp circuit method are as follows.
・Reduction of surge voltage. If the value of the resistor R3 is increased, the detection sensitivity of the collector voltage V _CE (t) decreases, so the effect of the conventional active clamp circuit system becomes relatively greater. Conversely, if the value of the resistor R3 is reduced, the detection sensitivity of the collector voltage V _CE (t) increases, so that the characteristic effect (new effect) of this embodiment can be obtained relatively larger than the conventional effect. .

したがって、図４の本実施例のパラメータで表現すると、下記式（４）のように表される。

ここで、Ｒ_ｔは、以下の式（５）で表される。
Ｒ_ｔ ＝ Ｒ１ ＋ Ｒ３ ＋ Ｒ４ （５） The diode D3 is a diode for extracting the gate charge of the transistor Q1.
The rate of increase in the collector voltage V _CE (t) of the IGBT 106 is expressed by the following equation (3B).

Therefore, when expressed using the parameters of this embodiment shown in FIG. 4, it is expressed as shown in the following equation (4).

Here, R _t is represented by the following formula (5).
_Rt = R1 + R3 + R4 (5)

Next, FIG. 5 shows the circuit operation waveforms of FIG. 4. In the graph of FIG. 5, the horizontal axis represents time, and the vertical axis represents various signals.
As explained above, the opening/closing signal is a signal output from an external control circuit, and is a signal for opening/closing the switch SW1 and the switch SW2. The opening/closing signals are supplied to input terminals IN2, IN3, and IN1 in FIG.
SW1 is a signal indicating the open/closed state of the switch SW1; low indicates an open state (non-conducting), and high indicates a conducting state. Similarly, SW2 is a signal indicating the open/closed state of the switch SW1, and a low signal indicates an open state (non-conducting state), and a high signal indicates a conductive state.
Vge represents the gate voltage of the IGBT 106. Further, V _CE represents the collector voltage V _CE (t) of the IGBT 106. Moreover, Ic represents the collector current of the IGBT 106.

This graph shows the operation when the opening/closing signal changes from low to high. At this time, the IGBT 106 transitions from the ON state to the OFF state, and the switch SW1 and the switch SW2 basically transition from the open state (non-conducting state) to the closed state (conducting state).

First, when the opening/closing signal changes from low to high, transistor Q4 turns off and enters a non-conducting state. At the same time, the switches SW1 and SW2 are turned ON and start drawing out the gate charge. As a result, the IGBT 106 starts transitioning from the ON state to the OFF state.
As the switches SW1 and SW2 draw out the gate charge, the IGBT begins to transition to a non-conductive state. As a result, the collector voltage _VCE starts to rise. In the graph of FIG. 5, the slope of this rise is expressed as "slope 1."
In this embodiment, by observing the slope 1, the transistor Q1 (corresponding to the detection circuit DET2 in FIG. 1) is turned on at a timing when it is predicted that noise or heat generation will occur.
As explained above, if the slope 1 is large, the timing at which the transistor Q1 is turned on becomes early, and when the slope 1 is small, the timing at which the transistor Q1 is turned on is delayed.

When the transistor Q1 (detection circuit DET2) turns on, the switch SW2 becomes "open" (non-conductive) (see FIG. 5), and the gate voltage Vge rises accordingly. Then, as a result of the switch SW2 being in the "open" state, the gate charge is drawn out at a low speed, and the rate at which the collector voltage _VCE rises is slowed down. As a result, the slope of the increase in collector voltage V _CE becomes "slope 2" (see FIG. 5).
Thereafter, when the gate charge is extracted, the IGBT 106 becomes OFF and becomes non-conductive. At this time, since the collector voltage V _CE is clamped by the constant voltage diode ZD1, which is a clamp circuit, surge voltage and the like can be suppressed. In FIG. 5, the period indicated as the ZZD1 conduction period is a period in which the constant voltage diode ZD1 is conductive and surge voltage and the like are suppressed. During this period, the constant voltage diode ZD1 is conductive, so that the control signal at the output terminal 102a increases due to the conduction of the constant voltage diode ZD1. This suppresses surge voltage and the like.

Thereafter, when the collector voltage V _CE of the IGBT 106 becomes lower than the Zener voltage of the constant voltage diode ZD1, the constant voltage diode ZD1 transitions to a non-conductive state.
When the constant voltage diode ZD1 becomes non-conductive, the detection circuit DET2 no longer detects a voltage exceeding the threshold value, and the switch SW2 also returns to the closed state (conductive state).
Execute the operations described above. As a result, according to the circuit of FIG. 4, it is possible to alleviate a steep rise in the collector voltage V _CE (t) of the IGBT 106 and a steep decrease in the collector current of the IGBT 106. Further, since the conduction time of the constant voltage diode ZD1 is shortened, heat generation of the constant voltage diode ZD1 can be suppressed. Further, it is possible to reduce the noise associated with them.

4. Effects and Others As explained above, the gate drive circuit in this embodiment predicts the occurrence of a surge voltage by observing a steep change in the collector voltage while using an active clamp circuit, and extracts the gate charge. Since the resistance value is changed (the resistance value is increased), surge voltage can be suppressed, and heat generation of the constant voltage diode in the active clamp circuit can be suppressed. Moreover, a steep rise in the collector voltage and a steep decrease in the collector current of the IGBT can be alleviated. As a result, noise can be reduced.

In the first embodiment, one detection circuit DET2 is used, and in the second embodiment, two detection circuits DET1 and DET2 are used, but three or more detection circuits may be provided.

Further, the embodiment described above is an example of means for realizing the present invention, and should be modified or changed as appropriate depending on the configuration of the device to which the present invention is applied and various conditions. It is not limited to this aspect. For example, in the embodiments described above, the IGBT was mainly described as the power semiconductor switch to be driven, but the invention can also be applied to a gate drive circuit that drives other power semiconductor switches (for example, MOSFET). Furthermore, in the embodiments and examples described above, the circuit diagrams mainly use N-channel MOSFETs and P-channel MOSFETs, but the circuits may also be constructed using N-channel MOSFETs instead of P-channel MOSFETs. That's fine, or vice versa. Also, other types of elements may be used. For example, the circuit may be configured using bipolar transistors.

10, 106 IGBT
12, ZL104 Load 14 Snubber circuit 16 Active clamp circuit 100, 200 Gate drive circuit 102, 202, 302 Predictive active clamp circuit 102a, 202a, 302a Output terminal 102b, 202b, 302b Detection terminal C _d capacitor C _S capacitor C _z parallel Capacitance D _S diode D _Z constant voltage diode DET2, DET3 Detection circuit R1, R2, R3 Resistance R _d resistance R _S resistance R _Z limiting resistance SW1, SW2, SW3 Switch V _Z ideal constant voltage diode Z1, Z2 Impedance circuit ZD1 Constant voltage diode

Claims (4)

A gate drive circuit that drives a power semiconductor element,
When the power semiconductor element turns off, if the collector-emitter voltage of the power semiconductor element reaches a predetermined voltage, the collector-emitter voltage of the power semiconductor element is clamped at the predetermined voltage, and the power an active clamp circuit that supplies a predetermined current to the gate terminal of a semiconductor element;
The active clamp circuit comprises:
a constant voltage diode having one end connected to the collector terminal of the power semiconductor element;
an impedance circuit connected between the other end of the voltage regulator diode and a negative power supply;
an output terminal connected to a connection point between the constant voltage diode and the impedance circuit and connected to the gate terminal of the power semiconductor element;
One end is connected to a connection point between the constant voltage diode and the impedance circuit, and the other end is connected to a negative power supply, and when the power semiconductor element is turned off, the power semiconductor element is turned off based on an external switching signal. a first extraction circuit consisting of a series circuit of a first switch and a first resistor for extracting charge from the gate terminal;
One end is connected to the connection point between the constant voltage diode and the impedance circuit, and the other end is connected to the negative power supply, and when the power semiconductor element is turned off, the gate terminal of the power semiconductor element is connected based on the opening/closing signal. a second extraction circuit consisting of a series circuit of a second switch and a second resistor for extracting charge from;
Based on the voltage at the connection point between the constant voltage diode and the impedance circuit, the rate of increase in the collector voltage over time when the power semiconductor element is turned off is determined, and when the rate of increase exceeds a predetermined threshold, the switch is activated. a detection circuit that outputs an open signal;
has
The impedance circuit is a parallel circuit of a resistor Rd and a capacitor Cd, the resistance value of the resistor Rd is expressed as Rd, the capacitance of the capacitor Cd is expressed as Cd, the constant voltage diode is approximated by a capacitor Cz, and this capacitor Cz The capacity of is expressed as Cz,
The rate of increase in the collector voltage VCE(t) of the power semiconductor element is expressed as follows, where t is time:

The voltage V1 at the connection point between the constant voltage diode and the impedance circuit is expressed as

It is expressed as
When the second switch receives the switch open signal, the second switch changes from a conductive state to a non-conductive state, thereby setting a resistance value for extracting the gate charge of the power semiconductor element in parallel with the first resistor and the second resistor. The gate drive is characterized in that by increasing the value from the value of the first resistor to the value of the first resistor, the extraction of the gate charge to the negative power supply is reduced, and the gate charge is extracted while alleviating turn-off of the power semiconductor element. circuit. The gate drive circuit according to claim 1,
The active clamp circuit is
When the surge voltage generated when turning off the power semiconductor element reaches or near the maximum rated voltage of the collector-emitter voltage of the power semiconductor element, the collector-emitter voltage is clamped at that voltage. , and at the same time, the gate drive circuit is an active clamp circuit that reduces surge voltage and prevents voltage breakdown by supplying current to the gate of the power semiconductor element. The gate drive circuit according to claim 1,
The constant voltage diode has a parallel capacitance parasitic to the constant voltage diode,
A gate drive circuit, wherein the impedance circuit includes at least a parallel circuit of a resistor and a capacitor. The gate drive circuit according to any one of claims 1 to 3,
n-1 types of n-th extraction circuits from the second extraction circuit to the n-th extraction circuit;
n-1 types of n-th detection circuits from the second detection circuit to the n-th detection circuit;
, where n is a natural number of 3 or more,
The n-th extraction circuit is connected to a connection point between the constant voltage diode and the impedance circuit, and is configured to extract charge from the gate terminal of the power semiconductor element based on the open/close signal when the power semiconductor element is turned off. It consists of a series circuit of an n-th switch and an n-th resistor,
The n-th detection circuit determines a rate of increase in collector voltage over time when the power semiconductor element is turned off based on the voltage at a connection point between the constant voltage diode and the impedance circuit, and determines whether the rate of increase is a predetermined rate of increase over time . If the nth threshold is exceeded, output an nth switch open signal;
When the n-th switch receives the n-th switch open signal, the n-th switch changes from a conductive state to a non-conductive state, thereby increasing the resistance value for extracting the gate charge of the power semiconductor element, and increasing the resistance value for extracting the gate charge of the power semiconductor element. A gate drive circuit characterized by extracting gate charge while alleviating turn-off.

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