JP7346855B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device.

Conventionally, silicon (Si) has been used as a constituent material of power semiconductor devices that control high voltages and large currents. Power semiconductor devices include bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). MOS type with an insulated gate consisting of a three-layer structure There are several types of transistors, including field-effect transistors, which are used depending on the purpose.

For example, bipolar transistors and IGBTs have higher current densities than MOSFETs and can handle large currents, but cannot be switched at high speed. Specifically, bipolar transistors can only be used at a switching frequency of about several kHz, and IGBTs can only be used at switching frequencies of about several tens of kHz. On the other hand, power MOSFETs have a lower current density than bipolar transistors and IGBTs, making it difficult to increase the current, but they are capable of high-speed switching operations up to several MHz.

Furthermore, unlike an IGBT, a MOSFET can use a parasitic diode formed by a pn junction between a p-type base region and an n ^- type drift region as a freewheeling diode for protecting the MOSFET. Therefore, when a MOSFET is used as an inverter device, it can be used without additionally connecting an external freewheeling diode to the MOSFET, so it is attracting attention from an economic standpoint.

There is a strong demand in the market for power semiconductor devices that combine high current and high speed, and efforts are being made to improve IGBTs and power MOSFETs, and their development has now progressed to the point where they have almost reached their material limits. For this reason, semiconductor materials that can replace silicon are being considered from the perspective of power semiconductor devices, and silicon carbide is a semiconductor material that can be used to create (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics. (SiC) is attracting attention.

Furthermore, silicon carbide is a chemically very stable semiconductor material, has a wide band gap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. Furthermore, silicon carbide has a maximum electric field strength that is at least one order of magnitude higher than that of silicon, so it is expected to be a semiconductor material that can sufficiently reduce on-resistance. Such a feature of silicon carbide is that it is a semiconductor with a wider band gap than other silicones (hereinafter referred to as a wide band gap semiconductor).

The structure of a conventional semiconductor device will be explained using an n-channel MOSFET using silicon carbide (SiC) as a wide bandgap semiconductor as an example. FIG. 15 is a plan view showing the layout of a conventional semiconductor device viewed from the front side of a semiconductor substrate. A conventional semiconductor device 120 shown in FIG. 15 includes a main semiconductor element 111 and one or more circuit sections for protecting and controlling the main semiconductor element 111 in an active region 101 of the same semiconductor substrate 110 made of silicon carbide. has. Reference numeral 102 is an edge termination area.

The main semiconductor element 111 is a vertical MOSFET, and is composed of a plurality of unit cells (functional units: not shown) arranged adjacent to each other in an effective area (hereinafter referred to as main effective area) 101a of the active region 101. Ru. The source pad 121a of the main semiconductor element 111 is provided on the front surface of the semiconductor substrate 110 in the main effective region 101a. The main effective region 101a is a portion of the active region 101 excluding the main ineffective region 101b, and occupies most of the active region 101. The main invalid region 101b is a region of the active region 101 where unit cells of the main semiconductor element 111 are not arranged.

Examples of the circuit section for protecting and controlling the main semiconductor element 111 include high-performance sections such as a current sensing section 112, a temperature sensing section 113, an overvoltage protection section (not shown), and an arithmetic circuit section (not shown). It will be done. A circuit section for protecting and controlling the main semiconductor element 111 is provided in the main invalid region 101b. The current sensing section 112 is a vertical MOSFET that includes a smaller number of unit cells having the same configuration as the main semiconductor element 111 than the number of unit cells (functional units of the element) of the main semiconductor element 111.

The current sensing unit 112 has a function of detecting over current (OC) flowing through the main semiconductor element 111. A unit cell of the current sensing section 112 is arranged in a part of a region (hereinafter referred to as an effective sense region) 112a directly below an electrode pad (hereinafter referred to as an OC pad) 122 of the current sensing section 112. A region 112c other than the sense valid region 112a (hereinafter referred to as a sense invalid region) directly under the OC pad 122 is a region where unit cells of the current sense section 112 are not arranged, and does not function as the current sense section 112.

In the sense invalid region 112c, a p-type region is provided in the surface region of the semiconductor substrate 110 over the entire sense invalid region 112c. Electrode pads other than the source pad 121a are provided on the front surface of the semiconductor substrate 110 in the main invalid region 101b. In FIG. 15, the source pad 121a, the gate pad 121b, the OC pad 122, and the electrode pads (anode pad 123a and cathode pad 123b) of the temperature sensing section 113 are designated as S, G, OC, A, and K, respectively. Illustrated.

In addition, with the increase in current, compared to a planar gate structure in which a channel is formed along the front surface of the semiconductor substrate, a channel ( A trench gate structure in which an inversion layer is formed is advantageous in terms of cost. The reason for this is that the trench gate structure can increase the density of unit cells (constituent units of an element) per unit area, thereby increasing the current density per unit area.

As the current density of the device increases, the rate of temperature rise increases depending on the volume occupied by the unit cell, so a double-sided cooling structure is required to improve discharge efficiency and stabilize reliability. Furthermore, in consideration of reliability, high-performance circuits such as a current sensing section, temperature sensing section, and overvoltage protection section are installed on the same semiconductor substrate as the vertical MOSFET, which is the main semiconductor element, to protect and control the main semiconductor element. It is necessary to have a highly functional structure in which functional parts are arranged.

A conventional semiconductor device equipped with a current sensing section is a semiconductor device equipped with high-performance sections such as a current sensing section, a temperature sensing section, and an overvoltage protection section on the same semiconductor substrate as a main semiconductor element. A device has been proposed in which each electrode pad is arranged on the front surface of the semiconductor substrate in the active region, and the unit cell of the main semiconductor element provided throughout the active region is also provided directly under each electrode pad in the high-performance area. (For example, see Patent Document 1 below.)

JP2017-079324A

However, the film quality of the gate insulating film formed on the surface of the semiconductor substrate made of silicon carbide is sensitive to electric charge, and the current sensor has a small surface area of the active region (hereinafter referred to as active area) occupying the semiconductor substrate compared to the main semiconductor element. The ESD (Electro-Static Discharge) resistance is lower than that of the main semiconductor element. Furthermore, the electric field tends to concentrate in the current sensing part, and the reverse recovery capability of the parasitic diode formed by the pn junction between the p-type base region and the n ^- type drift region is lower in the current sensing part than in the main semiconductor element. Put it away.

In order to solve the above-mentioned problems with the prior art, the present invention makes it possible to improve ESD resistance and reduce parasitic diodes when manufacturing a semiconductor device having a current sensing section on the same semiconductor substrate as a main semiconductor element. An object of the present invention is to provide a semiconductor device that can improve reverse recovery withstand capability.

In order to solve the above problems and achieve the objects of the present invention, a semiconductor device according to the present invention has the following features. The first conductivity type region is provided inside a semiconductor substrate made of a semiconductor having a wider bandgap than silicon. The first second conductivity type region is provided between the first main surface of the semiconductor substrate and the first conductivity type region. The first insulated gate field effect transistor uses the first conductivity type region as a drift region and the first second conductivity type region as a base region. A first source pad of the first insulated gate field effect transistor is provided on the first main surface of the semiconductor substrate and electrically connected to the first second conductivity type region. The second second conductivity type region is provided between the first main surface of the semiconductor substrate and the first conductivity type region in a region different from the first second conductivity type region. In the second insulated gate field effect transistor, the first conductivity type region is a drift region, and the second second conductivity type region is a base region. The second insulated gate field effect transistor has a plurality of cells having the same cell structure as the first insulated gate field effect transistor, but is smaller in number than the first insulated gate field effect transistor. The second source pad of the second insulated gate field effect transistor is provided on the first main surface of the semiconductor substrate, away from the first source pad. The second source pad is electrically connected to the second second conductivity type region. A common drain electrode of the first insulated gate field effect transistor and the second insulated gate field effect transistor is electrically connected to the second main surface of the semiconductor substrate. The second insulated gate field effect transistor has first and second cells. The first cell operates as the second insulated gate field effect transistor when a predetermined voltage is applied thereto. The second cell does not operate even if the predetermined voltage is applied. One or more pads provided on the first main surface of the semiconductor substrate, separated from the first source pad and the second source pad, and facing the semiconductor substrate in a direction perpendicular to the first main surface of the semiconductor substrate. The device further includes an electrode pad. The ineffective region where the second cell is provided extends from a region facing the second source pad in a direction perpendicular to the first main surface of the semiconductor substrate to a direction perpendicular to the first main surface of the semiconductor substrate. It extends to a region facing at least one of the electrode pads.

Furthermore, in order to solve the above-mentioned problems and achieve the objects of the present invention, a semiconductor device according to the present invention has the following features. The first conductivity type region is provided inside a semiconductor substrate made of a semiconductor having a wider bandgap than silicon. The first second conductivity type region is provided between the first main surface of the semiconductor substrate and the first conductivity type region. The first insulated gate field effect transistor uses the first conductivity type region as a drift region and the first second conductivity type region as a base region. A first source pad of the first insulated gate field effect transistor is provided on the first main surface of the semiconductor substrate and electrically connected to the first second conductivity type region. The second second conductivity type region is provided between the first main surface of the semiconductor substrate and the first conductivity type region in a region different from the first second conductivity type region. In the second insulated gate field effect transistor, the first conductivity type region is a drift region, and the second second conductivity type region is a base region. The second insulated gate field effect transistor has a plurality of cells having the same cell structure as the first insulated gate field effect transistor, but is smaller in number than the first insulated gate field effect transistor. The second source pad of the second insulated gate field effect transistor is provided on the first main surface of the semiconductor substrate, away from the first source pad. The second source pad is electrically connected to the second second conductivity type region. A common drain electrode of the first insulated gate field effect transistor and the second insulated gate field effect transistor is electrically connected to the second main surface of the semiconductor substrate. The second insulated gate field effect transistor has first and second cells. The first cell operates as the second insulated gate field effect transistor by applying a predetermined voltage. The second cell does not operate even if the predetermined voltage is applied. The second cell is provided with a source region, and the source region is electrically insulated from the second source pad.

Furthermore, in order to solve the above-mentioned problems and achieve the objects of the present invention, a semiconductor device according to the present invention has the following features. The first conductivity type region is provided inside a semiconductor substrate made of a semiconductor having a wider bandgap than silicon. The first second conductivity type region is provided between the first main surface of the semiconductor substrate and the first conductivity type region. The first insulated gate field effect transistor uses the first conductivity type region as a drift region and the first second conductivity type region as a base region. A first source pad of the first insulated gate field effect transistor is provided on the first main surface of the semiconductor substrate and electrically connected to the first second conductivity type region. The second second conductivity type region is provided between the first main surface of the semiconductor substrate and the first conductivity type region in a region different from the first second conductivity type region. In the second insulated gate field effect transistor, the first conductivity type region is a drift region, and the second second conductivity type region is a base region. The second insulated gate field effect transistor has a plurality of cells having the same cell structure as the first insulated gate field effect transistor, but is smaller in number than the first insulated gate field effect transistor. The second source pad of the second insulated gate field effect transistor is provided on the first main surface of the semiconductor substrate, away from the first source pad. The second source pad is electrically connected to the second second conductivity type region. A common drain electrode of the first insulated gate field effect transistor and the second insulated gate field effect transistor is electrically connected to the second main surface of the semiconductor substrate. The second insulated gate field effect transistor has first and second cells. The first cell operates as the second insulated gate field effect transistor when a predetermined voltage is applied thereto. The predetermined voltage is not applied to the second cell. The second second conductivity type region of the second cell is electrically insulated from the second source pad.

Further, in the semiconductor device according to the above-described invention, the surface area of the ineffective region where the second cell is provided is larger than the surface area of the second effective region where the first cell is provided. Features. Further, in the semiconductor device according to the above-described invention, the first source pad and the second source pad are provided on the first main surface of the semiconductor substrate, and the first main surface of the semiconductor substrate is provided separately from the first source pad and the second source pad. The semiconductor device further includes one or more electrode pads facing the semiconductor substrate in a direction perpendicular to the plane. The ineffective region where the second cell is provided extends from a region facing the second source pad in a direction perpendicular to the first main surface of the semiconductor substrate to a direction perpendicular to the first main surface of the semiconductor substrate. It is characterized in that it extends to a region facing at least one of the electrode pads.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the electrode pad is a gate pad of the first insulated gate field effect transistor.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the semiconductor device includes the electrode pad of a diode that detects the temperature of the first insulated gate field effect transistor.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the semiconductor device has the electrode pad of a diode that protects the first insulated gate field effect transistor from overvoltage.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the second insulated gate field effect transistor detects an overcurrent flowing through the first insulated gate field effect transistor.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the second second conductivity type region is provided apart from the first second conductivity type region.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the second second conductivity type region is electrically connected to the first second conductivity type region.

Further, in the semiconductor device according to the present invention, in the above-described invention, the surface area of the second effective region in which the first cell is provided is equal to the surface area of the first effective region in which the first insulated gate field effect transistor is provided. It is characterized by having a surface area of 1/1000 or less of the surface area of .

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the second cell is adjacent to the first cell.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the second cell surrounds the first cell.

Further, in the semiconductor device according to the above-described invention, the second cell is provided with a source region, and the source region is electrically insulated from the second source pad. do.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the second cell is not provided with a source region.

According to the semiconductor device according to the present invention, when manufacturing a semiconductor device equipped with a current sensing portion on the same semiconductor substrate as a main semiconductor element, by increasing the apparent area of the gate insulating film in the trench, The ESD resistance is improved by the second cell arranged in the region, and the reverse recovery resistance of the parasitic diode can be improved by alleviating local electric field concentration in the current sensing section.

FIG. 2 is a plan view showing a layout of the semiconductor device according to the first embodiment when viewed from the front side of a semiconductor substrate. FIG. 2 is a cross-sectional view showing the cross-sectional structure of the active region in FIG. 1; FIG. 2 is a cross-sectional view showing the cross-sectional structure of the active region in FIG. 1; FIG. 2 is a cross-sectional view showing the cross-sectional structure of the active region in FIG. 1; 2 is a circuit diagram showing an equivalent circuit of the semiconductor device 20 according to the first embodiment. FIG. FIG. 2 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment. 7 is a plan view showing a layout of a semiconductor device according to a second embodiment when viewed from the front surface side of a semiconductor substrate. FIG. FIG. 2 is a characteristic diagram showing ESD resistance of Examples 1 and 2. FIG. 3 is a characteristic diagram showing the reverse recovery withstand capacity of the parasitic diodes of Examples 1 and 2. FIG. FIG. 2 is a plan view showing a layout of a conventional semiconductor device viewed from the front side of a semiconductor substrate.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, a layer or region prefixed with n or p means that electrons or holes are the majority carriers, respectively. Furthermore, + and - appended to n and p mean that the impurity concentration is higher or lower than that of a layer or region to which n or p is not appended, respectively. Note that in the following description of the embodiment and the accompanying drawings, similar components are denoted by the same reference numerals, and overlapping description will be omitted. In this specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after it, and adding "-" in front of the index represents a negative index.

(Embodiment 1)
The semiconductor device according to the first embodiment is configured using a semiconductor having a wider band gap than silicon (Si) (wide band gap semiconductor) as a semiconductor material. The structure of the semiconductor device according to the first embodiment will be explained using an example in which silicon carbide (SiC) is used as a wide bandgap semiconductor. FIG. 1 is a plan view showing the layout of the semiconductor device according to the first embodiment, viewed from the front side of the semiconductor substrate.

The semiconductor device 20 according to the first embodiment shown in FIG. It has one or more circuit sections for controlling. The main semiconductor element 11 is a vertical MOSFET in which a drift current flows in the depth direction Z of the semiconductor substrate 10 in an on state. The main semiconductor element 11 includes a plurality of unit cells (functional units of the element) arranged adjacent to each other in a direction parallel to the front surface of the semiconductor substrate 10 and connected in parallel to each other by source pads (first source pads) 21a. ).

The main semiconductor element 11 performs the main operation of the semiconductor device 20 according to the first embodiment. The main semiconductor element 11 is arranged in an effective region (main effective region: first effective region) 1a of the active region 1. The main effective region 1a is a region through which the main current of the main semiconductor element 11 flows when the main semiconductor element 11 is turned on. The main effective region 1 a has, for example, a substantially rectangular planar shape and occupies most of the surface area of the active region 1 .

The circuit section for protecting and controlling the main semiconductor element 11 includes, for example, a current sensing section (second insulated gate field effect transistor) 12, a temperature sensing section 13, an overvoltage protection section (not shown), and an arithmetic circuit section (not shown). Examples include high-performance parts such as (shown in the figure). A circuit section for protecting and controlling the main semiconductor element 11 is arranged, for example, in the main invalid region (first region) 1b of the active region 1. The main invalid region 1b is a region where no unit cell of the main semiconductor element 11 is arranged, and does not function as the main semiconductor element 11.

The main invalid area 1b has, for example, a substantially rectangular planar shape, and one side thereof is adjacent to one side of the main effective area 1a. The main effective region 1a and the main ineffective region 1b are separated by n-type regions 32a and 32b (FIGS. 2 to 4), which will be described later. The main invalid region 1b is arranged, for example, between the main effective region 1a and the edge termination region 2 surrounding the active region 1.

The edge termination region 2 is a region between the active region 1 and the end of the semiconductor substrate 10, and maintains a breakdown voltage by relaxing the electric field on the front surface side of the semiconductor substrate 10. In the edge termination region 2, a voltage-resistant structure (not shown) such as a field limiting ring (FLR) or a junction termination extension (JTE) structure is arranged. Withstand voltage is the limit voltage at which an element will not malfunction or break down.

The source pad (electrode pad) 21a of the main semiconductor element 11 is arranged on the front surface of the semiconductor substrate 10 in the main effective region 1a. The main semiconductor element 11 has a larger current capacity than other circuit sections. Therefore, the source pad 21a of the main semiconductor element 11 has substantially the same planar shape as the main effective region 1a, and covers almost the entire surface of the main effective region 1a. The source pad of the main semiconductor element 11 is arranged apart from the electrode pads other than the source pad 21a.

The electrode pads other than the source pad 21a are arranged apart from each other on the front surface of the semiconductor substrate 10 in the main invalid region 1b. The electrode pads other than the source pad 21a include the gate pad 21b of the main semiconductor element 11, the electrode pad (hereinafter referred to as OC pad (second source pad)) 22 of the current sensing section 12, and the electrode pad of the temperature sensing section 13 (hereinafter referred to as an OC pad (second source pad)). These are electrode pads (hereinafter referred to as anode pads and cathode pads) 23a and 23b, electrode pads of an overvoltage protection section (hereinafter referred to as OV pads (not shown)), electrode pads (not shown) of an arithmetic circuit section, and the like.

The electrode pads other than the source pad 21a have, for example, a substantially rectangular planar shape and have a surface area necessary for bonding terminal pins 48b to 48e and wires, which will be described later. FIG. 1 shows a case where electrode pads other than the source pad 21a are arranged in a line along the boundary between the main invalid region 1b and the edge termination region 2 (the same applies to FIG. 12). Further, in FIG. 1, a source pad 21a, a gate pad 21b, an OC pad 22, an anode pad 23a, and a cathode pad 23b are illustrated in rectangular shapes labeled S, G, OC, A, and K, respectively.

The current sensing unit 12 operates under the same conditions as the main semiconductor element 11 and has a function of detecting an overcurrent (OC) flowing through the main semiconductor element 11. The current sensing section 12 is placed apart from the main semiconductor element 11. The current sensing section 12 is a vertical MOSFET that includes unit cells having the same configuration as the main semiconductor element 11 in a smaller number (for example, about 10) than the number of unit cells of the main semiconductor element 11 (for example, about 10,000). It is.

For example, when the semiconductor device 20 according to the first embodiment is an IPM (Intelligent Power Module), the current capacity of the main semiconductor element 11 is about 100A, and the current capacity of the current sensing section 12 is about 0.1A or less. . The unit cells of the current sensing section 12 are arranged adjacent to each other in a direction parallel to the front surface of the semiconductor substrate 10. The direction in which the unit cells of the current sensing section 12 are adjacent to each other may be the same as the direction in which the unit cells of the main semiconductor element 11 are adjacent to each other.

Further, all the unit cells of the current sensing section 12 are arranged directly under the OC pad 22. Among the unit cells of the current sensing section 12, a unit cell (first cell) arranged in a part of the area directly under the OC pad 22 (hereinafter referred to as a sense effective area (second effective area)) 12a is as follows. , operates as the current sensing section 12 by applying a predetermined voltage. The unit cells in the sense effective region 12a are connected in parallel to each other by OC pads 22.

Among the unit cells of the current sensing section 12, a unit cell (second cell) disposed in a region 12b immediately below the OC pad 22 other than the sense valid region 12a (hereinafter referred to as a first sense invalid region (invalid region)) ) is a dummy unit cell having a structure to which a predetermined voltage is not applied or a structure which does not operate even if a predetermined voltage is applied. That is, only some of the plurality of unit cells arranged directly under the OC pad 22 are used as the current sensing section 12.

The unit cells in the first sense invalid region 12b are arranged adjacent to the unit cells in the sense valid region 12a. The unit cell of the first sense invalid region 12b is, for example, a contact (electrical contact) between the OC pad 22 and the semiconductor portion (n ⁺ type source region 35b and p type base region (second second conductivity type region) 34b). ), it becomes a dummy unit cell (see Figures 2 to 4).

In this case, for example, by not forming the second contact hole 40b for making contact between the OC pad 22 and the semiconductor part in the interlayer insulating film 40 in the first sense invalid region 12b, the unit cells in the first sense invalid region 12b can be can be used as a dummy unit cell. Therefore, the surface area and arrangement of the sense effective region 12a can be changed only by changing the pattern of the etching mask for forming the contact hole in the interlayer insulating film 40. For example, by arranging the unit cells of the first sense invalid region 12b so as to surround the unit cells of the sense effective region 12a, it is possible to improve the ESD resistance and reverse recovery resistance of the unit cells arranged in the sense effective region 12a. can.

Further, the unit cell of the first sense invalid region 12b has only a p type base region 34b and a p ⁺⁺ type contact region 36b between two adjacent trenches 37b (mesa region), and an n ⁺ type source region 35b. It may also be a dummy unit cell by not having (not shown). In this case, the surface area and arrangement of the sense effective region 12a can be changed only by changing the pattern of the ion implantation mask for forming the n ⁺ -type source region 35b of the current sensing section 12.

The sense effective area 12a has, for example, a substantially rectangular planar shape. When a wire is bonded (joined) to the OC pad 22, the sense effective region 12a is arranged in a position that does not face the joint between the OC pad 22 and the wire (for example, the center of the OC pad 22) in the depth direction Z. It is good that it is done. Thereby, it is possible to suppress the load (pressure) applied to the unit cells of the sense effective region 12a due to wire bonding to the OC pad 22.

Furthermore, it is preferable that the sense effective region 12a be arranged away from the edge termination region 2 and closer to the active region 1 than the edge termination region 2 is. By arranging the sense effective region 12a apart from the edge termination region 2, it can be made less susceptible to the influence of the edge termination region 2. For example, it is preferable that the sense effective region 12a be placed a predetermined distance away from a p-type region (not shown) for element isolation, and as equidistant as possible from the p-type region.

The p-type region for element isolation is provided in the edge termination region 2 in a substantially rectangular shape surrounding the active region 1, and is a parasitic diode that electrically isolates the active region 1 and the edge termination region 2 ^. This is a p-type region formed by a pn junction with a type drift region. For example, the sense effective region 12a may be arranged approximately equidistant from two sides of the semiconductor substrate 10 that share one vertex. This makes it possible to reduce the influence of the parasitic diode in the edge termination region 2.

The surface area of the sense effective region 12a is preferably 1/1000 or less of the surface area of the main effective region 1a. Note that the total area of the n ⁺ -type source regions 35b, 35a included in each region 12a, 1a can be used as the surface area of each of the sense effective region 12a and the main effective region 1a. Furthermore, the total number of unit cells included in each of the regions 12a and 1a may be used as the surface area of the sense effective region 12a and the main effective region 1a.

The reason why the surface area of the sense effective region 12a is set to the above ratio with respect to the surface area of the main effective region 1a is as follows. As the surface area of the sensing effective region 12a increases, the conduction loss due to the on-resistance of the current sensing section 12 increases. By setting the surface area of the sense effective region 12a within the above range, the conduction loss of the current sensing section 12 can be made small enough to be ignored with respect to the conduction loss of the entire semiconductor device 20 according to the first embodiment. It is from.

The first sense invalid region 12b may be arranged closer to the active region 1 than the sense valid region 12a. The first sense invalid region 12b has, for example, a substantially rectangular planar shape and is in contact with the sense valid region 12a. In FIG. 1, the first sense invalid area 12b includes a substantially rectangular planar sense valid area 12a such that one vertex of each of the first sense invalid area 12b and the sense valid area 12a overlaps with each other. It has a rectangular planar shape and is in contact with two sides that share the vertex of the sense effective area 12a.

The first sense invalid area 12b occupies most of the area directly under the OC pad 22. The surface area of the first sense invalid region 12b may be larger than the surface area of the sense valid region 12a, for example. The larger the surface area of the first sense invalid region 12b, the smaller the area of the parasitic diode formed by the pn junction between the p-type region directly under the OC pad 22 and the n ^- type drift region (first conductivity type region) 32. Therefore, the ESD resistance of the current sensing section 12 can be increased.

Directly below the OC pad 22, there may be a region 12c (hereinafter referred to as a second sense invalid region) in which no unit cell of the current sensing section 12 is arranged. The second sense invalid region 12c surrounds, for example, a region immediately below the OC pad 22 in which a unit cell of the current sensing section 12 is arranged. In the second sense invalid region 12c, a p-type region is provided in the surface region of the semiconductor substrate 10 over the entire second sense invalid region 12c.

The temperature sensing section 13 has a function of detecting the temperature of the main semiconductor element 11 using the temperature characteristics of the diode. The temperature sensing section 13 may be, for example, a polysilicon diode made of a polysilicon (poly-Si) layer provided on the field insulating film 80c on the front surface of the semiconductor substrate 10 (FIG. 3). ), it may be a diffused diode formed by a pn junction between a p-type region and an n-type region formed inside the semiconductor substrate 10.

The overvoltage protection unit (not shown) is a diode that protects the main semiconductor element 11 from overvoltage (OV) such as a surge, for example. The current sensing section 12, the temperature sensing section 13, and the overvoltage protection section are controlled by the arithmetic circuit section, and the main semiconductor element 11 is controlled based on the output signals thereof. The arithmetic circuit section is composed of a plurality of semiconductor elements such as a CMOS (Complementary MOS) circuit.

Next, a cross-sectional structure of active region 1 of semiconductor device 20 according to the first embodiment will be described. 2 to 4 are cross-sectional views showing the cross-sectional structure of the active region of FIG. 1. FIG. FIG. 2 shows a cross-sectional structure taken along a cutting line X1-X2-X3-X4 from the main effective area 1a in FIG. 1 to the sense effective area 12a through the first sense invalid area 12b of the main invalid area 1b. In FIG. 2, only a part of the unit cells are shown in each of the main valid area 1a, the sense valid area 12a, and the first sense invalid area 12b, and most of the unit cells are omitted from illustration (the same applies to FIGS. 3 and 4).

FIG. 3 shows a cross-sectional structure taken along a cutting line X1'-X2'-X3'-Y1-Y2 from the main effective area 1a in FIG. shows. FIG. 4 shows cutting lines X1'-X2'-X3' and cutting lines Y2-Y3 from the main valid area 1a in FIG. The cross-sectional structure is shown. In FIG. 4, the temperature sensing section 13 between the current sensing section 12 and the gate pad section 14 is not shown.

The main semiconductor element 11 is a vertical MOSFET that includes a MOS gate (an insulated gate having a three-layer structure of metal-oxide film-semiconductor) on the front surface side of the semiconductor substrate 10 in the main effective region 1a. Here, we will take as an example a case where the main semiconductor element 11 and the circuit section that protects and controls the main semiconductor element 11 have the same wiring structure using pin-shaped wiring members (terminal pins 48a to 48d to be described later). As will be explained, a wiring structure using a wire may be used instead of the pin-shaped wiring member.

Semiconductor substrate 10 includes silicon carbide layers 71 and 72 that will become n ^- type drift region 32 and p-type base region (first second conductivity type region) 34a on n ⁺ type starting substrate 31 made of silicon carbide. This is an epitaxial substrate grown epitaxially. Each part constituting the MOS gate of the main semiconductor element 11 is provided on the front surface side of the semiconductor substrate 10. The parts constituting the MOS gate of the main semiconductor element 11 are a p-type base region 34a, an n ⁺ -type source region 35a, a p ^++- type contact region 36a, a trench 37a, a gate insulating film 38a, and a gate electrode 39a.

Trench 37a penetrates p-type silicon carbide layer 72 in the depth direction Z from the front surface of semiconductor substrate 10 (the surface of p-type silicon carbide layer 72) to reach n ^−-type silicon carbide layer 71. The trench 37a is formed, for example, in a direction X that is parallel to the front surface of the semiconductor substrate 10 and in which the electrode pads 21b, 23a, 23b, and 22 are lined up (see FIG. They may be arranged in a stripe shape extending in a direction Y perpendicular to the direction X (hereinafter referred to as a second direction), or they may be arranged in a matrix shape when viewed from the front surface side of the semiconductor substrate 10. . 2 and 3 show striped trenches 37a extending in the first direction X. In FIGS.

A gate electrode 39a is provided inside the trench 37a with a gate insulating film 38a interposed therebetween. A p-type base region 34a is provided between two adjacent trenches 37a (mesa region). Inside the semiconductor substrate 10, an n ^- type drift region 32 is provided in contact with the p type base region 34a at a position closer to the n + type drain region (n ⁺ type starting substrate 31) than the p ^type base region 34a. ing. An n ^- type current diffusion region 33a may be provided in the mesa region between the p-type base region 34a and the n-type drift region 32.

The n-type current spreading region 33a is a so-called current spreading layer (CSL) that reduces carrier spreading resistance. Further, the first and second p ⁺ type regions 61a and 62a may be selectively provided inside the semiconductor substrate 10, respectively. The first p ⁺ -type region 61a is provided at a position closer to the n ⁺ -type drain region than the p-type base region 34a, separated from the p-type base region 34a, and faces the bottom surface of the trench 37a in the depth direction Z.

The second p ⁺ -type region 62a is provided in the mesa region at a position closer to the n ⁺ -type drain region than the p-type base region 34a, and is separated from the first p ⁺ -type region 61a and the trench 37a. be in contact with The first and second p ⁺ type regions 61a and 62a form a pn junction with the n type current diffusion region 33a and the n ^- type drift region 32, and have the function of relaxing the electric field applied to the gate insulating film 38a at the bottom of the trench 37a. have 2 to 4 show cases in which an n-type current diffusion region 33a and first and second p ⁺ -type regions 61a and 62a are provided.

A p-type base region 34a, an n ⁺ -type source region 35a, and a p ^++- type contact region 36a are selectively provided in the surface region of the semiconductor substrate 10, respectively. N ⁺ type source region 35a and p ^{+ +} type contact region 36a are provided between the front surface of semiconductor substrate 10 and p type base region 34a. The n ⁺ type source region 35a is in contact with the gate insulating film 38a on the side wall of the trench 37a. The interlayer insulating film 40 is provided over the entire front surface of the semiconductor substrate 10 and covers the gate electrode 39a.

All the gate electrodes 39a of the main semiconductor element 11 are electrically connected to the gate pad 21b (see FIG. 1) via a gate runner (not shown) made of polysilicon, for example, in a portion not shown. A first contact hole 40a is provided that penetrates the interlayer insulating film 40 in the depth direction Z and reaches the semiconductor substrate 10. The n ⁺ type source region 35a and the p ^{+ +} type contact region 36a of the main semiconductor element 11 are exposed in the first contact hole 40a.

Inside the first contact hole 40a, a nickel silicide (NiSi, _Ni2Si , or thermally stable _NiSi2 : hereinafter collectively referred to as NiSi) film 41a is provided on the front surface of the semiconductor substrate 10. ing. The NiSi film 41a is in ohmic contact with the semiconductor substrate 10 inside the first contact hole 40a, and is electrically connected to the n ⁺ type source region 35a and the p ^{+ +} type contact region 36a.

In the main effective region 1a, a barrier metal 46a is provided over the entire surface of the interlayer insulating film 40 and the NiSi film 41a. The barrier metal 46a has a function of preventing mutual reactions between metal films of the barrier metal or between regions facing each other with the barrier metal interposed therebetween. The barrier metal 46a may have, for example, a laminated structure in which a first titanium nitride (TiN) film 42a, a first titanium (Ti) film 43a, a second TiN film 44a, and a second Ti film 45a are laminated in this order.

The first TiN film 42 a is provided only on the surface of the interlayer insulating film 40 and covers the entire surface of the interlayer insulating film 40 . The first Ti film 43a is provided on the surface of the first TiN film 42a and the NiSi film 41a. The second TiN film 44a is provided on the surface of the first Ti film 43a. The second Ti film 45a is provided on the surface of the second TiN film 44a. For example, the temperature sensing section 13 is not provided with a barrier metal.

The source pad 21a is buried in the first contact hole 40a and provided on the entire surface of the second Ti film 45a. Source pad 21a is electrically connected to n ⁺ type source region 35a and p ⁺⁺ type contact region 36a via barrier metal 46a and NiSi film 41a, and functions as a source electrode of main semiconductor element 11. The source pad 21a is, for example, an aluminum (Al) film or an Al alloy film with a thickness of about 5 μm.

Specifically, when the source pad 21a is made of an Al alloy film, the source pad 21a may be, for example, an aluminum-silicon (Al-Si) film containing about 5% or less of silicon; It may be an aluminum-silicon-copper (Al-Si-Cu) film containing about 5% or less of the total and about 5% or less of copper (Cu), or an aluminum-silicon-copper (Al-Si-Cu) film containing about 5% or less of copper. It may also be a copper (Al--Cu) film.

One end of a terminal pin 48a is bonded onto the source pad 21a via a plating film 47a and a solder layer (not shown). The other end of the terminal pin 48a is joined to a metal bar (not shown) arranged to face the front surface of the semiconductor substrate 10. Further, the other end of the terminal pin 48a is exposed to the outside of the case (not shown) in which the semiconductor substrate 10 is mounted, and is electrically connected to an external device (not shown).

The terminal pin 48a is a round bar-shaped (cylindrical) wiring member having a predetermined diameter. The terminal pin 48a is soldered to the plating film 47a in a state that it stands substantially perpendicular to the front surface of the semiconductor substrate 10. The terminal pin 48a serves as an external connection terminal for taking out the potential of the source pad 21a to the outside. Source pad 21a is connected to an external ground potential (lowest potential) via terminal pin 48a.

The plating film 47a has high adhesion to the source pad 21a even under high temperature conditions (for example, 200° C. to 300° C.), and is formed of a material that is less likely to peel off than wire bonding. The surface of the source pad 21a other than the plating film 47a is covered with a first protective film 49a. The boundary between the plating film 47a and the first protective film 49a is covered with a second protective film 50a. The first and second protective films 49a and 50a are, for example, polyimide films.

The drain electrode 51 is in ohmic contact with the entire back surface of the semiconductor substrate 10 (the back surface of the n ⁺ type starting substrate 31). A drain pad (electrode pad: not shown) is provided on the drain electrode 51 with a laminated structure in which, for example, a Ti film, a nickel (Ni) film, and a gold (Au) film are laminated in this order. The drain pad is soldered to a metal base plate (not shown), and at least partially contacts the base portion of the cooling fin (not shown) via the metal base plate.

By bonding the terminal pins 48a to the front surface of the semiconductor substrate 10 and bonding the back surface to the metal base plate in this manner, the semiconductor device according to the first embodiment has a cooling structure on each of both surfaces of the semiconductor substrate 10. It has a double-sided cooling structure. That is, the heat generated in the semiconductor substrate 10 is radiated from the fin portion of the cooling fin that is brought into contact with the back surface of the semiconductor substrate 10 via the metal base plate, and the heat generated by the semiconductor substrate 10 is radiated from the fin portion of the cooling fin that is brought into contact with the back surface of the semiconductor substrate 10 via the metal base plate, and the terminal pins 48a on the front surface of the semiconductor substrate 10 are bonded. Heat is radiated from the metal bar.

In the gate pad portion 14 of the main invalid region 1b, a gate pad 21b of the main semiconductor element 11 is provided on a field insulating film 80e covering the front surface of the semiconductor substrate 10 (FIG. 4). For example, the gate pad 21b is made of the same material as the source pad 21a and is formed at the same time as the source pad 21a. Gate pad 21b is electrically connected to a gate runner (not shown). The gate runner is provided on a field insulating film (not shown) covering the front surface of the semiconductor substrate 10 in the edge termination region 2, and surrounds the active region.

A terminal pin 48e is connected onto the gate pad 21b with the same wiring structure as the wiring structure on the source pad 21a. The terminal pin 48e is a round bar-shaped (cylindrical) wiring member. The terminal pin 48e is, for example, an external connection terminal that takes out the potential of the OC pad 22 to the outside, and connects the gate pad 21b to the gate potential of the main semiconductor element via an external device. Reference numerals 47e, 49e, and 50e are plating films and first and second protective films that constitute the wiring structure on the gate pad 21b.

A barrier metal 46e may be provided between the gate pad 21b and the field insulating film 80e, for example, with the same layered structure as the barrier metal 46a of the main semiconductor element 11. Gate pad 21b is arranged on barrier metal 46e. Reference numerals 42e, 43e, 44e, and 45e indicate a first TiN film, a first Ti film, a second TiN film, and a second Ti film, respectively, which constitute the barrier metal 46e.

Further, in the gate pad portion 14, a p-type region 34e is provided in a surface region of the front surface of the semiconductor substrate 10. The p-type region 34e faces the entire surface of the gate pad 21b in the depth direction Z. A p ⁺⁺ type contact region 36e may be provided between the front surface of the semiconductor substrate 10 and the p type region 34e. A second p ⁺ type region 62e may be provided between the p type region 34e and the n ⁻ type drift region 32.

These p type region 34e, p ⁺⁺ type contact region 36e, and second p ⁺ type region 62e are formed into a p type base region, which will be described later, by an n ⁻ type region 32b provided in the front surface region of the semiconductor substrate 10. 34b, p type region 34c, p ^{+ +} type contact region 36c and second p ⁺ type region 62c. The p type region 34e, the p ⁺⁺ type contact region 36e, and the second p ⁺ type region 62e are, for example, the p type base region 34a, the p ⁺⁺ type contact region 36a, and the second p ⁺ type region 62a of the main semiconductor element 11, respectively. have the same depth and impurity concentration.

In the main invalid region 1b, the p-type base region 34b of the current sensing section 12 is provided in the surface region of the front surface of the semiconductor substrate 10 in the sense valid region 12a and the first sense invalid region 12b. The p-type base region 34b of the current sensing section 12 is separated from the p-type base region 34a of the main semiconductor element 11 by an n ^- type region 32a provided in the front surface region of the semiconductor substrate 10. The p ^- type base region 34b of the current sensing section 12 and the p-type base region 34a of the main semiconductor element 11 may be electrically connected without providing the n - type region 32a.

The current sensing section 12 includes a p-type base region 34b, an n ⁺ -type source region 35b, a p ^++- type contact region 36b, a trench 37b, a gate insulating film 38b, and a gate electrode 39b, which have the same configuration as the corresponding sections of the main semiconductor element 11. and an interlayer insulating film 40. Each part of the MOS gate of the current sensing section 12 is provided in a sense valid region 12a and a first sense invalid region 12b. Similar to the main semiconductor element 11, the current sensing section 12 may include an n-type current diffusion region 33b and first and second p ⁺ -type regions 61b and 62b.

The gate electrode 39b of the current sensing section 12 is electrically connected to the gate pad 21b (see FIG. 1) via a gate runner. Gate electrode 39b is covered with interlayer insulating film 40. A second contact hole 40b that penetrates the interlayer insulating film 40 in the depth direction Z and reaches the semiconductor substrate 10 is provided in the sense effective region 12a. The n ⁺ type source region 35b and the p ^{+ +} type contact region 36b of the current sensing section 12 are exposed in the second contact hole 40b.

A NiSi film 41b that is in ohmic contact with the semiconductor substrate 10 is provided inside the second contact hole 40b. In the sense effective region 12a, a barrier metal 46b is provided over the entire surface of the interlayer insulating film 40 and the entire surface of the NiSi film 41b, with the same layered structure as the barrier metal 46a of the main semiconductor element 11, for example. Reference numerals 42b, 43b, 44b, and 45b are a first TiN film, a first Ti film, a second TiN film, and a second Ti film, respectively, which constitute the barrier metal 46b.

The OC pad 22 is provided over the entire surface of the barrier metal 46b so as to be embedded in the second contact hole 40b. OC pad 22 is electrically connected to n ⁺ -type source region 35b and p ⁺ -type contact region 36b of current sensing section 12 via barrier metal 46b and NiSi film 41b. The OC pad 22 functions as a source electrode of the current sensing section 12. The OC pad 22 is, for example, made of the same material as the source pad 21a and is formed at the same time as the source pad 21a.

In the first and second sense invalid regions 12b and 12c, no contact hole is provided in the interlayer insulating film 40. Thereby, the n ⁺ type source region 35b and the p ^{+ +} type contact region 36b of the first sense invalid region 12b are electrically insulated from the OC pad 22. A barrier metal 46b and an OC pad 22 extend from the sense valid region 12a on the interlayer insulating film 40 in the first and second sense invalid regions 12b and 12c. Terminal pin 48b is bonded onto OC pad 22 with the same wiring structure as that on source pad 21a. The terminal pin 48b is a round rod-shaped (cylindrical) wiring member having a smaller diameter than the terminal pin 48a.

The terminal pin 48b is, for example, an external connection terminal that takes out the potential of the OC pad 22 to the outside, and connects the OC pad 22 to the ground potential via the external resistor 15 (see FIG. 5). Reference numerals 47b, 49b, and 50b are plating films and first and second protective films that constitute the wiring structure on the OC pad 22. When a wire is used instead of the terminal pin 48b, the wire is preferably joined to the OC pad 22 in the first sense invalid region 12b.

Although not shown, when the unit cell in the first sense invalid region 12b has a structure that does not function without providing the n ⁺ type source region 35b, the mesa region in the first sense invalid region 12b has a p-type base region. 34b and p ⁺⁺ type contact region 36b are provided. Therefore, a second contact hole 40b that exposes the p-type base region 34b and the p ^++- type contact region 36b may be provided in the interlayer insulating film 40 in the first sense invalid region 12b.

In the second sense invalid region 12c, the surface region of the front surface of the semiconductor substrate 10 has a p-type region 34e, a p ^++- type contact region 36e, and a second p ⁺ -type region 62e of the gate pad portion 14. A type base region 34b, a p ⁺⁺ type contact region 36b, and a second p ⁺ type region 62b are provided. The p type base region 34b, the p ^{+ +} type contact region 36b, and the second p ⁺ type region 62b of the second sense invalid region 12c face the OC pad 22 in the depth direction Z.

The temperature sensing section 13 is, for example, a polysilicon diode formed by a pn junction between a p-type polysilicon layer 81 as a p-type anode region and an n-type polysilicon layer 82 as an n-type cathode region. P-type polysilicon layer 81 and n-type polysilicon layer 82 are provided on field insulating film 80c in main invalid region 1b. Temperature sensing section 13 is electrically insulated from main semiconductor element 11 and current sensing section 12 by field insulating film 80c.

Immediately below the p-type polysilicon layer 81 and the n-type polysilicon layer 82, in the surface region of the semiconductor substrate 10, there are a p-type region 34e of the gate pad portion 14, a p ⁺ type contact region 36e, and a second p ⁺ type region 62e. Similarly, a p type region 34c, a p ^{+ +} type contact region 36c, and a second p ⁺ type region 62c are provided. The p type region 34c and the p ⁺⁺ type contact region 36c are electrically connected to the p type base region 34b and the p ⁺⁺ type contact region 36b of the current sensing section 12.

Field insulating film 80c, p-type polysilicon layer 81, and n-type polysilicon layer 82 are covered with interlayer insulating film 83. Third and fourth contact holes 83a and 83b are provided that penetrate the interlayer insulating film 83 in the depth direction Z and expose the p-type polysilicon layer 81 and the n-type polysilicon layer 82, respectively. Anode pad 23a and cathode pad 23b are in contact with p-type polysilicon layer 81 and n-type polysilicon layer 82 at third and fourth contact holes 83a and 83b, respectively.

The anode pad 23a and the cathode pad 23b are, for example, made of the same material as the source pad 21a, and are formed at the same time as the source pad 21a. Terminal pins 48c and 48d are connected onto the anode pad 23a and the cathode pad 23b, respectively, with the same wiring structure as the wiring structure on the source pad 21a. Reference numerals 47c and 47d indicate plating films forming the wiring structure on the gate pad 21b. Reference numerals 49c and 50c are first and second protective films forming the wiring structure on the gate pad 21b.

The operation of the semiconductor device 20 according to the first embodiment will be explained. FIG. 5 is a circuit diagram showing an equivalent circuit of the semiconductor device 20 according to the first embodiment. As shown in FIG. 5, the current sensing section 12 is connected in parallel to the unit cells of a plurality of MOSFETs that constitute the main semiconductor element 11. The ratio of the sense current flowing through the current sensing section 12 to the main current flowing through the main semiconductor element 11 (hereinafter referred to as current sense ratio) is set in advance.

The current sensing ratio can be set by, for example, changing the number of unit cells between the main semiconductor element 11 and the current sensing section 12. A sense current smaller than the main current flowing through the main semiconductor element 11 flows through the current sensing section 12 according to the current sensing ratio. The source of the main semiconductor element 11 is connected to a ground point GND having a ground potential. A resistor 15, which is an external component, is connected between the source of the current sensing section 12 and the ground point GND.

When a voltage equal to or higher than the threshold voltage is applied to the gate electrode 39a of the main semiconductor element 11 while a positive voltage is applied to the drain electrode 51 with respect to the source electrode (source pad 21a) of the main semiconductor element 11, An n-type inversion layer (channel) is formed in a portion of the p-type base region 34a of the main semiconductor element 11 sandwiched between the n ⁺ -type source region 35a and the n-type current diffusion region 33a. As a result, a main current flows from the drain to the source of the main semiconductor element 11, and the main semiconductor element 11 is turned on.

At this time, under the same conditions as the main semiconductor element 11, a positive voltage is applied to the drain electrode 51 with respect to the source electrode (OC pad 22) of the current sensing section 12, and the gate electrode 39b of the current sensing section 12 is applied to the drain electrode 51. When a voltage equal to or higher than the threshold voltage is applied, an n-type inversion layer is formed in the portion of the p-type base region 34b of the sense effective region 12a sandwiched between the n ⁺ type source region 35b and the n-type current diffusion region 33b. It is formed. As a result, a sense current flows from the drain to the source of the current sensing section 12, and the current sensing section 12 is turned on.

The sense current flows to the ground point GND through the resistor 15 connected to the source of the current sensing section 12. This causes a voltage drop across the resistor 15. When an overcurrent is applied to the main semiconductor element 11, the sense current of the current sensing section 12 increases depending on the magnitude of the overcurrent in the main semiconductor element 11, and the voltage drop across the resistor 15 also increases. By monitoring the magnitude of the voltage drop across the resistor 15, an overcurrent in the main semiconductor element 11 can be detected.

On the other hand, when a voltage lower than the threshold voltage is applied to the gate electrode 39a of the main semiconductor element 11, the first and second p ⁺ type regions 61a and 62a of the main semiconductor element 11, the n type current diffusion region 33a, and the n ^- type drift The pn junction between region 32 is reverse biased. At this time, a voltage lower than the threshold voltage is also applied to the gate electrode 39b of the current sensing section 12, and the first and second p ⁺ type regions 61b, 62b, the n-type current diffusion region 33b, and the n ^- type drift of the current sensing section 12 are applied. The pn junction with region 32 is also reverse biased.

As a result, the main current of the main semiconductor element 11 and the sense current of the current sensing section 12 are cut off, and the main semiconductor element 11 and the current sensing section 12 maintain an off state. When a negative voltage with respect to the source electrode of the main semiconductor element 11 is applied to the drain electrode 51 when the main semiconductor element 11 is off, the p-type base region 34a and the first and second p ⁺ -type regions are formed in the main effective region 1a. Parasitic diodes formed at pn junctions between 61a and 62a and n-type current diffusion region 33a and n ^- type drift region 32 become conductive.

At this time, a negative voltage is applied to the drain electrode 51 with respect to the source electrode of the current sense section 12, and the sense effective region 12a is also applied to the p-type base region 34b, the first and second p ⁺ type regions 61b, 62b, and the n-type A parasitic diode is formed at the pn junction between current diffusion region 33b and n ^- type drift region 32. Also in the edge termination region 2, a parasitic diode is formed at a pn junction between a p-type region for element isolation and an n ^- type drift region 32. These parasitic diodes are turned off when the main semiconductor element 11 and the current sensing section 12 are switched from off to on.

When the parasitic diode in the active region 1 is turned off, holes in the n ^- type drift region 32 are extracted from the p-type base region 34a to the source pad 21a in the main effective region 1a. In the vicinity of the sense effective region 12a, the p-type of the sense effective region 12a is larger than the amount of hole current (reverse recovery current of the parasitic diode) drawn to the source pad 21a through the p-type base region 34a of the main effective region 1a. The amount of hole current drawn to the OC pad 22 through the mold base region 34b increases.

In the first embodiment, as described above, the dummy unit cells of the current sense section 12 are arranged in the first sense invalid region 12b, so that the unit cells of the current sense section 112 are arranged only in the sense valid region 112a. Compared to the conventional structure (see FIG. 15), the ESD resistance of the current sensing section 12 is increased. Therefore, compared to the conventional structure, the reverse recovery withstand capability of the parasitic diode in the main invalid region 1b can be increased.

Next, a method for manufacturing the semiconductor device 20 according to the first embodiment will be described. 6 to 11 are cross-sectional views showing the semiconductor device according to the first embodiment in the middle of manufacturing. Although only the main semiconductor element 11 is shown in FIGS. 6 to 11, each part of all the elements manufactured (manufactured) on the same semiconductor substrate 10 as the main semiconductor element 11 is formed simultaneously with each part of the main semiconductor element 11, for example. Ru. The formation of the current sensing section 12, temperature sensing section 13, and gate pad section 14 will be described with reference to FIGS. 1 to 4.

First, as shown in FIG. 6, an n ⁺ type starting substrate (semiconductor wafer) 31 made of silicon carbide is prepared. N ⁺ type starting substrate 31 may be, for example, a nitrogen (N)-doped silicon carbide single crystal substrate. Next, an n ⁻ type silicon carbide layer 71 doped with nitrogen at a lower concentration than that of the n ⁺ type starting substrate 31 is epitaxially grown on the front surface of the n ⁺ type starting substrate 31 . When main semiconductor element 11 has a breakdown voltage class of 3300 V, thickness t1 of n ^- type silicon carbide layer 71 may be, for example, about 30 μm.

Next, as shown in FIG. 7, the surface of n ^- type silicon carbide layer 71 is formed in main effective region 1a of each semiconductor substrate 10 (see FIG. 1) by photolithography and ion implantation of p-type impurities such as Al. A first p ⁺ type region 61a and a p ⁺ type region 91 are selectively formed in the regions. This p ⁺ type region 91 is part of the second p ⁺ type region 62a. The first p ⁺ -type regions 61a and the p ⁺ -type regions 91 are alternately and repeatedly arranged, for example, in the first direction X in FIG. 1 .

The first p ⁺ -type region 61a and the p ⁺ -type region 91 are arranged, for example, in a stripe shape extending in the second direction Y in FIG. 1 . The distance d2 between the first p ⁺ type region 61a and the p ⁺ type region 91 that are adjacent to each other may be, for example, about 1.5 μm. The depth d1 and impurity concentration of the first p ⁺ type region 61a and the p ⁺ type region 91 may be, for example, about 0.5 μm and about 5.0×10 ¹⁸ /cm ³ , respectively. Then, the ion implantation mask (not shown) used to form the first p ⁺ type region 61a and the p ⁺ type region 91 is removed.

Next, an n-type region 92 is formed in the surface region of the n ^- type silicon carbide layer 71 over the entire main effective region 1a in each semiconductor substrate 10 by photolithography and ion implantation of an n-type impurity such as nitrogen. do. The n-type region 92 is formed, for example, between the first p ⁺ -type region 61a and the p ⁺ -type region 91 and in contact with these regions. The depth d3 and impurity concentration of the n-type region 92 may be, for example, about 0.4 μm and about 1.0×10 ¹⁷ /cm ³ , respectively.

This n-type region 92 is part of the n-type current diffusion region 33a. A portion of n ^- type silicon carbide layer 71 sandwiched between n type region 92, first p ⁺ type region 61a and p ⁺ type region 91, and n ⁺ type starting substrate 31 becomes n ^- type drift region 32. . Then, the ion implantation mask (not shown) used to form the n-type region 92 is removed. The formation order of n-type region 92, first p ⁺ -type region 61a and p ⁺ -type region 91 may be changed.

Next, as shown in FIG. 8, an n ^- type silicon carbide layer doped with an n type impurity such as nitrogen is epitaxially grown on the n ^- type silicon carbide layer 71 to a thickness t2 of, for example, 0.5 μm. The thickness of n ^- type silicon carbide layer 71 is increased. The impurity concentration of thickened portion 71a of n ^- type silicon carbide layer 71 is such that the impurity concentration of thickened portion 71a of n ^- type silicon carbide layer 71 is sandwiched between thickened portion 71a of n - type silicon carbide layer 71 and n ⁺ type starting substrate 31. It may be the same as the impurity concentration of the part.

Next, by photolithography and ion implantation of p-type impurities such as Al, a thickened portion 71a of n ^- type silicon carbide layer 71 is placed in a portion facing p ⁺ type region 91 in the depth direction Z. A p ⁺ -type region 93 is selectively formed to a depth that reaches the p ⁺ -type region 91 . The p ⁺ type regions 91 and 93 are connected in the depth direction to form a second p ⁺ type region 62a. The width and impurity concentration of p ⁺ type region 93 are, for example, approximately the same as those of p ⁺ type region 91. Then, the ion implantation mask (not shown) used to form p ⁺ type region 93 is removed.

Next, by photolithography and ion implantation of n-type impurities such as nitrogen, a thickened portion 71a of n ^- type silicon carbide layer 71 is formed between adjacent p ⁺ type regions 93 in main effective region 1a. , an n-type region 94 is formed to a depth that reaches the n-type region 92. The impurity concentration of n-type region 94 is, for example, approximately the same as that of n-type region 92. The n-type regions 92 and 94 are connected in the depth direction to form the n-type current diffusion region 33a. The order in which the p ⁺ type region 93 and the n type region 94 are formed may be reversed. Then, the ion implantation mask (not shown) used to form the n-type region 94 is removed.

Next, as shown in FIG. 9, a p-type silicon carbide layer 72 doped with a p-type impurity such as Al is epitaxially grown on the n ^- type silicon carbide layer 71. The thickness t3 and impurity concentration of p-type silicon carbide layer 72 may be, for example, about 1.3 μm and about 4.0×10 ¹⁷ /cm ³ , respectively. Thereby, a semiconductor substrate (semiconductor wafer) 10 is formed in which an n ^- type silicon carbide layer 71 and a p type silicon carbide layer 72 are sequentially laminated on an n ⁺ type starting substrate 31 by epitaxial growth.

Next, by photolithography and ion implantation of an n-type impurity such as phosphorus (P), an n ⁺ -type source region 35a is formed in the surface region of the p-type silicon carbide layer 72 in the main effective region 1a of each semiconductor substrate 10. Form selectively. Then, the ion implantation mask used to form the n ⁺ type source region 35a is removed.

Next, by photolithography and ion implantation of p-type impurities such as Al, a p ^++- type contact region 36a is selectively formed in the surface region of the p-type silicon carbide layer 72 in the main effective region 1a of each semiconductor substrate 10. Form. Then, the ion implantation mask used to form the p ⁺⁺ type contact region 36a is removed.

Next, by photolithography and ion implantation of n-type ^{impurities such as phosphorus, n- type} regions 32a, 32b ( (see Figures 2 to 4). The n ^- type region 32a separates a portion of the main invalid region 1b other than the gate pad portion 14 from the main effective region 1a. The n ⁻ type region 32b separates the gate pad portion 14 from a portion of the main invalid region 1b other than the gate pad portion 14. Then, the ion implantation mask used to form the n ^- type regions 32a and 32b is removed.

The order of forming the n ⁺ type source region 35a, the p ^{+ +} type contact region 36a, and the n ⁻ type region 32a may be changed. In main effective region 1a, a portion sandwiched between n ⁺ type source region 35a, p ^{+ +} type contact region 36a, and n ^- type silicon carbide layer 71 becomes p type base region 34a. In each of the ion implantations described above, for example, a resist film or an oxide film may be used as an ion implantation mask.

Next, all the diffusion regions formed by ion implantation (first and second p ⁺ type regions 61a, 62a, n type current diffusion region 33a, n ⁺ type source region 35a, p ⁺ type contact region 36a and n ^- type region Regarding 32a), a heat treatment (activation annealing) is performed at a temperature of, for example, about 1700° C. for about 2 minutes to activate the impurities. Activation annealing may be performed once after all diffusion regions are formed, or may be performed each time a diffusion region is formed by ion implantation.

Next, as shown in FIG. 10, by photolithography and, for example, dry etching, the first p ⁺ type region 61a inside the n type current diffusion region 33a is penetrated through the n + type source region 35a and the p ^type base region 34a. A trench 37a is formed that reaches this point. For example, a resist film or an oxide film may be used as an etching mask for forming the trench 37a.

Next, as shown in FIG. 11, a gate insulating film 38a is formed along the surface of the semiconductor substrate 10 and the inner wall of the trench 37a. The gate insulating film 38a may be formed, for example, by thermal oxidation at a temperature of about 1000° C. in an oxygen (O ₂ ) atmosphere. Furthermore, the gate insulating film 38a may be a film deposited by a chemical reaction of high temperature oxide (HTO).

Next, a phosphorus-doped polysilicon layer, for example, is deposited and patterned on the gate insulating film 38a so as to fill the trench 37a, leaving a portion that will become the gate electrode 39a only inside the trench 37a. At this time, the portion of the polysilicon layer that will become the gate electrode 39a may be left so as to protrude outward from the front surface of the semiconductor substrate 10, or may be left so as to be lower than the front surface of the semiconductor substrate 10. You can leave it there.

All the elements other than the main semiconductor element 11 (for example, the current sensing section 12, the overvoltage protection section, such as a diffusion diode, and the CMOS (Complementary MOS) forming the arithmetic circuit section) are connected to the main semiconductor element 11 described above. In the formation of each part, each part is formed in the main invalid region 1b of the semiconductor substrate 10 at the same time as the corresponding part of the main semiconductor element 11.

For example, the diffusion regions of each element arranged on the semiconductor substrate 10 may be formed simultaneously with the diffusion regions of the same conductivity type, impurity concentration, and diffusion depth among the diffusion regions constituting the main semiconductor element 11. Furthermore, the gate trench, gate insulating film, and gate electrode of the element disposed on the semiconductor substrate 10 may be formed simultaneously with the trench 37a, gate insulating film 38a, and gate electrode 39a of the main semiconductor element 11, respectively.

Next, a field insulating film 80c is formed on the front surface of the semiconductor substrate 10. At this time, a field insulating film 80e is also formed on the front surface of the semiconductor substrate 10 in the gate pad portion 14. Next, a phosphorus-doped polysilicon layer, for example, which will become the n-type polysilicon layer 82 is deposited on the field insulating film 80c, and a part of the polysilicon layer is made into a p-type region to form the p-type polysilicon layer 81. Next, the polysilicon layer is patterned to leave only the portions that will become the p-type polysilicon layer 81 and the n-type polysilicon layer 82.

In the polysilicon layer deposited to form the p-type polysilicon layer 81 and the n-type polysilicon layer 82, a gate runner (not shown) is formed at the same time as the p-type polysilicon layer 81 and the n-type polysilicon layer 82 are formed. may be formed. In this case, a field insulating film (not shown) is also formed on the front surface of the semiconductor substrate 10 in the edge termination region 2. Then, a portion of the polysilicon layer that will become a gate runner may be left in the edge termination region 2.

Next, interlayer insulating films 40 and 83 are formed over the entire front surface of semiconductor substrate 10. The interlayer insulating films 40 and 83 may be made of, for example, PSG (Phospho Silicate Glass). The thickness of the interlayer insulating films 40 and 83 may be, for example, about 1 μm. Next, the interlayer insulating film 40 and the gate insulating films 38a, 38b are selectively removed by photolithography and etching to form first and second contact holes 40a, 40b.

At this time, a first contact hole 40a is formed to expose the n ⁺ type source region 35a and the p ^{+ +} type contact region 36a of the main semiconductor element 11. A second contact hole 40b is formed in the sense effective region 12a to expose the n ⁺ type source region 35b and the p ^{+ +} type contact region 36b of the current sensing section 12. No contact hole is formed in the first sense invalid region 12b. Next, the interlayer insulating films 40 and 83 are planarized (reflowed) by heat treatment.

Next, first TiN films 42a, 42b, and 42e are formed on the entire front surface of the semiconductor substrate 10, for example, by sputtering. The first TiN films 42a, 42b, 42e cover the entire surfaces of the interlayer insulating films 40, 83, and the portions (n ⁺ type source regions 35a, 35b and p ⁺⁺ type contact regions 36a, 36b).

Next, by photolithography and etching, the portions of the first TiN films 42a, 42b, 42e that cover the semiconductor substrate 10 inside the first and second contact holes 40a, 40b are removed, and the n ⁺ type source regions 35a, 35b are removed. Then, the p ⁺⁺ type contact regions 36a and 36b are exposed again. This leaves the first TiN films 42a, 42b, 42e as barrier metals 46a, 46b, 46e on the entire surface of the interlayer insulating films 40, 83.

Next, by sputtering, for example, a Ni film (not shown) is formed on the semiconductor portion (front surface of the semiconductor substrate 10) exposed to the first and second contact holes 40a and 40b. At this time, a Ni film is also formed on the first TiN films 42a, 42b, and 42e. Next, by heat treatment at, for example, about 970° C., the contact portions of the Ni film with the semiconductor portion are silicided to form NiSi films 41a and 41b in ohmic contact with the semiconductor portion.

During the heat treatment for silicidation of nickel, the first TiN films 42a, 42b are placed between the interlayer insulating films 40, 83 and the Ni film, so that the interlayer insulating film 40, 42b of the nickel atoms in the Ni film, Diffusion into the 83 can be prevented. The portions of the Ni film on the interlayer insulating films 40 and 83 are not in contact with the semiconductor portion and are therefore not silicided. Thereafter, the portion of the Ni film on the interlayer insulating films 40, 83 is removed to expose the interlayer insulating films 40, 83.

Next, for example, a Ni film is formed on the back surface of the semiconductor substrate 10. Next, the Ni film is silicided by heat treatment at, for example, about 970° C., and a NiSi film is formed as the drain electrode 51 in ohmic contact with the semiconductor portion (back surface of the semiconductor substrate 10). The heat treatment for silicidation when forming the NiSi film that will become the drain electrode 51 may be performed simultaneously with the heat treatment for forming the NiSi films 41a and 41b on the front surface of the semiconductor substrate 10.

Next, by sputtering, first Ti films 43a, 43b, 43e, second TiN films 44a, 44b, 44e, and second Ti films 45a, 45b, which will become barrier metals 46a, 46b, 46e, are formed on the front surface of the semiconductor substrate 10. , 45e, and an Al film (or Al alloy film) that will become the source pad 21a, gate pad 21b, and OC pad 22 are laminated in this order. The thickness of the Al film is, for example, approximately 5 μm or less.

Next, the metal film deposited on the front surface of the semiconductor substrate 10 is patterned by photolithography and etching to form portions that will become the barrier metals 46a, 46b, 46c, the source pad 21a, the gate pad 21b, and the OC pad 22. leave. At this time, the metal film deposited on the front surface of the semiconductor substrate 10 may be used to form an OV pad (not shown) of the overvoltage protection section or an electrode pad of the arithmetic circuit section.

The formation of the metal film on the front surface of the semiconductor substrate 10 is performed with the entire p-type polysilicon layer 81 and n-type polysilicon layer 82 of the temperature sensing section 13 covered with an interlayer insulating film 83. Next, the interlayer insulating film 83 is selectively removed by photolithography and etching to form third and fourth contact holes 83a and 83b. The n-type polysilicon layer 82 is exposed.

Next, the interlayer insulating film 83 is planarized by heat treatment. Next, by forming and patterning an Al film (or Al alloy film) on the front surface of the semiconductor substrate 10 so as to fill the third and fourth contact holes 83a and 83b, an anode of the temperature sensing section 13 is formed. Pad 23a and cathode pad 23b are formed.

Anode pad 23a and cathode pad 23b may be formed simultaneously with source pad 21a. In this case, after the barrier metals 46a, 46b, 46e are formed and before the Al film that becomes the electrode pad is formed, third and fourth contact holes 83a, 83b are formed to form the p-type polysilicon layer 81 and the n-type polysilicon layer 81. A portion of layer 82 may be exposed.

Next, by sputtering, for example, a Ti film, a Ni film, and a gold (Au) film are sequentially stacked on the surface of the drain electrode 51 to form a drain pad (not shown).

Next, the front surface of the semiconductor substrate 10 is protected with a polyimide film by, for example, CVD. Next, the polyimide film is selectively removed by photolithography and etching to form first protective films 49a to 49c and 49e that respectively cover the electrode pads, and these first protective films 49a to 49c and 49e are opened. do.

Next, after general plating pre-treatment, the parts of the electrode pads 21a, 22, 23a, 23b, 21b exposed to the openings of the first protective films 49a to 49c, 49e are plated by a general plating process. Films 47a to 47e are formed. At this time, the first protective films 49a to 49c and 49e function as a mask to suppress wetting and spreading of the plating films 47a to 47e. The thickness of the plating films 47a to 47e may be, for example, about 5 μm.

Next, for example, by CVD, a polyimide film is formed to become the second protective films 50a to 50c and 50e, covering each boundary between the plating films 47a to 47e and the first protective films 49a to 49c and 49e. Next, terminal pins 48a to 48e are bonded onto the plating films 47a to 47e using solder layers (not shown), respectively. At this time, the second protective films 50a to 50c, 50e function as a mask to suppress wetting and spreading of the solder layer.

Thereafter, the semiconductor substrate 10 is diced (cut) into individual chips, thereby completing the semiconductor device 20 shown in FIGS. 1 to 4.

As described above, according to the first embodiment, the unit cells of the current sensing section are arranged directly under the OC pad of the main invalid area to a wider range than the sense valid area, and only the unit cells of the sense valid area are disposed. is configured to operate as a current sensing section. The surface area of the p-type region that forms a parasitic diode in the main invalid region can be reduced by unit cells placed in a region other than the sense valid region (first sense invalid region) in the main invalid region, so that the parasitic The surface area of the diode can be reduced. Therefore, the reverse recovery withstand capability of the parasitic diode in the main ineffective region can be improved while maintaining the same current capability of the current sensing section as the conventional structure without changing the surface area of the sense effective region.

Furthermore, according to the first embodiment, since the unit cells in the first sense invalid area have the same configuration as the resistance cells in the sense valid area, the unit cells in the first sense invalid area are formed at the same time as the unit cells in the sense valid area. It is possible to simplify the process. Further, according to the first embodiment, since the unit cells in the first sense invalid region have the same configuration as the resistance cells in the sense valid region, the current capacity of the current sensing section can be increased by simply changing the surface area of the sense valid region. It can be changed and has a high degree of freedom in design. At this time, the surface area of the sense effective region can be changed simply by changing the pattern of the etching mask for forming the second contact hole in the interlayer insulating film, where the contact between the OC pad and the semiconductor part is formed. Easy to change.

(Embodiment 2)
Next, a semiconductor device according to a second embodiment will be explained. FIG. 12 is a plan view showing the layout of the semiconductor device according to the second embodiment when viewed from the front side of the semiconductor substrate. The difference between the semiconductor device 20' according to the second embodiment and the semiconductor device 20 according to the first embodiment (see FIGS. 1 to 4) is that the first sense invalid region 12b' is replaced with the OC pad 22 of the main invalid region 1b. This point extends directly below the other electrode pads.

The first sense invalid region 12b' faces the OC pad 22 in the depth direction Z, and also includes, for example, a gate pad 21b, an anode pad 23a, a cathode pad 23b, an OV pad (not shown), and an electrode of an arithmetic circuit section. It faces one or more electrode pads of pads (not shown). FIG. 12 shows a case where the first sense invalid region 12b' faces all the electrode pads arranged in the main invalid region 1b in the depth direction Z.

That is, in the second embodiment, even if the predetermined voltage of the current sensing section 12 is applied directly under the gate pad 21b, the anode pad 23a, the cathode pad 23b, the OV pad, and the electrode pad of the arithmetic circuit section, A non-functional unit cell (not shown) is arranged. Thereby, the ESD resistance of the current sensing section 12 can be further increased.

The cross-sectional structure along the cutting line X1-X2-X3-X4 in FIG. 12 is the same as that in Embodiment 1 (see FIG. 2). The cross-sectional structure along the cutting line X1'-X2'-X3'-Y1-Y2, the cutting line X1'-X2'-X3', and the cutting line Y2-Y3 in FIG. 34c and the p-type region 34e of the gate pad section 14 in FIG. 4, MOS gates are arranged similarly to the first sense invalid region 12b.

The first sense invalid region 12b' may be provided apart from the p-type base region 34a of the main semiconductor element 11 in the entire portion of the main invalid region 1b excluding the sense valid region 12a.

As described above, according to the second embodiment, the range in which the first sense invalid area is arranged in the main invalid area is not limited to just below the OC pad, but also to other electrode pads placed in the main invalid area. By expanding it to just below the , it is possible to further obtain the same effect as in the first embodiment.

(Example)
Next, the ESD resistance of the semiconductor devices 20 and 20' according to the first and second embodiments (hereinafter referred to as Examples 1 and 2; see FIGS. 1 and 12) was examined. FIG. 13 is a characteristic diagram showing the ESD tolerance of Examples 1 and 2. FIG. 14 is a characteristic diagram showing the reverse recovery tolerance of Examples 1 and 2. Semiconductor devices 20, 20' according to the first and second embodiments described above (hereinafter referred to as Examples 1 and 2; see FIGS. 1 and 12) and a conventional semiconductor device 120 (hereinafter referred to as a conventional example: FIG. 15) FIG. 13 shows the results of comparing the ESD withstand capacity of the two types, and FIG. 14 shows the results of comparing the reverse recovery withstand capacity of the parasitic diode.

As shown in FIG. 13, it was confirmed that Examples 1 and 2 can have higher ESD resistance than the conventional example. Moreover, as shown in FIG. 14, it was confirmed that Examples 1 and 2 can increase the reverse recovery withstand capability of the parasitic diode compared to the conventional example. In Examples 1 and 2, the unit cells of the current sensing section 12 are arranged in the first sense invalid region 12b, so that the p-type region forming a parasitic diode in the main invalid region 1b is reduced compared to the conventional example. This is because the surface area is small and the surface area of the parasitic diode can be reduced.

Furthermore, it was confirmed that Example 2 could have a higher ESD tolerance than Example 1. It was confirmed that in Example 2, the reverse recovery withstand capability of the parasitic diode can be increased compared to Example 1. In Example 2, compared to Example 1, the surface area of the first sense invalid region 12b arranged in the main invalid region 1b is larger, so that the surface area of the p-type region forming a parasitic diode in the main invalid region 1b is increased. This is because the surface area of the parasitic diode can be reduced.

On the other hand, as described above, the ESD resistance of Example 1 is smaller than that of Example 2, but since the range in which the trench 37b is arranged in the main invalid region 1b is narrower than that of Example 2, the formation of the trench 37b is defective. The negative effect of Therefore, it is preferable to determine the surface area of the first sense invalid region 12b in consideration of the trade-off relationship between suppressing formation defects of the trench 37b and improving ESD resistance or reverse recovery resistance of the parasitic diode.

As described above, the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of the present invention. For example, a planar gate structure may be provided instead of a trench gate structure. Furthermore, the present invention is also applicable to the case where a wide bandgap semiconductor other than silicon carbide is used as the semiconductor material instead of using silicon carbide as the semiconductor material. Furthermore, the present invention is equally applicable even when the conductivity type (n type, p type) is reversed.

INDUSTRIAL APPLICABILITY As described above, the semiconductor device according to the present invention is useful as a power semiconductor device used in a power conversion device, a power supply device of various industrial machines, and the like.

1 Active area 1a Effective area of active area (main effective area)
1b Invalid area of active area (main invalid area)
2 Edge Termination Region 10 Semiconductor Substrate 11 Main Semiconductor Element 12 Current Sense Section 12a Area in the main ineffective area where unit cells functioning as a current sense area are arranged (sense effective area)
12b, 12b' Area where dummy unit cells of the current sensing section are arranged in the main invalid area (first sense invalid area)
12c Area in the main invalid area where unit cells of the current sense section are not arranged (second sense invalid area)
13 Temperature sensing section 14 Gate pad section 15 Resistor 20, 20' Semiconductor device 21a Source pad (electrode pad)
21b Gate pad (electrode pad)
22 OC pad (electrode pad)
23a Anode pad (electrode pad)
23b Cathode pad (electrode pad)
31 n ⁺ type starting substrate 32 n ^- type drift region 32a, 32b n ^- type region 33a, 33b n type current diffusion region 34a, 34b p type base region 34c, 34e p type region 35a, 35b n ⁺ type source region 36a, 36b, 36c, 36e p ⁺⁺ type contact region 37a, 37b trench 38a, 38b gate insulating film 39a, 39b gate electrode 40, 83 interlayer insulating film 40a, 40b, 83a, 83b contact hole 41a, 41b NiSi film 42a, 42b, 42e First TiN film 43a, 43b, 43e First Ti film 44a, 44b, 44e Second TiN film 45a, 45b, 45e Second Ti film 46a, 46b, 46c, 46e Barrier metal 47a-47e Plating film 48a-48e Terminal pin 49a-49c , 49e first protective film 50a to 50c, 50e second protective film 51 drain electrode 61a, 61b, 62a to 62c, 62e, 91, 93 p ⁺ type region 71 n ^- type silicon carbide layer 71a n ^- type silicon carbide layer Part with increased thickness 72 P-type silicon carbide layer 80c, 80e Field insulating film 81 P-type polysilicon layer 82 N-type polysilicon layer 92, 94 N-type region GND Grounding point X Parallel to the front surface of the semiconductor chip Direction (first direction)
Y Direction parallel to the front surface of the semiconductor chip and orthogonal to the first direction (second direction)
Z Depth direction d1 Depth of p ⁺ type region d2 Distance between p ⁺ type regions d3 Depth of n type region t1 Thickness of n ^- type silicon carbide layer initially laminated on n ⁺ type starting substrate t2 Thickness of the thickened part of the n ^- type silicon carbide layer t3 Thickness of the p-type silicon carbide layer

Claims (16)

A semiconductor substrate made of a semiconductor with a wider bandgap than silicon,
a first conductivity type region provided inside the semiconductor substrate;
a first second conductivity type region provided between the first main surface of the semiconductor substrate and the first conductivity type region;
a first insulated gate field effect transistor in which the first conductivity type region is a drift region and the first second conductivity type region is a base region;
a first source pad of the first insulated gate field effect transistor provided on the first main surface of the semiconductor substrate and electrically connected to the first second conductivity type region;
a second second conductivity type region provided in a region between the first main surface of the semiconductor substrate and the first conductivity type region and different from the first second conductivity type region;
The first conductivity type region is a drift region, the second second conductivity type region is a base region, and a plurality of cells having the same cell structure as the first insulated gate field effect transistor are connected to the first insulated gate field effect transistor. a second insulated gate field effect transistor having a smaller number than the field effect transistor;
A second insulated gate field effect transistor of the second insulated gate field effect transistor provided on the first main surface of the semiconductor substrate away from the first source pad and electrically connected to the second second conductivity type region. source pad and
a drain electrode common to the first insulated gate field effect transistor and the second insulated gate field effect transistor, electrically connected to a second main surface of the semiconductor substrate;
Equipped with
The second insulated gate field effect transistor includes:
a first cell that operates as the second insulated gate field effect transistor when a predetermined voltage is applied;
a second cell that does not operate even if the predetermined voltage is applied ;
One or more pads provided on the first main surface of the semiconductor substrate, separated from the first source pad and the second source pad, and facing the semiconductor substrate in a direction perpendicular to the first main surface of the semiconductor substrate. further equipped with electrode pads,
The ineffective region where the second cell is provided extends from a region facing the second source pad in a direction perpendicular to the first main surface of the semiconductor substrate to a direction perpendicular to the first main surface of the semiconductor substrate. A semiconductor device characterized in that the semiconductor device extends to a region facing at least one of the electrode pads . A semiconductor substrate made of a semiconductor with a wider bandgap than silicon,
a first conductivity type region provided inside the semiconductor substrate;
a first second conductivity type region provided between the first main surface of the semiconductor substrate and the first conductivity type region;
a first insulated gate field effect transistor in which the first conductivity type region is a drift region and the first second conductivity type region is a base region;
a first source pad of the first insulated gate field effect transistor provided on the first main surface of the semiconductor substrate and electrically connected to the first second conductivity type region;
a second second conductivity type region provided in a region between the first main surface of the semiconductor substrate and the first conductivity type region and different from the first second conductivity type region;
The first conductivity type region is a drift region, the second second conductivity type region is a base region, and a plurality of cells having the same cell structure as the first insulated gate field effect transistor are connected to the first insulated gate field effect transistor. a second insulated gate field effect transistor having a smaller number than the field effect transistor;
A second insulated gate field effect transistor of the second insulated gate field effect transistor provided on the first main surface of the semiconductor substrate away from the first source pad and electrically connected to the second second conductivity type region. source pad and
a drain electrode common to the first insulated gate field effect transistor and the second insulated gate field effect transistor, electrically connected to a second main surface of the semiconductor substrate;
Equipped with
The second insulated gate field effect transistor includes:
a first cell that operates as the second insulated gate field effect transistor when a predetermined voltage is applied;
a second cell that does not operate even if the predetermined voltage is applied;
A semiconductor device, wherein the second cell is provided with a source region, and the source region is electrically insulated from the second source pad. A semiconductor substrate made of a semiconductor with a wider bandgap than silicon,
a first conductivity type region provided inside the semiconductor substrate;
a first second conductivity type region provided between the first main surface of the semiconductor substrate and the first conductivity type region;
a first insulated gate field effect transistor in which the first conductivity type region is a drift region and the first second conductivity type region is a base region;
a first source pad of the first insulated gate field effect transistor provided on the first main surface of the semiconductor substrate and electrically connected to the first second conductivity type region;
a second second conductivity type region provided in a region between the first main surface of the semiconductor substrate and the first conductivity type region and different from the first second conductivity type region;
The first conductivity type region is a drift region, the second second conductivity type region is a base region, and a plurality of cells having the same cell structure as the first insulated gate field effect transistor are connected to the first insulated gate field effect transistor. a second insulated gate field effect transistor having a smaller number than the field effect transistor;
A second insulated gate field effect transistor of the second insulated gate field effect transistor provided on the first main surface of the semiconductor substrate away from the first source pad and electrically connected to the second second conductivity type region. source pad and
a drain electrode common to the first insulated gate field effect transistor and the second insulated gate field effect transistor, electrically connected to a second main surface of the semiconductor substrate;
Equipped with
The second insulated gate field effect transistor includes:
a first cell that operates as the second insulated gate field effect transistor when a predetermined voltage is applied;
a second cell to which the predetermined voltage is not applied;
A semiconductor device, wherein the second second conductivity type region of the second cell is electrically insulated from the second source pad. 4. The semiconductor device according to claim 3, wherein the surface area of the ineffective region where the second cell is provided is larger than the surface area of the second effective region where the first cell is provided. One or more pads provided on the first main surface of the semiconductor substrate, separated from the first source pad and the second source pad, and facing the semiconductor substrate in a direction perpendicular to the first main surface of the semiconductor substrate. further equipped with electrode pads,
The ineffective region where the second cell is provided extends from a region facing the second source pad in a direction perpendicular to the first main surface of the semiconductor substrate to a direction perpendicular to the first main surface of the semiconductor substrate. 4. The semiconductor device according to claim 3, wherein the semiconductor device extends to a region facing at least one of the electrode pads. 6. The semiconductor device according to claim 1, wherein the electrode pad is a gate pad of the first insulated gate field effect transistor. 6. The semiconductor device according to claim 1, further comprising the electrode pad of a diode that detects the temperature of the first insulated gate field effect transistor. 6. The semiconductor device according to claim 1, further comprising the electrode pad of a diode that protects the first insulated gate field effect transistor from overvoltage. 9. The semiconductor device according to claim 1, wherein the second insulated gate field effect transistor detects an overcurrent flowing through the first insulated gate field effect transistor. 10. The semiconductor device according to claim 1, wherein the second second conductivity type region is provided apart from the first second conductivity type region. 3. The semiconductor device according to claim 1, wherein the second second conductivity type region is electrically connected to the first second conductivity type region. A surface area of the second effective region where the first cell is provided is 1/1000 or less of a surface area of the first effective region where the first insulated gate field effect transistor is provided. The semiconductor device according to any one of items 1 to 3. 13. The semiconductor device according to claim 1, wherein the second cell is adjacent to the first cell. 14. The semiconductor device according to claim 1, wherein the second cell surrounds the first cell. 4. The semiconductor device according to claim 1, wherein the second cell is provided with a source region, and the source region is electrically insulated from the second source pad. 4. The semiconductor device according to claim 1, wherein the second cell is not provided with a source region.

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