JP7324520B2 - LOGIC INTEGRATED CIRCUIT, CONFIGURATION INFORMATION SETTING METHOD, AND RECORDING MEDIUM - Google Patents

Description

The present invention relates to a reconfigurable logic integrated circuit, a configuration information setting method for setting a circuit in the logic integrated circuit, and a program.

Programmable logic integrated circuits such as FPGAs (Field Programmable Gate Arrays) (hereinafter also referred to as logic integrated circuits) are integrated circuits that can change logic operations and wiring connections by storing the operations and connections of logic operation circuits in memory elements. circuit. A general logic integrated circuit includes an input/output unit for inputting/outputting from/to the outside, a plurality of logic cells, internal wiring for connecting the input/output unit and the logic cells, and the like. Internal wiring of a logic integrated circuit includes a crossbar in which switches are arranged at intersections of a plurality of wirings, a multiplexer composed of CMOS (Complementary Metal Oxide Semiconductor), and the like. For example, Patent Literature 1 and Patent Literature 2 disclose a crossbar in which a unit element, which is a combination of two variable resistance elements whose resistance state changes according to an applied voltage, is arranged at the intersection.

When radiation enters a logic element that makes up a logic integrated circuit, a phenomenon called a single event transient (SET) occurs, in which the output voltage of the logic element transiently fluctuates due to the charge generated by the radiation. I can. When a SET occurs in a transistor included in a crossbar of a logic integrated circuit, the potential may be disturbed from the prescribed level and a digital pulse may propagate through the logic circuit. The short duration of SETs, typically less than 1 nanosecond, has so far been unlikely to lead to major problems. However, as the clock speed increases, the signal caused by SET propagates through the logic circuit, reaches the input terminal of the D flip-flop, and is likely to hold the wrong logic as the output of the D flip-flop. became. If the clock is triggered at the same time that the signal due to SET arrives at the input terminal, that signal can be latched into the D flip-flop causing a soft error.

By inserting a filter in the signal path that removes the signal due to SET, the signal can be prevented from propagating through the logic circuit. US Pat. No. 6,200,000 discloses an apparatus with a glitch filter that prevents propagation of input signal events that have changed state due to single event effects caused by radiation events. FIG. 26 shows an example in which a SET filter 513 is inserted between a lookup table (hereinafter LUT 511: Look Up Table) and a D flip-flop (hereinafter DFF 512: D Flip Flop) that constitute a logic integrated circuit. Further, if the logic circuit is made redundant, it is possible to avoid the signal caused by SET from influencing subsequent signals without using a SET filter. FIG. 27 shows an example in which the LUT group 521 has a triple redundant system and a majority circuit 525 is inserted between the LUT group 521 and the DFF 522 .

WO2012/043502 WO2013/190741 Japanese Patent Publication No. 2008-543179

With the configuration of FIG. 26 , the signal caused by SET is removed by the SET filter 513 even if it passes through the LUT 511 , so that the effect of SET can be prevented from propagating to the DFF 512 . However, in the configuration of FIG. 26, a delay corresponding to the filter time constant (approximately 1 nanosecond) of the SET filter 513 is generated. Therefore, there is a problem that it is difficult to satisfy the expected speed performance with the configuration that only inserts the SET filter 513 between the LUT 511 and the DFF 512 .

27, even if a signal caused by SET passes through one of the LUTs of the LUT group 521, the majority circuit 525 outputs a signal that is not affected by SET. Therefore, with the configuration of FIG. 27, it is possible to prevent the influence of SET from reaching subsequent signals without delaying the signal. However, if the logic circuit is made into a triple redundant system as shown in FIG. 27, the circuit scale will be tripled. Therefore, there is a problem that the area overhead increases in the configuration that only makes the logic circuit redundant.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic integrated circuit capable of reducing the effects of single event transients while satisfying both circuit scale and speed performance requirements in order to solve the above-described problems.

A logic integrated circuit according to one aspect of the present invention is supplied with a first non-redundant signal group out of a logic signal group, and generates at least two signals from a data signal group based on a combination of signals constituting the first signal group. a first logic selection circuit that selects a data signal; a filter circuit that receives at least two data signals selected by the first logic selection circuit and removes glitches included in the at least two data signals; A redundant second signal group and an output data signal group of the filter circuit are input, and at least one of the output data signal group is selected based on a combination of signals constituting the second signal group. 2 logic selection circuits.

In a configuration information setting method according to one aspect of the present invention, a non-redundant first signal group among logic signal groups is input, and at least two signal groups are selected from a data signal group based on a combination of signals constituting the first signal group. a first logic selection circuit that selects one data signal; a filter circuit that receives at least two data signals selected by the first logic selection circuit and removes glitches included in the at least two data signals; and a logic signal group. A redundant second signal group and an output data signal group of the filter circuit are input, and at least one of the output data signal group is selected based on a combination of signals constituting the second signal group. A configuration information setting method for setting configuration information in a logic integrated circuit comprising: a logic selection circuit; searching for wiring that minimizes an evaluation function including at least a delay cost; Configuration information to be assigned to the second signal line group through which the second signal group is propagated is generated, and a circuit configuration based on the generated configuration information is set in the logic integrated circuit.

A program of the present invention receives a first non-redundant signal group among logic signal groups, and selects at least two data signals from the data signal group based on a combination of signals constituting the first signal group. a first logic selection circuit, a filter circuit receiving at least two data signals selected by the first logic selection circuit and removing glitches included in the at least two data signals; a second logic selection circuit to which the second signal group and the output data signal group of the filter circuit are input, and which selects at least one of the output data signal group based on the combination of the signals forming the second signal group; A program for setting configuration information in a logic integrated circuit, comprising: searching for wiring that minimizes an evaluation function including at least a delay cost; and a process of setting a circuit configuration to the logic integrated circuit based on the generated configuration information.

According to the present invention, it is possible to provide a logic integrated circuit capable of reducing the effects of single event transients while satisfying both circuit scale and speed performance requirements.

1 is a block diagram showing an example of the configuration of a logic integrated circuit according to a first embodiment of the present invention; FIG. 1 is a block diagram showing an example of the configuration of a crossbar circuit included in a logic integrated circuit according to the first embodiment of the present invention; FIG. FIG. 4 is a conceptual diagram for explaining resistance states of variable resistance elements included in switch cells of the crossbar circuit provided in the logic integrated circuit according to the first embodiment of the present invention; FIG. 4 is a conceptual diagram for explaining another resistance state of the variable resistance element included in the switch cell of the crossbar circuit included in the logic integrated circuit according to the first embodiment of the present invention; 3 is a block diagram showing an example of the configuration of an LUT provided in the logic integrated circuit according to the first embodiment of the present invention; FIG. 3 is a block diagram showing an example of the configuration of a first logic selection circuit included in the LUT included in the logic integrated circuit according to the first embodiment of the present invention; FIG. 3 is a block diagram showing an example of the configuration of a filter circuit included in the LUT included in the logic integrated circuit according to the first embodiment of the present invention; FIG. 1 is a block diagram showing an example of a circuit configuration for implementing a filter circuit included in an LUT included in a logic integrated circuit according to the first embodiment of the present invention; FIG. 4 is a block diagram showing an example of the configuration of a second logic selection circuit included in the LUT included in the logic integrated circuit according to the first embodiment of the present invention; FIG. 1 is a block diagram showing an example of a circuit configuration for realizing an LUT included in the logic integrated circuit according to the first embodiment of the present invention; FIG. 3 is a block diagram showing another example of a circuit configuration for realizing an LUT included in the logic integrated circuit according to the first embodiment of the present invention; FIG. FIG. 4 is a block diagram showing an example of the configuration of a logic integrated circuit according to a second embodiment of the present invention; FIG. FIG. 11 is a block diagram showing an example of the configuration of an LUT included in the logic integrated circuit according to the second embodiment of the present invention; FIG. FIG. 11 is a block diagram showing an example of a circuit configuration for implementing a majority circuit included in the LUT provided in the logic integrated circuit according to the second embodiment of the present invention; FIG. 10 is a block diagram showing an example of the configuration of a second logic selection circuit included in the LUT included in the logic integrated circuit according to the second embodiment of the present invention; FIG. 11 is a block diagram showing an example of a circuit configuration for implementing an LUT included in the logic integrated circuit according to the second embodiment of the present invention; FIG. FIG. 11 is a block diagram showing an example of the configuration of a logic integrated circuit according to a third embodiment of the present invention; FIG. FIG. 12 is a block diagram showing an example of the configuration of an LUT included in the logic integrated circuit according to the third embodiment of the present invention; FIG. FIG. 12 is a block diagram showing an example of the configuration of a second logic selection circuit included in the LUT provided in the logic integrated circuit according to the third embodiment of the present invention; FIG. 12 is a block diagram showing another example of a circuit configuration for implementing an LUT included in the logic integrated circuit according to the third embodiment of the present invention; It is a block diagram which shows an example of a structure of the design support system based on the 4th Embodiment of this invention. FIG. 14 is a block diagram showing an example of a design support tool group used by the design support system according to the fourth embodiment of the present invention; It is a flow chart which shows an example of operation of a design support system concerning a 4th embodiment of the present invention. FIG. 14 is a flow chart showing an example of placement and routing processing by a placement and routing tool of the design support system according to the fourth embodiment of the present invention; FIG. It is a block diagram showing an example of hardware constitutions which realize a design support system concerning a 4th embodiment of the present invention. FIG. 11 is a block diagram showing an example of the configuration of a logic integrated circuit in which SET countermeasures are taken; FIG. 12 is a block diagram showing another example of the configuration of the logic integrated circuit with SET countermeasures;

EMBODIMENT OF THE INVENTION Below, embodiment for implementing this invention is described using drawing. However, the embodiments described below are technically preferable for carrying out the present invention, but the scope of the invention is not limited to the following. In addition, in all drawings used for the following description of the embodiments, the same symbols are attached to the same parts unless there is a particular reason. Further, in the following embodiments, repeated descriptions of similar configurations and operations may be omitted. Also, the directions of arrows in the drawings are only examples, and do not limit the directions of signals between blocks.

(First embodiment)
First, a logic integrated circuit according to a first embodiment of the present invention will be described with reference to the drawings. The logic integrated circuit of this embodiment is a programmable logic integrated circuit that can change the logic operation and wiring connection by storing the operation and connection of the logic operation circuit in a memory element. In this embodiment, an example will be described in which the output of the crossbar is connected to a DFF (D-type Flip Flop), which is a storage device, via a LUT (Look Up Table). In practice, multiple crossbars, LUTs, and DFFs are combined to form a larger logic integrated circuit. Note that a configuration using a multiplexer may be used instead of the crossbar. Alternatively, a configuration in which a plurality of crossbars are connected in multiple stages may be used.

FIG. 1 is a conceptual diagram for explaining an overview of the configuration of a logic integrated circuit 1 of this embodiment. As shown in FIG. 1, the logic integrated circuit 1 includes a crossbar circuit 11, an LUT 12, and a DFF 13. The crossbar circuit 11 includes a first signal line group 101 for propagating a non-redundant signal group (hereinafter also referred to as a first signal group) and a redundant signal group (hereinafter also referred to as a second signal group). It is connected to the LUT 12 via the second signal line group 102 for propagation. The first signal group consists of non-redundant signals S1 to S3. The second signal group consists of redundant signals S4 to S5.

The LUT 12 and DFF 13 constitute a logic block 100. FIG. Although FIG. 1 shows an example in which the logic block 100 is composed of one set of LUT12 and DFF13, the logic block 100 may be composed of multiple sets of LUT12 and DFF13. FIG. 1 shows an example in which the logic integrated circuit 1 is composed of a set of crossbar circuits 11, LUTs 12, and DFFs 13, but a plurality of logic blocks 100 are connected by the crossbar circuit 11 to form logic integration. Circuit 1 may be configured.

The crossbar circuit 11 has a configuration in which switch cells are arranged at positions where a plurality of first wirings extending in a first direction and a plurality of second wirings extending in a second direction intersecting the first direction intersect. A switch cell is a circuit for switching the connection between the first wiring and the second wiring. For example, a switch cell is realized by an SRAM (Static Random Access Memory) cell and one transistor having a switch function. Also, the switch cell may be realized by a configuration including a variable resistance element that can be switched on and off depending on the resistance state. The crossbar circuit 11 connects adjacent logic blocks.

The crossbar circuit 11 is connected to a wiring group (not shown) for propagating a logic signal group from the preceding logic block. A LUT 12 is connected to the rear stage of the crossbar circuit 11 . The crossbar circuit 11 includes a first signal line group 101 that propagates a first non-redundant signal group (signals S1 to S3) and a second signal line group 101 that propagates a redundant second signal group (signals S4 to S5). It is connected to the LUT 12 via the signal line group 102 . Each wiring constituting the first signal line group 101 and the second signal line group 102 is obtained by extending one of the plurality of second wirings.

The LUT 12 has an input side connected to the crossbar circuit 11 via the first signal line group 101 and a second signal line group 102 and an output side connected to the DFF 13 . A signal group (signals S1 to S5) from the crossbar circuit 11 is input to the LUT 12 via the first signal line group 101 and the second signal line group 102 . The LUT 12 selects at least a data group (also called a data signal group) stored in an internal storage element (not shown) according to a combination of a plurality of signals input to an input circuit (not shown) that decodes an address. One signal is selected and output to DFF13. For example, the LUT 12 receives a plurality of signals such as 4-input 1-output or 6-input 1-output, and outputs a single signal. The internal configuration of the LUT 12 will be described later.

DFF13 is connected to the output of LUT12. Data output from the LUT 12 is stored in the DFF 13 . The data stored in DFF 13 is output to subsequent logic blocks.

The outline of the configuration of the logic integrated circuit 1 has been described above. Next, individual elements constituting the logic integrated circuit 1 will be described with reference to the drawings.

[Crossbar circuit]
FIG. 2 is a circuit diagram showing an example of the configuration of the crossbar circuit 11. As shown in FIG. As shown in FIG. 2, the crossbar circuit 11 arranges switch cells 113 at positions where a plurality of first wirings 111 extending in the first direction and a plurality of second wirings 112 extending in the second direction intersect. It has a configuration that In FIG. 2, the switch cells 113 in the ON state are blacked out, and the switch cells 113 in the OFF state are outlined. Note that the ON state and OFF state of the switch cells 113 shown in FIG. 2 are only examples, and the states of the plurality of switch cells 113 can be set arbitrarily. Also, in FIG. 2, the configuration of programming drivers, control lines, and the like, which configure the crossbar circuit 11, is omitted.

The input of the first wiring 111 is connected to the output of the preceding logic block 100-1. The first wiring 111 is connected to the second wiring 112 via the switch cell 113 . A logic signal group output from the logic block 100-1 in the previous stage is input to the first wiring 111. FIG. A signal input to the first wiring 111 is transferred to the second wiring 112 via the switch cell 113 in the ON state.

The second wiring 112 is connected to the first wiring 111 via the switch cell 113 . The outputs of the second wiring 112 are the first signal line group 101 through which the non-redundant first signal group (signals S1 to S3) propagates, and the redundant second signal group (signals S4 to S5). and the input of the LUT 12 via the second signal line group 102. The second wiring 112 outputs a signal input from the first wiring 111 via the ON-state switch cell 113 to the LUT 12 via the first signal line group 101 or the second signal line group 102 . In FIG. 2, the second signal group to be propagated to the second signal line group 102 is configured to be redundant in the crossbar circuit 11, but it is configured to be redundant in the preceding logic block 100-1. You may

The switch cell 113 is arranged at a position where the first wiring 111 and the second wiring 112 intersect. The switch cell 113 is set to an ON state or an OFF state according to external control. When the switch cell 113 is on, the first wiring 111 and the second wiring 112 connected to the switch cell 113 are connected. On the other hand, when the switch cell 113 is in the off state, the first wiring 111 and the second wiring 112 connected to the switch cell 113 are disconnected.

For example, the switch cell 113 is implemented by a configuration including a resistance change switch including a resistance change element. A resistance change switch including a resistance change element is disclosed in Patent Document 1 (International Publication No. 2012/043502), Patent Document 2 (International Publication No. 2013/190741), and the like. Note that the switch cell 113 may be a pass transistor including, for example, an nMOSFET (n metal-oxide-semiconductor field-effect transistor) instead of the variable resistance element. In addition, although FIG. 2 illustrates a configuration in which the switch cells 113 are arranged at all intersections of the crossbar circuit 11, a configuration in which the switch cells 113 are not arranged at some intersections but thinned out may be employed.

An example of the configuration of the crossbar circuit 11 has been described above. The configuration of the crossbar circuit 11 in FIG. 2 is an example, and the configuration of the crossbar circuit 11 of the present embodiment is not limited to the form as it is.

[Resistance change element]
Here, a configuration example of the switch cell 113 arranged at the position where the first wiring 111 and the second wiring 112 intersect will be described with reference to the drawings. 3 and 4 are conceptual diagrams showing an example of the resistance change switch 110 included in the switch cell 113. FIG. 3 and 4, configurations such as cell transistors are omitted.

As shown in FIG. 3, the variable resistance switch 110 has a configuration in which two variable resistance elements 130 are connected in series. The variable resistance element 130 has an active electrode 131 , an inactive electrode 132 and a variable resistance layer 133 . The inactive electrodes 132 of the two variable resistance elements 130 are connected together to form a common node ND. For example, the active electrode 131 is made of a metallic material containing copper. The variable resistance element 130 may be configured such that the active electrodes 131 are connected to each other.

The variable resistance element 130 can take two resistance states, a high resistance state (FIG. 3) and a low resistance state (FIG. 4). In this embodiment, the high resistance state is defined as the OFF state (FIG. 3), and the low resistance state is defined as the ON state (FIG. 4). When the variable resistance element 130 is in the ON state (FIG. 4), signals applied at voltage levels pass through the variable resistance element 130 . On the other hand, when the variable resistance element 130 is in the OFF state (FIG. 3), the signal applied at the voltage level is cut off by the variable resistance element 130 . Also, the resistance state of the variable resistance element 130 is associated with 1 (data 1) and 0 (data 0) of the configuration information. In this embodiment, the low resistance state (on state) is defined as data 1, and the high resistance state (off state) is defined as data 0. FIG.

Here, a method for switching the conductive state of the variable resistance element 130 included in the switch cell 113 will be described.

First, a method for transitioning the variable resistance element 130 from a high resistance state (OFF state) to a low resistance state (ON state) will be described.

In the variable resistance element 130 in the high resistance state (off state) as shown in FIG. 3, when a positive voltage is applied to the active electrode 131 and the inactive electrode 132 is grounded, the metal such as copper contained in the active electrode 131 is ionized. are dissolved inside the variable resistance layer 133 as metal ions. As a result, as shown in FIG. 4, the metal ions dissolved in the variable resistance layer 133 are reduced and deposited as metal, and the deposited metal forms a metal bridge 135 that electrically connects the active electrode 131 and the inactive electrode 132. It is formed. When the active electrode 131 and the inactive electrode 132 are electrically connected by the metal bridge 135, the variable resistance element 130 transitions from the high resistance state (OFF state) to the low resistance state (ON state).

Next, a method for transitioning the variable resistance element 130 from the low resistance state (on state) to the high resistance state (off state) will be described.

In the variable resistance element 130 in the low resistance state (on state) as shown in FIG. It melts inside and part of the metal bridge 135 is broken. As a result, part of the metal bridge 135 is broken, the electrical connection between the active electrode 131 and the inactive electrode 132 is broken, and the variable resistance element 130 transitions to the high resistance state (off state). Between the active electrode 131 and the inactive electrode 132, before the electrical connection is completely disconnected, the electrical characteristics change due to an increase in electrical resistance and a change in the capacitance between the electrodes. The electrical connection is eventually broken. In order to change the variable resistance element 130 from the high resistance state (OFF state) to the low resistance state (ON state), a negative voltage may be applied to the inactive electrode 132 again.

As described above, by controlling the resistance change element 130 between the low resistance state and the high resistance state, the conduction state of the resistance change switch 110 constituting the switch cell 113 can be switched.

An example of the configuration of the crossbar circuit 11 has been described above. The configuration of the crossbar circuit 11 shown in FIGS. 2 to 4 is an example, and the configuration of the crossbar circuit 11 of the present embodiment is not limited as it is. For example, a resistance change nonvolatile memory element used for PRAM (Phase change Random Access Memory) or ReRAM (Resistive Random Access Memory) may be used as the resistance change element.

[LUT]
FIG. 5 is a block diagram showing an example of the configuration of the LUT 12. As shown in FIG. As shown in FIG. 5, the LUT 12 has a first logic selection circuit 121, a filter circuit 122, and a second logic selection circuit 123. FIG.

As shown in FIG. 5, the first logic selection circuit 121 is connected to the output of the crossbar circuit 11 via the first signal line group 101 and also to the filter circuit 122 . Also, the first logic selection circuit 121 includes a plurality of storage elements with addresses set therein. Data is stored in each of the plurality of storage elements.

A non-redundant first signal group is input to the first logic selection circuit 121 via the first signal line group 101 . The first logic selection circuit 121 selects and reads out data from a storage element at a specified address in accordance with a combination of selection signals forming the first signal group that is input. The first logic selection circuit 121 outputs at least two data signals based on the selected data to the filter circuit 122 .

FIG. 6 is a block diagram showing an example of the configuration of the first logic selection circuit 121. As shown in FIG. As shown in FIG. 6, the first logic selection circuit 121 includes a first input circuit 151 and a first selection circuit 152 . Also, the first logic selection circuit 121 includes a plurality of memory elements M1 to Mn (n is a natural number). An address is set in each of the plurality of storage elements M1 to Mn, and 1-bit data is stored. The outputs of the plurality of storage elements M1-Mn form a group of data signals. For example, the memory element M is composed of an SRAM (Static Random Access Memory). Also, the plurality of memory elements M1 to Mn may be configured as a crossbar.

The first input circuit 151 is connected to the crossbar circuit 11 via the first signal line group 101 and is also connected to the first selection circuit 152 . A signal for selecting the memory element M in which data to be read is stored is input to the first input circuit 151 . The first input circuit 151 outputs to the first selection circuit 152 a signal for reading data stored in the storage elements M at addresses corresponding to the combination of signals from the crossbar circuit 11 .

For example, the first input circuit 151 is a first negation circuit that generates a signal (hereinafter referred to as an inverted signal) obtained by inverting the input signal from each signal line constituting the first signal line group 101 . and a second NOT circuit for generating a signal obtained by further inverting the inverted signal. For example, the first input circuit 151 is connected to the first selection circuit 152 via a signal line for outputting an inverted signal and a signal line for outputting a signal obtained by further inverting the inverted signal.

The first selection circuit 152 is connected to the plurality of memory elements M, the first input circuit 151 and the filter circuit 122 . A selection signal is input from the first input circuit 151 to the first selection circuit 152 . The first selection circuit 152 reads data from the storage element M at the designated address according to the selection signal input from the first input circuit 151 . The first selection circuit 152 outputs at least two data signals based on the read data to the filter circuit 122 . FIG. 6 shows an example in which two data signals are selected from a group of data signals output from a plurality of memory elements M1 to Mn, and a data signal based on the selected data is output to the filter circuit 122. FIG.

As shown in FIG. 5, the filter circuit 122 has an input connected to the first logic selection circuit 121 and an output connected to the second logic selection circuit 123 . The filter circuit 122 is a filter that removes noise (hereinafter also referred to as a glitch) that occurs when SET (Single Effect Transient), in which the output voltage of a logic element transiently fluctuates due to the electric charge generated by the influence of radiation, occurs. is. A data signal selected by the first selection circuit 152 is input from the first selection circuit 152 to the filter circuit 122 . When the input data signal contains a glitch, the filter circuit 122 outputs an output data signal group from which the glitch has been removed to the second logic selection circuit 123 .

FIG. 7 is a block diagram showing an example of the configuration of the filter circuit 122. As shown in FIG. As shown in FIG. 7, filter circuit 122 includes first filter element 161 and second filter element 162 . A data signal selected by the first logic selection circuit 121 is input to each of the first filter element 161 and the second filter element 162 . Each of the first filter element 161 and the second filter element 162 removes glitches from the data signal from the first logic selection circuit 121 and outputs its output signal (also called the output data signal) to the second logic selection circuit 123. do. For example, the first filter element 161 and the second filter element 162 are implemented by analog or digital low-pass filters.

FIG. 8 is an example configuration of a digital filter element 160 (also called a SET filter) that implements the first filter element 161 and the second filter element 162 . As shown in FIG. 8, filter element 160 includes delay circuit 163 and guard gate 164 . Signal S input to filter element 160 is input to delay circuit 163 and guard gate 164 . The delay circuit 163 outputs a signal S′ obtained by delaying the signal S by a predetermined time constant to the guard gate 164 . Guard gate 164 removes glitches from signal S using signal S, signal S', and signal D from its own output. Filter element 160 outputs the signal produced by guard gate 164 . For example, it may be configured such that the time constant of the delay circuit 163 included in the filter element 160 can be adjusted.

Filter element 160 in the configuration of FIG. 8 uses signal S' to remove glitches caused by SET. Therefore, when the filter element 160 of FIG. 8 is used as the first filter element 161 and the second filter element 162, a delay corresponding to the time constant of the filter element 160 occurs. When constructing a large-scale logic integrated circuit that connects a plurality of logic blocks, signal delays are accumulated in a configuration in which a plurality of filter circuits 122 are connected in series. Therefore, in the present embodiment, signal paths with strict requirements for propagation delay are made redundant to take SET countermeasures, and the filter circuit 122 is not arranged on the signal paths. That is, in the present embodiment, the non-redundant first signal group is input to the first logic selection circuit 121 and the redundant second signal group is input to the second logic selection circuit 123 .

As shown in FIG. 5, the input of the second logic selection circuit 123 is connected to the output of the crossbar circuit 11 through the second signal line group 102 and also to the output of the filter circuit 122 . Therefore, the second logic selection circuit 123 receives the redundant second signal group (signals S4 to S5) of the logic signal group output from the preceding logic block 100-1 and the output data signal of the filter circuit 122. is input (see FIG. 2). Also, the output of the second logic selection circuit 123 is connected to the input of the DFF 13 . The second logic selection circuit 123 selects one of at least two output data signals from the filter circuit 122 in accordance with the combination of selection signals forming the second signal group input from the second signal line group 102. and output to the DFF 13.

FIG. 9 is a conceptual diagram showing an example of the configuration of the second logic selection circuit 123. As shown in FIG. As shown in FIG. 9, the second logic selection circuit 123 includes a second input circuit 171 and a second selection circuit 172 .

The second input circuit 171 has an input connected to the crossbar circuit 11 via the second signal line group 102 and an output connected to the second selection circuit 172 . A signal for selecting one of at least two output data signals output from the filter circuit 122 is input to the second input circuit 171 . The second input circuit 171 outputs a selection signal to the second selection circuit 172 for selecting an output data signal corresponding to the input signal.

For example, the second input circuit 171 generates, for each of the plurality of signal lines forming the second signal line group 102, a signal obtained by inverting the input signal from the signal line (hereinafter referred to as an inverted signal). It includes a 1 NOT circuit and a second NOT circuit for generating a signal obtained by further inverting the inverted signal. For example, the second input circuit 171 is connected to the second selection circuit 172 via a signal line for outputting an inverted signal and a signal line for outputting a signal obtained by further inverting the inverted signal.

The second selection circuit 172 is connected to the second input circuit 171 , the filter circuit 122 and the DFF 13 . A selection signal is input to the second selection circuit 172 from the second input circuit 171 . The second selection circuit 172 selects one of the two output data signals input from the filter circuit 122 according to the selection signal input from the second input circuit 171 . The second selection circuit 172 outputs the selected output data signal to the DFF 13 .

An example of the configuration of the LUT 12 has been described above. Note that the configuration of the LUT 12 shown in FIGS. 5 to 9 is an example, and the configuration of the LUT 12 of this embodiment is not limited as it is.

[Circuit configuration]
Next, an example of a circuit configuration for realizing the LUT 12 of the logic integrated circuit 1 of this embodiment will be described with reference to the drawings.

FIG. 10 is a conceptual diagram showing an example of the circuit configuration of the LUT 12 (LUT12-1). As shown in FIG. 10, the LUT 12-1 has a first logic selection circuit 121, a filter circuit 122, and a second logic selection circuit 123. FIG. 10 are the same as those in FIGS. 5 to 9 in order to make the correspondence easier to understand, the circuit configurations in FIGS. 5 to 9 are not limited to the circuit configuration in FIG.

The first logic selection circuit 121 includes a plurality of storage elements M1-M16, a first input circuit 151, and a first selection circuit 152. FIG. The first input circuit 151 includes a plurality of NOT circuits N11-N12 (also called logic NOT circuits). The first selection circuit 152 includes a plurality of selection transistors T11-T13. In FIG. 10, only some of the selection transistors T11 to T13 are given reference numerals, and the reference numerals of most of the selection transistors T11 to T13 are omitted.

Filter circuit 122 includes a first filter element 161 and a second filter element 162 . The first filter element 161 and the second filter element 162 are inserted between one of the two outputs of the first logic selection circuit 121 and one of the inputs of the second logic selection circuit 123. .

Second logic selection circuit 123 includes a second input circuit 171 and a second selection circuit 172 . The second input circuit 171 includes two NOT circuits N21 and two NOT circuits N22. The second selection circuit 172 includes two selection transistors T21 and two selection transistors T22.

The above is the description of the schematic circuit configuration of the LUT 12-1. Next, the configuration included in the LUT 12-1 will be described in detail.

One of the signal lines forming the first signal line group 101 is connected to each input of the plurality of NOT circuits N11. Non-redundant signals are input from the first signal line group 101 to the plurality of NOT circuits N11. Each output of the plurality of NOT circuits N11 is connected to the gate of one of the plurality of selection transistors T11 to T13 included in the first selection circuit 152 and to the input of one of the plurality of NOT circuits N12. . Each input of the plurality of NOT circuits N12 is connected to the output of one of the plurality of NOT circuits N11. Each output of the plurality of NOT circuits N12 is connected to the gate of one of the plurality of selection transistors T11-T13 included in the first selection circuit 152. FIG. NOT circuit N11 and NOT circuit N12 invert and output the value of the input signal.

One end of each diffusion layer (source or drain) of the plurality of select transistors T11 is connected to one of the memory elements M1 to M16. The other end of the diffusion layer of each of the select transistors T11 is connected to one end of the diffusion layer of the subsequent select transistor T12 together with the other end of the diffusion layer of any adjacent select transistor T11. More specifically, the other end of the diffusion layer of each of the plurality of selection transistors T11 is connected to the gate of the inverted input signal and forms a pair with the other end of the diffusion layer of the following selection transistor T12. connected at one end.

One end of each diffusion layer of the plurality of selection transistors T12 is connected to the other end of the diffusion layers of the two preceding selection transistors T11. The other end of the diffusion layer of each of the select transistors T12 is connected to one end of the diffusion layer of the subsequent select transistor T13 together with the other end of the diffusion layer of any adjacent select transistor T12.

One end of each of the diffusion layers of the plurality of selection transistors T13 is connected to the other end of the diffusion layers of the two preceding selection transistors T12. The other end of the diffusion layer of each of the select transistors T13 is connected to the filter circuit 122 together with the other end of the diffusion layer of any adjacent select transistor T13.

The first logic selection circuit 121 of LUT12-1 has two selection transistor groups including eight selection transistors T11, four selection transistors T12, and two selection transistors T13. Each output of the two selection transistor groups included in the first logic selection circuit 121 is connected to either one of the first filter element 161 and the second filter element 162 included in the filter circuit 122 . Each of the two data signals selected by the first logic selection circuit 121 is output to one of the first filter element 161 and the second filter element 162 included in the subsequent filter circuit 122 .

One of the two signal lines forming the second signal line group 102 is connected to each input of the two NOT circuits N21 (also referred to as first logical NOT circuits). Redundant signals are input to the NOT circuit N21 from any of the signal lines forming the second signal line group 102 . One output of the two NOT circuits N21 is connected to the gate of one of the two selection transistors T21 included in the second selection circuit 172 and the input of one of the two NOT circuits N22. The output of the other of the two NOT circuits N21 is connected to the gate of the other of the two selection transistors T22 included in the second selection circuit 172 and the input of the other of the two NOT circuits N22. The NOT circuit N21 inverts the value of the input signal and outputs it.

In other words, one of the two signal lines forming the second signal line group 102 is connected to the input of the NOT circuit N21 connected to the gate of the selection transistor T21. The other of the two signal lines forming the second signal line group 102 is connected to the input of the NOT circuit N21 connected to the gate of the selection transistor T22.

An output of one of the plurality of NOT circuits N21 is connected to each input of the two NOT circuits N22 (also referred to as second logical NOT circuits). One output of the two NOT circuits N22 is connected to the gate of the other of the two selection transistors T21 included in the second selection circuit 172. FIG. The output of the other of the two NOT circuits N22 is connected to the gate of the other of the two selection transistors T22 included in the second selection circuit 172. The NOT circuit N22 inverts the value of the input signal.

One end of one diffusion layer of the two selection transistors T21 (also referred to as first selection transistors) is connected to the first filter element 161 included in the filter circuit 122 . The other end of one diffusion layer of the two selection transistors T21 is connected to one end of the diffusion layer of the paired selection transistor T22. One end of the other diffusion layer of the two selection transistors T21 is connected to the second filter element 162 included in the filter circuit 122. FIG. The other end of the other diffusion layer of the two selection transistors T21 is connected to one end of the diffusion layer of the paired selection transistor T22.

One end of the diffusion layer of one of the two selection transistors T22 (also referred to as a second selection transistor) is connected to the other end of the diffusion layer of the paired selection transistor T21. One end of the other diffusion layer of the two selection transistors T22 is connected to the other end of the diffusion layer of the paired selection transistor T21. The other ends of the diffusion layers of the two select transistors T22 are connected to the input D terminal of the DFF13.

The first filter element 161 is connected to one of the two outputs from the first logic selection circuit 121 and to one end of one diffusion layer of the two selection transistors T21 included in the second logic selection circuit 123. . The second filter element 162 is connected to the other of the two outputs from the first logic selection circuit 121 and to one end of the diffusion layer of the other of the two selection transistors T21 included in the second logic selection circuit 123. . The first filter element 161 and the second filter element 162 remove glitches from the input signal and output an output data signal to one of the two selection transistors T21 included in the second logic selection circuit 123. FIG. For example, the first filter element 161 and the second filter element 162 are implemented by SET filters that remove glitches caused by SET.

The LUT 12 - 1 in FIG. 10 receives non-redundant signals from the first signal line group 101 and double-redundant signals from the second signal line group 102 . Then, the LUT 12-1 in FIG. 10 selects one signal according to the combination of those signals and outputs the selected signal. In other words, the LUT 12-1 in FIG. 10 effectively has 4 inputs and 1 output. Note that the LUT 12-1 may have a larger circuit configuration.

In the configuration of FIG. 10 , glitches included in signals input from first signal line group 101 are removed by first filter element 161 and second filter element 162 included in filter circuit 122 . Even if one of the signals of the second signal line group 102 temporarily assumes an incorrect value due to the occurrence of SET, the output of the second selection circuit 172 is temporarily in a high impedance state. The voltage level is held before it occurs. Therefore, according to the configuration of FIG. 10, it is possible to prevent the DFF 13 from being affected by SET.

Although FIG. 10 shows an example in which the selection transistors T11 to T13 included in the LUT 12-1 are configured with nFETs (n field effect transistors), the selection transistors included in the LUT 12-1 may be configured with pFETs. Also, in the LUT 12-1, a transmission gate may be configured by combining nFETs and pFETs instead of selecting transistors configured by nFETs or pFETs. Also, a pull-up circuit may be inserted before the DFF 13 to restore the logic amplitude.

Next, a circuit configuration different from that of the LUT 12-1 in FIG. 10 will be described. FIG. 11 is a conceptual diagram showing an example of a circuit configuration (LUT12-2) different from the LUT12-1 of FIG. In addition, in FIG. 11, the same reference numerals are assigned to the same configurations as in FIG. 10, and detailed description thereof will be omitted. The LUT 12-2 of FIG. 11 has a circuit configuration obtained by adding multiplexers 181 to 182 to the LUT 12-1 of FIG. The output of LUT 12 - 2 is connected to the DFF 13 and the input of multiplexer 183 . In FIG. 10, selection control lines for inputting selection control signals to multiplexers 181 to 183 are omitted. Also, the multiplexer 183 may be included in the configuration of the LUT 12-2.

A multiplexer 181 (also referred to as a first multiplexer) is connected to one of the two outputs from the first logic selection circuit 121 and to the output of the first filter element 161 . A multiplexer 182 (also referred to as a second multiplexer) is connected to the other of the two outputs from the first logic selection circuit 121 and the output of the second filter element 162 . The multiplexers 181 and 182 select and output one of the two input signals. The two signal paths from the first logic selection circuit 121 connected to the multiplexer 181 and the multiplexer 182 are bypass paths when the first filter element 161 and the second filter element 162 are not used. For example, when constructing a circuit that does not use the DFF 13, a detour route is selected.

A multiplexer 183 (also referred to as a third multiplexer) is connected to the output from the second logic selection circuit 123 and the output Q of the DFF 13 . The multiplexer 183 selects and outputs one of the two input signals. A signal path from the second logic selection circuit 123 connected to the multiplexer 183 is a detour path when the DFF 13 is not used. For example, when configuring a circuit that uses only the first logic selection circuit 121 and the second logic selection circuit 123 without using the DFF 13, the detour path is selected.

By using the LUT 12-2 in FIG. 11, a circuit that bypasses the DFF 13 and the filter circuit 122 can be constructed.

An example of the circuit configuration for realizing the LUT 12 of the logic integrated circuit 1 has been described above. The circuit configurations of FIGS. 10 and 11 are examples, and the circuit configuration of the LUT 12 is not limited to the form as it is.

As described above, the logic integrated circuit of this embodiment includes LUTs, crossbar circuits, and flip-flops. The LUT comprises a first logic selection circuit, a filter circuit and a second logic selection circuit.

The first logic selection circuit is connected to a first signal line group through which a non-redundant first signal group among logic signal groups from the preceding logic block is propagated. The first logic selection circuit selects and outputs at least one data signal based on a combination of signals forming a first signal group input from the first signal line group. In other words, the first logic selection circuit receives a non-redundant first signal group among the logic signal groups, and selects at least two data from the data signal group based on a combination of signals forming the first signal group. Select a signal.

The filter circuit receives at least two data signals selected by the first logic selection circuit and removes glitches included in the at least two data signals.

The second logic selection circuit is connected to the second signal line group through which the redundant second signal group of the logic signal group from the preceding logic block is propagated, and to the filter circuit. The second logic selection circuit selects and outputs at least one of the data signals input from the filter circuit based on a combination of signals forming a second signal group input from the second signal line group. In other words, the second logic selection circuit receives the redundant second signal group of the logic signal group and the output data signal group of the filter circuit, and selects based on the combination of the signals forming the second signal group. , selects at least one of the output data signals. For example, the second signal line group through which the second signal group is propagated is assigned the signal with the largest delay among the logic signal groups.

The crossbar circuit routes signals contained in the logic signal group to either a first logic selection circuit to which the first signal group is propagated or a second logic selection circuit to which the second signal group is propagated.

The flip-flop reads the output data signal selected by the second logic selection circuit in synchronization with the clock.

In this embodiment, the first logic selection circuit is connected to the first signal line group through which the first signal group is propagated, and is based on the combination of the signals constituting the first signal group input from the first signal line group. to select the two data signals. A filter circuit removes glitches contained in each of the two data signals selected by the first logic selection circuit. The second logic selection circuit is connected to a second signal line group through which the double redundant second signal group is propagated, and selects a combination of signals constituting the second signal group input from the second signal line group. Based on this, one of the output data signal groups from the filter circuit is selected.

For example, the second logic selection circuit has two each of first selection transistors, second selection transistors, first logical NOT circuits, and second logical NOT circuits. The first select transistor is paired with one of the two second select transistors. One end of the diffusion layer of the first selection transistor is connected to a signal line through which one of the two output data signals output from the filter circuit is propagated, and one end of the diffusion layer of the paired second selection transistor is connected to the diffusion layer. is connected. One end of the diffusion layer of the second selection transistor is connected to the other end of the diffusion layer of the paired first selection transistor. The second selection transistor has the other end of the diffusion layer connected to the other end of the diffusion layer of the other second selection transistor, and the other end of the diffusion layer forms a common output terminal with the other second selection transistor. do. The first logical NOT circuit is paired with either one of the two second logical NOT circuits. The first logical NOT circuit has an input connected to one of the signal lines through which the second signal group having the double redundancy is propagated, and a gate of one of the two first selection transistors. , and the input of a paired second logical NOT circuit. The second logical NOT circuit has an input connected to the output of the paired first logical NOT circuit. The output of the second logic NOT circuit is connected to the gate of the first selection transistor different from the first selection transistor to which the output of the paired first logic NOT circuit is connected.

For example, the second logic selection circuit comprises a first multiplexer and a second multiplexer. The first multiplexer has inputs connected to a signal line through which the first data signal output from the first logic selection circuit is propagated and a signal line through which the first data signal that has passed through the filter circuit is propagated. An output is connected to one of the first select transistors. The second multiplexer has inputs connected to a signal line through which the second data signal output from the first logic selection circuit is propagated and a signal line through which the second data signal that has passed through the filter circuit is propagated. An output is connected to the other of the first selection transistors.

For example, the second logic selection circuit comprises a flip-flop and a third multiplexer. The flip-flop reads the output data signal selected by the second logic selection circuit in synchronization with the clock. The third multiplexer has inputs connected to a signal line through which a signal output from the second logic selection circuit is propagated and a signal line through which a signal output from the flip-flop is propagated, and selects one of the input signals. to choose.

For example, the crossbar circuit includes a plurality of first wirings extending in a first direction, a plurality of second wirings extending in a second direction that intersects with the first direction, and positions at which the first wirings and the second wirings intersect. a plurality of switch cells arranged in the . Each of the plurality of second wirings is connected to either a first logic selection circuit or a second logic selection circuit. A switch cell contains a resistance change switch. For example, a resistance change switch has an active electrode mainly composed of copper, an inactive electrode mainly composed of a metal with lower activity than copper, and a resistance change electrode arranged between the active electrode and the inactive electrode. element.

In this embodiment, among the signal inputs of the LUT, non-redundant signals are input to the first signal line group, and the same redundant signals are input to the second signal line group. Filters are placed on non-redundant paths to prevent glitches. On the other hand, a configuration in which no filter is arranged in a redundant path is adopted. In this embodiment, the signal path with the most severe propagation delay is assigned to the second signal line group to take SET countermeasures without increasing the propagation delay, and filters are arranged in the other signal paths to avoid a redundant configuration. Take SET measures. As a result, according to this embodiment, it is possible to reduce the influence of single event transients while satisfying the requirements for circuit scale and speed performance.

(Second embodiment)
Next, a logic integrated circuit according to a second embodiment of the present invention will be described with reference to the drawings. The logic integrated circuit of this embodiment differs from that of the first embodiment in that it has a majority circuit that selects signals having a large number of values from the triple-redundant second signal group.

FIG. 12 is a conceptual diagram for explaining an overview of the configuration of the logic integrated circuit 2 of this embodiment. As shown in FIG. 12, the logic integrated circuit 2 includes a crossbar circuit 21, an LUT 22, and a DFF 23. The crossbar circuit 21 is connected to the LUT 22 via a first signal line group 201 for propagating a non-redundant first signal group and a second signal line group 202 for propagating a redundant second signal group. be. The first signal group consists of non-redundant signals S1 to S3. The second signal group consists of redundant signals S4 to S6.

LUT 22 and DFF 23 constitute logic block 200 . Although FIG. 12 shows an example in which the logic block 200 is composed of one set of LUT22 and DFF23, the logic block 200 may be composed of multiple sets of LUT22 and DFF23. FIG. 12 shows an example in which the logic integrated circuit 2 is composed of a set of crossbar circuits 21, LUTs 22, and DFFs 23. A plurality of logic blocks 200 are connected by the crossbar circuit 21 to form logic integration. Circuit 2 may be configured. Note that the crossbar circuit 21 and the DFF 23 have the same configurations as the crossbar circuit 11 and the DFF 13 of the first embodiment, respectively, so detailed description thereof will be omitted.

FIG. 13 is a block diagram showing an example of the configuration of the LUT 22. As shown in FIG. As shown in FIG. 13, the LUT 22 has a first logic selection circuit 221, a filter circuit 222, a second logic selection circuit 223, and a majority circuit 225. FIG. Since the configurations of the first logic selection circuit 221 and the filter circuit 222 are the same as those of the first embodiment, detailed description thereof will be omitted. The second logic selection circuit 223 and the majority circuit 225, which are different from the first embodiment, will be described below.

The input of the second logic selection circuit 223 is connected to the output of the majority circuit 225 and the output of the filter circuit 222 . Also, the output of the second logic selection circuit 223 is connected to the input of the DFF 23 . The second logic selection circuit 223 selects one of at least two data signals from the filter circuit 222 according to the selection signal input from the majority circuit 225 and outputs it to the DFF 23 .

The majority circuit 225 has an input connected to the crossbar circuit 21 via the second signal line group 202 and an output connected to the second logic selection circuit 223 . The majority circuit 225 selects and outputs a large number of values among the signals forming the second signal group input via the second signal line group 202 . In the example of FIG. 13, the majority circuit 225 outputs “1” if two or more of the three inputs from the second signal line group 202 are “1”, and outputs “0” if two or more are “0”. If there is, output "0".

FIG. 14 is a configuration example of a circuit (majority circuit 280) that implements the majority circuit 225. As shown in FIG. Majority circuit 280 includes three AND circuits 281 to 283 and one OR circuit 284 . In the example of FIG. 14, the second signal line group 202 is composed of three second signal lines 202-1 to 202-3. Inputs of the AND circuit 281 are connected to the second signal lines 202-1 and 202-2. Inputs of the AND circuit 282 are connected to the second signal lines 202-2 and 202-3. Inputs of the AND circuit 283 are connected to the second signal lines 202-1 and 202-3. The outputs of AND circuits 281 to 283 are connected to the input of OR circuit 284 . The OR circuit 284 selects one value from the inputs of the AND circuits 281 to 283 and outputs it to the second input circuit 271 .

FIG. 15 is a conceptual diagram showing an example of the configuration of the second logic selection circuit 223. As shown in FIG. As shown in FIG. 15, the second logic selection circuit 223 includes a second input circuit 271 and a second selection circuit 272 .

As shown in FIG. 15, the second input circuit 271 has an input connected to the output of the majority circuit 225 and an output connected to the second selection circuit 272 . A selection signal for selecting one of the at least two data signals output from the filter circuit 222 is input to the second input circuit 271 . The second input circuit 271 outputs a selection signal for reading the data signal corresponding to the input signal to the second selection circuit 272 .

For example, the second input circuit 271 includes a first NOT circuit that generates a signal obtained by inverting the input signal from the majority circuit 225 (hereinafter referred to as an inverted signal), and a signal obtained by further inverting the inverted signal. and a second NOT circuit. For example, the second input circuit 271 is connected to the second selection circuit 272 via a signal line for outputting an inverted signal and a signal line for outputting a signal obtained by further inverting the inverted signal.

The second selection circuit 272 is connected to the second input circuit 271 , the filter circuit 222 and the DFF 23 . A selection signal is input to the second selection circuit 272 from the second input circuit 271 . The second selection circuit 272 selects one of the data signals input from the filter circuit 222 according to the selection signal input from the second input circuit 271 . The second selection circuit 272 outputs the selected data signal to the DFF23.

An example of the configuration of the LUT 22 has been described above. Note that the configuration of the LUT 22 shown in FIGS. 13 to 15 is an example, and the configuration of the LUT 22 of this embodiment is not limited as it is.

[Circuit configuration]
Next, an example of a circuit configuration for realizing the LUT 22 of the logic integrated circuit 2 of this embodiment will be described with reference to the drawings.

FIG. 16 is a conceptual diagram showing an example of the circuit configuration of the LUT 22 (LUT22-1). As shown in FIG. 16, the LUT 22-1 has a first logic selection circuit 221, a filter circuit 222, a second logic selection circuit 223, and a majority circuit 225. Although the reference numerals in FIG. 16 are the same as those in FIGS. 12 to 15 in order to make the correspondence easier to understand, the circuit configurations in FIGS. 12 to 15 are not limited to the circuit configuration in FIG.

The first logic selection circuit 221 includes a plurality of storage elements M1-M16, a first input circuit 251, and a first selection circuit 252. FIG. The first input circuit 251 includes a plurality of NOT circuits N11-N12 (also called logic NOT circuits). The first selection circuit 252 includes a plurality of selection transistors T11-T13. In FIG. 16, only some of the selection transistors T11 to T13 are given reference numerals, and the reference numerals of most of the selection transistors T11 to T13 are omitted. Further, since the configuration of the first logic selection circuit 221 is the same as the configuration of the first logic selection circuit 121 shown in FIG. 10, detailed description thereof will be omitted.

Filter circuit 222 includes a first filter element 261 and a second filter element 262 . The first filter element 261 and the second filter element 262 are inserted between one of the two outputs of the first logic selection circuit 221 and one of the inputs of the second logic selection circuit 223. . Since the configuration of the filter circuit 222 is the same as the configuration of the filter circuit 122 shown in FIG. 10, detailed description thereof will be omitted.

Second logic selection circuit 223 includes a second input circuit 271 and a second selection circuit 272 . Second input circuit 271 includes NOT circuit N21 and NOT circuit N22. The second selection circuit 272 includes a selection transistor T21 and a selection transistor T22.

Three signal lines forming the second signal line group 202 are connected to the inputs of the majority circuit 225 . The NOT circuit N21 of the second input circuit 271 is connected to the output of the majority circuit 225. FIG. The majority circuit 225 selects a signal having a large number of values (also called a selection signal) among the three signals input from the three signal lines, and outputs the selected signal to the second input circuit 271 .

The above is the description of the schematic circuit configuration of the LUT 22-1. Next, the configuration included in the LUT 22-1 will be described in detail. In the following, the description of the configuration similar to that of the LUT 12-1 in FIG. 10 will be omitted, and the configuration of the second logic selection circuit 223 will be mainly described.

The output of the majority circuit 225 is connected to the input of the NOT circuit N21 (also referred to as the first negative logic circuit). The output of the NOT circuit N21 is connected to the gate of the selection transistor T21 included in the second selection circuit 272 and the input of the NOT circuit N22. The selection signal output from the majority circuit 225 is input to the NOT circuit N21. The NOT circuit N21 outputs a signal obtained by inverting the value of the input selection signal to the gate of the selection transistor T21 and the input of the NOT circuit N22.

The output of the NOT circuit N21 is connected to the input of the NOT circuit N22 (also called a second NOT logic circuit). The output of the NOT circuit N22 is connected to the gate of the selection transistor T22 included in the second selection circuit 272. FIG. The NOT circuit N22 outputs a signal obtained by inverting the value of the input signal to the gate of the selection transistor T22.

One end of the diffusion layer of the selection transistor T21 (also referred to as the first selection transistor) is connected to the first filter element 261 included in the filter circuit 222 . The other end of the diffusion layer of the selection transistor T21 is connected to the input of the DFF 23 together with the other end of the diffusion layer of the selection transistor T22.

One end of the diffusion layer of the selection transistor T22 (also referred to as a second selection transistor) is connected to a second filter element 262 included in the filter circuit 222 . The other end of the diffusion layer of the selection transistor T22 is connected to the input of the DFF23 together with the other end of the diffusion layer of the selection transistor T21.

The LUT 22 - 1 in FIG. 16 receives non-redundant signals from the first signal line group 201 and triple redundant signals from the second signal line group 202 . The LUT 22-1 in FIG. 16 selects and outputs one data signal according to the combination of selection signals. The LUT 22-1 in FIG. 16 is effectively 4 inputs and 1 output. Note that the LUT 22-1 may have a larger circuit configuration.

In the configuration of FIG. 16 , glitches included in signals input from first signal line group 201 are removed by first filter element 261 and second filter element 262 included in filter circuit 222 . On the other hand, even if the signal input from the second signal line group 202 temporarily assumes an incorrect value when SET occurs, the majority circuit 225 holds the voltage level before SET occurs. Therefore, according to the configuration of FIG. 16, it is possible to prevent the DFF 13 from being affected by SET.

As described above, the logic integrated circuit of the present embodiment is connected to the second signal line group through which the second signal group is propagated, and among the signals constituting the second signal group input from the second signal line group, It has a majority circuit that selects a signal with a large number of values and outputs the selected signal to a second logic selection circuit.

A first logic selection circuit is connected to a first signal line group through which a first signal group is propagated, and selects a data signal group based on a combination of signals constituting a first signal group input from the first signal line group. Select two data signals contained in . A filter circuit removes glitches contained in each of the two data signals selected by the first logic selection circuit. The second logic selection circuit selects one of the two output data signals input from the filter circuit based on the signal selected by the majority circuit.

For example, the second logic selection circuit has a first logic NOT circuit, a second logic NOT circuit, a first selection transistor, and a second selection transistor. One end of the diffusion layer of the first select transistor is connected to a signal line through which one of two data signals output from the filter circuit is propagated. The other end of the diffusion layer of the first selection transistor is connected to one end of the diffusion layer of the second selection transistor to form a common output terminal with the second selection transistor. One end of the diffusion layer of the second selection transistor is connected to a signal line through which the other of the two data signals output from the filter circuit is propagated. The other end of the diffusion layer of the second selection transistor is connected to one end of the diffusion layer of the first selection transistor to form a common output terminal with the first selection transistor. The first logical NOT circuit has an input connected to the output of the majority circuit and an output connected to the gate of the first selection transistor and the input of the second logical NOT circuit. The second logical NOT circuit has an input connected to the output of the first logical NOT circuit and an output connected to the gate of the second selection transistor.

In this embodiment, as in the first embodiment, the signal path with the most severe propagation delay is assigned to the second signal line group to take SET countermeasures without increasing the propagation delay, and filters are applied to the other signal paths. By arranging the , SET countermeasures are taken without redundant configuration. As a result, according to this embodiment, it is possible to reduce the influence of single event transients while satisfying the requirements for circuit scale and speed performance. Moreover, according to the present embodiment, by inserting the majority circuit, the second logic selection circuit can be simplified compared to the first embodiment.

(Third Embodiment)
Next, a logic integrated circuit according to a third embodiment of the present invention will be described with reference to the drawings. The logic integrated circuit of this embodiment is different from the first and second embodiments in that it has a majority circuit that selects a signal having a large number of values among the data signals output from the triple-redundant second logic selection circuit. is different.

FIG. 17 is a conceptual diagram for explaining an overview of the configuration of the logic integrated circuit 3 of this embodiment. As shown in FIG. 17, the logic integrated circuit 3 includes a crossbar circuit 31, LUT32, and DFF33. The crossbar circuit 31 is connected to the LUT 32 via a first signal line group 301 for propagating a non-redundant first signal group and a second signal line group 302 for propagating a redundant second signal group. be. The first signal group consists of non-redundant signals S1 to S3. The second signal group consists of redundant signals S4 to S6.

LUT 32 and DFF 33 constitute logic block 300 . Although FIG. 17 shows an example in which the logic block 300 is composed of one set of LUT32 and DFF33, the logic block 300 may be composed of multiple sets of LUT32 and DFF33. FIG. 17 shows an example in which the logic integrated circuit 3 is composed of a set of crossbar circuits 31, LUTs 32, and DFFs 33. A plurality of logic blocks 300 are connected by the crossbar circuit 31 to form logic integration. Circuit 3 may be configured. Note that the crossbar circuit 31 and the DFF 33 have the same configurations as the crossbar circuit 11 and the DFF 13 of the first embodiment, respectively, so detailed description thereof will be omitted.

FIG. 18 is a block diagram showing an example of the configuration of the LUT 32. As shown in FIG. As shown in FIG. 18, the LUT 32 has a first logic selection circuit 321, a filter circuit 322, a second logic selection circuit 323, and a majority circuit 325. Since the configurations of the first logic selection circuit 321 and the filter circuit 322 are the same as those of the first embodiment, detailed description thereof will be omitted. The second logic selection circuit 323 and the majority circuit 325, which are different from the first embodiment, will be described below.

In FIG. 18, the second logic selection circuit 323 is triple redundant. Each input of the triple-redundant second logic selection circuit 323 is connected to the crossbar circuit 31 via one of the signal lines forming the second signal line group 302, and is connected to the output of the filter circuit 322. be done. The output of the triple redundant second logic selection circuit 323 is connected to the input of the majority circuit 325 . Each of the triple-redundant second logic selection circuits 323 selects one of at least three data signals from the filter circuit 322 according to the signal input from the second signal line group 302 to select a majority circuit. 325 output. Note that the second logic selection circuit 323 may be redundant with a multiplicity other than triple.

Although FIG. 18 shows that all the second logic selection circuits 323 are connected to the filter circuit 322, one second logic selection circuit 323 may be connected to the filter circuit 322. . Also, at least one second logic selection circuit 323 may be configured to be connected to the filter circuit 322 .

The majority circuit 325 has an input connected to each output of the triple redundant second logic selection circuit 323 and an output connected to the DFF 33 . The majority circuit 325 selects and outputs a majority value signal from the data signals input from the second logic selection circuit 323 . For example, the majority circuit 325 outputs "1" if two or more of the three inputs from the triple-redundant second logic selection circuit 323 are "1", and outputs "0" if two or more are "1". If so, output "0". For example, majority circuit 325 is implemented by majority circuit 280 of FIG.

FIG. 19 is a conceptual diagram showing an example of the configuration of the second logic selection circuit 323. As shown in FIG. As shown in FIG. 19, the second logic selection circuit 323 includes a second input circuit 371 and a second selection circuit 372 .

As shown in FIG. 19, the second input circuit 371 has an input connected to one of the signal lines forming the second signal line group 302 and an output connected to the input of the majority circuit 325 . A selection signal for selecting one of at least one data signal output from the filter circuit 322 is input to the second input circuit 371 . The second input circuit 371 outputs a selection signal for reading the data signal corresponding to the input signal to the second selection circuit 372 .

For example, the second input circuit 371 includes a first logical NOT circuit that generates a signal (hereinafter referred to as an inverted signal) obtained by inverting the input signal from one of the signal lines forming the second signal line group 302; and a second logical NOT circuit for generating a signal obtained by further inverting the inverted signal. For example, the second input circuit 371 is connected to the second selection circuit 372 via a signal line for outputting an inverted signal and a signal line for outputting a signal obtained by further inverting the inverted signal.

The second selection circuit 372 is connected to the second input circuit 371 , the filter circuit 322 and the majority circuit 325 . A selection signal is input to the second selection circuit 372 from the second input circuit 371 . The second selection circuit 372 selects one of the data signals input from the filter circuit 322 according to the selection signal input from the second input circuit 371 . The second selection circuit 372 outputs the selected data signal to the majority circuit 325 .

An example of the configuration of the LUT 32 has been described above. Note that the configuration of the LUT 32 shown in FIGS. 17 to 19 is an example, and the configuration of the LUT 32 of this embodiment is not limited as it is.

[Circuit configuration]
Next, an example of a circuit configuration for realizing the LUT 32 of the logic integrated circuit 3 of this embodiment will be described with reference to the drawings.

FIG. 20 is a conceptual diagram showing an example of the circuit configuration of the LUT 32 (LUT32-1). In addition, in FIG. 20, the same reference numerals are given to the same configurations as in FIG. 16, and detailed description thereof will be omitted. The LUT 32-1 of FIG. 20 has a circuit configuration in which the second logic selection circuit 323 is triple redundant, and a majority circuit 325 is arranged after the triple redundant second logic selection circuit 323. FIG. In the description of the LUT 32-1 in FIG. 20, detailed description of the same parts as those of the LUT 22-1 in FIG. 16 will be omitted.

The first logic selection circuit 321 includes a plurality of storage elements M1-M16, a first input circuit 351, and a first selection circuit 352. FIG. The first input circuit 351 includes a plurality of NOT circuits N11-N12 (also called logic NOT circuits). The first selection circuit 352 includes a plurality of selection transistors T11-T13. In FIG. 20, only some of the selection transistors T11 to T13 are given reference numerals, and the reference numerals of most of the selection transistors T11 to T13 are omitted. Further, since the configuration of the first logic selection circuit 321 is the same as the configuration of the first logic selection circuit 121 shown in FIG. 10, detailed description thereof will be omitted.

Filter circuit 322 includes a first filter element 361 and a second filter element 362 . The first filter element 361 and the second filter element 362 are inserted between one of the two outputs of the first logic selection circuit 321 and one of the inputs of the second logic selection circuit 323. . Since the configuration of the filter circuit 322 is the same as the configuration of the filter circuit 122 shown in FIG. 10, detailed description thereof will be omitted.

The second logic selection circuit 323 is triple redundant. One of the signal lines forming the triple-redundant second signal line group 302 is connected to the input of the NOT circuit N21 included in each of the triple-redundant second logic selection circuits 323 . Also, the output of the first filter element 361 is connected to one end of the diffusion layer of the selection transistor T21 included in each of the triple-redundant second logic selection circuits 323 . The output of the second filter element 362 is connected to one end of the diffusion layer of the selection transistor T22 included in each of the triple-redundant second logic selection circuits 323 . The second logic selection circuit 323 selects one of the two data signals output from the first logic selection circuit 321 based on the signal from the second signal line group 302, and selects the selected signal as a majority circuit. 325 output. At least one of the triple-redundant second logic selection circuits 323 may be connected to the filter circuit 322 , and the other second logic selection circuits 323 may not be connected to the filter circuit 322 .

The outputs of the triple redundant second logic selection circuits 323 are connected to the inputs of the majority circuit 325 . The input D terminal of the DFF 33 is connected to the output of the majority circuit 325 . The majority circuit 325 outputs "1" to the DFF 33 when two or more of the three signals output from the three second logic selection circuits 323 are "1", and outputs "1" when two or more are "0". If there is, output "0" to DFF33.

As shown in FIG. 20, the second logic selection circuit 323 is made redundant, and the majority circuit 325 is arranged after the redundant second logic selection circuit 323. The function similar to that of the LUT 22-1 of FIG. realizable.

As described above, the logic integrated circuit of the present embodiment is connected to the multiplexed second logic selection circuit, and the output data signals selected by the multiplexed second logic selection circuit have a large number of values. has a majority circuit that outputs A first logic selection circuit is connected to a first signal line group through which a first signal group is propagated, and selects two data signals based on a combination of signals constituting a first signal group input from the first signal line group. to select. The filter circuit removes glitches contained in each of the two data signals output from the first logic selection circuit. Each second logic selection circuit is connected to one of the signal lines constituting the second signal line group through which the second signal group is propagated, and based on the signal from the connected signal line, the filter circuit One of the two input data signals is selected and output to the majority circuit.

For example, each of the multiplexed second logic select circuits has a first select transistor, a second select transistor, a first logical NOT circuit, and a second logical NOT circuit. One end of the diffusion layer of the first select transistor is connected to a signal line through which one of two output data signals output from the filter circuit is propagated. The other end of the diffusion layer of the first selection transistor is connected to one end of the diffusion layer of the second selection transistor to form a common output terminal with the second selection transistor. One end of the diffusion layer of the second select transistor is connected to a signal line through which the other of the two output data signals output from the filter circuit is propagated. The other end of the diffusion layer of the second selection transistor is connected to one end of the diffusion layer of the first selection transistor to form a common output terminal with the first selection transistor. The first logical NOT circuit has an input connected to one of the signal lines through which the second signal group propagates, and an output connected to the gate of the first selection transistor and the input of the second logical NOT circuit. The second logical NOT circuit has an input connected to the output of the first logical NOT circuit and an output connected to the gate of the second selection transistor. The output is connected to the input of the majority circuit.

In this embodiment, as in the first embodiment, the signal path with the most severe propagation delay is assigned to the second signal line group to take SET countermeasures without increasing the propagation delay, and filters are applied to the other signal paths. By arranging the , SET countermeasures are taken without redundant configuration. As a result, according to this embodiment, it is possible to reduce the influence of single event transients while satisfying the requirements for circuit scale and speed performance. Further, according to the present embodiment, by inserting the majority circuit after the second logic selection circuit, it is possible to further reduce the effect of single event transients on the subsequent stages, compared to the second embodiment.

(Fourth embodiment)
Next, a design support system according to a fourth embodiment of the present invention, a configuration information setting method executed by the design support system, and a program executed by a computer constituting the design support system will be described with reference to the drawings. The design support system according to the present embodiment calculates the signal path with the maximum delay, generates configuration information for allocating the signal path to the second signal line group, and transfers the configuration information to the logic integrated circuit described above. .

(composition)
FIG. 21 is a conceptual diagram showing an example of the configuration of the design support system 40 of this embodiment. FIG. 22 is a conceptual diagram showing an example of the configuration of the design support tool group 400 included in the design support system 40. As shown in FIG.

As shown in FIG. 21 , the design support system 40 includes a configuration information generation device 41 and a configuration information transfer device 42 . The design support system 40 is connected to the logic integrated circuit 4 at least when setting a logic circuit in the logic integrated circuit 4 . The logic integrated circuit 4 is any one of the logic integrated circuits 1 to 3 of the first to third embodiments.

As shown in FIG. 21 , the configuration information generation device 41 is connected to the configuration information transfer device 42 . Also, the configuration information generation device 41 is connected to the logic integrated circuit 4 via the configuration information transfer device 42 . The connection between the configuration information generation device 41 and the configuration information transfer device 42 and the connection between the configuration information transfer device 42 and the logic integrated circuit 4 may be wired or wireless. Not particularly limited.

As shown in FIG. 21 , the configuration information generation device 41 includes an arithmetic unit 411 , a storage unit 412 , a display unit 413 and an input/output unit 414 . The calculation unit 411 , storage unit 412 , display unit 413 and input/output unit 414 are connected to each other via a bus 415 . The configuration information generation device 41 is implemented by, for example, a computer system.

The calculation unit 411 controls the overall operation of the configuration information generation device 41 by executing processing according to a program stored in advance in the storage unit 412 . Further, the calculation unit 411 implements the functions of the design support tool group 400 by executing processing according to a program stored in advance in the storage unit 412 .

The storage unit 412 is a storage medium such as a memory that stores design information and programs. The design information includes circuit behavioral description information created by the designer and information implemented in the logic integrated circuit 4 such as constraint information. For example, the design information includes information such as netlist information, which is the processing result of the arithmetic unit 411, layout and wiring information, resource information and configuration information of the logic integrated circuit 4, and rewriting history information.

The display unit 413 can display a SET filter insertion position, a node having a critical path delay, and the like. Further, the display unit 413 may display an instruction input screen and processing results of the design support tool group 400 . For example, the display unit 413 may display information about the number of times the switch cell has been rewritten (also referred to as the number of changes). For example, the display unit 413 may display display information such as graph display of data after statistical processing or color display on a floor planner. For example, the user can create a desired floor plan by checking display information on the display unit 413 .

The input/output unit 414 is an interface for transmitting and receiving signals and data between input devices such as a keyboard, mouse, and touch panel, configuration information transfer device 42, and output devices such as a printing device (not shown). The input/output unit 414 provides the user with settings for assigning the maximum delay signal to the second signal group through which the redundant signals are propagated. By using the function provided by the input/output unit 414, the user can implement placement and wiring in the logic integrated circuit 4 in which the maximum delay signal is assigned to the second signal group.

The configuration information transfer device 42 is connected to the configuration information generation device 41 and the logic integrated circuit 4 . The configuration information transfer device 42 controls data transmission such as configuration information between the configuration information generation device 41 and the logic integrated circuit 4 . For example, the configuration information transfer device 42 receives data such as configuration information transmitted from the configuration information generation device 41, converts it into transmission data of the data input/output specifications of the logic integrated circuit 4, and transfers the transmission data. Further, for example, the configuration information transfer device 42 receives data such as configuration information output from the logic integrated circuit 4, converts it into transmission data of the data input/output specifications of the configuration information generation device 41, and transfers the data. The data conversion method by the configuration information transfer device 42 is not particularly limited.

The design support tool group 400 shown in FIG. 22 is stored in advance in the storage unit 412 shown in FIG. A design support tool group 400 in FIG. 22 is a tool that the calculation unit 411 reads from the storage unit 412 and executes. As shown in FIG. 22 , the design support tool group 400 includes a logic synthesis tool 401 , placement and routing tool 402 and configuration information generation tool 403 .

The logic synthesis tool 401 (also referred to as logic synthesis means) receives as input a behavioral description file including behavioral description information and constraint information such as delay and power input by the designer of the logic integrated circuit 4 using the input/output unit 414 . do. The logic synthesis tool 401 performs logic synthesis of the input behavioral description file. The logic synthesis tool 401 creates a netlist using logic elements provided in the logic integrated circuit 4 . A netlist is information about logic elements and connections between logic elements.

The placement and routing tool 402 (also referred to as placement and routing means) generates resource information such as logic elements and routing resources of the logic integrated circuit 4 . Based on the resource information of the logic integrated circuit 4, the placement and routing tool 402 virtualizes the logic elements included in the netlist so that the maximum delay path is assigned to the second signal line group through which redundant signals are propagated. Arrange and route according to In other words, the placement and routing tool 402 places logic elements included in the netlist based on the generated resource information, and wires the arranged logic elements to virtually generate at least one signal path.

A configuration information generation tool 403 (also referred to as configuration information generation means) generates circuit configuration information. The configuration information generation tool 403 assigns wiring resources and switch resources to the signal paths routed by the placement and routing tool 402 so that the maximum delay path is assigned to the second signal line group through which redundant signals are propagated. conduct. The configuration information generation tool 403 outputs the generated configuration information of the logic integrated circuit 4 . For example, the configuration information generation tool 403 causes the display unit 413 to display configuration information, and outputs the configuration information from the input/output unit 414 to the configuration information transfer device 42 .

The above is the description of the configuration of the configuration information generation device 41 . Next, the operation of the configuration information generation device 41 will be described with reference to the drawings.

(motion)
FIG. 23 is a flow chart for explaining the design support method by the configuration information generating device 41 of this embodiment. In the following description according to the flowchart of FIG. 23, the configuration information generation device 41 will be described as the subject of the operation.

In FIG. 23, first, the configuration information generating device 41 receives a behavioral description file of a circuit (step S41). The behavioral description file is input by the input/output unit 414 .

For example, the behavioral description file is created using a hardware description language. An example of a hardware description language is Verilog-HDL (Hardware Description Language). An example of a hardware description language is VHDL (Very high-speed integrated circuit Hardware Description Language).

Next, the configuration information generating device 41 logically synthesizes the input behavioral description file (step S42). Logic synthesis of the behavioral description file is executed by the logic synthesis tool 401 .

Next, the configuration information generating device 41 generates a netlist (step S43). A netlist is generated by the logic synthesis tool 401 . A logic synthesis tool 401 generates a netlist using logic elements included in the logic integrated circuit 4 . The logic synthesis tool 401 optimizes the circuit so that the logic integrated circuit satisfies the timing constraint information preset by the designer.

Next, the configuration information generation device 41 executes placement and wiring processing for circuits to be mounted on the logic integrated circuit 4 (step S44). The configuration information generation device 41 assigns the signal path with the maximum delay cost to the second signal line group through which the redundant signals are propagated. The circuit placement and routing process is performed by the placement and routing tool 402 .

Next, the configuration information generating device 41 generates circuit configuration information based on the layout and wiring results (step S45). The configuration information generating device 41 assigns the maximum delay path to the second signal line group through which the redundant signals are propagated. Generation of configuration information is performed by the configuration information generation tool 403 .

When the circuit configuration information is determined, the configuration information generation device 41 and the logic integrated circuit 4 are connected via the configuration information transfer device 42 based on the operation performed by the user on the input/output unit 414 . As a result, a communication path between the configuration information generating device 41 and the logic integrated circuit 4 is established. The configuration information generation device 41 transmits configuration information to the logic integrated circuit 4 via the configuration information transfer device 42 . Upon receiving the configuration information from the configuration information transfer device 42, the logic integrated circuit 4 starts the configuration operation. When the configuration operation of all configuration information is completed, the circuit is mounted on the logic integrated circuit 4 .

The above is the description of the operation of the configuration information generation device 41 . The processing according to the flowchart of FIG. 22 is an example of the operation of the configuration information generation device 41, and the operation of the configuration information generation device 41 of this embodiment is not limited to the method as it is.

[Placement and routing process]
Next, the layout and wiring processing of the configuration information generation device 41 will be described with reference to the drawings. FIG. 24 is a flowchart for explaining the details of the placement and routing process (step S44) executed by the placement and routing tool 402 of the configuration information generating device 41. FIG. In the following description according to the flowchart of FIG. 24, the placement and routing tool 402 will be described as the subject of the operation.

In FIG. 24, the placement and routing tool 402 first generates resource information such as logic elements and routing resources (step S441).

Memory resources configured by switch cells may be used to store the configuration information of the logic elements. A routing resource is composed of a wiring resource and a switch resource. A switch resource may be made up of switch cells. The resource information may include a set of identification number of a logic element and identification number of a switch cell within a switch resource that stores configuration information for that logic element. The resource information includes a directed graph and an undirected graph of the wiring resource as information in which the identification number of a certain wiring resource and the identification number of the switch cell inside the switch resource connected to the wiring resource are linked. good too.

Next, the placement and routing tool 402 assigns each logic element included in the netlist to a placement slot of the logic integrated circuit 4 (step S442).

A slot is a place to place a logical element. For example, the placement and routing tool 402 uses the sum of virtual wire lengths of nets as an evaluation value (also called an evaluation function), and searches for a placement that minimizes the evaluation function. For example, the virtual wiring length of a net is the sum of the x-axis length and the y-axis length of a rectangle surrounding the slot positions of all logic elements included in the net. Note that the evaluation functions used by the placement and routing tool 402 are not limited to those listed here.

Next, the placement and wiring tool 402 determines which wiring resource and switch resource are used to connect each logic element included in the netlist (step S443).

For example, the placement and routing tool 402 searches for wiring that minimizes an evaluation function including at least a delay cost in order to minimize delay time and avoid missing wiring paths. A delay cost is a cost calculated based on the delay time of a wiring route. The placement and routing tool 402 performs routing so that the signal path with the maximum delay cost is assigned to the second signal line group through which redundant signals are propagated.

Also, for example, the placement and routing tool 402 searches for routing that minimizes an evaluation function that includes congestion costs in addition to delay costs. A congestion cost is a cost calculated based on the number of contending nets for a given routing resource. The place and route tool 402 resolves conflicts by iteratively routing with increasing congestion costs. If the place and route tool 402 cannot resolve conflicts, it may perform routing using other procedures such as logic replication.

The above is the description of the placement and routing processing by the placement and routing tool 402 . The processing according to the flowchart of FIG. 24 is an example, and the placement and routing processing by the placement and routing tool 402 of this embodiment is not limited to the method as it is.

As described above, the design support system of this embodiment searches for wiring that minimizes the evaluation function including at least the delay cost for the logic integrated circuits of the first to third embodiments. Then, the design support system of the present embodiment generates configuration information for allocating the signal path with the maximum delay cost to the second signal line group through which the second signal group is propagated, and based on the generated configuration information, Set the circuit configuration to logic integrated circuit. As a result, according to the present embodiment, the signal path with the maximum delay among the logic signal groups is assigned to the second signal line group.

(hardware)
Here, the hardware configuration for executing the processing of the design support system according to the fourth embodiment of the present invention will be described by taking the information processing device 90 of FIG. 25 as an example. Note that the information processing device 90 of FIG. 25 is an example configuration for executing the processing of the design support system of the fourth embodiment, and does not limit the scope of the present invention.

As shown in FIG. 25, an information processing device 90 includes a processor 91 , a main memory device 92 , an auxiliary memory device 93 , an input/output interface 95 and a communication interface 96 . In FIG. 25, the interface is abbreviated as I/F (Interface). Processor 91 , main storage device 92 , auxiliary storage device 93 , input/output interface 95 and communication interface 96 are connected to each other via bus 99 so as to enable data communication. Also, the processor 91 , the main storage device 92 , the auxiliary storage device 93 and the input/output interface 95 are connected to a network such as the Internet or an intranet via a communication interface 96 .

The processor 91 expands a program stored in the auxiliary storage device 93 or the like into the main storage device 92 and executes the expanded program. In this embodiment, a configuration using a software program installed in the information processing device 90 may be used. The processor 91 executes processing by the design support system according to this embodiment.

The main memory 92 has an area in which programs are expanded. The main memory device 92 may be a volatile memory such as a DRAM (Dynamic Random Access Memory). Also, a non-volatile memory such as MRAM (Magnetoresistive Random Access Memory) may be configured and added as the main storage device 92 .

The auxiliary storage device 93 stores various data. The auxiliary storage device 93 is configured by a local disk such as a hard disk or flash memory. It should be noted that it is possible to store various data in the main storage device 92 and omit the auxiliary storage device 93 .

The input/output interface 95 is an interface for connecting the information processing device 90 and peripheral devices. A communication interface 96 is an interface for connecting to an external system or device through a network such as the Internet or an intranet based on standards and specifications. The input/output interface 95 and the communication interface 96 may be shared as an interface for connecting with external devices.

The information processing apparatus 90 may be configured to connect input devices such as a keyboard, mouse, and touch panel as necessary. These input devices are used to enter information and settings. Note that when a touch panel is used as an input device, the display screen of the display device may also serve as an interface of the input device. Data communication between the processor 91 and the input device may be mediated by the input/output interface 95 .

Further, the information processing device 90 may be equipped with a display device for displaying information. When a display device is provided, the information processing device 90 is preferably provided with a display control device (not shown) for controlling the display of the display device. The display device may be connected to the information processing device 90 via the input/output interface 95 .

Further, the information processing device 90 may be equipped with a disk drive, if necessary. Disk drives are connected to bus 99 . Between the processor 91 and a recording medium (program recording medium) not shown, the disk drive mediates reading of data programs from the recording medium and writing of processing results of the information processing device 90 to the recording medium. The recording medium can be implemented by, for example, an optical recording medium such as a CD (Compact Disc) or a DVD (Digital Versatile Disc). The recording medium may be a semiconductor recording medium such as a USB (Universal Serial Bus) memory or an SD (Secure Digital) card, a magnetic recording medium such as a flexible disk, or other recording medium.

The above is an example of the hardware configuration for enabling the design support system according to the fourth embodiment. Note that the hardware configuration of FIG. 25 is an example of the hardware configuration for executing arithmetic processing of the design support system according to the fourth embodiment, and does not limit the scope of the present invention. The scope of the present invention also includes a program that causes a computer to execute processing related to the design support system according to the fourth embodiment. Furthermore, a program recording medium recording the program according to the fourth embodiment is also included in the scope of the present invention.

The components of the design support system of the fourth embodiment can be combined arbitrarily. Also, the components of the design support system of the fourth embodiment may be realized by software or circuits.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

Some or all of the above-described embodiments can also be described in the following supplementary remarks, but are not limited to the following.
(Appendix 1)
A first logic selection circuit to which a first non-redundant signal group among the logic signal group is input and which selects at least two data signals from the data signal group based on a combination of signals forming the first signal group. and,
a filter circuit receiving the at least two data signals selected by the first logic selection circuit and removing glitches included in the at least two data signals;
A redundant second signal group of the logic signal group and the output data signal group of the filter circuit are input, and the output data signal group is determined based on the combination of the signals constituting the second signal group. and a second logic selection circuit that selects at least one of them.
(Appendix 2)
2. The logic integrated circuit according to claim 1, wherein a signal having the longest delay among the logic signal groups is assigned to the second signal line group through which the second signal group is propagated.
(Appendix 3)
The first logic selection circuit,
selecting two of the data signals from the data signal group based on a combination of signals that form the first signal group;
The filter circuit is
3. A logic integrated circuit according to claim 1 or 2, wherein said glitches included in each of said two data signals selected by said first logic selection circuit are removed.
(Appendix 4)
The first logic selection circuit,
The first signal group is connected to a first signal line group through which the first signal group is propagated, and two of the data signals are selected based on a combination of signals constituting the first signal group input from the first signal line group. ,
The filter circuit is
removing glitches in each of the two data signals selected by the first logic selection circuit;
The second logic selection circuit,
Based on a combination of signals constituting the second signal group connected to the second signal line group through which the double redundant second signal group is propagated and input from the second signal line group, the 3. The logic integrated circuit according to appendix 1 or 2, wherein one of the output data signal groups from the filter circuit is selected.
(Appendix 5)
The second logic selection circuit,
having two each of a first selection transistor, a second selection transistor, a first logical NOT circuit, and a second logical NOT circuit;
The first selection transistor is
One end of the diffusion layer is connected to a signal line which is paired with one of the two second selection transistors and propagates one of the two output data signals output from the filter circuit, forming a pair. the other end of the diffusion layer is connected to one end of the diffusion layer of the second selection transistor;
The second selection transistor is
One end of the diffusion layer is connected to the other end of the diffusion layer of the paired first selection transistor, and the other end of the diffusion layer is connected to the other end of the diffusion layer of the second selection transistor. The other end forms an output end common to the other second selection transistor,
The first logical NOT circuit,
An input is connected to either one of signal lines paired with one of the two second logic NOT circuits and through which the double-redundant second signal group is propagated, and two an output is connected to the gate of one of the first selection transistors and the input of the paired second logical NOT circuit;
The second logical NOT circuit,
An input is connected to the output of the paired first logic NOT circuit, and an output is connected to the gate of the first selection transistor different from the first selection transistor to which the output of the paired first logic NOT circuit is connected. The logic integrated circuit according to appendix 4, which is connected.
(Appendix 6)
Inputs are connected to a signal line through which the first data signal output from the first logic selection circuit is propagated and a signal line through which the first data signal that has passed through the filter circuit is propagated, a first multiplexer whose output is connected to one of the 1 selection transistors;
Inputs are connected to a signal line through which the second data signal output from the first logic selection circuit is propagated and a signal line through which the second data signal that has passed through the filter circuit is propagated. 6. A logic integrated circuit according to claim 5, comprising a second multiplexer whose output is connected to the other of the one selection transistors.
(Appendix 7)
a flip-flop that reads the output data signal selected by the second logic selection circuit in synchronization with a clock;
Inputs are connected to a signal line through which the signal output from the second logic selection circuit is propagated and a signal line through which the signal output from the flip-flop is propagated, and one of the input signals is selected. 7. The logic integrated circuit of claim 6, comprising a third multiplexer that
(Appendix 8)
Selecting and selecting signals having a large number of values among signals constituting the second signal group input from the second signal line group and connected to the second signal line group through which the second signal group is propagated a majority circuit that outputs a signal to the second logic selection circuit;
The first logic selection circuit,
are connected to a first signal line group through which the first signal group is propagated, and are included in the data signal group based on a combination of signals constituting the first signal group input from the first signal line group selecting two said data signals;
The filter circuit is
removing the glitch in each of the two data signals selected by the first logic selection circuit;
The second logic selection circuit,
3. The logic integrated circuit according to appendix 1 or 2, wherein one of the two output data signals input from the filter circuit is selected based on the signal selected by the majority circuit.
(Appendix 9)
The second logic selection circuit,
having a first selection transistor, a second selection transistor, a first logical NOT circuit, and a second logical NOT circuit;
The first selection transistor is
One end of the diffusion layer is connected to a signal line through which one of the two output data signals output from the filter circuit is propagated, and the other end of the diffusion layer is connected to one end of the diffusion layer of the second selection transistor. , the other end of the diffusion layer forms an output end common to the second selection transistor,
The second selection transistor is
One end of the diffusion layer is connected to a signal line through which the other of the two output data signals output from the filter circuit is propagated, and the other end of the diffusion layer is connected to one end of the diffusion layer of the first selection transistor. , the other end of the diffusion layer forms the output terminal common to the first selection transistor,
The first logical NOT circuit,
an input connected to the output of the majority circuit and an output connected to the gate of the first selection transistor and the input of the second logical NOT circuit;
The second logical NOT circuit,
9. A logic integrated circuit according to Claim 8, wherein an input is connected to the output of said first logical negation circuit and an output is connected to the gate of said second select transistor.
(Appendix 10)
a majority circuit connected to the multiplexed second logic selection circuit and outputting a signal having a majority value among the output data signals selected by the multiplexed second logic selection circuit;
The first logic selection circuit,
The first signal group is connected to a first signal line group through which the first signal group is propagated, and two of the data signals are selected based on a combination of signals constituting the first signal group input from the first signal line group. ,
The filter circuit is
removing the glitches included in each of the two data signals output from the first logic selection circuit;
Each of the multiplexed second logic selection circuits,
The two outputs are connected to one of the signal lines constituting the second signal line group through which the second signal group is propagated, and are input from the filter circuit based on the signals from the connected signal lines. 3. The logic integrated circuit according to appendix 1 or 2, wherein one of the data signals is selected and output to the majority circuit.
(Appendix 11)
Each of the multiplexed second logic selection circuits,
having a first selection transistor, a second selection transistor, a first logical NOT circuit, and a second logical NOT circuit;
The first selection transistor is
One end of the diffusion layer is connected to a signal line through which one of the two output data signals output from the filter circuit is propagated, and the other end of the diffusion layer is connected to one end of the diffusion layer of the second selection transistor. , the other end of the diffusion layer forms an output end common to the second selection transistor,
The second selection transistor is
One end of the diffusion layer is connected to a signal line through which the other of the two output data signals output from the filter circuit is propagated, and the other end of the diffusion layer is connected to one end of the diffusion layer of the first selection transistor. , the other end of the diffusion layer forms the output terminal common to the first selection transistor,
The first logical NOT circuit,
An input is connected to one of the signal lines through which the second signal group propagates, and an output is connected to the gate of the first selection transistor and the input of the second logical NOT circuit,
The second logical NOT circuit,
an input connected to the output of the first logical NOT circuit and an output connected to the gate of the second select transistor;
The output end is
11. A logic integrated circuit according to claim 10, connected to an input of said majority circuit.
(Appendix 12)
The logic integrated circuit further comprises:
A crossbar for routing signals included in the logic signal group to either the first logic selection circuit to which the first signal group is propagated or the second logic selection circuit to which the second signal group is propagated. a circuit;
12. The logic integrated circuit according to any one of appendices 1 to 11, further comprising a flip-flop that reads the output data signal selected by the second logic selection circuit in synchronization with a clock.
(Appendix 13)
The crossbar circuit is
a plurality of first wirings extending in a first direction;
a plurality of second wirings extending in a second direction intersecting the first direction;
a plurality of switch cells arranged at positions where the first wiring and the second wiring intersect;
Each of the plurality of second wirings,
connected to one of the first logic selection circuit and the second logic selection circuit;
The switch cell is
13. The logic integrated circuit of Claim 12, comprising a resistance change switch.
(Appendix 14)
The resistance change switch is
An additional note comprising an active electrode mainly composed of copper, an inactive electrode mainly composed of a metal having lower activity than copper, and a variable resistance element arranged between the active electrode and the inactive electrode. 14. The logic integrated circuit according to 13.
(Appendix 15)
A first logic selection circuit to which a first non-redundant signal group among the logic signal group is input and which selects at least two data signals from the data signal group based on a combination of signals forming the first signal group. a filter circuit that receives at least two data signals selected by the first logic selection circuit and removes glitches contained in the at least two data signals; a second logic selection circuit that receives a signal group and an output data signal group of the filter circuit and selects at least one of the output data signal group based on a combination of signals that form the second signal group; A configuration information setting method for setting configuration information in a logic integrated circuit comprising
Find the wire that minimizes the merit function including at least the delay cost,
generating configuration information for allocating the signal path with the maximum delay cost to a second signal line group through which the second signal group is propagated;
A configuration information setting method for setting a circuit configuration in the logic integrated circuit based on the generated configuration information.
(Appendix 16)
A first logic selection circuit to which a first non-redundant signal group among the logic signal group is input and which selects at least two data signals from the data signal group based on a combination of signals forming the first signal group. a filter circuit that receives at least two data signals selected by the first logic selection circuit and removes glitches contained in the at least two data signals; a second logic selection circuit that receives a signal group and an output data signal group of the filter circuit and selects at least one of the output data signal group based on a combination of signals that form the second signal group; A program for setting configuration information in a logic integrated circuit comprising
a process of searching for wiring that minimizes an evaluation function including at least a delay cost;
a process of generating configuration information for allocating the signal path having the maximum delay cost to a second signal line group through which the second signal group is propagated;
A program for causing a computer to execute a process of setting a circuit configuration in the logic integrated circuit based on the generated configuration information.

This application claims priority based on Japanese Patent Application No. 2018-210701 filed on November 8, 2018, and the entire disclosure thereof is incorporated herein.

1, 2, 3 logic integrated circuit 11, 21, 31 crossbar circuit 12, 22, 32 LUT
13, 23, 33 DFFs
40 design support system 41 configuration information generation device 42 configuration information transfer device 100, 200, 300 logic block 101, 201, 301 first signal line group 102, 202, 302 second signal line group 111 first wiring 112 second wiring 113 switch cell 121, 221, 321 first logic selection circuit 122, 222, 322 filter circuit 123, 223, 323 second logic selection circuit 130 variable resistance element 131 active electrode 132 inactive electrode 133 variable resistance layer 151, 251, 351 second 1-input circuit 152, 252, 352 first selection circuit 160 filter element 161, 261, 361 first filter element 162, 262, 362 second filter element 171, 271, 371 second input circuit 172, 272, 372 second selection Circuits 225, 280, 325 Majority Circuits 281, 282, 283 AND Circuit 284 OR Circuit 400 Design Support Tool Group 401 Logic Synthesis Tool 402 Placement and Wiring Tool 403 Configuration Information Generation Tool 411 Operation Section 412 Storage Section 413 Display Section 414 Input/Output Section 415 Bus 511 LUTs
512, 522 DFF
513 SET filter 521 LUT group 525 majority circuit

Claims (16)

A first logic selection circuit to which a first non-redundant signal group among the logic signal group is input and which selects at least two data signals from the data signal group based on a combination of signals forming the first signal group. and,
a filter circuit receiving the at least two data signals selected by the first logic selection circuit and removing glitches included in the at least two data signals;
A redundant second signal group of the logic signal group and the output data signal group of the filter circuit are input, and the output data signal group is determined based on the combination of the signals constituting the second signal group. and a second logic selection circuit that selects at least one of them. 2. The logic integrated circuit according to claim 1, wherein the second signal line group through which the second signal group is propagated is assigned a signal with the longest delay among the logic signal groups. The first logic selection circuit,
selecting two of the data signals from the data signal group based on a combination of signals that form the first signal group;
The filter circuit is
3. A logic integrated circuit according to claim 1, wherein said glitches included in each of said two data signals selected by said first logic selection circuit are removed. The first logic selection circuit,
The first signal group is connected to a first signal line group through which the first signal group is propagated, and two of the data signals are selected based on a combination of signals constituting the first signal group input from the first signal line group. ,
The filter circuit is
removing glitches in each of the two data signals selected by the first logic selection circuit;
The second logic selection circuit,
Based on a combination of signals constituting the second signal group connected to the second signal line group through which the double redundant second signal group is propagated and input from the second signal line group, the 3. A logic integrated circuit according to claim 1, wherein one of said group of output data signals from said filter circuit is selected. The second logic selection circuit,
having two each of a first selection transistor, a second selection transistor, a first logical NOT circuit, and a second logical NOT circuit;
The first selection transistor is
One end of the diffusion layer is connected to a signal line which is paired with one of the two second selection transistors and propagates one of the two output data signals output from the filter circuit, forming a pair. the other end of the diffusion layer is connected to one end of the diffusion layer of the second selection transistor;
The second selection transistor is
One end of the diffusion layer is connected to the other end of the diffusion layer of the paired first selection transistor, and the other end of the diffusion layer is connected to the other end of the diffusion layer of the second selection transistor. The other end forms an output end common to the other second selection transistor,
The first logical NOT circuit,
An input is connected to either one of signal lines paired with one of the two second logic NOT circuits and through which the double-redundant second signal group is propagated, and two an output is connected to the gate of one of the first selection transistors and the input of the paired second logical NOT circuit;
The second logical NOT circuit,
An input is connected to the output of the paired first logic NOT circuit, and an output is connected to the gate of the first selection transistor different from the first selection transistor to which the output of the paired first logic NOT circuit is connected. 5. The logic integrated circuit of claim 4, connected. Inputs are connected to a signal line through which the first data signal output from the first logic selection circuit is propagated and a signal line through which the first data signal that has passed through the filter circuit is propagated, a first multiplexer whose output is connected to one of the 1 selection transistors;
Inputs are connected to a signal line through which the second data signal output from the first logic selection circuit is propagated and a signal line through which the second data signal that has passed through the filter circuit is propagated. 6. The logic integrated circuit according to claim 5, further comprising a second multiplexer whose output is connected to the other of the one selection transistors. a flip-flop that reads the output data signal selected by the second logic selection circuit in synchronization with a clock;
Inputs are connected to a signal line through which the signal output from the second logic selection circuit is propagated and a signal line through which the signal output from the flip-flop is propagated, and one of the input signals is selected. 7. The logic integrated circuit of claim 6, comprising a third multiplexer that Selecting and selecting signals having a large number of values among signals constituting the second signal group input from the second signal line group and connected to the second signal line group through which the second signal group is propagated a majority circuit that outputs a signal to the second logic selection circuit;
The first logic selection circuit,
are connected to a first signal line group through which the first signal group is propagated, and are included in the data signal group based on a combination of signals constituting the first signal group input from the first signal line group selecting two said data signals;
The filter circuit is
removing the glitch in each of the two data signals selected by the first logic selection circuit;
The second logic selection circuit,
3. A logic integrated circuit according to claim 1, wherein one of the two output data signals input from said filter circuit is selected based on the signal selected by said majority circuit. The second logic selection circuit,
having a first selection transistor, a second selection transistor, a first logical NOT circuit, and a second logical NOT circuit;
The first selection transistor is
One end of the diffusion layer is connected to a signal line through which one of the two output data signals output from the filter circuit is propagated, and the other end of the diffusion layer is connected to one end of the diffusion layer of the second select transistor. , the other end of the diffusion layer forms an output end common to the second selection transistor,
The second selection transistor is
One end of the diffusion layer is connected to a signal line through which the other of the two output data signals output from the filter circuit is propagated, and the other end of the diffusion layer is connected to one end of the diffusion layer of the first selection transistor. , the other end of the diffusion layer forms the output terminal common to the first selection transistor,
The first logical NOT circuit,
an input connected to the output of the majority circuit and an output connected to the gate of the first selection transistor and the input of the second logical NOT circuit;
The second logical NOT circuit,
9. A logic integrated circuit as claimed in claim 8, wherein an input is connected to the output of said first logical NOT circuit and an output is connected to the gate of said second select transistor. a majority circuit connected to the multiplexed second logic selection circuit and outputting a signal having a majority value among the output data signals selected by the multiplexed second logic selection circuit;
The first logic selection circuit,
The first signal group is connected to a first signal line group through which the first signal group is propagated, and two of the data signals are selected based on a combination of signals constituting the first signal group input from the first signal line group. ,
The filter circuit is
removing the glitches included in each of the two data signals output from the first logic selection circuit;
Each of the multiplexed second logic selection circuits,
The two outputs are connected to one of the signal lines constituting the second signal line group through which the second signal group is propagated, and are input from the filter circuit based on the signals from the connected signal lines. 3. A logic integrated circuit according to claim 1, wherein one of the data signals is selected and output to said majority circuit. Each of the multiplexed second logic selection circuits,
having a first selection transistor, a second selection transistor, a first logical NOT circuit, and a second logical NOT circuit;
The first selection transistor is
One end of the diffusion layer is connected to a signal line through which one of the two output data signals output from the filter circuit is propagated, and the other end of the diffusion layer is connected to one end of the diffusion layer of the second selection transistor. , the other end of the diffusion layer forms an output end common to the second selection transistor,
The second selection transistor is
One end of the diffusion layer is connected to a signal line through which the other of the two output data signals output from the filter circuit is propagated, and the other end of the diffusion layer is connected to one end of the diffusion layer of the first selection transistor. , the other end of the diffusion layer forms the output terminal common to the first selection transistor,
The first logical NOT circuit,
An input is connected to one of the signal lines through which the second signal group propagates, and an output is connected to the gate of the first selection transistor and the input of the second logical NOT circuit,
The second logical NOT circuit,
an input connected to the output of the first logical NOT circuit and an output connected to the gate of the second select transistor;
The output end is
11. A logic integrated circuit according to claim 10, connected to an input of said majority circuit. The logic integrated circuit further comprises:
A crossbar for routing signals included in the logic signal group to either the first logic selection circuit to which the first signal group is propagated or the second logic selection circuit to which the second signal group is propagated. a circuit;
12. The logic integrated circuit according to claim 1, further comprising a flip-flop for reading the output data signal selected by said second logic selection circuit in synchronization with a clock. The crossbar circuit is
a plurality of first wirings extending in a first direction;
a plurality of second wirings extending in a second direction intersecting the first direction;
a plurality of switch cells arranged at positions where the first wiring and the second wiring intersect;
Each of the plurality of second wirings,
connected to one of the first logic selection circuit and the second logic selection circuit;
The switch cell is
13. The logic integrated circuit according to claim 12, comprising a resistance change switch. The resistance change switch is
An active electrode containing copper as a main component, an inactive electrode containing a metal having a lower activity than copper as a main component, and a variable resistance element arranged between the active electrode and the inactive electrode. Item 14. A logic integrated circuit according to item 13. A first logic selection circuit to which a first non-redundant signal group among the logic signal group is input and which selects at least two data signals from the data signal group based on a combination of signals forming the first signal group. a filter circuit that receives at least two data signals selected by the first logic selection circuit and removes glitches contained in the at least two data signals; a second logic selection circuit that receives a signal group and an output data signal group of the filter circuit and selects at least one of the output data signal group based on a combination of signals that form the second signal group; A configuration information setting method for setting configuration information in a logic integrated circuit comprising
Find the wire that minimizes the merit function including at least the delay cost,
generating configuration information for allocating the signal path with the maximum delay cost to a second signal line group through which the second signal group is propagated;
A configuration information setting method for setting a circuit configuration in the logic integrated circuit based on the generated configuration information. A first logic selection circuit to which a first non-redundant signal group among the logic signal group is input and which selects at least two data signals from the data signal group based on a combination of signals forming the first signal group. a filter circuit that receives at least two data signals selected by the first logic selection circuit and removes glitches contained in the at least two data signals; a second logic selection circuit that receives a signal group and an output data signal group of the filter circuit and selects at least one of the output data signal group based on a combination of signals that form the second signal group; A program for setting configuration information in a logic integrated circuit comprising
a process of searching for wiring that minimizes an evaluation function including at least a delay cost;
a process of generating configuration information for allocating the signal path having the maximum delay cost to a second signal line group through which the second signal group is propagated;
A non-transitory recording medium storing a program for causing a computer to execute a process of setting a circuit configuration in the logic integrated circuit based on the generated configuration information.

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