JP7313138B2 - Display and electrical equipment - Google Patents

Description

The present invention relates to display devices and electrical devices.

Patent Document 1 (for example, FIGS. 11 and 12) describes a configuration of a display device including a display section in which a plurality of pixels are arranged and a driving section for driving each pixel. The drive unit supplies a predetermined drive signal to one of the pixels positioned in each column to cause the pixel to emit light. This drive unit includes a digital-analog converter that performs digital-analog conversion, generates analog signals as the drive signals based on a plurality of (for example, K-bit (K>2)) digital signals, and supplies them to corresponding pixels.

JP 2016-57618 A

Generally, a digital-to-analog converter performs digital-to-analog conversion using switching elements such as transistors. At that time, accompanying noise (for example, switching noise such as clock feedthrough and channel charge injection) may occur. This noise reduces the signal conversion accuracy (eg, linearity) during digital-to-analog conversion, and can cause, for example, unexpected fluctuations in the signal values of analog signals generated by the digital-to-analog conversion. This can be a significant problem in the case of the configuration of Patent Document 1, which generates an analog signal based on a plurality of digital signals. Therefore, the display device of Patent Document 1 has room for improvement in terms of the above configuration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique that is advantageous for increasing the accuracy of signal conversion during digital-to-analog conversion.

One aspect of the present invention relates to a display device, the display device comprising:
a signal converter that converts a digital signal into an analog signal;
a display unit to which the analog signal is input and which includes a light-emitting element whose light emission amount is controlled by the signal level of the analog signal, the display device comprising:
a level-up shifter for level-up-shifting a signal received as a digital signal;
a signal amplitude limiter that limits the amplitude range of the digital signal from the level-up shifter and outputs the signal to the signal converter;
the lower limit of the amplitude of the digital signal input to the signal amplitude limiter is a first value;
the upper limit of the amplitude of the digital signal input to the signal amplitude limiter is a second value higher than the first value;
the upper limit of the amplitude of the digital signal output by the signal amplitude limiter is the second value;
the lower limit of the amplitude of the digital signal output by the signal amplitude limiter is a third value higher than the first value and lower than the second value;
The signal amplitude limiter includes a first CMOS inverter circuit and a second CMOS inverter circuit that inverts the logic level of the signal from the first CMOS inverter circuit,
the voltage corresponding to the first value is a first voltage, the voltage corresponding to the second value is a second voltage, the voltage corresponding to the third value is a third voltage;
An NMOS transistor and a PMOS transistor forming each of the first CMOS inverter circuit and the second CMOS inverter circuit are connected in series in an electric path between a node to which the second voltage is applied and a node to which the third voltage is applied, and the first voltage is applied to the back gate terminal of the NMOS transistor.

According to the present invention, it is possible to improve the accuracy of signal conversion by digital-to-analog conversion.

It is a figure for demonstrating the structural example of the display apparatus which concerns on embodiment. It is a figure for demonstrating the structural example of a drive part. FIG. 4 is a diagram for explaining a configuration example of a level-up shifter; FIG. FIG. 4 is a diagram for explaining a configuration example of a signal amplitude limiter; FIG. 4 is a diagram for explaining a configuration example of a signal converter; It is a figure for demonstrating the example of application of a display apparatus. It is a figure for demonstrating the example of application of a display apparatus. It is a figure for demonstrating the example of application of a display apparatus. It is a figure for demonstrating the example of application of a display apparatus.

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be noted that each drawing is only described for the purpose of explaining the structure or configuration, and the dimensions shown in the drawing do not necessarily reflect the actual one. Also, the same reference numerals are given to the same elements in the accompanying drawings, and duplicate descriptions will be omitted below.

FIG. 1A shows a configuration example of a display device 1 according to an embodiment. The display device 1 is an organic EL display (Organic Electro-Luminescence Display) in this embodiment, and includes a display section 2 , a selection section 3 , a drive section 4 and a control section 5 . The display unit 2 is a pixel array in which a plurality of pixels PX ₁₁ and the like are arranged in a matrix (that is, to form a plurality of rows and a plurality of columns). Let M be the number of rows and N be the number of columns of the pixel array (both M and N are integers of 2 or more), and in the figure, the pixel in the i-th row and the j-th column is indicated as pixel PX _ij . For example, the pixel in the first row and second column is denoted as pixel PX ₁₂ , and the pixel in the Mth row and Nth column is denoted as pixel _PXMN .

Incidentally, the pixels PX ₁₁ to PX _MN can be simply referred to as "pixel PX" in the following description unless they are distinguished from each other. Also, the rows and columns of the pixel array as the display section 2 may be simply referred to as "rows" and "columns" respectively in the following description.

The selection unit 3 is also called, for example, a vertical scanning circuit, a scanning signal driver, or the like, and sequentially supplies a selection signal or a scanning signal SIG3 to the plurality of pixels PX on a row-by-row basis via a signal line provided in each row. The driving unit 4 is also called a horizontal scanning circuit, an information signal driver, etc., and sequentially supplies a driving signal or an information signal SIG4 to the plurality of pixels PX on a column-by-column basis via a signal line provided for each column. The control unit 5 drives the plurality of pixels PX individually by controlling the selection unit 3 and the driving unit 4, and causes the display unit 2 to display a predetermined image.

For example, the control unit 5 supplies a control signal for selecting a row to the selection unit 3, supplies an image signal forming image data to the drive unit 4, and additionally supplies a signal (synchronization signal or clock signal) for synchronous control of the selection unit 3 and the drive unit 4. The selection unit 3 outputs a row selection signal as a signal SIG3 based on the control signal from the control unit 5 . Further, the drive unit 4 outputs a signal SIG4 as a signal for driving the pixel PX based on the image signal. The control unit 5 may be expressed as an image processing unit or simply as a processing unit or the like.

FIG. 1B1 illustrates an example of the structure of the pixel PX. The pixel PX has an organic light-emitting diode (OLED) E1 and a transistor T1. Although the details will be described later, the organic light-emitting element E1 is configured to be capable of emitting light when a voltage is applied. A P-channel transistor (MOS transistor, thin film transistor, or the like) is used as the transistor T1. The transistor T1 has a drain terminal connected to the anode of the organic light emitting element E1, a gate terminal receiving the signal SIG3, and a source terminal receiving the signal SIG4. A cathode of the organic light emitting element E1 is grounded.

According to the above-described pixel configuration of FIG. 1B1, the pixel PX is driven in response to receiving the activation level signal SIG4 from the driving section 4 while being selected by receiving the activation level signal SIG3 from the selection section 3, thereby causing the organic light emitting element E1 to emit light. That is, in response to the signal SIG4 being supplied while the transistor T1 is in a conductive state by the signal SIG3, the organic light emitting element E1 is driven and emits light. The amount of light emitted by the organic light emitting element E1 follows the signal value (signal level) of the signal SIG4.

In the example of FIG. 1B1, a pixel configuration having a single transistor T1 is illustrated for ease of explanation, but the pixel PX is not limited to this. For example, transistors T2 and T3 may be used instead of transistor T1, as shown in pixel PX' in FIG. 1B2. P-channel type thin film transistors are used for the transistors T2 and T3. The transistor T2 is connected at its drain terminal to the gate terminal of the transistor T3, receives the signal SIG3 at its gate terminal, and receives the signal SIG4 at its source terminal. Also, the transistor T3 is connected in series with the organic light emitting element E1 between the power supply voltage and the ground voltage. Such a configuration can also achieve the same function as the pixel PX.

The configuration of the pixel PX is not limited to these, and various elements can be added to the pixel PX according to purposes. For example, a reset transistor or the like for initializing the state of the pixel PX (for example, the voltage of the organic light emitting element E1) may be added.

FIG. 1D is a schematic cross-sectional view for explaining an example of the structure of the pixel PX. The pixel PX is formed by providing an organic light emitting element E1 and a transistor T1 between a plurality of insulating layers 2101 to 2104 laminated on a substrate 2100 such as a glass substrate. Transistor T1 is provided between layers 2101-2102 and includes a gate electrode 2111, a gate insulating film 2112, a semiconductor member 2113, a source electrode 2114 and a drain electrode 2115. FIG. The organic light-emitting element E1 is provided between layers 2102-2103 and includes an organic compound layer 2120, a lower electrode 2121 and an upper electrode 2122. FIG. The organic light emitting element E1 and the transistor T1 are electrically connected through a contact plug 2119. FIG. The organic compound layer 2120 emits light in response to voltage application, and although detailed description is omitted, for example, a charge injection layer, a charge transport layer, a hole injection layer, a hole transport layer, a recombination layer, and the like are laminated. A light-transmitting conductive material such as ITO (indium tin oxide) can be used for the electrodes 2121 and 2122 .

Although detailed description is omitted, each of the plurality of pixels PX is provided with a color filter so as to cover the organic light emitting element E1. For example, red, green, and blue color filters may be provided in a manner that follows the Bayer arrangement.

FIG. 2 shows a configuration example of the driving unit 4. As shown in FIG. Driving section 4 includes signal processing section 41 , signal converting section 42 , voltage generating section 43 , output section 44 , level up shifter 45 and signal amplitude limiting section 46 .

The signal processing unit 41 includes a shift register 411 and a latch array 412, aligns the image signals received as digital signals from the control unit 5 in correspondence with columns, and latches them at a predetermined timing based on the clock signal CLK. The latch array 412 may be configured by arranging a plurality of known latch circuits. Also, the signal processing unit 41 may be expressed as a signal distribution unit, a data expansion unit, or the like.

The signal converter 42 includes a plurality of digital-to-analog converters (DAC) 421 each configured to be able to perform digital-to-analog conversion (DA conversion). A plurality of DACs 421 are arranged corresponding to a plurality of columns, that is, N DACs 421 are arranged in this embodiment. Although the details will be described later, the signal converter 42 converts the digital signal received from the signal processor 41 via the level-up shifter 45 and the signal amplitude limiter 46 into an analog signal by the DAC 421 .

The voltage generator 43 can generate a plurality of reference voltages required for DA conversion in the signal converter 42 and supplies the plurality of reference voltages to each DAC 421 of the signal converter 42 . Although the details will be described later, for example, a known voltage dividing circuit can be used for the voltage generator 43 .

The output unit 44 includes a plurality of buffers 441 , amplifies the analog signal received from the signal conversion unit 42 and outputs the amplified analog signal to the display unit 2 . A plurality of buffers 441 are arranged corresponding to a plurality of columns, that is, N buffers 441 are arranged in this embodiment. For example, the buffer 441 corresponding to a column amplifies the analog signal received from the DAC 421 of that column and outputs the amplified analog signal to the pixels PX of that column as signal SIG4.

A plurality of level-up shifters 45 and signal amplitude limiters 46 are arranged for each column, and here, K (K is an integer of 2 or more) are arranged. That is, in this embodiment, the total number of level-up shifters 45 is N×K (the same applies to the signal amplitude limiter 46). Although details will be described later, the level-up shifter 45 level-up-shifts the image signal received as a digital signal by the signal processing unit 41 and outputs the image signal to the signal amplitude limiter 46 . Then, the signal amplitude limiting section 46 limits the amplitude of the image signal and outputs it to the signal converting section 42 . In other words, the DAC 421 corresponding to a certain column receives the K image signals whose amplitudes are limited from the K signal amplitude limiters 46 of the column and performs DA conversion.

Summarizing the driving section 4, the DAC 421 corresponding to a certain column receives K digital signals from the signal processing section 41 via the level-up shifter 45 and the signal amplitude limiting section 46, and uses the K digital signals to generate an analog signal. This analog signal is amplified by the corresponding buffer 441 in the output section 44 and then output as the signal SIG4 to the corresponding pixel PX.

FIG. 3A shows a configuration example of the level-up shifter 45. As shown in FIG. Level-up shifter 45 includes circuit portions 451-453.

The circuit section 451 is a CMOS inverter circuit that inverts the logic level of the signal (referred to as signal _DA ) received from the latch array 412 of the signal processing section 41 and includes an NMOS transistor 4511 and a PMOS transistor 4512 . The NMOS transistor 4511 and the PMOS transistor 4512 are electrically connected in series between a high voltage side power supply voltage V0 (eg, 1.5 [V]) and a low voltage side power supply voltage V1 (eg, 0 [V] (ground voltage)). The back gate terminals of the transistors 4511 and 4512 are connected to the source terminals.

The circuit section 452 is a CMOS inverter circuit that inverts the logic level of the signal received from the circuit section 451 and includes an NMOS transistor 4521 and a PMOS transistor 4522 . NMOS transistor 4521 and PMOS transistor 4522 are electrically connected in series between the power supply voltages V0-V1. The back gate terminals of the transistors 4521 and 4522 are connected to the source terminals.

The circuit portion 453 includes an NMOS transistor 4531 and a PMOS transistor 4532 as well as an NMOS transistor 4533 and a PMOS transistor 4534, and outputs a signal _DB based on signals from the circuit portions 451 and 452. FIG. The NMOS transistor 4531 and the PMOS transistor 4532 are electrically connected in series between a power supply voltage V2 (for example, 10 [V]) on the high voltage side and the power supply voltage V1. An NMOS transistor 4533 and a PMOS transistor 4534 are electrically connected in series between the power supply voltages V2-V1. The NMOS transistor 4531 receives the signal from the circuit section 452 at its gate terminal, and the NMOS transistor 4533 receives the signal from the circuit section 451 at its gate terminal. PMOS transistor 4532 is connected to the electrical path between NMOS transistor 4533 and PMOS transistor 4534 at its gate terminal. PMOS transistor 4534 is connected to the electrical path between NMOS transistor 4531 and PMOS transistor 4532 at its gate terminal. The back gate terminals of the transistors 4531 to 4534 are connected to the source terminals.

The output terminal of level-up shifter 45 is provided in the electrical path between NMOS transistor 4533 and PMOS transistor 4534 . With the circuit configuration described above, the signal _DA input as a digital signal to the circuit portion 451 is level-up-shifted and output as the signal _DB . Specifically, the level-up shifter 45 outputs a signal _DB having a low voltage side signal value of V1 and a high voltage side signal value of V2 in response to receiving a signal _DA having a low voltage side signal value of V1 and a high voltage side signal value of V0.

FIG. 4A shows a configuration example of the signal amplitude limiter 46. As shown in FIG. A signal amplitude limiter 46 receives the signal _DB from the level-up shifter 45, limits the amplitude of the signal, and outputs it as a signal _DC . In this embodiment, the signal amplitude limiter 46 includes inverter circuits 461 and 462 . Inverter circuit 461 corresponds to a first CMOS inverter circuit for inverting the logic level of signal _DB received from level-up shifter 45 and includes NMOS transistor 4611 and PMOS transistor 4612 . Inverter circuit 462 corresponds to a second CMOS inverter circuit that inverts the logic level of the signal from inverter circuit 461 and includes NMOS transistor 4621 and PMOS transistor 4622 .

As shown in FIG. 4A, the signal amplitude limiter 46 is supplied with the voltage V2 as the high voltage side power supply voltage, and is supplied with the voltages V1 and V3 as the low voltage side power supply voltages. NMOS transistor 4611 and PMOS transistor 4612 are electrically connected in series between power supply voltages V2-V3, and NMOS transistor 4621 and PMOS transistor 4622 are electrically connected in series between power supply voltages V2-V3. On the other hand, the back gate terminals of NMOS transistors 4611 and 4621 are connected to power supply voltage V1.

With such a configuration, the signal amplitude limiter 46 can limit the amplitude of the signal _DB and output it as the signal _DC . For example, the signal value on the low voltage side of the signal _DB is V1 (here, 0 [V]), and in this case, the signal value on the low voltage side of the signal _DC is V3 (here, 5 [V]). On the other hand, the signal value on the high voltage side of both the signal _DB and the signal _DC is V2 (here, 10 [V]). In other words, when the signal D _B becomes the signal D _C by the signal amplitude limiter 46, the signal value on the high voltage side is maintained (substantially remains at 10 [V]), and the signal value on the low voltage side increases (from 0 [V] to 5 [V]). In this way, the amplitude of signal _DC (5[V]) will be limited/smaller than the amplitude of signal _DB (10[V]).

FIG. 4B is a timing chart for explaining how the signal values of the signals D _A to D _C change. For ease of explanation, the signal value on the high voltage side (upper limit of signal value) is expressed as H level (high level), and the signal value on the low voltage side (lower limit of signal value) is expressed as L level (low level). The signal _DA is a digital signal with an H level of V0 and an L level of V1. The signal _DB is a digital signal having an H level of V2 and an L level of V1. The signal _DC is a digital signal having an H level of V2 and an L level of V3. Note that V1 corresponds to the first value, V2 corresponds to the second value, and V3 corresponds to the third value.

For example, when signal _DA changes from L level to H level at time t10, output signal _DB from level up shifter 45 receiving signal _DA changes from L level to H level at time t11. Furthermore, in response to this, the output signal _DC from the signal amplitude limiter 46 that has received the signal _DB changes from L level to H level at time t12.

Similarly, when signal _DA changes from H level to L level at time t20, signal _DB from level up shifter 45 receiving signal _DA changes from H level to L level at time t21. Furthermore, in response to this, the signal _DC from the signal amplitude limiter 46 that has received the signal _{DB changes} from H level to L level at time t22.

In FIG. 4B, the waveforms of the signals D _A to D _C are shown with time delays between times t10 to t12 and between times t20 to t22, but they are shown for convenience only.

Referring to FIG. 4A again, in this embodiment, the source terminals of both NMOS transistors 4611 and 4621 are connected to the power supply voltage V3, but other embodiments may be partially modified. For example, even in a configuration in which the source terminal of the transistor 4621 is connected to the power supply voltage V3 and the source terminal of the transistor 4611 is connected to the power supply voltage V1, the function of the signal amplitude limiter 46 can be realized.

As still another embodiment, a level-up shifter 45' shown in FIG. 3(B) may be used instead of the level-up shifter 45 shown in FIG. 3(A). The level-up shifter 45' includes a circuit section 453' in place of the circuit section 453. FIG. Circuit portion 453' includes transistors 4531-4534, and further includes resistive elements R11 and R12. The resistive element R11 is arranged in the electrical path between the NMOS transistor 4531 and the PMOS transistor 4532, and the resistive element R12 is arranged in the electrical path between the NMOS transistor 4533 and the PMOS transistor 4534.

In the example of FIG. 3A described above, both the voltages V1 and V3 are supplied to the signal amplitude limiter 46 as the power supply voltage on the low voltage side, the source terminals of the NMOS transistors 4611 and 4621 are supplied with the power supply voltage V3, and the back gate terminals are supplied with the power supply voltage V1.

In the level-up shifter 45, when the PMOS transistor 4532 is in a non-conducting state, a voltage corresponding to the power supply voltage V2 (eg, 10 V) is input to the gate terminal of the PMOS transistor 4532. On the other hand, when the PMOS transistor 4532 is in a conductive state, the gate terminal of the PMOS transistor 4532 receives the power supply voltage V1 (eg, ground voltage). Similarly to the PMOS transistor 4532, the PMOS transistor 4534 also receives the power supply voltage V2 at its gate terminal when it is in a non-conducting state, and receives the power supply voltage V1 at its gate terminal when it is in a conducting state. Therefore, the on-resistance becomes sufficiently small when the conductive state is established.

On the other hand, when the NMOS transistor 4531 is in a conducting state, the power supply voltage V0 (for example, 1.5 V) is input to the gate terminal of the NMOS transistor 4531 . Also, when the NMOS transistor 4531 is in a non-conducting state, the power supply voltage V1 (for example, ground voltage) is input to the gate terminal of the NMOS transistor 4531 . Similarly, the power supply voltage V0 is input to the gate terminal when the NMOS transistor 4533 is conductive, and the power supply voltage V1 is input to the gate terminal when the NMOS transistor 4533 is non-conductive. That is, when the NMOS transistor is on, the potential difference between the gate terminal and the source terminal is smaller than when the PMOS transistor is on.

In a normal logic circuit, W/L, which is the ratio of the gate width W of the PMOS transistor to the gate length L, can be designed to be larger than the W/L of the NMOS transistor so that the logic threshold is 1/2 of the potential difference between the power supply voltages (for example, (power supply voltage V0+power supply voltage V1)/2=0.75V). However, as described above, in the level-up shifter 45 of this embodiment, it is difficult to sufficiently increase the potential difference between the gate terminal and the source terminal of the NMOS transistor. As a method of bringing the logic threshold close to 1/2 of the potential difference, a method of increasing the ratio W/L of the gate width W to the gate length L of the NMOS transistors 4531 and 4533 is conceivable. On the other hand, increasing the gate width W of the NMOS transistor increases the leakage current flowing between the drain terminal and the source terminal and/or between the drain terminal and the back gate terminal, which may increase the power consumption of the level-up shifter 45.

In the level-up shifter 45' shown in FIG. 3B, a resistance element R11 is provided between the NMOS transistor 4531 and the PMOS transistor 4532. A resistance element R12 is provided between the NMOS transistor 4533 and the PMOS transistor 4534. FIG. This makes it possible to reduce the leakage current flowing through each of the NMOS transistors 4531 and 4533, so that the power consumption of the level-up shifter 45' can be made smaller than that of the level-up shifter 45'. Semiconductor diffused resistors, wiring patterns, or the like may be used for the resistance elements R11 and R12, or MOS transistors may be operated in a linear region to serve as the resistance elements R11 and R12.

FIG. 5 shows the circuit configurations of the signal converter 42 and the voltage generator 43. As shown in FIG. As for the signal conversion unit 42, the figure shows the DAC 421 corresponding to a certain column, but the same applies to the DACs 421 of other columns.

In this embodiment, the voltage generator 43 is a voltage dividing circuit formed by a plurality of resistance elements R20 electrically connected in series between the power supply voltages V2 and V3, and with such a configuration, it is possible to generate a plurality of reference voltages _VREF . A plurality of reference voltages V _REF are set in the range from power supply voltage V3 to V2, and their voltage values are different from each other. For ease of explanation, the above voltage dividing circuit is exemplified as the voltage generator 43 here, but other circuit configurations capable of generating a plurality of desired voltages may be adopted.

The DAC 421 includes a plurality of electrical paths 4210 configured to transmit the plurality of reference voltages V _REF to the output section 44 , and each electrical path 4210 is formed by a plurality of switch elements 4211 . Each switch element 4211 may be a PMOS transistor acting as a pass transistor in electrical path 4210 .

In this embodiment where the number of signal amplitude limiters 46 corresponding to a certain column is K, the number of reference voltages V _REF is 2 ^K , the number of electrical paths 4210 is 2 ^K , and the number of switch elements 4211 provided in a single electrical path 4210 is K. These K switching elements 4211 are supplied with K signals _DC or their inverted signals, respectively. As shown in FIG. 5, the DAC 421 further includes a plurality of inverter circuits 4212, and the inverted signal is generated by the inverter circuits 4212. As shown in FIG.

With such a configuration, one of the 2 ^K electrical paths 4210 is rendered conductive and the corresponding reference voltage V _REF (one of the 2 ^K reference voltages V _REF ) is transmitted to the output section 44 . That is, the DA conversion is realized by the DAC 421 outputting the corresponding reference voltage V _REF as an analog signal based on the K-bit digital signal D _C (d_1, d_2, . . . , d_K).

Switching noise may occur in the signal conversion unit 42 and the voltage generation unit 43 when switching between the conducting state and the non-conducting state of the plurality of switch elements 4210 described above (briefly, DA conversion by the DAC 421). This switching noise includes crosstalk to the source voltage and/or the drain voltage when the gate voltage is changed, so-called clock feedthrough, channel charge injection, and the like. This can cause the voltage value of the reference voltage _VREF output as an analog signal, for example, to fluctuate, which can lead to a decrease in signal conversion accuracy (for example, linearity) during DA conversion.

In this embodiment, the amplitude of the signal _DC is limited by the signal amplitude limiter 46, as described above. Therefore, according to the present embodiment, deterioration in signal conversion accuracy due to switching noise is suppressed. In addition, it becomes possible to switch the plurality of switch elements 4210 in a relatively short time, and along with this, unnecessary current that may occur in the electrical path 4210 can be suppressed.

As described with reference to FIG. 4B, in the present embodiment, the signal _DA as a digital signal supplied from the signal processing unit 41 to the level-up shifter 45 has an H level of V0 (e.g., 1.5 [V]) and an L level of V1 (e.g., 0 [V]). However, the present invention is not limited to this mode, and the signal processing section 41 may process a signal having a relatively large amplitude as a digital signal. For example, the signal processing unit 41 may output a signal as a digital signal with the H level set to V2 (eg, 10 [V]) and the L level set to V1 (eg, 0 [V]). In this case, the level-up shifter 45 can be omitted.

Further, in this embodiment, both the signal _DC and its inverted signal may be supplied to the DAC 421, and the DAC 421 may be configured without the inverter 4212 so that each switch 4211 is connected to either the signal _DC or its inverted signal.

As described above, according to the present embodiment, the display device 1 includes the display unit 2 , the signal conversion unit 42 and the signal amplitude limiter 46 . The signal amplitude limiter 46 limits the amplitude of the signal _DB received as a digital signal, and outputs it to the signal converter 42 as a signal _DC . That is, the amplitude range of the digital signal _DC output from the signal amplitude limiter 46 is smaller than the amplitude range of the digital signal _DB input to the signal amplitude limiter 46 . The signal converter 42 converts this signal _DC into an analog signal by means of the DAC 421 . Therefore, noise that may occur during DA conversion is appropriately suppressed as compared to the case where the amplitude is not limited. This noise suppression improves the accuracy of signal conversion in the signal converter 42, and the analog signal is appropriately generated without unintentionally fluctuating the signal value.

The display device 1 of the above embodiment can be applied to various electrical devices such as electronic viewfinders of cameras, displays of televisions, and display panels of mobile devices.

FIG. 6A is a schematic diagram of the imaging device 61. FIG. The imaging device 61 includes an operation unit 611 , a rear display 612 and an electronic viewfinder 613 attached to a housing 610 . The user can use the operation unit 611 to capture an image of a desired subject, and can confirm an image obtained by the capturing on the rear display 612 . The display device 1 can be applied to the electronic viewfinder 613, and the user can use the electronic viewfinder 613 to check the subject and its surrounding environment when capturing an image. In this case, the display device 1 further displays information associated with the subject and its surrounding environment (for example, information necessary for appropriately realizing imaging such as the intensity of external light and the moving speed of the subject) to notify the user. Note that the concept of the imaging device 61 includes a camera having an imaging function as a main function as well as a camera having an imaging function as an auxiliary function.

FIG. 6B is a schematic diagram of the portable device 62. As shown in FIG. The portable device 62 includes a display section 621 and an operation section 622 attached to a housing 620 respectively. The display device 1 can be applied to the display unit 621 , and the user can display a desired image on the display unit 621 using the operation unit 622 . The display unit 621 also functions as another operation unit, that is, can function as a touch panel. Examples of the mobile device 62 include portable electronic devices and mobile devices, such as mobile phones such as smart phones, and game devices.

FIG. 6C is a schematic diagram of the monitor device 63. As shown in FIG. The monitor device 63 includes a frame 630 , a support base 631 that supports the frame 630 , and a display section 632 bordered by the frame 630 . The display device 1 can be applied to the display unit 632, and the user can use a remote controller (not shown) or an operation unit (not shown) provided on the frame 630 or the support base 631 to display a desired image on the display unit 632. Note that the monitor device 63 may be any device capable of displaying a desired image, and the concept of the monitor device 63 includes a television monitor (broadcast receiver), a personal computer monitor, and the like.

FIG. 6D is a schematic diagram of a foldable type (foldable) device 64 . The device 64 includes a housing 640 , a folding portion (bending portion) 641 that allows the housing 640 to be folded, a first display portion 642 and a second display portion 643 . The first and second display portions 642 and 643 are attached to the housing 640 on both sides of the bent portion 641, respectively. For example, the first and second display units 642 and 643 are in a resting state when the housing 640 is folded and closed, and are in a driving state when the housing 640 is open. The display device 1 can be applied to each of the first and second display units 642 and 643, and the first and second display units 642 and 643 can display different images, or can display one image. One or both of the first and second display units 642 and 643 can also function as an operation unit, that is, can function as a touch panel. The concept of such a device 64 includes, for example, a display (so-called foldable display) and a tablet terminal such as a smart phone (so-called foldable phone).

FIG. 7 shows an example of an exploded view of an electronic device 71 to which the display device 1 is applied. The electronic device 71 includes a touch panel section 711, a display panel section 712, a mounting substrate 713, a battery 714, and cover sections 715 and 716 for housing them. The touch panel section 711 is electrically connected to the mounting board 713 via a flexible printed circuit board (FPC) 7111 . The user can input operation details via the touch panel unit 711 . The display panel section 712 is electrically connected to the mounting board 713 via the FPC 7121 . The display device 1 can be applied to the display panel section 712, and the display panel section 712 displays an image corresponding to the content of the user's operation.

The mounting board 713 is formed by mounting a plurality of electronic components (for example, a power supply IC, a semiconductor package such as a processor) on a rigid board. For example, the power supply IC receives power from the battery 714 and generates power for driving the touch panel section 711 and the display panel section 712 respectively. The power is supplied to the touch panel portion 711 and the display panel portion 712 through the FPCs 7111 and 7121, respectively. Also, for example, the processor receives, via the FPC 7111, a signal indicating the operation content input to the touch panel unit 711, and outputs a signal for displaying an image corresponding to the received signal to the display panel unit 712 via the FPC 7121.

Electrical devices to which the display device 1 can be applied are not limited to the electronic devices described above whose main purpose is to display images. For example, the display device 1 can be applied to indoor lighting devices, and can also be applied to vehicles such as two-wheeled vehicles and four-wheeled vehicles. That is, the concept of electrical device includes various devices that can operate based on electrical energy.

FIG. 8 shows an example of an exploded view of a lighting device 81 to which the display device 1 is applied. The illumination device 81 includes a housing 810 , a light source section 811 , an optical film 812 and a light diffusion section 813 . The light source unit 811 emits light when a switch (not shown) is turned on. The light from the light source part 811 is diffused in various directions in the light diffusion part 813 after passing through the optical film 812 . This makes it possible to properly illuminate the room. The display device 1 can be applied to this light source unit 811, and the light source unit 811 can selectively generate light of various colors for illuminating the room (in this example, the display device 1 is not intended to display an image). For example, the light source unit 811 can selectively generate light such as daylight color, daylight white color, white color, warm white color, and incandescent color based on the operation content input by the user.

FIG. 9 is a schematic diagram of the rear portion of a vehicle 91 to which the display device 1 is applied. A vehicle 91 includes a windshield 911 and lamps 912 attached to a vehicle body 910 . A driver of the vehicle 91 can visually recognize the situation outside the vehicle through the windshield 911 . The display device 1 can be applied to the windshield 911 and can display information necessary for driving (for example, information indicating the presence or absence of pedestrians, navigation information, etc.) on the windshield 911 . Also, the lamp body 912 emits light based on the driving operation by the driver. The display device 1 can also be applied to this lighting body 912, and the lighting body 912 can selectively emit light according to the driving operation by the driver (in this example, the display device 1 is not intended to display an image). For example, the light body 912 can be used as a tail lamp that indicates that the vehicle 91 is in a braking state, or can be used as a direction indicator (blinker) that indicates that the vehicle 91 is turning left or right.

Although some preferred embodiments have been exemplified above, the present invention is not limited to these examples, and part thereof may be changed or combined without departing from the scope of the present invention. In addition, the individual terms described in this specification are only used for the purpose of describing the present invention, and it goes without saying that the present invention is not limited to the strict meanings of the terms and may include equivalents thereof.

1: display device, 2: display unit, 42: signal converter, 46: signal amplitude limiter.

Claims (5)

a signal converter that converts a digital signal into an analog signal;
a display unit to which the analog signal is input and which includes a light-emitting element whose light emission amount is controlled by the signal level of the analog signal, the display device comprising:
a level-up shifter for level-up-shifting a signal received as a digital signal;
a signal amplitude limiter that limits the amplitude range of the digital signal from the level-up shifter and outputs the signal to the signal converter;
the lower limit of the amplitude of the digital signal input to the signal amplitude limiter is a first value;
the upper limit of the amplitude of the digital signal input to the signal amplitude limiter is a second value higher than the first value;
the upper limit of the amplitude of the digital signal output by the signal amplitude limiter is the second value;
the lower limit of the amplitude of the digital signal output by the signal amplitude limiter is a third value higher than the first value and lower than the second value;
The signal amplitude limiter includes a first CMOS inverter circuit and a second CMOS inverter circuit that inverts the logic level of the signal from the first CMOS inverter circuit,
the voltage corresponding to the first value is a first voltage, the voltage corresponding to the second value is a second voltage, the voltage corresponding to the third value is a third voltage;
An NMOS transistor and a PMOS transistor forming the first CMOS inverter circuit and the second CMOS inverter circuit, respectively, are connected in series in an electric path between a node to which the second voltage is applied and a node to which the third voltage is applied, and the first voltage is applied to the back gate terminal of the NMOS transistor. The signal conversion unit is supplied with a plurality of reference voltages within a range from the third value to the second value and having different voltage values,
2. The display device according to claim 1 , wherein the signal converter outputs one of the plurality of reference voltages corresponding to the signal received from the signal amplitude limiter as the analog signal. The display unit is a pixel array in which a plurality of pixels are arranged in a matrix,
A plurality of the signal amplitude limiting units are provided for each column of the pixel array,
3. The display device according to claim 1 , wherein the signal converter outputs the analog signal for driving the pixels of a certain column based on the digital signals output from each of the plurality of signal amplitude limiting units of the column. The display unit is a pixel array in which a plurality of pixels are arranged in a matrix,
4. The display device according to any one of claims 1 to 3 , wherein each pixel includes an organic light emitting element capable of emitting light with an amount of light corresponding to the analog signal. An electrical device comprising the display device according to any one of claims 1 to 4 .

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