JP7312056B2 - Semiconductor light emitting device and method for manufacturing semiconductor light emitting device - Google Patents

Description

The present invention relates to a semiconductor light emitting device and a method for manufacturing a semiconductor light emitting device.

A light-emitting device for deep ultraviolet light has an aluminum gallium nitride (AlGaN)-based n-type clad layer, an active layer, and a p-type clad layer that are sequentially stacked on a substrate. An n-side electrode is formed on the partial region of the n-type clad layer exposed by etching, and a p-side electrode is formed on the p-type clad layer. A protective insulating film made of silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), or the like is provided on the n-side electrode and the p-side electrode (see Patent Document 1, for example).

Japanese Patent No. 5985782

It is preferable that the surface of the light-emitting element can be more suitably coated.

The present invention has been made in view of these problems, and one of its exemplary purposes is to improve the reliability of semiconductor light emitting devices.

A semiconductor light emitting device according to one aspect of the present invention comprises an n-type semiconductor layer of an n-type aluminum gallium nitride (AlGaN) based semiconductor material provided on a substrate, and an AlGaN based semiconductor material provided in a first region on the n-type semiconductor layer. a p-type semiconductor layer of a p-type AlGaN-based semiconductor material provided on the active layer, a second region different from the first region on the n-type semiconductor layer, a side surface of the active layer, and a p-type semiconductor a first covering layer made of aluminum oxide (Al ₂ O ₃ ), an n-side contact electrode penetrating the first covering layer and in contact with the n-type semiconductor layer; a p-side contact electrode penetrating the covering layer and contacting the p-type semiconductor layer; a second covering layer provided so as to cover the first covering layer, the n-side contact electrode and the p-side contact electrode; It has an n-side pad electrode that penetrates and is connected to the n-side contact electrode, and a p-side pad electrode that penetrates through the second covering layer and is connected to the p-side contact electrode.

According to this aspect, since the n-type semiconductor layer, the active layer, and the p-type semiconductor layer made of AlGaN-based semiconductor material are coated with aluminum oxide (Al ₂ O ₃ ) having excellent moisture resistance, these semiconductor layers are The surface can be more suitably coated. Furthermore, by providing the second covering layer that further covers the first covering layer, the n-side contact electrode, and the p-side contact electrode, the surfaces of the contact electrodes can be suitably covered while protecting the first covering layer. Thereby, a highly reliable semiconductor light emitting device can be provided.

A third layer made of aluminum oxide (Al ₂ O ₃ ) is provided to cover at least part of each of the surface of the substrate, the second coating layer, the side surface of the n-side pad electrode and the side surface of the p-side pad electrode. A coating layer may be further provided.

A mounting substrate including an n-side mounting electrode connected to the n-side pad electrode and a p-side mounting electrode connected to the p-side pad electrode may be further provided. The third covering layer may further be provided to cover at least part of the surface of the mounting substrate.

The concentration of hydrogen contained in the first coating layer is lower than the concentration of hydrogen contained in the third coating layer.

A protective insulation layer may be provided between the p-type semiconductor layer and the first covering layer and made of silicon oxide (SiO ₂ ) or silicon oxynitride (SiON).

The n-type semiconductor layer may have a molar fraction of aluminum nitride (AlN) of 20% or more, and the active layer may be configured to emit ultraviolet light with a wavelength of 350 nm or less.

Another aspect of the invention is a method for manufacturing a semiconductor light emitting device. This method comprises forming an n-type semiconductor layer of an n-type aluminum gallium nitride (AlGaN) semiconductor material on a substrate, an active layer of an AlGaN semiconductor material on the n-type semiconductor layer, and a p-type AlGaN semiconductor material on the active layer. sequentially stacking p-type semiconductor layers; removing portions of the p-type semiconductor layer, the active layer, and the n-type semiconductor layer so as to partially expose the n-type semiconductor layer; and exposing the n-type semiconductor layer. forming a first coating layer made of aluminum oxide (Al ₂ O ₃ ) so as to cover the region, the side surface of the active layer, and the p-type semiconductor layer; forming an n-side contact electrode in contact with the n-type semiconductor layer by partially removing the first covering layer to form a p-side contact electrode in contact with the p-type semiconductor layer; forming a second covering layer covering the layer, the n-side contact electrode, and the p-side contact electrode; partially removing the second covering layer to connect the n-side pad electrode to the n-side contact electrode; and partially removing the second covering layer to form a p-side pad electrode connected to the p-side contact electrode.

According to this aspect, since the n-type semiconductor layer, the active layer, and the p-type semiconductor layer made of AlGaN-based semiconductor material are coated with aluminum oxide (Al ₂ O ₃ ) having excellent moisture resistance, these semiconductor layers are The surface can be more suitably coated. Furthermore, by providing the second covering layer that further covers the first covering layer, the n-side contact electrode, and the p-side contact electrode, the surfaces of the contact electrodes can be suitably covered while protecting the first covering layer. Thereby, a highly reliable semiconductor light emitting device can be provided.

The first coating layer may be formed by atomic layer deposition using an organoaluminum compound and oxygen gas (O ₂ ) plasma or ozone gas (O ₃ ) as raw materials.

A third coating layer made of aluminum oxide (Al ₂ O ₃ ) is formed so as to cover at least part of the surface of the substrate, the second coating layer, the side surface of the n-side pad electrode and the side surface of the p-side pad electrode. You may further provide the process of carrying out. The third coating layer may be formed by atomic layer deposition using an organoaluminum compound and water (H ₂ O) as raw materials.

According to the present invention, reliability of a semiconductor light emitting device can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing which shows roughly the structure of the semiconductor light-emitting device which concerns on embodiment. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the structure of the semiconductor light-emitting device which concerns on another embodiment. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light-emitting device.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the description, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted as appropriate. Also, in order to facilitate understanding of the explanation, the dimensional ratio of each component in each drawing does not necessarily match the dimensional ratio of the actual light emitting element.

FIG. 1 is a cross-sectional view schematically showing the configuration of a semiconductor light emitting device 10 according to an embodiment. The semiconductor light emitting element 10 is an LED (Light Emitting Diode) chip configured to emit "deep ultraviolet light" with a center wavelength λ of approximately 360 nm or less. In order to output deep ultraviolet light with such a wavelength, the semiconductor light emitting device 10 is made of an aluminum gallium nitride (AlGaN) based semiconductor material with a bandgap of about 3.4 eV or more. In this embodiment, a case of emitting deep ultraviolet light having a center wavelength λ of approximately 240 nm to 350 nm will be described.

As used herein, "AlGaN-based semiconductor material" refers to a semiconductor material containing at least aluminum nitride (AlN) and gallium nitride (GaN), and a semiconductor material containing other materials such as indium nitride (InN). shall include Therefore, the “AlGaN-based semiconductor material” referred to in this specification is, for example, a composition of In _1-xy Al _x Ga _y N (0<x+y≦1, 0<x<1, 0<y<1). and includes aluminum gallium nitride (AlGaN) or indium aluminum gallium nitride (InAlGaN). The "AlGaN-based semiconductor material" of the present specification is, for example, AlN and GaN each having a molar fraction of 1% or more, preferably 5% or more, 10% or more, or 20% or more.

In order to distinguish materials that do not contain AlN, they are sometimes referred to as "GaN-based semiconductor materials". "GaN-based semiconductor material" includes GaN and InGaN. Similarly, the term "AlN-based semiconductor material" may be used to distinguish materials that do not contain GaN. The "AlN-based semiconductor material" includes AlN and InAlN.

The semiconductor light emitting device 10 includes a die 12 , a mounting substrate 14 , metal bonding materials 16 n and 16 p, and a coating layer (also referred to as a third coating layer) 18 . Die 12 includes a substrate 20, a buffer layer 22, an n-type cladding layer 24, an active layer 26, an electron blocking layer 28, a p-type cladding layer 30, a protective insulating layer 32, and a first cladding layer 34. , an n-side contact electrode 36, an n-side protective metal layer 38, a p-side contact electrode 40, a p-side protective metal layer 42, a second coating layer 44, an n-side pad electrode 46, and a p-side pad electrode 48. and

In FIG. 1, the direction from the board 20 to the mounting board 14 is sometimes called "upper side". 2 to 12, which will be described later, after laminating each layer on the substrate 20, the die 12 is turned upside down and mounted on the mounting substrate .

_The substrate 20 is a substrate having translucency to deep ultraviolet light emitted by the semiconductor light emitting device 10, and is, for example, a sapphire ( _Al2O3 ) substrate. The substrate 20 has a first major surface 20a and a second major surface 20b opposite the first major surface 20a. The first main surface 20a is one main surface that serves as a crystal growth surface for growing each layer above the buffer layer 22 . An outer peripheral surface 20c having a height different from that of the first main surface 20a is provided on the outer periphery of the first main surface 20a. The second main surface 20b is one main surface that serves as a light extraction surface for extracting deep ultraviolet light emitted from the active layer 26 to the outside. Alternatively, the substrate 20 may be an aluminum nitride (AlN) substrate or an aluminum gallium nitride (AlGaN) substrate.

A buffer layer 22 is formed on the first main surface 20 a of the substrate 20 . The buffer layer 22 is a base layer (template layer) for forming each layer above the n-type cladding layer 24 . The buffer layer 22 is, for example, an undoped AlN layer, and more specifically, an AlN (HT-AlN; High Temperature AlN) layer grown at a high temperature. The buffer layer 22 may include an undoped AlGaN layer formed on the AlN layer. In a modification, if the substrate 20 is an AlN substrate or an AlGaN substrate, the buffer layer 22 may be composed of only an undoped AlGaN layer. That is, the buffer layer 22 includes at least one of an undoped AlN layer and an AlGaN layer.

The n-type cladding layer 24 is an n-type semiconductor layer formed on the buffer layer 22 . The n-type cladding layer 24 is an n-type AlGaN-based semiconductor material layer, for example, an AlGaN layer doped with silicon (Si) as an n-type impurity. The composition ratio of the n-type cladding layer 24 is selected so as to transmit the deep ultraviolet light emitted by the active layer 26. For example, the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. is formed as The n-type cladding layer 24 has a bandgap greater than the wavelength of deep ultraviolet light emitted from the active layer 26, and is formed to have a bandgap of 4.3 eV or more, for example. The n-type cladding layer 24 is preferably formed so that the molar fraction of AlN is 80% or less, that is, the band gap is 5.5 eV or less, and the molar fraction of AlN is 70% or less (that is, the band gap is 5.5 eV or less). It is more desirable that the gap be 5.2 eV or less). The n-type cladding layer 24 has a thickness of about 1 μm to 3 μm, for example, about 2 μm.

The n-type cladding layer 24 is formed so that the concentration of silicon (Si), which is an impurity, is 1×10 ¹⁸ /cm ³ or more and 5×10 ¹⁹ /cm ³ or less. The n-type cladding layer 24 is preferably formed so that the Si concentration is 5×10 ¹⁸ /cm ³ or more and 3×10 ¹⁹ /cm ³ or less, and 7×10 ¹⁸ /cm ³ or more and 2×10 ¹⁹ /cm 3 or more. It is preferably formed so as to be cm ³ or less. In one embodiment, the Si concentration of the n-type cladding layer 24 is around 1×10 ¹⁹ /cm ³ and ranges from 8×10 ¹⁸ /cm ³ to 1.5×10 ¹⁹ /cm ³ .

The active layer 26 is composed of an AlGaN-based semiconductor material, and is sandwiched between the n-type cladding layer 24 and the electron blocking layer 28 to form a double heterojunction structure. The active layer 26 may have a single-layer or multi-layer quantum well structure, for example, a laminate of a barrier layer made of an undoped AlGaN-based semiconductor material and a well layer made of an undoped AlGaN-based semiconductor material. It may consist of a body. The active layer 26 is configured to have a bandgap of 3.4 eV or more in order to output deep ultraviolet light with a wavelength of 355 nm or less. For example, the AlN composition ratio is selected so as to output deep ultraviolet light with a wavelength of 310 nm or less. be done. The active layer 26 is provided on the first upper surface 24a of the n-type cladding layer 24 and is not provided on the second upper surface 24b adjacent to the first upper surface 24a. That is, the active layer 26 is not formed over the entire surface of the n-type clad layer 24, but is formed only in a partial region of the n-type clad layer 24. As shown in FIG.

An electron blocking layer 28 is formed over the active layer 26 . The electron block layer 28 is an undoped AlGaN-based semiconductor material layer, and is formed, for example, so that the molar fraction of AlN is 40% or more, preferably 50% or more. The electron blocking layer 28 may be formed such that the molar fraction of AlN is 80% or more, or may be formed of an AlN-based semiconductor material that does not contain GaN. The electron blocking layer has a thickness of about 1 nm to 10 nm, for example, a thickness of about 2 nm to 5 nm. The electron block layer 28 may be a p-type AlGaN-based semiconductor material layer.

The p-type cladding layer 30 is a p-type semiconductor layer formed on the electron blocking layer 28 . The p-type cladding layer 30 is a p-type AlGaN-based semiconductor material layer, for example, an AlGaN layer doped with magnesium (Mg) as a p-type impurity. The p-type cladding layer 30 has a thickness of approximately 300 nm to 700 nm, for example, approximately 400 nm to 600 nm. The p-type cladding layer 30 may be made of a p-type GaN-based semiconductor material that does not contain AlN.

A protective insulating layer 32 is provided on the p-type clad layer 30 . The protective insulating layer 32 is composed of silicon oxide (SiO ₂ ) or silicon oxynitride (SiON). The protective insulating layer 32 is made of a material having a lower refractive index with respect to deep ultraviolet light output from the active layer 26 than the p-type cladding layer 30 . The AlGaN semiconductor material forming the p-type cladding layer 30 has a refractive index of about 2.1 to 2.56 depending on the composition ratio. On the other hand, the refractive index of SiO ₂ forming the protective insulating layer 32 is about 1.4, and the refractive index of SiON is about 1.4 to 2.1. By providing the protective insulating layer 32 with a low refractive index, more of the ultraviolet light from the active layer 26 is totally reflected at the interface between the p-type cladding layer 30 and the protective insulating layer 32, thereby increasing the amount of ultraviolet light from the substrate 20, which is the light extraction surface. It can be directed to the second main surface 20b. In particular, since silicon oxide (SiO ₂ ) has a large difference in refractive index from the p-type cladding layer 30, the reflection characteristics can be further improved. The thickness of the protective insulating layer 32 is 50 nm or more, and can be, for example, 100 nm or more and 500 nm or less.

The first covering layer 34 covers the protective insulating layer 32 , the second upper surface 24 b of the n-type cladding layer 24 , and the side surfaces of the n-type cladding layer 24 , the active layer 26 and the electron blocking layer 28 . provided in The first covering layer 34 may cover the side surfaces of the buffer layer 22 and the outer peripheral surface 20c of the substrate 20, as shown. The first coating layer 34 is composed of aluminum oxide (Al ₂ O ₃ ). Aluminum oxide (Al ₂ O ₃ ) forming the first coating layer 34 is superior in moisture resistance to silicon oxide (SiO ₂ ). Therefore, by covering the entire upper and side surfaces of the semiconductor layer with the first covering layer 34, a protective function with excellent moisture resistance can be provided. In addition, since aluminum oxide (Al ₂ O ₃ ) constituting the first coating layer 34 has a low absorptivity of deep ultraviolet light output from the active layer 26, the provision of the first coating layer 34 reduces the light output. can also be suppressed. The thickness of the first coating layer 34 can be 10 nm or more and 50 nm or less, for example, about 10 nm to 30 nm.

The Al ₂ O ₃ forming the first coating layer 34 preferably has a dense structure with a high film density, and is preferably formed using, for example, an atomic layer deposition (ALD) method. Also, the first coating layer 34 preferably has a low hydrogen concentration. If the first coating layer 34 contains high-concentration hydrogen (H), the hydrogen diffuses into the active layer 26 and the p-type cladding layer 30, causing deterioration of these semiconductor layers. In order to obtain Al ₂ O ₃ with a low hydrogen concentration, it is preferable to use oxygen gas (O ₂ ) plasma or ozone gas (O ₃ ) instead of water (H ₂ O) as a supply source of oxygen atoms. That is, the first coating layer 34 is preferably formed by ALD using an organic aluminum compound such as trimethylaluminum (TMA) and O ₂ plasma or O ₃ as raw materials.

The n-side contact electrode 36 is provided on the second upper surface 24b of the n-type cladding layer 24 and is in contact with the n-type cladding layer 24 through an opening penetrating the first coating layer 34 on the second upper surface 24b of the n-type cladding layer 24. . The n-side contact electrode 36 includes, for example, a Ti layer on and in contact with the n-type cladding layer 24 and an Al layer on and in contact with the Ti layer. The thickness of the Ti layer is about 1 nm to 10 nm, preferably 5 nm or less, more preferably 2 nm or less. By reducing the thickness of the Ti layer, the ultraviolet light reflectance of the n-side contact electrode 36 viewed from the n-type cladding layer 24 can be increased. The thickness of the Al layer is about 100 nm to 1000 nm, preferably 200 nm or more, more preferably 300 nm or more. By increasing the thickness of the Al layer, the ultraviolet light reflectance of the n-side contact electrode 36 can be increased. It is preferable that the n-side contact electrode 36 does not contain gold (Au), which may cause a decrease in ultraviolet light reflectance.

The p-side contact electrode 40 is provided on the p-type cladding layer 30 and contacts the p-type cladding layer 30 through an opening penetrating the protective insulating layer 32 on the p-type cladding layer 30 and the first covering layer 34 . The p-side contact electrode 40 is made of transparent conductive oxide (TCO) such as tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (ITO). The thickness of the p-side contact electrode 40 is about 20 nm to 500 nm, preferably 50 nm or more, more preferably 100 nm or more.

The n-side protective metal layer 38 is provided on the n-side contact electrode 36 and the p-side protective metal layer 42 is provided on the p-side contact electrode 40 . The n-side protective metal layer 38 and the p-side protective metal layer 42 (also collectively referred to as a protective metal layer) are formed of a metal material having high adhesion to the second coating layer 44, and are composed of a single metal film or a metal laminated film. consists of Since the protective metal layers 38 and 42 function as stop layers in the dry etching process for forming the opening penetrating the second coating layer 44, they are preferably made of a metal material that is highly resistant to etching gases. As a material for the protective metal layers 38 and 42, for example, a platinum group metal can be used, and palladium (Pd) can be used. The thickness of the protective metal layers 38 and 42 is preferably 50 nm or more, preferably 100 nm or more.

The second covering layer 44 is provided to cover the first covering layer 34 , the n-side contact electrode 36 and the n-side protective metal layer 38 , the p-side contact electrode 40 and the p-side protective metal layer 42 . The second coating layer 44 is composed of an insulating oxide, nitride or oxynitride, such as silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum nitride (AlN), silicon oxynitride (SiON) or Aluminum oxynitride (AlON) can be used. The thickness of the second coating layer 44 is 50 nm or more, preferably 100 nm or more. The thickness of the second coating layer 44 may be about 500 nm to 1000 nm. By increasing the thickness of the second covering layer 44, the contact electrodes 36, 40 and the protective metal layers 38, 42, which are thicker than the semiconductor layers, can be preferably covered.

The n-side pad electrode 46 and the p-side pad electrode 48 (generically referred to as pad electrodes) are portions that are bonded when the die 12 is mounted on the mounting substrate 14 . The n-side pad electrode 46 is provided on the n-side protective metal layer 38 and is in contact with the n-side protective metal layer 38 through an opening penetrating the second covering layer 44 . The n-side pad electrode 46 is electrically connected to the n-side contact electrode 36 via the n-side protective metal layer 38 . The p-side pad electrode 48 is provided on the p-side protective metal layer 42 and is in contact with the p-side protective metal layer 42 through an opening penetrating the second covering layer 44 . The p-side pad electrode 48 is electrically connected to the p-side contact electrode 40 via the p-side protective metal layer 42 .

The pad electrodes 46 and 48 are configured to contain gold (Au) from the viewpoint of corrosion resistance, and are, for example, a laminate of nickel (Ni)/Au, titanium (Ti)/Au, or Ti/platinum (Pt)/Au. Consists of structure. When the pad electrodes 46 and 48 are bonded with gold tin (AuSn), the pad electrodes 46 and 48 may include an AuSn layer as a metal bonding material.

Die 12 is mounted on mounting substrate 14 . The mounting substrate 14 includes a base 50, mounting electrodes 52n and 52p, and external terminals 54n and 54p. The base 50 is a plate-like member made of a ceramic material such as aluminum nitride (AlN). The mounting electrodes 52n and 52p are provided on the first main surface 50a of the base 50. As shown in FIG. The mounting electrodes 52n, 52p are metal electrodes that are bonded to the pad electrodes 46, 48 of the die 12, and are configured to contain gold (Au) from the viewpoint of corrosion resistance. The external terminals 54n and 54p are metal terminals for soldering the semiconductor light emitting element 10 to a printed circuit board or the like, and are provided on the second main surface 50b of the base 50 opposite to the first main surface 50a. Inside the base 50, the n-side mounting electrode 52n and the n-side external terminal 54n are electrically connected, and the p-side mounting electrode 52p and the p-side external terminal 54p are electrically connected.

The metal bonding materials 16n and 16p bond the die 12 and the mounting substrate 14 together. The metal bonding materials 16n and 16p are made of a gold-tin (AuSn) or tin-zinc (SnZn)-based solder material. The n-side metal bonding material 16n bonds the n-side pad electrode 46 and the n-side mounting electrode 52n, and the p-side metal bonding material 16p bonds the p-side pad electrode 48 and the p-side mounting electrode 52p.

The third coating layer 18 is provided so as to cover the entire surface of the die 12, part of the surface of the mounting substrate 14, and the metal bonding materials 16n and 16p. The third covering layer 18 covers the second main surface 20b and side surfaces 20d of the substrate 20, the surface of the second covering layer 44, and the side surfaces of the n-side pad electrode 46 and the p-side pad electrode 48. FIG. The third covering layer 18 also covers the first main surface 50a and the side surface 50c of the mounting substrate 14, and the surfaces of the mounting electrodes 52n and 52p.

The third coating layer 18 is made of aluminum oxide (Al ₂ O ₃ ), and is deposited using an atomic layer deposition (ALD) method so as to have a dense structure with a high film density, similar to the first coating layer 34 described above. preferably formed. On the other hand, since the third coating layer 18 does not come into direct contact with semiconductor layers such as the active layer 26 of the die 12, the hydrogen concentration does not necessarily have to be low. That is, the hydrogen concentration of the third coating layer 18 may be higher than the hydrogen concentration of the first coating layer 34 . Therefore, water (H ₂ O) may be used as a supply source of oxygen atoms of Al ₂ O ₃ constituting the third coating layer 18, and an organic aluminum compound such as TMA and H ₂ O are used as raw materials. It may be formed by an ALD method. By using H ₂ O as a raw material, it becomes easier to spread the raw material into a narrow gap compared to the case of using O ₂ plasma or O ₃ , and even in a narrow gap between the die 12 and the mounting substrate 14, dense Al can be obtained. ₂ O ₃ can be preferably formed. The thickness of the third coating layer 18 can be 10 nm or more and 50 nm or less, for example, about 10 nm to 30 nm.

Next, a method for manufacturing the semiconductor light emitting device 10 will be described. 2 to 13 are diagrams schematically showing the manufacturing process of the semiconductor light emitting device 10. First, as shown in FIG. First, as shown in FIG. 2, a buffer layer 22, an n-type cladding layer 24, an active layer 26, an electron blocking layer 28, a p-type cladding layer 30, and a protective insulation layer 32 are formed on a first main surface 20a of a substrate 20. are formed in sequence.

The substrate 20 is a sapphire (Al ₂ O ₃ ) substrate, and a buffer layer 22 is formed on the (0001) plane of the sapphire substrate, for example. The buffer layer 22 includes, for example, a high temperature grown AlN (HT-AlN) layer and an undoped AlGaN (u-AlGaN) layer. The n-type clad layer 24, the active layer 26, the electron block layer 28, and the p-type clad layer 30 are layers formed of an AlGaN-based semiconductor material, an AlN-based semiconductor material, or a GaN-based semiconductor material, and are formed by metalorganic chemical vapor deposition. It can be formed using well-known epitaxial growth methods such as the (MOVPE) method and the molecular beam epitaxy (MBE) method. Protective insulating layer 32 is composed of SiO ₂ or SiON and can be formed using well-known techniques such as chemical vapor deposition (CVD).

Next, as shown in FIG. 3, a first mask 61 is formed on the protective insulating layer 32, and the protective insulating layer 32, the p-type cladding layer 30, and the first region W1 where the first mask 61 is not formed are formed. Parts of the electron blocking layer 28, the active layer 26 and the n-type cladding layer 24 are removed. As a result, a second upper surface 24b (exposed surface) of the n-type cladding layer 24 is formed in the first region (also called exposed region) W1. In the step of forming the exposed surface of the n-type clad layer 24 , each layer can be removed by dry etching 71 . For example, reactive ion etching by turning etching gas into plasma can be used, for example, inductive coupled plasma (ICP) etching can be used. After that, the first mask 61 is removed.

Next, as shown in FIG. 4, a second mask 62 is formed on the protective insulating layer 32 and on the second upper surface 24b of the n-type cladding layer 24. Next, as shown in FIG. After that, the protective insulating layer 32, the p-type cladding layer 30, the electron blocking layer 28, the active layer 26 and the n-type cladding layer 24 are dry-etched in the second region (also referred to as the peripheral region) W2 where the second mask 62 is not formed. 72. The second area W2 is an isolation area between elements when a plurality of light emitting elements (dies) are formed on one substrate. In the second region W2, the buffer layer 22 may be partially removed, or the buffer layer 22 may be completely removed to expose the substrate 20. FIG. In the second region W2, part of the substrate 20 may be removed to expose the outer peripheral surface 20c of the substrate 20 having a height different from that of the first main surface 20a. After that, the second mask 62 is removed.

Next, as shown in FIG. 5, a first covering layer 34 is formed to cover the entire upper surface of the device structure. The first coating layer 34 is made of Al ₂ O ₃ and is formed, for example, by the ALD method using TMA and O ₂ plasma or O ₃ as raw materials. The first covering layer 34 is formed on the protective insulating layer 32 , on the second upper surface 24 b of the n-type cladding layer 24 , on the n-type cladding layer 24 , the active layer 26 , the electron blocking layer 28 and the p-type cladding layer 30 . It is formed to cover the sides. The protective insulating layer 32 may cover the side surface of the buffer layer 22, or may cover the outer peripheral surface 20c of the substrate 20 and at least part of the side surface.

Next, as shown in FIG. 6, a third mask 63 is formed on the first covering layer 34 . The third mask 63 is formed except for the n-side electrode region W3n on the second upper surface 24b of the n-type cladding layer 24 and the p-side electrode region W3p on the p-type cladding layer 30 . Subsequently, the first covering layer 34 is removed by dry etching 73 in the n-side electrode region W3n and the p-side electrode region W3p. Thereby, a first opening 81 exposing the n-type cladding layer 24 is formed in the n-side electrode region W3n, and a second opening 82 exposing the protective insulating layer 32 is formed in the p-side electrode region W3p. After that, the third mask 63 is removed.

Next, as shown in FIG. 7, the n-side contact electrode 36 is formed on the n-type cladding layer 24 exposed in the first opening 81, and the n-side protective metal layer 38 is formed on the n-side contact electrode 36. It is formed. The n-side contact electrode 36 has, for example, a laminated structure of a Ti layer and an Al layer, and the n-side protective metal layer 38 is, for example, a Pd layer. The n-side contact electrode 36 and the n-side protective metal layer 38 can be formed by sputtering or electron beam (EB) evaporation.

Next, as shown in FIG. 8, a fourth mask 64 is formed except for the fourth region W4 corresponding to the second opening 82. Next, as shown in FIG. Subsequently, the protective insulating layer 32 is removed by wet etching in the fourth region to form a third opening 83 exposing the p-type cladding layer 30 . The protective insulating layer 32 can be removed using, for example, buffered hydrofluoric acid (BHF), which is a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH ₄ F). By wet-etching the protective insulating layer 32, damage to the p-type cladding layer 30 exposed in the third opening 83 can be reduced as compared with dry-etching the protective insulating layer 32. FIG. After that, the fourth mask 64 is removed.

Next, as shown in FIG. 9 , the p-side contact electrode 40 is formed on the p-type cladding layer 30 exposed through the third opening 83 , and the p-side protective metal layer 42 is formed on the p-side contact electrode 40 . It is formed. The p-side contact electrode 40 is, for example, an ITO layer, and the p-side protective metal layer 42 is, for example, a Pd layer. The p-side contact electrode 40 and the p-side protective metal layer 42 can be formed by sputtering or electron beam (EB) evaporation.

Next, as shown in FIG. 10, a second covering layer 44 is formed to cover the entire upper surface of the device structure. The second covering layer 44 covers the first covering layer 34, the n-side contact electrode 36, the n-side protective metal layer 38, the p-side contact electrode 40, and the p-side protective metal layer 42. formed in The second coating layer 44 is, for example, a SiO ₂ layer and can be formed using well-known techniques such as chemical vapor deposition (CVD).

Next, as shown in FIG. 11, a fifth mask 65 is formed on the second covering layer 44. Then, as shown in FIG. The fifth mask 65 is formed except for the n-side electrode region W5n corresponding to the n-side contact electrode 36 and the p-side electrode region W5p corresponding to the p-side contact electrode 40 . Subsequently, the second covering layer 44 is removed by dry etching 75 in the n-side electrode region W5n and the p-side electrode region W5p. The second coating layer 44 can be dry-etched using a CF-based etching gas, for example, hexafluoroethane (C ₂ F ₆ ) can be used. In this dry etching step, the n-side protective metal layer 38 and the p-side protective metal layer 42 function as etching stop layers, and can prevent damage to the underlying n-side contact electrode 36 and p-side contact electrode 40 . . As a result, a fourth opening 84 exposing the n-side protective metal layer 38 in the n-side electrode region W5n and a fifth opening 85 exposing the p-side protective metal layer 42 in the p-side electrode region W5p are formed. . After that, the fifth mask 65 is removed.

Next, as shown in FIG. 12, the n-side pad electrode 46 is formed on the n-side protective metal layer 38 exposed through the fourth opening 84, and the p-side protective metal layer 42 exposed through the fifth opening 85 is formed. A p-side pad electrode 48 is formed thereon. The pad electrodes 46 and 48 can be formed, for example, by depositing a Ni layer or a Ti layer and then depositing an Au layer thereon. Another metal layer may be provided on the Au layer, for example, a Sn layer, an AuSn layer, and a Sn/Au layered structure may be formed. Through the above steps, the die 12 shown in FIG. 1 is completed.

Next, the die 12 is mounted on the mounting board 14 as shown in FIG. First, the die 12 is arranged so that the n-side pad electrode 46 is positioned on the n-side mounting electrode 52n and the p-side pad electrode 48 is positioned on the p-side mounting electrode 52p. Subsequently, metal bonding materials 16n and 16p such as gold tin (AuSn) and solder are melted to bond the pad electrodes 46 and 48 and the mounting electrodes 52n and 52p.

After that, a third covering layer 18 is formed so as to cover the entire surface of the die 12 mounted on the mounting substrate 14 . The third coating layer 18 is made of Al ₂ O ₃ and is formed, for example, by the ALD method using TMA and H ₂ O as raw materials. Thereby, the semiconductor light emitting device 10 shown in FIG. 1 is completed.

According to the present embodiment, the first coating layer 34 that is in direct contact with the semiconductor layers such as the n-type cladding layer 24, the active layer 26 and the electron blocking layer 28 is an Al ₂ O ₃ layer formed by the ALD method. , the moisture resistance of these semiconductor layers can be enhanced. Moreover, by not using water (H ₂ O) as a raw material for the first coating layer 34, the concentration of hydrogen contained in the first coating layer 34 can be reduced. That is, the hydrogen concentration of the first covering layer 34 can be made lower than that of the third covering layer 18 . As a result, deterioration of the semiconductor layer due to diffusion of hydrogen contained in the first covering layer 34 into the semiconductor layer can be preferably prevented.

According to the present embodiment, by further providing the second coating layer 44 on the first coating layer 34, the function of protecting the die 12 can be enhanced. Since the first coating layer 34 made of Al ₂ O ₃ is formed by the ALD method, it is difficult to increase the film thickness, and a thickness of about 50 nm may be the practical upper limit. On the other hand, the film thickness of the n-side contact electrode 36 and the p-side contact electrode 40 is 50 nm or more, and preferably 100 nm or more. There is On the other hand, since the second covering layer 44 formed by the CVD method or the like can easily have a thickness of 100 nm or more, it can suitably cover a contact electrode having a large thickness. According to this embodiment, the sealing performance of the die 12 can be improved by combining the dense but thin first coating layer 34 and the thick second coating layer 44 .

According to the present embodiment, after the die 12 is mounted on the mounting substrate 14, the third covering layer 18 further covers the entire surface, so that the sealing performance of the semiconductor light emitting device 10 can be improved. In particular, by coating the surfaces of the metal materials such as the pad electrodes 46 and 48, the mounting electrodes 52n and 52p, and the metal bonding materials 16n and 16p, corrosion of the metal materials can be preferably prevented. In addition, by forming the third coating layer 18 from Al ₂ O ₃ , it is possible to improve the adhesion to a metal material containing gold (Au), thereby preventing deterioration in reliability due to peeling of the third coating layer 18. can be suppressed.

According to the present embodiment, the third coating layer 18 is formed by the ALD method using water (H ₂ O) as a raw material. And the third covering layer 18 can be formed so as to cover the entire mounting board 14 . If O ₂ plasma or O ₃ is used as a raw material like the first coating layer 34 , activated oxygen (O) is deactivated before it reaches the gap between the die 12 and the mounting substrate 14 . As a result, there may be places where the Al ₂ O ₃ layer is not properly formed. On the other hand, when H ₂ O is used as a raw material, it is not necessary to be in a plasma state, so the raw material can be sufficiently spread in the gap between the die 12 and the mounting substrate 14, and the Al ₂ O ₃ layer can be formed more appropriately. can be formed. Thereby, the reliability of the third coating layer 18 can be improved.

According to the present embodiment, by providing the protective insulating layer 32 between the p-type cladding layer 30 and the first covering layer 34, the p-type cladding layer 30 is not exposed during the etching process for exposing the p-type cladding layer 30. can reduce the damage effect of Thereby, the contact resistance of the p-side contact electrode 40 can be improved, and the output characteristics of the semiconductor light emitting device 10 can be improved.

FIG. 14 is a cross-sectional view schematically showing the configuration of a semiconductor light emitting device 110 according to another embodiment. This embodiment differs from the above-described embodiments in that the second covering layer 144 has a two-layer structure of a first layer 144a and a second layer 144b. The present embodiment will be described below, focusing on the differences from the above-described embodiments.

The semiconductor light emitting device 110 includes a die 112, a mounting substrate 14, metal bonding materials 16n and 16p, and a third coating layer . Mounting substrate 14, metal bonding materials 16n and 16p, and third coating layer 18 are configured in the same manner as in the above-described embodiment.

Die 112 includes a substrate 20, a buffer layer 22, an n-type cladding layer 24, an active layer 26, an electron blocking layer 28, a p-type cladding layer 30, a protective insulating layer 32, and a first cladding layer 34. , an n-side contact electrode 36, an n-side protective metal layer 38, a p-side contact electrode 40, a p-side protective metal layer 42, a second coating layer 144, an n-side pad electrode 46, and a p-side pad electrode 48. and The die 112 is constructed similarly to the die 12 according to the above-described embodiment, except that the second coating layer 144 has a two-layer structure.

The second covering layer 144 includes a first layer 144a and a second layer 144b. The first layer 144 a is provided so as to be in direct contact with the first covering layer 34 , the n-side contact electrode 36 , the n-side protective metal layer 38 , the p-side contact electrode 40 and the p-side protective metal layer 42 . The second layer 144b is provided so as to cover the first layer 144a, and is formed from the first covering layer 34, the n-side contact electrode 36, the n-side protective metal layer 38, the p-side contact electrode 40 and the p-side protective metal layer 42. placed apart.

The first layer 144a is made of, for example, SiO ₂ and has a lower refractive index than the first covering layer 34 and the second layer 144b. The first layer 144a is configured to be thicker than the first covering layer 34 and the second layer 144b. The thickness of the first layer 144a is 100 nm or more, for example, about 500 nm to 1000 nm. The thickness of the first layer 144 a is configured to be ten times or more the thickness of the first covering layer 34 . The thickness of the first layer 144 a may be greater than the thickness of the n-side contact electrode 36 and the p-side contact electrode 40 . The thickness of the first layer 144a may be larger than the total thickness of the n-side contact electrode 36 and the n-side protective metal layer 38, or larger than the total thickness of the p-side contact electrode 40 and the p-side protective metal layer 42. may

The second layer 144b is made of a material different from that of the first layer 144a, and is made of a nitride such as AlN or SiN. The second layer 144b is made of SiN, for example, and has a higher refractive index than the protective insulating layer 32, the first coating layer 34, and the first layer 144a. For ultraviolet light with a wavelength of 280 nm, the refractive index of _SiO2 is 1.49, the refractive index of _Al2O3 is _1.82 , the refractive index of SiN is 2.18, and the refractive index of AlN is is 2.28. Therefore, the refractive index (2.18 or 2.28) of the second layer 144b made of SiN or AlN is the refractive index (1.49) of the protective insulating layer ₃₂ and the first layer 144a made of SiO2. and greater than the refractive index (1.82) of the first coating layer 34 made of Al ₂ O ₃ . The thickness of the second layer 144b is smaller than the thickness of the first layer 144a, and is about 50 nm to 200 nm. The thickness of the second layer 144b may be smaller than the thickness of the protective insulating layer 32. FIG. The thickness of the second layer 144 b may be greater than the thicknesses of the first coating layer 34 and the third coating layer 18 .

According to the present embodiment, by laminating the second layer 144b made of a different material from the first layer 144a on the first layer 144a, pinholes that may occur in the first layer 144a can be preferably blocked. It is possible to improve the sealing performance of the second covering layer 144 .

According to this embodiment, the refractive index of the material of the protective insulation layer 32 is _n1 , the refractive index of the material of the first coating layer 34 is _n2 , and the refractive index of the first layer 144a of the second coating layer 144 is is _n3 and the refractive index of the second layer 144b of the second coating layer 144 is _n4 , the relational expressions of _n1 < _n2 < _n4 and _n3 < _n2 < _n4 hold. do. According to the present embodiment, by making the refractive index _n3 of the first layer 144a smaller than the refractive index _n2 of the first coating layer 34, the deep ultraviolet light generated in the active layer 26 is The light can be totally reflected at the interface between 34 and the first layer 144a and directed toward the second main surface 20b, which is the light extraction surface. Thereby, the light extraction efficiency of the semiconductor light emitting device 10 can be enhanced. In addition, by covering the first layer 144a with the second layer 144b made of nitride having a higher refractive index than the material of the first layer 144a, the sealing performance and reliability of the second covering layer 144 are improved. be able to.

Next, a method for manufacturing the semiconductor light emitting device 110 will be described. A part of the manufacturing process of the semiconductor light emitting device 110 is common to a part of the manufacturing process of the semiconductor light emitting device 10 described above, and first, the steps shown in FIGS. 2 to 9 are performed. 15 to 18 are diagrams schematically showing the manufacturing steps of the semiconductor light emitting device 110, and show the steps subsequent to FIG.

As shown in FIG. 15, a second covering layer 144 is formed to cover the entire top surface of the device structure. The second covering layer 144 includes a first layer 144a and a second layer 144b. The first layer 144a covers the exposed surface of the first covering layer 34 and covers the exposed surfaces of the n-side contact electrode 36, the n-side protective metal layer 38, the p-side contact electrode 40 and the p-side protective metal layer 42. is formed as The second layer 144b is formed to cover the exposed surface of the first layer 144a. The first layer 144a is, for example, a SiO ₂ layer and can be formed using a well-known technique such as plasma CVD. The second layer 144b is, for example, a SiN layer, and can be formed using a well-known technique such as plasma CVD.

Next, as shown in FIG. 16, a sixth mask 66 is formed over the second covering layer 144 . The sixth mask 66 is formed except for the n-side electrode region W6n corresponding to the n-side contact electrode 36 and the p-side electrode region W6p corresponding to the p-side contact electrode 40 . Subsequently, the second layer 144b of the second covering layer 144 is removed by dry etching 76 in the n-side electrode region W6n and the p-side electrode region W6p. The second coating layer 144 can be dry-etched using a CF-based etching gas, for example, hexafluoroethane (C ₂ F ₆ ) can be used. This dry etching step is performed until the second layer 144b is removed in the n-side electrode region W6n and the p-side electrode region W6p to expose the first layer 144a. As a result, a sixth opening 86 exposing the first layer 144a in the n-side electrode region W6n and a seventh opening 87 exposing the p-side protective metal layer 42 in the p-side electrode region W6p are formed. As shown in FIG. 16, in this dry etching process, the exposed portion of the first layer 144a may be further removed by a predetermined depth. That is, a step may be formed on the top surface of the first layer 144a. After that, the sixth mask 66 is removed.

Next, as shown in FIG. 17, a seventh mask 67 is formed on the second covering layer 144. As shown in FIG. The seventh mask 67 is formed except for the n-side electrode region W7n corresponding to the n-side contact electrode 36 and the p-side electrode region W7p corresponding to the p-side contact electrode 40 . A seventh mask 67 is provided to completely cover the second layer 144b and to cover and protect the sidewalls of the second layer 144b in the sixth opening 86 and the seventh opening 87. FIG. Therefore, the opening width of the n-side electrode region W7n of the seventh mask 67 is smaller than the opening width of the n-side electrode region W6n of the sixth mask 66. FIG. Similarly, the opening width of the p-side electrode region W7p of the seventh mask 67 is smaller than the opening width of the p-side electrode region W6p of the sixth mask 66 . Subsequently, the first layer 144a of the second covering layer 144 is removed by dry etching 77 in the n-side electrode region W7n and the p-side electrode region W7p. The second coating layer 144 can be dry-etched using a CF-based etching gas, for example, hexafluoroethane (C ₂ F ₆ ) can be used. This dry etching step is performed until the first layer 144a is removed in the n-side electrode region W7n and the p-side electrode region W7p to expose the n-side protective metal layer 38 and the p-side protective metal layer . In this dry etching step, the n-side protective metal layer 38 and the p-side protective metal layer 42 function as etching stop layers, and can prevent damage to the underlying n-side contact electrode 36 and p-side contact electrode 40 . . As a result, an eighth opening 88 exposing the n-side protective metal layer 38 in the n-side electrode region W7n and a ninth opening 89 exposing the p-side protective metal layer 42 in the p-side electrode region W7p are formed. . After that, the seventh mask 67 is removed.

Next, as shown in FIG. 18, the n-side pad electrode 46 is formed on the n-side protective metal layer 38 exposed through the eighth opening 88, and the p-side protective metal layer 42 exposed through the ninth opening 89 is formed. A p-side pad electrode 48 is formed thereon. The pad electrodes 46 and 48 can be formed, for example, by depositing a Ni layer or a Ti layer and then depositing an Au layer thereon. Another metal layer may be provided on the Au layer, for example, a Sn layer, an AuSn layer, and a Sn/Au layered structure may be formed. Through the above steps, the die 112 shown in FIG. 14 is completed.

13, the die 112 is mounted on the mounting board 14, and the third covering layer 18 is formed so as to cover the entire surface of the die 112 mounted on the mounting board 14. FIG. The third coating layer 18 is made of Al ₂ O ₃ and is formed, for example, by the ALD method using TMA and H ₂ O as raw materials. Thereby, the semiconductor light emitting device 110 shown in FIG. 14 is completed.

The present invention has been described above based on the examples. Those skilled in the art will understand that the present invention is not limited to the above-described embodiments, and that various design changes and modifications are possible, and that such modifications are within the scope of the present invention. It is about to be done.

In the above embodiment, when the Al ₂ O ₃ layer is formed by the ALD method, the first step of introducing TMA and the second step of introducing O ₂ plasma, O ₃ or H ₂ O are alternately repeated. be In this case, the first step may be carried out first so that the surface to be coated with the Al ₂ O ₃ layer is first coated with TMA. That is, by performing the second step first, the surface to be covered with the Al ₂ O ₃ layer may be prevented from being damaged by being oxidized or etched by O ₂ plasma or the like. In particular, the side surfaces of the active layer 26 can be prevented from being damaged by applying TMA first when forming the first coating layer 34 covering the side surfaces of the active layer 26 . Thereby, the reliability of the semiconductor light emitting devices 10 and 110 can be improved.

In the above embodiments, instead of the n-side protective metal layer 38, an n-side protective layer made of conductive titanium nitride (TiN) may be used. Similarly, instead of the p-side protective metal layer 42, a p-side protective layer made of titanium nitride (TiN) may be used. Even when the n-side protective layer and the p-side protective layer made of TiN are used, the TiN layer can function as a stop layer in the dry etching process. In addition, by using TiN, the adhesion to the second covering layer 44 or the second covering layer 144 can be improved, and the peeling of the second covering layer 44 or the second covering layer 144 from the contact electrodes 36 and 38 is preferable. can be prevented.

In the above embodiments, the semiconductor light emitting devices 10 and 110 having the dies 12 and 112 mounted on the mounting substrate 14 are shown. In another embodiment, dies 12 and 112 that are not mounted on mounting substrate 14 may be used as semiconductor light emitting devices. In this case, the surfaces of the dies 12 and 112 may or may not be provided with the third coating layer 18 .

DESCRIPTION OF SYMBOLS 10... Semiconductor light-emitting element, 12... Die, 14... Mounting board, 16... Metal joining material, 18... Third coating layer, 20... Substrate, 24... N-type clad layer, 26... Active layer, 30... P-type clad layer , 32... Protective insulating layer 34... First covering layer 36... n-side contact electrode 40... p-side contact electrode 44... Second covering layer 46... n-side pad electrode 48... p-side pad electrode 52 Mounting electrodes, 52n n-side mounting electrodes, 52p p-side mounting electrodes.

Claims (12)

an n-type semiconductor layer of an n-type aluminum gallium nitride (AlGaN) based semiconductor material provided on a substrate;
an active layer of an AlGaN-based semiconductor material provided in a first region on the n-type semiconductor layer;
a p-type semiconductor layer of a p-type AlGaN semiconductor material provided on the active layer;
A second region different from the first region on the n-type semiconductor layer, a side surface of the active layer, and the p-type semiconductor layer are provided to cover the second region, and are made of aluminum oxide (Al ₂ O ₃ ). and a first coating layer having a film thickness of 10 nm or more and 50 nm or less;
an n-side contact electrode penetrating the first covering layer and contacting the n-type semiconductor layer;
a p-side contact electrode penetrating through the first covering layer and in contact with the p-type semiconductor layer;
a second coating layer provided to cover the first coating layer, the n-side contact electrode and the p-side contact electrode and having a thickness of 100 nm or more;
an n-side pad electrode penetrating through the second covering layer and connected to the n-side contact electrode;
a p-side pad electrode that penetrates the second covering layer and is connected to the p-side contact electrode ;
said second coating layer comprises a _SiO2 layer having a thickness greater than or equal to 10 times the thickness of said first coating layer ;
The semiconductor light emitting device , wherein the second coating layer further comprises a nitride layer covering the SiO2 layer _. an n-type semiconductor layer of an n-type aluminum gallium nitride (AlGaN) based semiconductor material provided on a substrate;
an active layer of an AlGaN-based semiconductor material provided in a first region on the n-type semiconductor layer;
a p-type semiconductor layer of a p-type AlGaN semiconductor material provided on the active layer;
A second region different from the first region on the n-type semiconductor layer, a side surface of the active layer, and the p-type semiconductor layer are provided to cover the second region, and are made of aluminum oxide (Al ₂ O ₃ ). a first coating layer coated with
an n-side contact electrode penetrating the first covering layer and contacting the n-type semiconductor layer;
a p-side contact electrode penetrating through the first covering layer and in contact with the p-type semiconductor layer;
a second covering layer provided to cover the first covering layer, the n-side contact electrode and the p-side contact electrode;
an n-side pad electrode penetrating through the second covering layer and connected to the n-side contact electrode;
a p-side pad electrode that penetrates the second covering layer and is connected to the p-side contact electrode;
The second coating layer is composed of a first layer made of a material having a lower refractive index than the material of the first coating layer and a material having a higher refractive index than the material of the first coating layer. and a second layer covering the one layer. It is provided so as to cover at least a part of each of the surface of the substrate, the second coating layer, the side surface of the n-side pad electrode and the side surface of the p-side pad electrode, and is made of aluminum oxide (Al ₂ O ₃ ). 3. The semiconductor light-emitting device according to claim 1, further comprising a third coating layer. further comprising a mounting substrate including an n-side mounting electrode connected to the n-side pad electrode and a p-side mounting electrode connected to the p-side pad electrode;
4. The semiconductor light emitting device according to claim 3, wherein said third covering layer is further provided so as to cover at least part of the surface of said mounting substrate. 5. The semiconductor light emitting device according to claim 3, wherein the concentration of hydrogen contained in said first coating layer is lower than the concentration of hydrogen contained in said third coating layer. 6. A protective insulating layer provided between the p-type semiconductor layer and the first covering layer and made of silicon oxide (SiO ₂ ) or silicon oxynitride (SiON), further comprising a protective insulating layer. The semiconductor light emitting device according to any one of 1. 3. The semiconductor light emitting device of claim 2, wherein the second coating layer comprises a _SiO2 layer having a thickness ten times or more that of the first coating layer. The semiconductor light emitting device of claim 7, wherein the second covering layer further comprises a nitride layer covering the _SiO2 layer. The n-type semiconductor layer has a molar fraction of aluminum nitride (AlN) of 20% or more,
9. The semiconductor light-emitting device according to claim 1, wherein said active layer is configured to emit ultraviolet light having a wavelength of 350 nm or less. On a substrate, an n-type semiconductor layer made of n-type aluminum gallium nitride (AlGaN) based semiconductor material, an active layer made of AlGaN based semiconductor material on the n-type semiconductor layer, and a p-type semiconductor layer made of p-type AlGaN based semiconductor material on the active layer a step of sequentially laminating the
removing portions of the p-type semiconductor layer, the active layer and the n-type semiconductor layer so as to expose a portion of the n-type semiconductor layer;
Aluminum oxide (Al ₂ O ₃ ) with a thickness of 10 nm or more and 50 nm or less so as to cover the exposed region of the n-type semiconductor layer, the side surface of the active layer, and the p-type semiconductor layer. forming a first coating layer;
partially removing the first covering layer to form an n-side contact electrode in contact with the n-type semiconductor layer;
partially removing the first covering layer to form a p-side contact electrode in contact with the p-type semiconductor layer;
forming a second coating layer having a thickness of 100 nm or more, covering the first coating layer, the n-side contact electrode, and the p-side contact electrode;
partially removing the second covering layer to form an n-side pad electrode connected to the n-side contact electrode;
forming a p-side pad electrode connected to the p-side contact electrode by partially removing the second covering layer ;
The step of forming the second coating layer comprises: forming a SiO2 layer having a thickness 10 times or more the thickness of the first coating layer; and _forming a nitride layer covering the SiO2 layer _. A method for manufacturing a semiconductor light emitting device , comprising : On a substrate, an n-type semiconductor layer made of n-type aluminum gallium nitride (AlGaN) based semiconductor material, an active layer made of AlGaN based semiconductor material on the n-type semiconductor layer, and a p-type semiconductor layer made of p-type AlGaN based semiconductor material on the active layer a step of sequentially laminating the
removing portions of the p-type semiconductor layer, the active layer and the n-type semiconductor layer so as to expose a portion of the n-type semiconductor layer;
forming a first covering layer made of aluminum oxide (Al ₂ O ₃ ) so as to cover the exposed region of the n-type semiconductor layer, the side surface of the active layer, and the p-type semiconductor layer; and,
partially removing the first covering layer to form an n-side contact electrode in contact with the n-type semiconductor layer;
partially removing the first covering layer to form a p-side contact electrode in contact with the p-type semiconductor layer;
forming a second covering layer covering the first covering layer, the n-side contact electrode, and the p-side contact electrode;
partially removing the second covering layer to form an n-side pad electrode connected to the n-side contact electrode;
forming a p-side pad electrode connected to the p-side contact electrode by partially removing the second covering layer;
The step of forming the second coating layer includes forming a first layer composed of a material having a lower refractive index than the material of the first coating layer, and a step of forming a first layer composed of a material having a higher refractive index than the material of the first coating layer. and forming a second layer covering the first layer. A third layer made of aluminum oxide (Al ₂ O ₃ ) so as to cover at least part of the surface of the substrate, the second coating layer, the side surface of the n-side pad electrode and the side surface of the p-side pad electrode. Further comprising the step of forming a coating layer,
The first coating layer is formed by an atomic layer deposition method using an organic aluminum compound and oxygen gas (O ₂ ) plasma or ozone gas (O ₃ ) as raw materials,
12. The method of manufacturing a semiconductor light-emitting device according to claim 10, wherein the third coating layer is formed by an atomic layer deposition method using an organoaluminum compound and water ( _H2O ) as raw materials. .

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