JP7307654B2 - switch device - Google Patents

Description

The invention disclosed in this specification relates to a switching device.

The applicant of the present application has previously proposed many new technologies regarding switch devices such as in-vehicle IPDs (intelligent power devices) (see Patent Document 1, for example).

WO2017/187785

However, the conventional switch device has room for further improvement in its overcurrent protection function.

An object of the invention disclosed in the present specification is to provide a switching device capable of applying appropriate overcurrent protection in view of the above problems found by the inventors of the present application.

A switch device disclosed in the present specification includes an output terminal to which a load is connected, a switch element connected to the output terminal, and an overcurrent limit for limiting an output current flowing through the switch element to an overcurrent limit value or less. a current protection circuit, wherein the overcurrent protection circuit sets the overcurrent limit value to a predetermined reference value irrespective of the chip temperature when a short-circuit abnormality of the output terminal does not occur; When a terminal short-circuit abnormality occurs, the higher the chip temperature, the lower the overcurrent limit value from the reference value (first configuration).

In the switch device having the first configuration, the overcurrent protection circuit includes a temperature detection section that detects the chip temperature, a short circuit detection section that detects a short circuit abnormality of the output terminal, the temperature detection section, and a a limit value setting unit that sets the overcurrent limit value according to detection results of both of the short circuit detection units; and an overcurrent detection unit that detects whether or not the output current has reached the overcurrent limit value. It is preferable to use a configuration (second configuration) that includes the

Further, in the switch device having the second configuration, the temperature detection unit uses a temperature detection element of a temperature protection circuit that forcibly turns off the switch element when the chip temperature is abnormally high (third configuration). should be

Further, in the switch device having the second or third configuration, the switch element is a high-side switch connected between the power supply terminal and the output terminal, and the short-circuit detection section is connected to the output terminal. A configuration for detecting a ground fault (fourth configuration) is preferable.

Further, in the switch device having the second or third configuration, the switch element is a low-side switch connected between the output terminal and the ground terminal, and the short-circuit detection section is connected between the output terminal and the ground terminal. A configuration (fifth configuration) for detecting a fault may be employed.

Further, in the switch device having any one of the second to fifth configurations, the limit value setting unit includes a first set current generation unit that generates a predetermined first set current, and a limit value that increases as the chip temperature increases. a second set current generation unit that generates a second set current, and sets a differential current obtained by subtracting the second set current from the first set current as the overcurrent limit value (sixth configuration) should be

Further, in the switch device having the sixth configuration, the limit value setting unit disables the second set current generation unit when the output terminal is not short-circuited, and the output terminal is short-circuited. A configuration (seventh configuration) may be employed in which the second set current generator is enabled when an abnormality occurs.

Further, the electronic equipment disclosed in this specification includes a switch device having any one of the first to seventh configurations, and a load connected to the switch device (eighth configuration). It is said that

In the electronic device having the eighth configuration, the load may be a bulb lamp, a relay coil, a solenoid, a light-emitting diode, or a motor (ninth configuration).

Further, the vehicle disclosed in this specification has a configuration (tenth configuration) having the electronic device having the above eighth or ninth configuration.

According to the invention disclosed in this specification, it is possible to provide a switch device capable of applying appropriate overcurrent protection.

FIG. 1 shows a semiconductor integrated circuit device according to a first embodiment; FIG. 4 is a diagram showing a configuration example of a gate control unit according to the first embodiment; 1 is a diagram showing a configuration example of an overcurrent protection circuit in the first embodiment; FIG. Diagram showing overcurrent protection operation in load short reliability test Diagram showing overcurrent protection operation (first example) when short-circuit detection is not performed FIG. 10 is a diagram showing overcurrent protection operation (second example) when short circuit detection is not performed; FIG. 4 is a diagram showing a configuration example of a temperature detection unit according to the first embodiment; FIG. 3 is a diagram showing a configuration example of a short-circuit detection unit according to the first embodiment; A diagram showing an example of a short-circuit detection operation (ground fault detection operation) in the first embodiment. FIG. 4 is a diagram showing a configuration example of a limit value setting unit according to the first embodiment; FIG. 4 is a diagram showing a configuration example of a first set current generator and a second set current generator; FIG. 4 is a diagram showing a configuration example of an overcurrent detection unit according to the first embodiment; The figure which shows 2nd Embodiment of a semiconductor integrated circuit device A diagram showing a configuration example of an overcurrent protection circuit according to the second embodiment. FIG. 11 is a diagram showing a configuration example of a temperature detection unit according to the second embodiment; FIG. 11 is a diagram showing a configuration example of a short-circuit detection unit according to the second embodiment; A diagram showing an example of a short-circuit detection operation (supply fault detection operation) in the second embodiment. The figure which shows one structural example of the limit value setting part in 2nd Embodiment. FIG. 11 is a diagram showing a configuration example of an overcurrent detection unit according to the second embodiment; External view showing one configuration example of a vehicle

<Semiconductor Integrated Circuit Device (First Embodiment)>
FIG. 1 is a diagram showing a first embodiment of a semiconductor integrated circuit device. The semiconductor integrated circuit device 1 of the present embodiment is an in-vehicle high-side switch LSI (=in-vehicle A type of IPD).

The semiconductor integrated circuit device 1 has external terminals T1 to T4 as means for establishing electrical connection with the outside of the device. The external terminal T1 is a power supply terminal (VBB pin) for receiving supply of a power supply voltage VBB (12 V, for example) from a battery (not shown). The external terminal T2 is a load connection terminal or an output terminal (OUT pin) for externally connecting a load 3 (bulb lamp, relay coil, solenoid, light emitting diode, motor, etc.). The external terminal T3 is a signal input terminal (IN pin) for receiving external input of the external control signal Si from the ECU 2 . The external terminal T4 is a signal output terminal (SENSE pin) for externally outputting the state notification signal So to the ECU2. An external sense resistor 4 is externally attached between the external terminal T4 and the ground terminal.

The semiconductor integrated circuit device 1 also includes an NMOSFET 10, an output current monitoring unit 20, a gate control unit 30, a control logic unit 40, a signal input unit 50, an internal power supply unit 60, an abnormality protection unit 70, and an output It is formed by integrating a current detection section 80 and a signal output section 90 .

The NMOSFET 10 is a high withstand voltage (for example, 42 V withstand voltage) power transistor having a drain connected to the external terminal T1 and a source connected to the external terminal T2. The NMOSFET 10 connected in this way functions as a switch element (high side switch) for conducting/interrupting a current path from the terminal to which the power supply voltage VBB is applied to the ground terminal via the load 3 . The NMOSFET 10 is turned on when the gate drive signal G1 is at high level, and turned off when the gate drive signal G1 is at low level.

Also, the NMOSFET 10 may be designed to have an on-resistance value of several tens of mΩ. However, the lower the on-resistance value of the NMOSFET 10, the more likely overcurrent will flow when a ground fault (=short-circuit to a ground terminal or a similar low-potential terminal) occurs in the external terminal T2, resulting in abnormal heat generation. Become. Therefore, the lower the on-resistance of the NMOSFET 10, the more important the overcurrent protection circuit 71 and temperature protection circuit 73, which will be described later.

The output current monitoring unit 20 includes NMOSFETs 21 and 21 ′ and a sense resistor 22 and generates a sense voltage Vs (=sense signal) according to the output current Io flowing through the NMOSFET 10 .

NMOSFETs 21 and 21' are both mirror transistors connected in parallel with NMOSFET 10, and generate sense currents Is and Is' according to the output current Io. The size ratio between NMOSFET 10 and NMOSFETs 21 and 21' is m:1 (where m>1). Therefore, the sense currents Is and Is' have the magnitude of the output current Io reduced by 1/m. As with the NMOSFET 10, the NMOSFETs 21 and 21' are turned on when the gate drive signal G1 is at high level, and turned off when the gate voltage G1 is at low level.

The sense resistor 22 (resistance value: Rs) is connected between the source of the NMOSFET 21 and the external terminal T2, and the sense voltage Vs (=Is×Rs+Vo) corresponding to the sense current Is, where Vo is applied to the external terminal T2. It is a current-to-voltage conversion element that produces an output voltage appearing.

The gate control unit 30 performs on/off control of the NMOSFETs 10 and 21 by generating a gate drive signal G1 obtained by increasing the current capability of the gate control signal S1 and outputting it to the gates of the NMOSFETs 10 and 21, respectively. The gate control section 30 has a function of controlling the NMOSFET 10 (and the NMOSFETs 21 and 21') so as to limit the output current Io according to the overcurrent protection signal S71.

The control logic unit 40 receives the internal power supply voltage Vreg and generates the gate control signal S1. For example, when the external control signal Si is at a high level (=the logic level for turning on the NMOSFET 10), the internal power supply voltage Vreg is supplied from the internal power supply section 60, so that the control logic section 40 is in an operating state to control the gate. The signal S1 becomes high level (=Vreg). On the other hand, when the external control signal Si is at a low level (=the logic level for turning off the NMOSFET 10), the internal power supply voltage Vreg is not supplied from the internal power supply section 60, so the control logic section 40 is in a non-operating state, and gate control is performed. The signal S1 becomes low level (=GND). In addition, the control logic unit 40 monitors various abnormal protection signals (overcurrent protection signal S71, open protection signal S72, temperature protection signal S73, and undervoltage protection signal S74). The control logic unit 40 also has a function of generating the output switching signal S2 according to the monitoring results of the overcurrent protection signal S71, the open protection signal S72, and the temperature protection signal S73 among the above-described abnormality protection signals. there is

The signal input unit 50 is a Schmitt trigger that receives the input of the external control signal Si from the external terminal T3 and transmits it to the control logic unit 40 and the internal power supply unit 60 . For example, the external control signal Si becomes high level when the NMOSFET 10 is turned on, and becomes low level when the NMOSFET 10 is turned off.

The internal power supply section 60 generates a predetermined internal power supply voltage Vreg from the power supply voltage VBB and supplies it to each section of the semiconductor integrated circuit device 1 . Whether or not the internal power supply unit 60 can operate is controlled according to the external control signal Si. More specifically, the internal power supply section 60 becomes active when the external control signal Si is at high level, and becomes non-operating when the external control signal Si is at low level.

The abnormality protection unit 70 is a circuit block for detecting various abnormalities of the semiconductor integrated circuit device 1, and includes an overcurrent protection circuit 71, an open protection circuit 72, a temperature protection circuit 73, and a low voltage protection circuit 74. .

The overcurrent protection circuit 71 generates an overcurrent protection signal S71 according to the monitoring result of the sense voltage Vs (=whether or not an overcurrent abnormality has occurred in the output current Io). For example, the overcurrent protection signal S71 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The open protection circuit 72 generates an open protection signal S72 according to the monitoring result of the output voltage Vo (=whether or not the load 3 has an open abnormality). For example, the open protection signal S72 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The temperature protection circuit 73 includes a temperature detection element (not shown) that detects abnormal heat generation in the semiconductor integrated circuit device 1 (especially around the NMOSFET 10), and detects the temperature according to the detection result (=whether abnormal heat generation occurs). Generate a protection signal S73. For example, the temperature protection signal S73 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The voltage reduction protection circuit 74 generates a voltage reduction protection signal S74 according to the monitoring result of the power supply voltage VBB or the internal power supply voltage Vreg (=whether or not a voltage reduction abnormality has occurred). For example, the low voltage protection signal S74 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The output current detection unit 80 generates a sense current Is' (=Io/m) corresponding to the output current Io by matching the source voltage of the NMOSFET 21' with the output voltage Vo using bias means (not shown). output to the signal output unit 90.

The signal output unit 90 outputs one of the sense current Is′ (=corresponding to the detection result of the output current Io) and the fixed voltage V90 (=corresponding to an abnormality flag, not explicitly shown in the figure) to an external device based on the output selection signal S2. It is selectively output to the terminal T4. When the sense current Is' is selectively output, the output detection voltage V80 (=Is'×R4 ) is transmitted to the ECU 2 . The output detection voltage V80 increases as the output current Io increases, and decreases as the output current Io decreases. On the other hand, when the fixed voltage V90 is selectively output, the fixed voltage V90 is transmitted to the ECU 2 as the state notification signal So. When reading the current value of the output current Io from the state notification signal So, the state notification signal So may be A/D [analog-to-digital] converted. On the other hand, when reading the abnormality flag from the state notification signal So, the logic level of the state notification signal So may be determined using a threshold value slightly lower than the fixed voltage V90.

<Gate control unit (first embodiment)>
FIG. 2 is a diagram showing a configuration example of the gate control section 30 in the first embodiment. The gate control unit 30 of this configuration example includes a gate driver 31, an oscillator 32, a charge pump 33, a clamper 34, an NMOSFET 35, a resistor 36 (resistance value: R36), and a capacitor 37 (capacitance value: C37). , Zener diode 38 .

The gate driver 31 is connected between the output end of the charge pump 33 (=the end to which the boosted voltage VG is applied) and the external terminal T2 (=the end to which the output voltage Vo is applied), and controls the current capability of the gate control signal S1. A raised gate drive signal G1 is generated. The gate drive signal G1 becomes high level (=VG) when the gate control signal S1 is high level, and becomes low level (=Vo) when the gate control signal S1 is low level.

The oscillator 32 generates a clock signal CLK having a predetermined frequency and outputs it to the charge pump 33 . Whether or not the oscillator 32 can operate is controlled according to an enable signal Sa from the control logic unit 40 .

The charge pump 33 is an example of a booster that generates a boosted voltage VG higher than the power supply voltage VBB by driving a flying capacitor using the clock signal CLK and supplies the boosted voltage VG to the gate driver 31 . Whether or not the charge pump 33 operates is controlled according to the enable signal Sb from the control logic unit 40 .

The clamper 34 is connected between the external terminal T<b>1 (=application terminal of the power supply voltage VBB) and the gate of the NMOSFET 10 . In an application in which an inductive load 3 is connected to the external terminal T2, when the NMOSFET 10 is switched from on to off, the back electromotive force of the load 3 causes the output voltage Vo to become a negative voltage (<GND). Therefore, a clamper 34 (so-called active clamp circuit) is provided for energy absorption.

The drain of NMOSFET 35 is connected to the gate of NMOSFET 10 . The source of NMOSFET 35 is connected to external terminal T2. The gate of the NMOSFET 35 is connected to the application end of the overcurrent protection signal S71. A resistor 36 and a capacitor 37 are connected in series between the drain and gate of the NMOSFET 35 .

The cathode of Zener diode 38 is connected to the gate of NMOSFET 10 . The anode of Zener diode 38 is connected to the source of NMOSFET 10 . The Zener diode 38 connected in this manner functions as a clamping element that limits the gate-source voltage (=VG-Vo) of the NMOSFET 10 to a predetermined value or less.

In the gate control unit 30 of this configuration example, when the overcurrent protection signal S71 is raised to a high level, the gate drive signal G1 changes from a steady high level (=VG) to a predetermined time constant τ (=R36×C37). is lowered by As a result, the conductivity of the NMOSFET 10 gradually decreases, so that the output current Io is limited. On the other hand, when the overcurrent protection signal S71 is lowered to a low level, the gate drive signal G1 is raised with a predetermined time constant τ. As a result, the conductivity of the NMOSFET 10 gradually increases, so that the restriction on the output current Io is lifted.

Thus, the gate control section 30 of this configuration example has a function of controlling the gate drive signal G1 so as to limit the output current Io according to the overcurrent protection signal S71.

<Study on overcurrent protection>
By the way, in the semiconductor integrated circuit device 1, which requires high reliability as an in-vehicle IPD, the NMOSFET 10 is connected to the NMOSFET 10 while the external terminal T2 (=output terminal) is shorted to power supply or grounded via a path having an inductance (for example, 5 μH). A load short-circuit reliability test (AEC-Q100-012) is imposed, in which the on/off is repeated for multiple cycles (300 cycles to 1 million cycles depending on the grade).

If the overcurrent limit value Iocd of the overcurrent protection circuit 71 is set to several tens of A to 100 A due to the low on-resistance of the NMOSFET 10 in recent years, the NMOSFET 10 can generate a large power of several hundred W to 1000 W. is consumed. Therefore, in the semiconductor integrated circuit device 1, the NMOSFET 10 is repeatedly turned on/off in the overheat detection state (high temperature state).

At such a high temperature, the durability of the NMOSFET 10 also deteriorates due to the influence of heat. Therefore, in order to clear the load short-circuit reliability test, it is common to lower the overcurrent limit value Iocd to suppress the power consumption (and heat generation) of the NMOSFET 10. FIG.

However, the semiconductor integrated circuit device 1 can also be connected to a load 3 that requires a very large output current Io (100A class). Therefore, it is not desirable to simply lower the overcurrent limit value Iocd.

In view of the above considerations, the following proposes an overcurrent protection circuit 71 capable of ensuring both normal current capacity and improved safety at high temperatures.

<Overcurrent protection circuit (first embodiment)>
FIG. 3 is a diagram showing a configuration example of the overcurrent protection circuit 71. As shown in FIG. The overcurrent protection circuit 71 of this configuration example includes a temperature detection section 71A, a short circuit detection section 71B, a limit value setting section 71C, and an overcurrent detection section 71D.

The temperature detector 71A detects a chip temperature Tj and generates a temperature detection signal SA. Note that the chip temperature Tj is the pn junction temperature near the NMOSFET 10, for example. Also, the temperature detection signal SA is, for example, an analog voltage signal corresponding to the chip temperature Tj.

By monitoring the output voltage Vo, the short-circuit detection unit 71B detects a ground fault of the external terminal T2 and generates a short-circuit detection signal SB. The short-circuit detection signal SB is, for example, a binary signal that becomes low level when a ground fault is detected and becomes high level when a ground fault is not detected.

The limit value setting unit 71C sets an overcurrent limit value Iocd (also referred to as an overcurrent detection current Iocd in this specification) according to both the temperature detection signal SA and the short circuit detection signal SB. More specifically, when the ground fault of the external terminal T2 does not occur (SB=H), the limit value setting unit 71C does not depend on the temperature detection signal SA (and thus the chip temperature Tj) An overcurrent limit value Iocd is set to a predetermined reference value. On the other hand, when the external terminal T2 is grounded (SB=L), the limit value setting unit 71C reduces the overcurrent limit value Iocd from the reference value as the chip temperature Tj increases according to the temperature detection signal SA. reduce. For example, the overcurrent limit value Iocd is inversely proportional to the chip temperature Tj (Iocd∝1/Tj).

The overcurrent detection unit 71D monitors the sense voltage Vs to detect whether the sense current Is (and thus the output current Io) has reached the overcurrent limit value Iocd, and generates an overcurrent protection signal S71. do.

In the overcurrent protection circuit 71 configured as described above, the overcurrent limit value Iocd is set to a predetermined reference value regardless of the chip temperature Tj when the external terminal T2 is not grounded. Therefore, it is possible to make the most of the current capability of the NMOSFET 10 .

On the other hand, when the external terminal T2 is grounded, the overcurrent limit value Iocd is lowered from its reference value as the chip temperature Tj rises. Therefore, the higher the chip temperature Tj, the smaller the output current Io can be reduced, so that the power consumption (and the heat generation) of the NMOSFET 10 can be suppressed.

In this way, by implementing a variable control function for the overcurrent limit value Iocd in response to both the temperature detection signal SA and the short circuit detection signal SB, it is possible to ensure both normal current capacity and improved safety at high temperatures. becomes possible.

FIG. 4 is a diagram showing the overcurrent protection operation in the load short-circuit reliability test. From the top, output current Io (solid line), overcurrent limit value Iocd (large dashed line), chip temperature Tj, and short circuit detection. Signal SB is depicted. Although the output current Io and the overcurrent limit value Iocd are not originally directly compared, for convenience of explanation, they are depicted as being directly compared in this figure.

As shown in this figure, in the load short reliability test, when the NMOSFET 10 is repeatedly turned on and off with the external terminal T2 grounded (SB=L), the NMOSFET 10 generates heat and the chip temperature Tj rises. continue. At this time, the overcurrent limit value Iocd is lowered from the reference value as the chip temperature Tj rises, so heat generation of the NMOSFET 10 is suppressed. Therefore, it is possible to prevent deterioration in durability of the NMOSFET 10 due to the influence of heat, and to fully satisfy the standard of the load short-circuit reliability test.

<Significance of introduction of short-circuit detector>
Next, the significance of the introduction of the short-circuit detection section 71B will be supplementarily explained. If the overcurrent limit value Iocd is variably controlled based only on the temperature detection signal SA without introducing the short-circuit detection unit 71B, the chip temperature Tj will be reduced even when the external terminal T2 is not grounded. As it rises, the overcurrent limit value Iocd is lowered from its reference value. Therefore, the normal operation and start-up operation of the semiconductor integrated circuit device 1 may be hindered. A specific description will be given below with reference to the drawings.

5 and 6 are diagrams respectively showing overcurrent protection operations (first and second examples) when short-circuit detection is not performed. From the top, external control signal Si, output current Io (solid line) , the overcurrent limit value Iocd (large dashed line), and the chip temperature Tj are depicted. Although the output current Io and the overcurrent limit value Iocd are not originally directly compared, for the convenience of explanation, they are illustrated as being directly compared in each drawing.

For example, as shown in FIG. 5, as the chip temperature Tj rises during normal operation, the overcurrent limit value Iocd changes to the normal value of the output current Io (=current value required by the load 3; ), it becomes impossible to supply the load 3 with a sufficient output current Io.

Further, for example, if the load 3 is a capacitive load (such as a bulb lamp), as shown in FIG. 6, a large output current Io (=capacitive load charging current, FIG. (see small dashed line in the middle) should be output. However, if the overcurrent limit value Iocd is lowered from the reference value due to heat generated during startup, the output current Io is limited to a small value, so it takes a long time to charge the capacitive load, which can cause startup delays. .

On the other hand, if the short-circuit detector 71B is introduced as trigger means for determining whether or not to perform variable control of the overcurrent limit value Iocd according to the chip temperature Tj, the overcurrent limit value Iocd will be detected as long as the external terminal T2 is not grounded. Since the current limit value Iocd is never lowered from the reference value, the normal operation and start-up operation of the semiconductor integrated circuit device 1 are not disturbed.

Subsequently, each part of the overcurrent protection circuit 71 (the temperature detection part 71A, the short circuit detection part 71B, the limit value setting part 71C, and the overcurrent detection part 71D) will be specifically described in detail with reference to the drawings. .

<Temperature detector (first embodiment)>
FIG. 7 is a diagram showing a configuration example of the temperature detection section 71A (=an example in which part of the temperature protection circuit 73 is used as the temperature detection section 71A). The temperature detection unit 71A (or the temperature protection circuit 73) of this configuration example includes P-channel MOS field effect transistors A1 to A3, a current source A4, diodes A5 to A7, resistors A8 and A9, a comparator A10, It includes an N-channel MOS field effect transistor A11 and an inverter A12.

The sources of the transistors A1 to A3 are all connected to the application end of the internal power supply voltage Vreg. The gates of the transistors A1 to A3 are all connected to the drain of the transistor A1. The drain of the transistor A1 is connected to the current source A4 (=means for generating the reference current IREF). The transistors A1 to A3 connected in this way form a current mirror that mirrors the reference current IREF input to the drain of the transistor A1 and outputs it from the drains of the transistors A2 and A3.

The drain of transistor A2 and the anode of diode A5 are both connected to the application terminal of node voltage VA1. The cathode of diode A5 is connected to the anode of diode A6. The cathode of diode A6 is connected to the anode of diode A7. The cathode of diode A7 is connected to ground. The diodes A5 to A7 connected in this way function as temperature detection elements that generate a node voltage VA1 (=temperature dependent voltage) according to the chip temperature Tj.

More specifically, the node voltage VA1 is a voltage (=3Vf) obtained by adding forward voltage drops Vf of the diodes A5 to A7, and has a negative temperature characteristic with respect to the chip temperature Tj. That is, the higher the chip temperature Tj, the lower the node voltage VA, and the lower the chip temperature Tj, the higher the node voltage VA. Note that the temperature detection unit 71A outputs the node voltage VA1 as the temperature detection signal SA.

The drain of transistor A3 and the first end of resistor A8 are connected to the application end of node voltage VA2. A second end of resistor A8 is connected to a first end of resistor A9. A second end of the resistor A9 is connected to the ground end.

The comparator A10 compares the node voltage VA1 input to the non-inverting input terminal (+) and the node voltage VA2 input to the inverting input terminal (-) to generate a comparison signal VA3. The comparison signal VA3 becomes high level when VA1>VA2, and becomes low level when VA1<VA2.

The drain of transistor A11 is connected to the connection node between resistors A8 and A9. The source of transistor A11 is connected to the ground terminal. The gate of the transistor A11 is connected to the application terminal of the comparison signal VA3. The transistor A11 turns on when VA3=H and turns off when VA3=L. When the transistor A11 is on, the node voltage VA2 drops because the resistor A9 is short-circuited across both ends. On the other hand, when the transistor A11 is off, the node voltage VA2 rises because the resistor A9 is open across both ends. By turning on/off the transistor A11 in accordance with the comparison signal VA3 in this manner, the node voltage VA2 can have hysteresis.

Inverter A12 generates temperature protection signal S73 (=inverted comparison signal VA3B) by inverting the logic level of comparison signal VA3. Therefore, the temperature protection signal S73 becomes low level (=logical level when no abnormality is detected) when VA1>VA2, and becomes high level (=logic level when abnormality is detected) when VA<VA2. When the chip temperature Tj is abnormally high (S73=H), the NMOSFET 10 is forcibly turned off.

In this manner, the temperature detection unit 71A may generate the temperature detection signal SA (=node voltage VA1) using the diodes A5 to A7, which are the temperature detection elements of the temperature protection circuit 73. FIG. According to this configuration, the temperature detection section 71A can be mounted without increasing the circuit scale.

<Short circuit detector (first embodiment)>
FIG. 8 is a diagram showing a configuration example of the short-circuit detection section 71B (ground fault detection section). The short circuit detector 71B of this configuration example includes resistors B1 and B2, a current source B3, a comparator B4, a logic gate B5, and a P-channel MOS field effect transistor B6.

A first terminal of the resistor B1 is connected to an application terminal (=external terminal T1) of the power supply voltage VBB. A second end of the resistor B1 is connected to a first end of the resistor B2. The second end of the resistor B2 and the first end of the current source B3 are both connected to the application end of the node voltage VB. The second end of the current source B3 is connected to the application end of the reference voltage VREG (=VBB-5V).

The comparator B4 compares the output voltage Vo input to the non-inverting input terminal (+) from the external terminal T2 with the node voltage VB1 input to the inverting input terminal (-) to generate a comparison signal VB2. The comparison signal VB2 becomes high level when Vo>VB1, and becomes low level when Vo<VB1.

Logic gate B5 receives the input of comparison signal VB2 and outputs short-circuit detection signal SB. When a buffer is used as the logic gate B5, the short-circuit detection signal SB becomes high level (=logical level when no ground fault is detected) when VB2=H, and becomes low level (=logic level when the ground fault is not detected) when VB2=L. = logical level when ground fault is detected).

The source of the transistor B6 is connected to the application terminal of the power supply voltage VBB. The drain of transistor B6 is connected to the connection node between resistors B1 and B2. The gate of the transistor B6 is connected to the application end of the short-circuit detection signal SB (or the comparison signal VB2 is also possible). Transistor B6 turns on when SB=L and turns off when SB=H. When the transistor B6 is on, the node voltage VB1 rises because the resistor B1 is short-circuited across both ends. On the other hand, when the transistor B6 is off, the node voltage VB1 drops because the resistor B1 is opened across the two ends. Thus, by turning on/off the transistor B6 according to the short-circuit detection signal SB, the node voltage VB1 can have hysteresis.

FIG. 9 is a diagram showing an example of the short-circuit detection operation (ground fault detection operation) in the short-circuit detection section 71B, in which the output voltage Vo and the short-circuit detection signal SB are depicted in order from the top. When the short-circuit detection signal SB is at high level (=logic level when no ground fault is detected), the transistor B6 is turned off, so the node voltage VB1 is set to the lower threshold VB1L (=ground fault detection threshold).

When a ground fault occurs in the external terminal T2 and the output voltage Vo falls below the lower threshold value VB1L, the short circuit detection signal SB falls to low level (=logical level at the time of ground fault detection). At this time, the transistor B6 is turned on, so the node voltage VB1 is raised to the upper threshold VB1H (=ground fault release threshold).

When the ground fault of the external terminal T2 is resolved and the output voltage Vo exceeds the upper threshold value VB1H, the short circuit detection signal SB rises to high level. At this time, the transistor B6 is turned off, so the node voltage VB1 is again lowered to the lower threshold VB1L.

<Limit value setting unit (first embodiment)>
FIG. 10 is a diagram showing a configuration example of the limit value setting section 71C. The limit value setting unit 71C of this configuration example includes a first set current generation unit C1, a second set current generation unit C2, a level shifter C3, P-channel MOS field effect transistors C4 to C7, and an N-channel MOS field effect transistor. and effect transistors C8-C12.

The first set current generator C1 generates a first set current Iocd1 set to a predetermined fixed current value (eg, 2 μA).

The second set current generator C2 generates a second set current Iocd2 of a variable current value (for example, maximum 1 μA) that increases as the chip temperature Tj increases according to the temperature detection signal SA.

The level shifter C3 shifts the short circuit detection signal SB to an appropriate signal level and outputs it to the gate of the transistor C8.

The sources of the transistors C4 and C5 are both connected to the application terminal of the power supply voltage VBB. The gates of transistors C4 and C5 are both connected to the drain of transistor C4. The drain of the transistor C4 is connected to the output terminal of the second set current generator C2. The transistors C4 and C5 connected in this manner form a current mirror CM1 that mirrors the second set current Iocd2 input to the drain of the transistor C4 and outputs it from the drain of the transistor C5.

The sources of the transistors C6 and C7 are both connected to the application terminal of the power supply voltage VBB. The gates of transistors C6 and C7 are both connected to the drain of transistor C6. The drain of the transistor C6 is connected to the output terminal of the first set current generator C1. The transistors C6 and C7 connected in this manner form a current mirror CM2 that mirrors the first set current Iocd1 input to the drain of the transistor C6 and outputs it from the drain of the transistor C7.

The sources of the transistors C9 and C10 are both connected to the application terminal of the reference voltage VBBM5 (=VBB-5V). Note that the reference voltage VBBM5 drops to a negative voltage together with the output voltage Vo during the active clamp operation, unlike the reference voltage VREG (=VBB-5V) described above. The gates of transistors C9 and C10 are both connected to the drain of transistor C9. The drain of the transistor C9 is connected to the drain of the transistor C5 (=mirror output terminal of the second set current Iocd2). The transistors C9 and C10 connected in this manner form a current mirror CM3 that mirrors the second set current Iocd2 input to the drain of the transistor C9 and outputs it from the drain of the transistor C10.

The drain of transistor C8 is connected to the drain of transistor C9. The source of transistor C8 is connected to the source of transistor C9. The gate of the transistor C8 is connected to the input end of the short circuit detection signal SB via the level shifter C3. The transistor C8 turns on when SB=H (logic level when ground fault is not detected) and turns off when SB=L (logic level when ground fault is detected).

When the transistor C8 is on, the second set current Iocd2 does not flow through the drain of the transistor C9, so the current mirror CM3 is disabled. On the other hand, when the transistor C8 is off, the current mirror CM3 is enabled because the second set current Iocd2 flows through the drain of the transistor C9. The enable state/disable state of the current mirror CM3 is equivalent to the enable state/disable state of the second set current generator C2, respectively.

In this manner, the limit value setting unit 71C performs on/off control of the transistor C8 according to the short-circuit detection signal SB, thereby setting the second setting value when the ground fault of the external terminal T2 does not occur (SB=H). The current generator C2 is disabled, and the second set current generator C2 is enabled when the external terminal T2 is grounded (SB=L).

The sources of the transistors C11 and C12 are both connected to the application end of the reference voltage VBBM5. The gates of the transistors C11 and C12 are both connected to the drain of the transistor C11. The drain of transistor C11 is connected to the drains of transistors C7 and C10, respectively. Therefore, a differential current (=Iocd1-Iocd2) obtained by subtracting the second set current Iocd2 from the first set current Iocd1 is input to the drain of the transistor C11. The transistors C11 and C12 connected in this manner form a current mirror CM4 that mirrors the differential current (=Iocd1-Iocd2) input to the drain of the transistor C11 and outputs the overcurrent detection current Iocd from the drain of the transistor C12. are doing.

In the limit value setting unit 71C configured as described above, for example, when SB=H (logical level when no ground fault is detected), the current mirror CM3 is disabled, so that the overcurrent detection current Iocd is set as the first setting. The current Iocd1 (=2 μA) is output as it is. This state corresponds to a state in which the overcurrent limit value Iocd is set to the reference value.

On the other hand, when SB=L (logical level at the time of ground fault detection), the current mirror CM3 is enabled, so the differential current (=Iocd1-Iocd2) is output as the overcurrent detection current Iocd. That is, the overcurrent detection current Iocd decreases as the chip temperature Tj rises (and thus the second set current Iocd2 increases). This state corresponds to a state in which the overcurrent limit value Iocd is lowered from the reference value.

Note that the current mirrors CM1 to CM4 not only generate the overcurrent detection current Iocd by subtracting the second set current Iocd2 from the first set current Iocd1, but also It also has a function as a level shifter that connects the part C2 and the subsequent overcurrent detection part 71D.

FIG. 11 is a diagram showing one configuration example of each of the first set current generator C1 and the second set current generator C2. The first set current generator C1 (framed by a dashed line) in this configuration example includes P-channel MOS field effect transistors P1 and P2, N-channel MOS field effect transistors N1 and N2, and a current source CS. On the other hand, the second set current generator C2 (framed by a two-dot chain line) in this configuration example includes P-channel MOS field effect transistors P1 and P3 to P6, N-channel MOS field effect transistors N3 to N6, and a resistor R1. , a current source CS. That is, the transistor P1 and the current source CS are shared by both the first set current generator C1 and the second set current generator C2.

The sources of the transistors P1 to P4 are all connected to the application terminal of the internal power supply voltage Vreg. The gates of the transistors P1 to P4 are all connected to the drain of the transistor P1. A drain of the transistor P1 is connected to a current source CS (means for generating a reference current IREF). The transistors P1 to P4 connected in this way form a current mirror that mirrors the reference current IREF input to the drain of the transistor P1 and outputs it from the respective drains of the transistors P2 to P4. Note that the transistor P1 and the current source CS may be the transistor A1 and the current source A4 (see FIG. 7) of the temperature detection section 71A.

The sources of the transistors N1 and N2 are both connected to the ground terminal. The gates of transistors N1 and N2 are both connected to the drain of transistor N1. The drain of transistor N1 is connected to the drain of transistor P2 (=mirror output of reference current IREF). The transistors N1 and N2 connected in this manner form a current mirror that mirrors the reference current IREF input to the drain of the transistor N1 and outputs the first set current Iocd1 from the drain of the transistor N2.

The drain of the transistor P2 and the first end of the resistor R1 are both connected to the application end of the node voltage VC. A second end of the resistor R1 is connected to the ground end. Note that the node voltage VC corresponds to a threshold voltage for temperature derating. The sources of transistors P5 and P6 are both connected to the drain of transistor P4. A gate of the transistor P5 is connected to the input terminal of the temperature detection signal SA. The gate of the transistor P6 is connected to the application terminal of the node voltage VC. The drain of transistor N3 is connected to the drain of transistor P5. The drain of transistor N4 is connected to the drain of transistor P6. The sources of transistors N3 and N4 are both connected to the ground terminal. The gates of transistors N3 and N4 are both connected to the drain of transistor N4.

The transistors P5 and P6 and the transistors N3 and N4 connected in this way generate a current signal IC corresponding to the difference (=VC-SA) between the temperature detection signal SA and the node voltage VC and output it from the drain of the transistor N3. It functions as a gm amplifier (transconductance amplifier).

The current signal IC is, for example, 0 A when SA>VC, and increases from 0 A to a maximum of 1 μA according to the difference (=VC-SA) when SA<VC.

The sources of transistors N5 and N6 are both connected to the ground terminal. The gates of transistors N5 and N6 are both connected to the drain of transistor N5. The drain of the transistor N5 is connected to the drain of the transistor N3 (the output end of the current signal SC). The transistors N5 and N6 connected in this manner form a current mirror that mirrors the current signal IC input to the drain of the transistor N5 and outputs it from the drain of the transistor N6 as the second set current Iocd2.

<Overcurrent detector (first embodiment)>
FIG. 12 is a diagram showing a configuration example of the overcurrent detection section 71D. The overcurrent detector 71D of this configuration example includes P-channel MOS field effect transistors D1 to D3, N-channel MOS field effect transistors D4 and D5, and a resistor D6.

The sources of the transistors D1 to D3 are all connected to the application end of the boosted voltage VG. Gates of the transistors D1 to D3 are all connected to the drain of the transistor D1. The drain of the transistor D1 is connected to the input terminal of the overcurrent detection current Iocd (=corresponding to the overcurrent limit value Iocd).

The transistors D1 to D3 connected in this manner form a current mirror that mirrors the overcurrent detection current Iocd input to the drain of the transistor D1 and outputs the reference current Iref from the respective drains of the transistors D2 and D3. .

The drain of transistor D2 is connected to the drain of transistor D4. The drain of the transistor D3 is connected to the drain of the transistor D5 and the output end of the overcurrent protection signal S71. The gates of transistors D4 and D5 are both connected to the drain of transistor D4.

The source of the transistor D4 is connected to the first end of the resistor D6 (resistance value: Rref). A second terminal of the resistor D6 is connected to an application terminal (=external terminal T2) of the output voltage Vo. The source of the transistor D5 is connected to the application terminal of the sense voltage Vs.

In the overcurrent detection section 71D configured as described above, the reference voltage Vref (=Iref×Rref+Vo) is applied to the source of the transistor D4. On the other hand, a sense voltage Vs (=Is×Rs+Vo) corresponding to the sense current Is (and the output current Io) is applied to the source of the transistor D5. Therefore, the overcurrent protection signal S71 drawn from the drain of the transistor D5 becomes low level (=logical level when no abnormality is detected) when the sense voltage Vs is lower than the reference voltage Vref, and the sense voltage Vs is lower than the reference voltage Vref. is high (=logical level at the time of abnormality detection).

<Semiconductor Integrated Circuit Device (Second Embodiment)>
FIG. 13 is a diagram showing a second embodiment of a semiconductor integrated circuit device. The semiconductor integrated circuit device 1 of this embodiment is an in-vehicle low-side switch LSI (=a type of in-vehicle IPD) that conducts/disconnects between a load 3 and a ground terminal.

The semiconductor integrated circuit device 1 has external terminals T11 to T13 as means for establishing electrical connection with the outside of the device. The external terminal T11 is a load connection terminal or an output terminal (OUT pin) for externally connecting a load 3 (bulb lamp, relay coil, solenoid, light emitting diode, motor, etc.). The external terminal T12 is a ground terminal (GND pin) connected to the ground terminal. The external terminal T13 is a signal input terminal (IN pin) for receiving an external input of the external control signal IN.

The semiconductor integrated circuit device 1 is formed by integrating the NMOSFET 110, the output current monitoring section 120, the gate control section 130, and the overcurrent protection circuit 171. FIG. The semiconductor integrated circuit device 1 also integrates other circuit blocks (for example, see FIG. 1), but their illustration and explanation are omitted here.

The NMOSFET 110 is a high withstand voltage (for example, 42 V withstand voltage) power transistor having a drain connected to the external terminal T11 and a source connected to the external terminal T12. The NMOSFET 110 connected in this manner functions as a switch element (low-side switch) for conducting/interrupting a current path from the terminal to which the power supply voltage VBB is applied to the ground terminal via the load 3 . The NMOSFET 110 is turned on when the gate drive signal G1 is at high level, and turned off when the gate drive signal G1 is at low level.

Also, the NMOSFET 110 may be designed to have an on-resistance value of several tens of mΩ, like the NMOSFET 10 described above. However, the lower the on-resistance of the NMOSFET 110, the more likely overcurrent will flow when the external terminal T11 is short-circuited (=short-circuited to the terminal to which the power supply voltage VBB is applied or to a high-potential terminal). Fever easily occurs. Therefore, as the on-resistance value of the NMOSFET 110 is lowered, the importance of the overcurrent protection circuit 171 and temperature protection circuit (not shown) increases.

The output current monitoring unit 120 includes an NMOSFET 121 and a sense resistor 122 and generates a sense voltage Vs according to the output current Io flowing through the NMOSFET 110 .

The NMOSFET 121 is a mirror transistor connected in parallel with the NMOSFET 110 and generates a sense current Is corresponding to the output current Io. The size ratio between NMOSFET 110 and NMOSFET 121 is m:1 (where m>1). Therefore, the sense current Is has a magnitude obtained by reducing the output current Io to 1/m. As with the NMOSFET 110, the NMOSFET 121 is turned on when the gate drive signal G1 is at high level and turned off when the gate voltage G1 is at low level.

The sense resistor 122 (resistance value: Rs) is connected between the source of the NMOSFET 121 and the external terminal T12, and is a current/voltage conversion element that generates a sense voltage Vs (=Is×Rs) corresponding to the sense current Is. is.

The gate control unit 130 is a circuit block that performs on/off control of the NMOSFETs 110 and 121 by generating a gate drive signal G1 according to the external control signal IN. A resistor 136 and a capacitor 137 are included.

The gate driver 131 includes a switch 131a, a P-channel MOS field effect transistor 131b, and resistors 131c and 131d. A first terminal of the switch 131a and a gate of the transistor 131b are both connected to the external terminal T13. A second end of the switch 131a is connected to a first end of the resistor 131c. The source of the transistor 131b and the second end of the resistor 131c are both connected to the output end of the gate drive signal G1. The drain of transistor 131b is connected to the first end of resistor 131d. A second end of the resistor 131d is connected to the external terminal T12.

The switch 131a is turned on/off according to the inverted low voltage detection signal UVLOB (=logically inverted signal of the low voltage detection signal UVLO). More specifically, the switch 131a turns on when UVLOB=H (UVLO=L) and turns off when UVLOB=L (UVLO=H).

In the semiconductor integrated circuit device 1, which is a low-side switch LSI, the external control signal IN functions not only as an on/off control signal for the NMOSFET 110, but also as a driving voltage for driving each part of the semiconductor integrated circuit device 1. used.

Therefore, the logic level of the inverted low voltage detection signal UVLOB (and the low voltage detection signal UVLO) is switched depending on whether the external control signal IN is input, and the ON/OFF state of the switch 131a is switched. More specifically, when IN=L, UVLOB=L (logical level when low voltage is detected) and switch 131a is turned off. On the other hand, when IN=H, UVLOB=H (logic level when low voltage is not detected), and switch 131a is turned on.

Also, the transistor 131b is turned on/off according to the external control signal IN. More specifically, transistor 131b turns off when IN=H and turns on when IN=L.

That is, in the gate driver 131 of this configuration example, when IN=H, the switch 131a is turned on and the transistor 131b is turned off. As a result, the NMOSFET 110 is turned on because the gate drive signal G1 is raised to a high level. Note that the rising speed of the gate drive signal G1 (=the slew rate when ON) can be arbitrarily set by adjusting the resistor 131c.

On the other hand, when IN=L, the switch 131a is turned off and the transistor 131b is turned on. As a result, the NMOSFET 110 is turned off because the gate drive signal G1 is lowered to a low level. Note that the falling speed of the gate driving signal G1 (=the slew rate when turned off) can be arbitrarily set by adjusting the resistor 131d.

The clamper 134 is connected between the external terminal T<b>11 (=applying terminal of the output voltage Vo) and the gate of the NMOSFET 110 . In an application in which an inductive load 3 is connected to the external terminal T11, when the NMOSFET 110 is switched from ON to OFF, the back electromotive force of the load 3 causes the output voltage Vo to become a positive voltage (>VBB) higher than the power supply voltage VBB. Become. Therefore, a clamper 134 (so-called active clamp circuit) is provided for energy absorption.

The drain of the NMOSFET 135 is connected to the gate of the NMOSFET 110 (=application terminal of the gate driving signal G1). The source of NMOSFET 135 is connected to external terminal T12. The gate of the NMOSFET 135 is connected to the application end of the overcurrent protection signal S171. A resistor 136 and a capacitor 137 are connected in series between the drain and gate of the NMOSFET 135 .

In the gate control unit 130 of this configuration example, when the overcurrent protection signal S171 is raised to a high level (=logical level at the time of overcurrent detection), the gate drive signal G1 changes from a high level (=IN) in a steady state to a predetermined level. is lowered with a time constant τ (=R136×C137). As a result, the conductivity of the NMOSFET 110 gradually decreases, so that the output current Io is limited. On the other hand, when the overcurrent protection signal S171 is lowered to a low level (=logical level when overcurrent is not detected), the gate drive signal G1 is raised with a predetermined time constant τ. As a result, the conductivity of the NMOSFET 110 gradually increases, so the restriction on the output current Io is lifted.

Thus, the gate control section 130 of this configuration example has a function of controlling the gate drive signal G1 so as to limit the output current Io according to the overcurrent protection signal S171. This point is the same as the gate control unit 30 of the first embodiment (FIG. 2).

The overcurrent protection circuit 171 generates an overcurrent protection signal S171 according to the monitoring result of the sense voltage Vs (=whether an overcurrent abnormality occurs in the output current Io). For example, the overcurrent protection signal S171 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

<Overcurrent Protection Circuit (Second Embodiment)>
FIG. 14 is a diagram showing a configuration example of the overcurrent protection circuit 171. As shown in FIG. The overcurrent protection circuit 171 of this configuration example includes a temperature detection section 171A, a short circuit detection section 171B, a limit value setting section 171C, and an overcurrent detection section 171D.

The functional units 171A to 171D described above respectively correspond to the functional units 71A to 71D forming the overcurrent protection circuit 71 of the first embodiment (FIG. 3).

Thus, the overcurrent protection circuit 171 is basically the same as the overcurrent protection circuit 71 of the first embodiment (FIG. 3), and overcurrent is limited according to both the temperature detection signal SA and the short circuit detection signal SB. By performing variable control of the value Iocd, it is possible to ensure both current capacity during normal operation and safety improvement during high temperature.

Below, each part of the overcurrent protection circuit 171 (temperature detection part 171A, short circuit detection part 171B, limit value setting part 171C, and overcurrent detection part 171D) will be described with reference to the drawings from the first embodiment. We will focus on the changes in

<Temperature detector (second embodiment)>
FIG. 15 is a diagram showing a configuration example of the temperature detection section 171A. The temperature detection unit 171A of this configuration example is a functional unit that detects the chip temperature Tj and generates a temperature detection signal SA. Changes have been made.

The first change is the omission of transistor A3, resistors A8 and A9, comparator A10, and transistor A11. Thus, the temperature detector 171A may be mounted independently of the temperature protection circuit.

The second change is that the external control signal IN is applied instead of the internal power supply voltage Vreg as the drive voltage for the temperature detection section 171A. Thus, in the semiconductor integrated circuit device 1, which is a low-side switch LSI, the external control signal IN can be used as the drive voltage for the temperature detection section 171A.

The third change is that a resistor A13 is inserted between the source of each of the transistors A1 and A2 and the power terminal (=application terminal of the external control signal IN). According to this configuration, internal propagation of noise components and surge components superimposed on the external control signal IN can be suppressed.

<Short circuit detector (second embodiment)>
FIG. 16 is a diagram showing a configuration example of the short-circuit detection section 171B (supply fault detection section). The short-circuit detection unit 171B of this configuration example is a functional unit that detects a power short-circuit of the external terminal T2 by monitoring the output voltage Vo and generates a short-circuit detection signal SB. source B9;

The comparator B7 has an output voltage Vo input to the inverting input terminal (-) from the external terminal T11 via the resistor B8 (=surge protection element), and a node input to the non-inverting input terminal (+) from the voltage source B9. A short-circuit detection signal SB is generated by comparing it with the voltage VB3. The short-circuit detection signal SB is at high level (=logical level when power fault is not detected) when Vo<VB3, and is at low level (=logic level when power fault is detected) when Vo>VB3.

Note that the node voltage VB3 may have hysteresis following the short-circuit detection unit 71B (FIG. 8) of the first embodiment, or a logic gate (buffer, inverter, etc.) may be connected to the output terminal of the comparator B7. is also optional.

FIG. 17 is a diagram showing an example of the short circuit detection operation (supply fault detection operation) in the short circuit detector 171B, and depicts the output voltage Vo and the short circuit detection signal SB in order from the top.

When a power fault occurs in the external terminal T11 and the output voltage Vo exceeds the node voltage VB3, the short-circuit detection signal SB falls to a low level (=logical level at the time of power fault detection). On the other hand, when the power supply fault of the external terminal T11 is eliminated and the output voltage Vo becomes lower than the node voltage VB3, the short circuit detection signal SB rises to high level (logical level when power supply fault is not detected).

<Limit value setting unit (second embodiment)>
FIG. 18 is a diagram showing a configuration example of the limit value setting unit 171C. The limit value setting unit 171C of this configuration example is a functional unit that sets the overcurrent limit value Iocd (overcurrent detection current Iocd) according to both the temperature detection signal SA and the short circuit detection signal SB. Based on the , some changes have been made.

The first change is that the drain of transistor N6 is connected to the drain of transistor N1. With such a circuit change, a differential current (=Iocd1-Iocd2) obtained by subtracting the second set current Iocd2 from the first set current Iocd1 is input to the drain of the transistor N1. A mirrored overcurrent detection current Iocd is output.

That is, the limit value setting unit 171C omits the level shifter C3 and the current mirrors CM1 to CM4 from the limit value setting unit 71C (FIG. 10) of the first embodiment, and the first set current generation unit C1 and the second set current generation unit It can be understood as a configuration in which C2 is directly connected.

The second change is that an N-channel MOS field effect transistor N7 is added as a component included in the second set current generator C2. The drain of transistor N7 is connected to the drain of transistor N3. The source of transistor N7 is connected to the source of transistor N3. The gate of the transistor N7 is connected to the input terminal of the short detection signal SB. The transistor N7 is turned on when SB=H (logical level when no power fault is detected) and turned off when SB=L (logic level when power fault is detected).

When the transistor N7 is on, the current signal IC does not flow through the drain of the transistor N5, so the second set current Iocd2 does not flow through the drain of the transistor N6. On the other hand, when the transistor N7 is off, the current signal IC flows through the drain of the transistor N5, so the second set current Iocd2 also flows through the drain of the transistor N6.

In this manner, the limit value setting unit 171C controls the on/off of the transistor N7 according to the short-circuit detection signal SB so that the second set current generation unit C2 is disabled, and when the external terminal T11 is short-circuited (SB=L), the second set current generator C2 is enabled.

The third point of change is that the external control signal IN is applied instead of the internal power supply voltage Vreg as the drive voltage for the limit value setting section 171C. Thus, in the semiconductor integrated circuit device 1, which is a low-side switch LSI, the external control signal IN can be used as the drive voltage for the limit value setting section 171C.

A fourth change is that a resistor R2 is inserted between the source of each of the transistors P1 to P4 and the power terminal (=application terminal of the external control signal IN). According to this configuration, internal propagation of noise components and surge components superimposed on the external control signal IN can be suppressed. Note that the transistor P1, current source CS, and resistor R2 may be the transistor A1, current source A4, and resistor A13 (see FIG. 15) of the temperature detection section 171A, respectively.

<Overcurrent detector (second embodiment)>
FIG. 19 is a diagram showing a configuration example of the overcurrent detector 171D. The overcurrent detection unit 171D of this configuration example monitors the sense voltage Vs to detect whether or not the sense current Is (and thus the output current Io) has reached the overcurrent limit value Iocd, thereby providing overcurrent protection. It is a functional portion that generates the signal S171, and is based on the overcurrent detection portion 71D (FIG. 12) of the first embodiment with some modifications.

The first change is that the external control signal IN and the ground voltage GND are applied instead of the aforementioned boosted voltage VG and output voltage Vo, respectively. Thus, the overcurrent detector 171D operates between IN and GND instead of between VG and Vo.

The second change is that a resistor D7 is inserted between the source of each of the transistors D1 to D3 and the power terminal (=the terminal to which the external control signal IN is applied). According to this configuration, internal propagation of noise components and surge components superimposed on the external control signal IN can be suppressed.

<Application to vehicles>
FIG. 20 is an external view showing one configuration example of the vehicle. A vehicle X of this configuration example is equipped with a battery (not shown in the drawing) and various electronic devices X11 to X18 that operate with power supplied from the battery. Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual ones for convenience of illustration.

The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

The electronic device X12 is a lamp control unit that controls lighting and extinguishing of HID [high intensity discharged lamps] and DRL [daytime running lamps].

The electronic device X13 is a transmission control unit that performs control related to the transmission.

The electronic device X14 is a body control unit that performs control related to the motion of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

The electronic device X15 is a security control unit that drives and controls door locks, security alarms, and the like.

Electronic device X16 includes wipers, electric door mirrors, power windows, dampers (shock absorbers), electric sunroofs, electric seats, and other electronic devices built into vehicle X at the factory shipment stage as standard equipment or manufacturer options. is.

The electronic device X17 is an electronic device arbitrarily mounted on the vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].

The electronic device X18 is an electronic device having a high withstand voltage motor, such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

The semiconductor integrated circuit device 1, the ECU 2, and the load 3 described above can be incorporated in any of the electronic devices X11 to X18.

<Other Modifications>
Further, in the above-described embodiments, a high-side switch LSI or a low-side switch LSI for vehicle use has been described as an example, but the scope of application of the invention disclosed herein is limited to this. For example, it can be widely applied not only to other vehicle-mounted IPDs (such as vehicle-mounted power supply LSIs), but also to semiconductor integrated circuit devices (for example, general-purpose power supply control circuits) for applications other than vehicle-mounted applications.

In the above embodiment, an example was given in which the overcurrent limit value is lowered according to the chip temperature when a short-circuit abnormality of the output terminal is detected. An application is also conceivable in which, when an abnormality, temperature abnormality, etc.) is detected, the judgment value (overvoltage detection value, etc.) for detecting another abnormality is switched to a value with higher safety.

In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is indicated by the scope of claims rather than the description of the above-described embodiments. It should be understood that all changes that fall within the meaning and range of equivalency to the claims are included.

INDUSTRIAL APPLICABILITY The invention disclosed in this specification can be used for an in-vehicle IPD and the like.

1 Semiconductor integrated circuit device (switch device)
2 ECUs
3 load 4 external sense resistor 10, 110 NMOSFET (switch element)
20, 120 Output current monitor 21, 21', 121 NMOSFET
22, 122 sense resistor 30, 130 gate controller 31, 131 gate driver 131a switch 131b P-channel MOS field effect transistor 131c, 131d resistor 32 oscillator 33 charge pump (booster)
34, 134 Clamper 35, 135 NMOSFET
36, 136 resistors 37, 137 capacitors 38 Zener diodes (clamp elements)
40 control logic section 50 signal input section 60 internal power supply section 70 abnormality protection section 71, 171 overcurrent protection circuit 71A, 171A temperature detection section 71B, 171B short circuit detection section 71C, 171C limit value setting section 71D, 171D overcurrent detection section 72 Open protection circuit 73 Temperature protection circuit 74 Undervoltage protection circuit 80 Output current detector 90 Signal output A1 to A3 P-channel MOS field effect transistor A4 Current source A5 to A7 Diode A8, A9 Resistor A10 Comparator A11 N-channel MOS electric field Effect transistor A12 Inverter A13 Resistor B1, B2 Resistor B3 Current source B4 Comparator B5 Logic gate B6 P-channel MOS field effect transistor B7 Comparator B8 Resistor B9 Voltage source C1 First set current generator C2 Second set current generator C3 Level shifter C4 ~C7 P-channel MOS field effect transistors C8~C12 N-channel MOS field effect transistors CM1~CM4 Current mirror CS Current sources D1~D3 P-channel MOS field effect transistors D4, D5 N-channel MOS field effect transistors D6, D7 Resistors N1 to N6 N-channel MOS field effect transistors P1 to P6 P-channel MOS field effect transistors R1, R2 Resistors T1 to T4, T11 to T13 External terminals X Vehicles X11 to X18 Electronic equipment

Claims (10)

an output terminal to which a load is connected;
a switch element connected to the output terminal;
an overcurrent protection circuit that limits an output current flowing through the switch element to an overcurrent limit value or less;
has
The overcurrent protection circuit sets the overcurrent limit value to a predetermined reference value irrespective of the chip temperature when the short-circuit abnormality of the output terminal does not occur, and when the short-circuit abnormality of the output terminal occurs. A switching device, wherein the higher the chip temperature, the lower the overcurrent limit value from the reference value. The overcurrent protection circuit is
a temperature detection unit that detects the chip temperature;
a short-circuit detection unit that detects a short-circuit abnormality of the output terminal;
a limit value setting unit that sets the overcurrent limit value according to detection results of both the temperature detection unit and the short circuit detection unit;
an overcurrent detection unit that detects whether the output current has reached the overcurrent limit value;
2. The switch device of claim 1, comprising: 3. The switch device according to claim 2, wherein the temperature detection unit uses a temperature detection element of a temperature protection circuit that forcibly turns off the switch element when the chip temperature is abnormally high. 3. The switch element is a high-side switch connected between a power supply terminal and the output terminal, and the short-circuit detector detects a ground fault of the output terminal. 4. The switch device according to 3. 3. The switch element is a low-side switch connected between the output terminal and the ground terminal, and the short-circuit detection section detects a short-to-power supply of the output terminal. The switch device according to . The limit value setting unit
a first set current generator that generates a predetermined first set current;
a second set current generator for generating a second set current that increases as the chip temperature increases;
including
6. The switch device according to claim 2, wherein a differential current obtained by subtracting the second set current from the first set current is set as the overcurrent limit value. The limit value setting unit disables the second set current generating unit when the output terminal is not short-circuited, and generates the second set current when the output terminal is short-circuited. 7. The switch device according to claim 6, wherein the switch device is enabled. a switch device according to any one of claims 1 to 7;
a load connected to the switch device;
An electronic device comprising: 9. The electronic device according to claim 8, wherein the load is a bulb lamp, a relay coil, a solenoid, a light emitting diode, or a motor. A vehicle comprising the electronic device according to claim 8 or 9.

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