JP7306248B2 - semiconductor module - Google Patents

Description

The technology disclosed in this specification relates to a semiconductor module.

Patent Document 1 discloses a semiconductor substrate, a pair of surface electrodes provided on one main surface of the semiconductor substrate, a polyimide film provided between the pair of surface electrodes, and a pair of electrodes straddling the polyimide film. a metal block provided to cover the surface electrode of the semiconductor module. A polyimide film is provided to cover a gate liner disposed between a pair of surface electrodes. A pair of surface electrodes and a metal block are joined via solder.

JP 2007-48889 A

Polyimide is an organic material and has low wettability to solder. For this reason, according to the study of the present inventors, it has been found that in such a semiconductor module, solder cavities are formed on the polyimide film covering the gate liner. As a result, it has been found that when the semiconductor module is sealed with resin, the resin penetrates into the cavity of the solder.

The present inventors have found that when resin penetrates into solder cavities, thermal stress increases due to the difference in linear expansion coefficient between the resin and the solder. The present specification provides a technique for suppressing the intrusion of resin into solder cavities.

A semiconductor module disclosed in this specification includes a semiconductor substrate, a pair of surface electrodes provided on one main surface of the semiconductor substrate, and a pair of surface electrodes provided between the pair of surface electrodes. A polyimide film covering the gate liner disposed between the surface electrodes, and a polyimide film provided so as to cover the pair of surface electrodes across the polyimide film and joined to the pair of surface electrodes via solder and a metal block having a The width of the surface of the polyimide film in the facing direction of the pair of surface electrodes is smaller than the distance between the surface of the polyimide film and the metal block.

According to the above semiconductor module, the cross-sectional area of the solder cavity formed on the polyimide film is small, or the cavity cannot be formed. Therefore, in the semiconductor module described above, the resin is prevented from entering the cavity of the solder. As a result, in the semiconductor module, an increase in thermal stress can be suppressed, and high reliability can be obtained.

1 schematically shows a plan view of a semiconductor device of this embodiment. FIG. 1 schematically shows a plan view of a semiconductor module according to the present embodiment; FIG. FIG. 3 is a cross-sectional view of the semiconductor module of the present embodiment, showing a cross-sectional view corresponding to line III-III in FIG. 2 ; FIG. 3 is a cross-sectional view of the semiconductor module of the present embodiment, showing a cross-sectional view corresponding to line IV-IV in FIG. 2 ; FIG. 2 schematically shows an enlarged cross-sectional view of a main part in the vicinity of the gate liner of the semiconductor module of the present embodiment. The top view of the semiconductor module of the modification of this embodiment is shown typically. FIG. 7 is a cross-sectional view of a semiconductor module of a modified example of the present embodiment, and shows a cross-sectional view corresponding to line VII-VII of FIG. 6 ; FIG. 7 is a cross-sectional view of a semiconductor module of a modified example of the present embodiment, showing a cross-sectional view corresponding to line VIII-VIII of FIG. 6 ;

FIG. 1 schematically shows a plan view of a semiconductor device 1 according to this embodiment. A semiconductor device 1 includes a semiconductor substrate 10 on which various diffusion regions and/or epitaxial layers are formed. In semiconductor substrate 10 various diffusion regions and/or epitaxial layers form power device structures of the type referred to, for example, as MOSFETs, IGBTs or reverse-conducting IGBTs. A pair of surface electrodes 12 , a gate pad 14 and a polyimide film 16 are provided on the surface of the semiconductor substrate 10 .

Each of the pair of surface electrodes 12 has a rectangular shape in plan view (when viewed from the direction (z direction) perpendicular to the main surface of the semiconductor substrate 10). The long sides of the surface electrodes 12 are parallel to the y direction, and the short sides are parallel to the x direction. The pair of surface electrodes 12 are arranged to face each other in the x direction. As an example, the surface electrode 12 is configured by laminating an AlSi layer of aluminum silicon and a Ni layer of nickel.

The gate pad 14 is a pad to which a gate liner provided on the semiconductor substrate 10 is connected, as will be described later. The position of the gate pad 14 on the semiconductor substrate 10 is not particularly limited. Although not shown, a plurality of pads are provided on the semiconductor substrate 10 in addition to the gate pad 14 .

A polyimide film 16 covers the surface of the semiconductor substrate 10 so that the pair of surface electrodes 12 and the gate pad 14 are exposed. In this specification, the polyimide film 16 provided between the pair of surface electrodes 12 is particularly referred to as a liner polyimide film 16a.

FIG. 2 schematically shows a plan view of the semiconductor module 100. As shown in FIG. In FIG. 2, the positions of the pair of surface electrodes 12 are indicated by dashed lines. The semiconductor module 100 is constructed by bonding a metal block 26 to the pair of surface electrodes 12 of the semiconductor device 1 shown in FIG. The metal block 26 is provided so as to cover the pair of surface electrodes 12 across the liner polyimide film 16a (see FIG. 1). The material of the metal block 26 is copper (Cu), although it is an example.

A sectional view corresponding to line III-III in FIG. 2 is shown in FIG. 3, and a sectional view corresponding to line IV-IV in FIG. 2 is shown in FIG. It should be noted that although structures such as an interlayer insulating film are also provided on the surface of the semiconductor substrate 10, they are omitted for the sake of clarity.

As shown in FIGS. 3 and 4, a gate liner 18 is arranged along the y direction between the pair of surface electrodes 12 . The gate liner 18 is covered with a liner polyimide film 16a. The material of the gate liner 18 is, by way of example, polysilicon.

Cavities 24a for solder 24 are formed on the surface of the liner polyimide film 16a. Polyimide is an organic material and has low wettability to the solder 24 . Therefore, when the solder 24 is applied to join the metal block 26, the solder 24 does not wet the surface of the liner polyimide film 16a, and an arch-shaped cavity 24a is formed.

FIG. 5 shows an enlarged cross-sectional view of the main part in the vicinity of the gate liner 18. As shown in FIG. In the semiconductor module 100, the width W1 of the surface of the liner polyimide film 16a is configured to be smaller than the distance D1 between the surface of the liner polyimide film 16a and the metal block . Here, the width W1 of the surface of the liner polyimide film 16a is the width of the pair of surface electrodes 12 in the opposing direction (x direction). In the semiconductor module 100, the relationship of W1<D1 is established. When such a relationship is established, the cross-sectional area of the cavity 24a of the solder 24 is formed to be extremely small.

As described in Background Art, if the cross-sectional area of the cavity 24a of the solder 24 is large, the resin will enter the cavity 24a of the solder 24 when the semiconductor module 100 is sealed with resin. Thermal stress increases due to the difference in coefficient of linear expansion between In the conventional semiconductor module, the relation was W1>D1. This is because the width W1 of the liner polyimide film 16a is set large in order to ensure the insulation of the gate liner 18 with respect to other conductors. As a result, the cross-sectional area of the cavity 24a of the solder 24 becomes large, causing the above problem. On the other hand, in the semiconductor module 100 of the present embodiment, the cross-sectional area of the cavity 24a of the solder 24 is extremely small due to the relationship W1<D1, so that the penetration of the resin into the cavity 24a of the solder 24 is suppressed. . As a result, in the semiconductor module 100, an increase in thermal stress is suppressed, and high reliability is obtained.

6 to 8 show a modified semiconductor module 101. FIG. Components common to those of the semiconductor module 100 shown in FIGS. 2 to 4 are denoted by common reference numerals, and descriptions thereof are omitted.

In the semiconductor module 101, no cavities of the solder 24 are formed on the surface of the liner polyimide film 16a. As described with reference to FIG. 5, when the width W1 of the surface of the liner polyimide film 16a is configured to be smaller than the distance D1 between the surface of the liner polyimide film 16a and the metal block 26, The surface tension of the solder 24 against the liner polyimide film 16a can no longer maintain the arch-shaped cavity of the solder 24, and the solder 24 also wets onto the surface of the liner polyimide film 16a. Although such a phenomenon does not necessarily occur, if the relationship W1<D1 holds, the probability of such a phenomenon occurring increases. Since no cavities are formed for the solder 24, penetration of resin can be prevented. As a result, the semiconductor module 101 can remarkably suppress an increase in thermal stress and obtain higher reliability.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or in the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims as of the filing. In addition, the techniques exemplified in this specification or drawings achieve multiple purposes at the same time, and achieving one of them has technical utility in itself.

Reference Signs List 1: semiconductor device 10: semiconductor substrate 12: surface electrode 14: gate pad 16: polyimide film 16a: liner polyimide film 18: gate liner 24: solder 24a: cavity 26: metal block 100: semiconductor module

Claims (1)

a semiconductor substrate;
a pair of surface electrodes provided on one main surface of the semiconductor substrate;
a polyimide film provided between the pair of surface electrodes and covering a gate liner disposed between the pair of surface electrodes;
A metal block provided to cover the pair of surface electrodes across the polyimide film and joined to the pair of surface electrodes via solder,
A semiconductor module, wherein the width of the surface of the polyimide film in the direction in which the pair of surface electrodes face each other is smaller than the distance between the surface of the polyimide film and the metal block.

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