JP7294098B2 - Method for producing p-type group III nitride semiconductor - Google Patents

Description

The present invention relates to a method for producing a p-type group III nitride semiconductor by implanting Mg ions into a group III nitride semiconductor.

As a method for manufacturing a p-type group III nitride semiconductor, a method is known in which p-type impurity ions are implanted into the group III nitride semiconductor, and then annealing is performed to activate the p-type impurity to form a p-type region. It is

In Patent Document 1, a through film is continuously crystal-grown on a semiconductor layer made of a group III nitride semiconductor, p-type impurities are ion-implanted into the semiconductor layer from above the through film, and the p-type impurities are activated by annealing. A method for producing a p-type Group III nitride semiconductor is described. By providing the through film, it is possible to prevent n-type impurities from adhering to the surface of the semiconductor layer, and to suppress diffusion of the n-type impurities into the semiconductor layer due to knock-on during ion implantation. As a result, it is possible to suppress the deposition of p-type impurities on the surface of the semiconductor layer and the deterioration of the surface state.

In Patent Document 2, an implantation protection film is formed on a GaN layer, Mg ions are implanted through the implantation protection film, an annealing protection film is formed after removing the implantation protection film, and annealing is performed to form a p-type region. It is described to form It also states that the injection peak is the GaN layer.

JP 2017-54944 A JP 2018-154553 A

However, as a result of investigation by the inventor, it was found that Mg could not be activated in the implantation peak region into which Mg ions were implanted, even if annealing was performed, and thus a p-type region could not be formed. It turned out to be

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to prevent unintended i-type regions from being formed in a method of manufacturing a p-type group III nitride semiconductor by ion implantation of p-type impurities.

The present invention comprises a through film forming step of forming a through film on a semiconductor layer made of a group III nitride semiconductor, and controlling the injection energy from above the through film so that the injection peak is in the through film. An ion implantation step of ion-implanting a mold impurity to form an ion-implanted region in the semiconductor layer, a protective film forming step of forming a protective film on the through film, a heat treatment temperature of T (° C.), and a heat treatment time of t ( 5t+T>1350, 1250≦T≦1500, and 5≦t≦90 by annealing at a heat treatment temperature and a heat treatment time in a range that satisfies 5t+T>1350, 1250≦T≦1500, and 5≦t≦90, thereby diffusing the p-type impurity from the through film and removing the p-type impurity. A method for manufacturing a p-type group III nitride semiconductor, comprising an annealing step of activating the ion-implanted region to make it a p-type region, and a removing step of removing the through film and the protective film.

Further, the present invention provides a through film forming step of forming a through film on a semiconductor layer made of a group III nitride semiconductor for adjusting the injection amount of p-type impurities and the position of the injection peak in the next step, and a through film forming step. An ion implantation step of forming an ion implantation region in the semiconductor layer by controlling the implantation energy so that the implantation peak is in the through film from above, implanting p-type impurity ions, and removing all the through film. A through film removing step, a protective film forming step of forming a protective film on the semiconductor layer to prevent nitrogen from being released by annealing in the next step , a heat treatment temperature of T (° C.), and a heat treatment time of t (minutes). ), 5t+T>1350, 1250≦T≦1500, and 5≦t≦90 are annealed at a heat treatment temperature and heat treatment time to activate the p-type impurity and convert the ion-implanted region into a p-type region. and a removing step of removing the protective film.

In the present invention, the protective film may be a multilayer film. Cracking of the protective film during annealing can be suppressed.

In the case of a multilayer film, a multilayer film can be formed by sequentially stacking a first protective film made of AlN and a second protective film made of SiN. The stress generated in the protective film can be relaxed and cracks can be suppressed. Also, the first protective film is preferably formed by MOCVD, and the second protective film is preferably formed by sputtering. It is possible to achieve both prevention of damage to the surface of the semiconductor layer and relaxation of stress.

In the case of a multilayer film, a first protective film made of AlN and a second protective film made of Al ₂ O ₃ are laminated in this order, and the first protective film is formed by a sputtering method, and the second protective film is formed by sputtering. may be formed by sputtering or ALD. The average thermal expansion coefficient of the entire protective film can be brought close to that of the Group III nitride semiconductor, and cracks in the protective film can be suppressed.

In the present invention, the depth of the injection peak in the ion implantation process is preferably 0.5 times or more and 1 time or less the thickness of the through film. Formation of the i-type region can be more reliably prevented.

In the present invention, the implantation energy in the ion implantation step is preferably 50 keV or less. It becomes easier to control the injection peak to be in the through film.

In the present invention, the dose in the ion implantation process is preferably 1×10 ¹⁵ /cm ² or more. It is possible to further increase the Mg concentration of the p-type region.

According to the present invention, a p-type region can be formed in a desired region in a group III nitride semiconductor, and an unintended i-type region can be prevented from being formed.

4A to 4C are diagrams showing the manufacturing steps of the p-type group III nitride semiconductor of Example 1; 4A to 4C are diagrams showing the manufacturing steps of the p-type group III nitride semiconductor of Example 1; Graph showing the relationship between Mg concentration and depth. 4A and 4B are diagrams showing the results of pn determination of the semiconductor layer 11. FIG. Graph showing the relationship between Mg concentration and depth. 4A and 4B are diagrams showing the results of pn determination of the semiconductor layer 11. FIG. FIG. 8 is a diagram showing the configuration of a protective film 26 of Example 2; FIG. 10 is a diagram showing a part of the manufacturing process of the p-type group III nitride semiconductor of Example 3; The figure which showed the structure of trench MOSFET. FIG. 4 is a diagram showing ranges of heat treatment temperature and heat treatment time for obtaining a high-concentration p-type region;

Specific examples of the present invention will be described below with reference to the drawings, but the present invention is not limited to the examples.

Example 1 is a method for producing a p-type Group III nitride semiconductor. 1 and 2 are diagrams showing the manufacturing steps of the p-type group III nitride semiconductor of Example 1. FIG. The manufacturing process of the p-type group III nitride semiconductor of Example 1 will be described with reference to this figure.

(Semiconductor layer forming step)
First, a semiconductor layer 11 made of Si-doped n-GaN is formed by MOCVD on a substrate 10 made of GaN (FIG. 1(a)). The Si concentration of the semiconductor layer 11 is 5×10 ¹⁵ /cm ³ . The main surface of the semiconductor layer 11 is the c-plane, and the surface of the semiconductor layer 11 is the Ga-polar plane.

The substrate 10 is not limited to a GaN substrate, and any material that allows crystal growth of a Group III nitride semiconductor can be used. For example, sapphire, Si, SiC, ZnO, etc. can be used. Also, the semiconductor layer 11 is not limited to GaN, and may be a Group III nitride semiconductor of any composition. For example, it may be AlN, InN, AlGaN, InGaN, AlGaInN, or the like. Also, the Si concentration of the semiconductor layer 11 is not limited to the above, and may be non-doped.

(Step of forming through film 12)
Next, a through film 12 made of AlN grown at a low temperature and having a thickness of 50 nm is continuously grown on the semiconductor layer 11 by MOCVD (see FIG. 1B). The through film 12 adjusts the amount of Mg ions to be implanted in a post-process and the position of the peak of implantation. The growth conditions for the through film 12 are, for example, a growth temperature of 200° C. or more and 800° C. or less and a growth pressure of 10 kPa or more and 100 kPa or less. Within this range, the through film 12 grown at a low temperature can be easily formed.

Through film 12 may be formed by a method other than MOCVD, such as sputtering. However, it is preferable to grow continuously by MOCVD as in the first embodiment. It is possible to prevent the surface of the semiconductor layer 11 from being contaminated with impurities, suppress the unintentional formation of an n-type region by Si on the surface of the semiconductor layer 11, and prevent the impurities from being removed during ion implantation in the subsequent process. This is because injection into the semiconductor layer 11 due to knock-on can be suppressed.

The material of the through film 12 is preferably a material that does not contain Si as a constituent element. This is because it is possible to prevent Si from being implanted into the semiconductor layer 11 due to knock-on during ion implantation, and to prevent an n-type region from being formed in an unintended region. For example, _Al2O3 , AlN, InN, GaN, AlGaN, InGaN _, etc. can be used. In particular, as in Example 1, AlN is preferred. This is because it can be continuously grown on the semiconductor layer 11 by the MOCVD method. In addition, the difference in thermal expansion coefficient from GaN is small, and cracks are less likely to occur in subsequent annealing. Also, if it is AlN, it is easy to remove the through film 12 in a post-process. Also, the through film 12 is preferably grown at a low temperature with low crystallinity. Low-temperature growth with low crystallinity can alleviate the stress due to the difference in coefficient of thermal expansion from the semiconductor layer 11, and can suppress the occurrence of cracks in the through film 12 during subsequent annealing.

The thickness of the through film 12 is not limited to 50 nm, and may be any range as long as the ion implantation dose and the ion implantation peak position can be controlled. For example, 50-150 nm. In order to alleviate the stress due to the difference in coefficient of thermal expansion with the semiconductor layer 11, the through film 12 is preferably thin, more preferably 100 nm or less, still more preferably 80 nm or less.

(Ion implantation process)
Next, a mask 13 is formed on the through film 12 . Mask 13 has an opening 14 . The mask 13 may be made of any material, such as photoresist and SiO ₂ , as long as it can block ions. Next, Mg is ion-implanted from above the through film 12 . Mg ions are blocked in the region where the mask 13 is provided, and Mg ions are implanted only through the opening 14 . As a result, Mg ions are implanted into the region of the through film 12 and the semiconductor layer 11 under the opening 14 to form an ion-implanted region 15 (see FIG. 1(c)). After ion implantation, the mask 13 is removed. If it is not necessary to limit the ion-implantation region, the mask 13 need not be provided.

Here, the ion implantation is performed so that the position of the implantation peak (depth from the surface of the through film 12 ) is within the through film 12 . The depth of the implantation peak can be easily controlled by controlling the implantation energy. For example, by setting the injection energy to 50 keV or less, it becomes easy to control the injection peak to be in the through film 12 . Specifically, the depth of the injection peak can be less than 100 nm, and if the through film 12 has a thickness of 100 nm, the injection peak can be positioned in the through film 12 . It is preferable that the thickness of the through film 12 can be reduced as the injection energy is lowered. If the injection energy is set to 20 keV or less, the injection peak depth can be set to 50 nm or less, and the thickness of the through film 12 can be set to 50 nm accordingly. Also, the implantation energy is preferably 10 keV or higher. If the energy is lower than this, it becomes difficult to ion-implant Mg into the semiconductor layer 11 at a sufficient concentration.

The depth of the injection peak is preferably 0.5 times or more and 1 time or less the thickness of the through film 12 . Formation of an i-type region in semiconductor layer 11 can be more reliably prevented, and through film 12 can be made sufficiently thin.

The dose of ion implantation is preferably 1×10 ¹⁴ /cm ² or more. It is possible to sufficiently improve the Mg concentration in the semiconductor layer 11 and sufficiently thicken the p-type region. Also, the concentration gradient facilitates the diffusion of Mg. More preferably, it is 1×10 ¹⁵ /cm ² or more. The high-concentration implantation increases the concentration gradient of Mg, allowing Mg in the through film 12 to diffuse further into the semiconductor layer 11 .

Ion implantation may be performed at room temperature, but is preferably performed at a temperature higher than room temperature. Can reduce the amount of infusion damage. In particular, it is preferable to carry out at a temperature of 500° C. or higher. Mg can be diffused from the through film 12 into the semiconductor layer 11, and damage caused during implantation can be suppressed. The upper limit of the temperature may be within a range in which the semiconductor layer 11 and the through film 12 are not decomposed, and is, for example, 1000° C. or less. More preferably, it is 800° C. or less. This is because less nitrogen escapes from the semiconductor layer 11 . More preferably, the temperature is 600°C or higher and 800°C or lower.

Although Mg is ion-implanted in the first embodiment, other p-type impurities such as Be may be ion-implanted. In particular, it is preferable to ion-implant Mg as in the first embodiment.

(Protective film forming step)
Next, a protective film 16 made of AlN and having a thickness of 600 nm is formed on the through film 12 by MOCVD (see FIG. 2A). This protective film 16 is provided to prevent nitrogen from desorbing from the through film 12 and the semiconductor layer 11 in the subsequent annealing step.

The material of the protective film 16 is not limited to AlN, and SiN, SiO ₂ , Al ₂ O ₃ or the like can be used. In Example 1, AlN, which is the same material as the through film 12, is used as the protective film 16 to reduce the difference in thermal expansion coefficient from that of the semiconductor layer 11, thereby suppressing cracking of the protective film 16 during annealing in the next step. .

Moreover, the method of forming the protective film 16 is not limited to the MOCVD method, and methods such as sputtering, CVD, and vapor deposition can be used. In Example 1, the MOCVD method is used to prevent the surface of the semiconductor layer 11 from being damaged. Moreover, if sputtering is used, the stress due to the difference in thermal expansion coefficient from the semiconductor layer 11 can be relaxed due to its crystallinity. When using the MOCVD method or the CVD method, it is preferable to grow at a low temperature. The protective film 16 can be made polycrystalline or amorphous, the stress caused by the difference in coefficient of thermal expansion with the semiconductor layer 11 can be relieved, and the occurrence of cracks in the protective film 16 during annealing in the next step can be suppressed. can be done.

The thickness of the protective film 16 is arbitrary as long as it can sufficiently suppress the detachment of nitrogen and sufficiently suppress cracks during annealing. For example, 50-200 nm.

A protective film may also be provided on the rear surface of the substrate 10 . Desorption of nitrogen from the back surface of the substrate 10 in the subsequent annealing step can be suppressed. The protective film at this time can be made of the same material as the protective film 16 described above.

(annealing process)
Next, annealing is performed to heat the through film 12 and the semiconductor layer 11 . The heat treatment temperature and heat treatment time are in a range that satisfies 5t+T>1350, 1250≦T≦1500, and 5≦t≦90, where T (° C.) is the heat treatment temperature and t (minutes) is the heat treatment time. and As a result, Mg is diffused from the through film 12 into the semiconductor layer 11 and Mg in the semiconductor layer 11 is activated.

Regions deeper than the implant peak suffer less implant damage. Therefore, the implantation damage is sufficiently recovered by annealing. Moreover, Mg in the semiconductor layer 11 is also activated as an acceptor. Therefore, of the ion-implanted region 15, the region in the semiconductor layer 11 becomes the p-type region 17 (see FIG. 2B).

The reason why the heat treatment temperature and the heat treatment time are set within the above ranges is to sufficiently diffuse Mg from the through film 12 to the semiconductor layer 11 and increase the hole concentration in the p-type region 17 . If it is longer than 90 minutes, cracks may occur in the protective film 16, which is not preferable. If the heat treatment temperature and heat treatment time are out of the above ranges and the heat treatment time is less than 30 minutes, Mg will not diffuse sufficiently. Also, the higher the heat treatment temperature, the faster the diffusion of Mg and the shorter the heat treatment time.

More preferable heat treatment temperature and heat treatment time ranges satisfy 5t+T≧1400, 1250≦T≦1500, and 5≦t≦90. Within this range, p-type region 17 can be obtained more reliably.

Annealing is performed in a nitrogen atmosphere or an ammonia atmosphere. This is for suppressing detachment of nitrogen from the through film 12 and the semiconductor layer 11 . In particular, it is preferable to carry out in an ammonia atmosphere.

(Step of removing through film 12 and protective film 16)
Next, the through film 12 and the protective film 16 are removed by wet etching with an aqueous TMAH solution (see FIG. 2(c)). As described above, the semiconductor layer 11 having the p-type region 17 in a desired region can be formed. Although the TMAH aqueous solution can wet-etch AlN, it cannot wet-etch the Ga-polar plane of GaN. can.

The Mg concentration of p-type region 17 is, for example, 1×10 ¹⁷ to 1×10 ²⁰ /cm ³ . In forming a p-type region by ion implantation, the activation rate of Mg is low, so if the Mg concentration is less than 1×10 ¹⁷ /cm ³ , it is difficult to form a p-type region. The thickness of p-type region 17 can be controlled by the peak position of ion implantation, dose amount, annealing temperature, and annealing time. For example, it can be 0.1 to 1 μm thick.

A protective film is preferably provided on the rear surface of the substrate 10 before wet etching. Since the back surface of the substrate 10 is the N-polar surface of GaN, it is roughened by the TMAH aqueous solution. Therefore, if a protective film is provided on the back surface of the substrate 10, the back surface can be prevented from becoming rough. The material of the protective film is, for example, _SiO2 .

As described above, according to the manufacturing method of the p-type group III nitride semiconductor of the first embodiment, since the peak of the ion implantation is in the through film 12, the i-type region is formed in an unintended region. p-type region 17 can be formed in a desired region.

Next, experimental results regarding Example 1 will be described.

(Experiment 1)
A semiconductor layer 11 made of n-GaN was formed on a substrate 10 in the same manner as in Example 1, and Mg was ion-implanted without providing a through film 12 . The implantation energy was 230 keV and the dose amount was 2.3×10 ¹⁵ /cm ² . After that, annealing was performed at 1250° C. for 30 minutes in an ammonia atmosphere. The Mg concentration of the semiconductor layer 11 before and after annealing was analyzed by SIMS (secondary ion mass spectrometry). Also, the cross section of the semiconductor layer 11 after annealing in the stacking direction was analyzed by SMM (scanning microwave microscopy) to determine pn.

FIG. 3 is a graph showing the relationship between Mg concentration (cm ⁻³ ) and depth (μm). The depth is the depth from the surface of the semiconductor layer 11 . In addition, the dotted line in FIG. 3 indicates before annealing, and the actual indicates after annealing. 4A and 4B are diagrams showing the results of pn determination of the semiconductor layer 11. FIG.

As shown in FIG. 3, the injection peak had a depth of 0.2 μm, and the Mg concentration distribution was mountain-shaped with the injection peak as the apex. Also, there was no change in the position of the injection peak before and after annealing. On the other hand, the Mg concentration near the injection peak decreased by annealing, and the Mg concentration increased in the region far from the injection peak. In other words, it was found that Mg was diffused by annealing.

As a result of FIG. 4, it was found that the region from the surface to a depth of 0.4 μm was an i-type region, and the region from a depth of 0.4 μm to 1 μm was a p-type region. Comparing with the results of FIG. 3, it was found that the p-type region was formed deeper than the injection peak and the Mg concentration ranged from 2×10 ¹⁷ to 2×10 ¹⁸ /cm ³ .

The reason why the i-type region is generated is that the implantation damage is large in the region near the implantation peak, and the implantation damage cannot be recovered by annealing. In addition, since the implantation damage is also large in the region shallower than the implantation peak, even if annealing is performed, the implantation damage is not sufficiently recovered, and the implantation damage remains, so that the region becomes an i-type region.

On the other hand, the region deeper than the injection peak is considered to have become a p-type region because the implantation damage was less, the implantation damage was recovered by annealing, and Mg was activated as an acceptor.

In addition, since the annealing time at 1250° C. is 30 minutes, which is longer than the conventional one, Mg diffuses from the injection peak, and it was found that the Mg concentration in the p-type region can be made higher.

(Experiment 2)
Next, the implantation energy was changed to 50 keV, and the other conditions were the same as in Experiment 1, and the Mg concentration of the semiconductor layer 11 after annealing was analyzed by SIMS. In addition, the cross section in the lamination direction of the semiconductor layer 11 after annealing was analyzed by SMM, and pn determination was performed.

FIG. 5 is a graph showing the relationship between Mg concentration (cm ⁻³ ) and depth (μm). The depth is the depth from the surface of the semiconductor layer 11 . FIG. 6 is a diagram showing the result of pn determination of the semiconductor layer 11. As shown in FIG.

As shown in FIG. 5, since the injection energy was reduced, the injection peak position became shallower, reaching a depth of 0.06 μm. From FIGS. 3 and 5, it was found that the injection peak position can be easily controlled by controlling the injection energy. Further, it was found that by controlling the injection energy to be small so that the position of the injection peak is shallow, it is possible to control the position of the injection peak to be in the through film 12 as in Example 1. rice field.

As a result of FIG. 6, it was found that the region from the surface to a depth of 0.1 μm is an i-type region, and the region from a depth of 0.1 μm to 0.9 μm is a p-type region. Comparing with the results of FIG. 5, it was found that the p-type region was formed deeper than the injection peak and the Mg concentration was in the range of 2×10 ¹⁷ to 1×10 ¹⁹ /cm ³ .

Further, comparing FIGS. 3 and 5, it was found that by reducing the injection energy, the gradient of the Mg concentration in the region deeper than the injection peak becomes large, and the i-type region formed immediately below the p-type region can be thinned. . It was also found that the p-type region can also be thickened.

Further, from the results of FIG. 5, it is found that if the thickness of the through film 12 is set to 0.1 μm, it is possible to make the injection peak within the through film 12 when ion implantation is performed under the conditions of FIG. It has been found that i-type regions in layer 11 can be avoided. It was also found that if the injection energy is reduced, the injection peak can be controlled in the through film 12 even when the through film 12 is thin.

(Experiment 3)
When the injection energy was changed to 20 keV in Experiment 1, the position of the injection peak became shallower than 50 nm. Therefore, it was found that if the thickness of the through film 12 is set to 50 nm, the injection peak can be positioned in the through film 12 .

(Experiment 4)
The range in which a p-type region (a region having a hole concentration of 1×10 ¹⁶ /cm ³ or more) can be obtained in the semiconductor layer 11 was investigated by changing the implantation energy at 20 keV and changing the heat treatment temperature and heat treatment time of annealing after ion implantation. . The conditions are the same as in Experiment 1 except for the implantation energy, the heat treatment temperature for annealing, and the heat treatment time.

As a result, it became like FIG. In FIG. 10, the horizontal axis indicates the heat treatment time t (minutes), the vertical axis indicates the heat treatment temperature T (° C.), the circle indicates that the p-type region was obtained, and the x indicates that the p-type region was not obtained. . As shown in FIG. 10, (t, T) where the p-type region was obtained is (5, 1400), (10, 1350), (20, 1300), (30, 1250), (90, 1250). there were. On the other hand, (t, T) where no p-type region was obtained was (5, 1250), (5, 1300), (10, 1250), (20, 1250). From this result, it is considered that a p-type region can be obtained in a range that satisfies 5t+T>1350, 1250≤T≤1500, and 5≤t≤90, and more reliably 5t+T≥1400, 1250≤T≤1500. , and 5≦t≦90.

In Example 2, in the method of manufacturing a p-type group III nitride semiconductor of Example 1, the protective film 16 formed on the through film 12 is replaced with a protective film 26 described below. Other than that, it is the same as the first embodiment.

As shown in FIG. 7, the protective film 26 is a multilayer film in which a first protective film 26A and a second protective film 26B are laminated in order from the through film 12 side. The first protective film 26A is made of AlN and has a thickness of 200 nm. The second protective film 26B is made of SiN and has a thickness of 150 nm.

The reason why the protective film 26 is made of such a multilayer film is as follows. As in Example 1, the formation of the p-type region 17 requires annealing at a high temperature for a long time. Annealing at a high temperature for a long time may crack the protective film 26 . This is particularly noticeable when using a substrate 10 with a large diameter. Therefore, by making the protective film 26 a multi-layered film, cracking of the protective film 26 during annealing is suppressed.

Also, by using AlN for the first protective film 26A in contact with the semiconductor layer 11, the difference in thermal expansion coefficient from the semiconductor layer 11 is reduced, and the stress generated in the protective film 26 is alleviated. Further, by forming the second protective film 26B made of SiN with high fracture toughness on the first protective film 26A, the occurrence of cracks due to high temperatures on the surface of the first protective film 26A is suppressed.

The first protective film 26A and the second protective film 26B may be formed by any method, but are preferably formed by sputtering or MOCVD. When the film is formed by sputtering, the bond in the film becomes loose, so that the stress due to the difference in thermal expansion coefficient from the semiconductor layer 11 can be relaxed. However, if it is formed by direct sputtering, the surface of the semiconductor layer 11 may be damaged by sputtering. Therefore, the first protective film 26A should be formed by MOCVD, and the second protective film 26B should be formed by sputtering. By forming the first protective film 26A by MOCVD, the surface of the semiconductor layer 11 can be prevented from being damaged, and by forming the second protective film 26B by sputtering, stress can be alleviated. In other words, both prevention of damage to the surface of the semiconductor layer 11 and relaxation of stress can be achieved.

Alternatively, the first protective film 26A may be AlN formed by sputtering, and the second protective film 26B may be Al ₂ O ₃ formed by sputtering or ALD. AlN formed by sputtering has a smaller thermal expansion coefficient than GaN, while Al ₂ O ₃ has a larger thermal expansion coefficient than GaN. , cracks in the protective film 26 can be greatly suppressed.

Example 3 is the same as Example 1 except that part of the manufacturing process of Example 1 is changed as follows.

Example 3 is the same as Example 1 up to the ion implantation step. In Example 3, the through film 12 is removed after the ion implantation step (see FIG. 8A). After that, a protective film 16 is formed on the semiconductor layer 11 (see FIG. 8B). After forming the protective film 16, the same procedure as in the first embodiment is performed.

In Example 3, since there is no diffusion of Mg from the through film 12 in the annealing process, there is a possibility that the Mg concentration in the p-type region 17 will decrease, but there are the following advantages. The surface of the through film 12 is damaged by ion implantation. Therefore, if the protective film 16 is formed on the through film 12, the adhesion between the through film 12 and the protective film 16 may be poor, and the protective film 16 may peel off during annealing. Therefore, if the protective film 16 is formed after removing the through film 12 as in the third embodiment, peeling of the protective film 16 during annealing can be suppressed.

(Various modifications)
The method for producing a p-type group III nitride semiconductor of Example 1-3 can be used for producing various semiconductor devices. Examples include trench MOSFETs, Schottky barrier diodes, and IGBTs.

As an example, the trench MOSFET of FIG. 9 is shown. The trench MOSFET shown in FIG. and a second n-layer 103 made of n-GaN provided on 102 .

Also, trench 104 penetrating second n-layer 103 and p-layer 1002 and reaching first n-layer 101, and over the bottom, side and top surfaces of trench 104 (the surface of second n-layer 103 and the vicinity of trench 104) It has a gate insulating film 105 provided, a gate electrode 106 provided so as to fill the trench with the gate insulating film 105 interposed therebetween, and a source electrode 107 provided on the rear surface of the substrate 100 .

Also, a recess 108 penetrating the second n-layer 103 and reaching the p-layer 102, and a source electrode 109 provided over the bottom, side and top surfaces of the recess 108 (the surface of the second n-layer 103 and the region near the recess 108). and have Furthermore, a p-type region 110 is provided in a region extending from the bottom surface of the recess 108 to a position deeper than the bottom surface of the trench 104 .

The p-type region 110 is provided to alleviate electric field concentration that occurs at the corners of the trench during device operation. The p-type region 110 is a region formed by ion implantation, and can be formed using the method for manufacturing a p-type group III nitride semiconductor of Example 1-3.

INDUSTRIAL APPLICABILITY The present invention can be used to fabricate semiconductor devices made of Group III nitride semiconductors.

10: substrate 11: semiconductor layer 12: through film 13: mask 14: opening 15: ion implantation region 16: protective film 17: p-type region

Claims (9)

a through film forming step of forming a through film on a semiconductor layer made of a group III nitride semiconductor for adjusting the injection amount of p-type impurities and the injection peak position in the next step;
an ion implantation step of ion-implanting a p-type impurity from above the through film to form an ion-implanted region in the semiconductor layer by controlling the implantation energy so that the implantation peak is in the through film;
a through film removing step of removing all of the through film;
a protective film forming step of forming a protective film on the semiconductor layer to prevent nitrogen from being released by annealing in the next step ;
Assuming that the heat treatment temperature is T (° C.) and the heat treatment time is t (minutes), annealing at a heat treatment temperature and a heat treatment time in a range that satisfies 5t+T>1350, 1250≦T≦1500, and 5≦t≦90 reduces the p an annealing step of activating the type impurity to make the ion-implanted region a p-type region;
a removing step of removing the protective film;
A method for producing a p-type Group III nitride semiconductor, comprising: 2. The method of manufacturing a p-type group III nitride semiconductor according to claim 1, wherein the protective film is a multilayer film. 3. The manufacturing of the p-type group III nitride semiconductor according to claim 2 , wherein the protective film is a multilayer film in which a first protective film made of AlN and a second protective film made of SiN are laminated in order. Method. 4. The method of manufacturing a p-type group III nitride semiconductor according to claim 3 , wherein said first protective film is formed by MOCVD, and said second protective film is formed by sputtering. The protective film is a multilayer film in which a first protective film made of AlN and a second protective film made of Al ₂ O ₃ are laminated in order,
The first protective film is formed by a sputtering method, and the second protective film is formed by a sputtering method or an ALD method,
3. The method for manufacturing a p-type group III nitride semiconductor according to claim 2 , wherein: 6. The p according to any one of claims 1 to 5 , wherein the depth of the injection peak in the ion implantation step is set to 0.5 times or more and 1 time or less the thickness of the through film. A method for producing a type III nitride semiconductor. 7. The method of manufacturing a p-type group III nitride semiconductor according to claim 1 , wherein the ion implantation step has an implantation energy of 50 keV or less. The method for manufacturing a p-type group III nitride semiconductor according to any one of claims 1 to 7 , wherein a dose amount in said ion implantation step is 1 x ¹⁰¹⁵ /cm2 or ^more . 9. The method for manufacturing a p-type group III nitride semiconductor according to claim 1, wherein the ion implantation step is performed at a temperature of 500[deg.] C. or more and 800[deg.] C. or less.

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