JP7261595B2 - Display device - Google Patents

Description

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device capable of displaying a plurality of colors.

It has been a long time since many new display devices with thin flat display panels using the principles of liquid crystal, electroluminescence, etc. have been used in place of conventional cathode-ray tubes. Some liquid crystal display devices are characterized not only by being thin and lightweight, but also by being able to be driven at a low voltage. A liquid crystal display device forms a liquid crystal layer between two substrates. One substrate is an array substrate in which a plurality of pixels are arranged in a matrix to form a display area. The other substrate is a counter substrate, and may form a color filter or the like.

In particular, in a thin film transistor (TFT) type liquid crystal display device, each pixel on an array substrate is provided with a TFT, which is a switching element, and each pixel can independently hold a voltage for driving a liquid crystal layer. High-quality display with little talk is possible. Further, each pixel is provided with a gate wiring (scanning wiring) for controlling ON/OFF of the TFT and a source wiring (signal wiring) for inputting image data. Each pixel usually corresponds to a region surrounded by gate wiring and source wiring.

For recent liquid crystal display devices, a fringe field switching (FFS) system, which has excellent viewing angle characteristics and high light transmittance, has been proposed. An FFS-type liquid crystal display device performs display by applying a fringe electric field (an oblique electric field including both horizontal electric field and vertical electric field components) to a liquid crystal layer. In the FFS liquid crystal display device, a transparent pixel electrode and a transparent common electrode (transparent counter electrode, transparent common electrode) are formed on one side of the array substrate, and the transparent pixel electrode and the transparent common electrode are stacked vertically via an insulating film. be done. Normally, the lower layer side is a plate-shaped (sometimes branched) electrode, and the upper layer side is an electrode having a plurality of slits at approximately the same positions as the plate-shaped electrodes on the lower layer side. The liquid crystal is controlled by the electric field from the lower layer electrode side. At this time, a high light transmittance can be achieved by forming both the pixel electrode and the common electrode from a transparent conductive film.

Such FFS type liquid crystal display devices having wide viewing angle characteristics and high transmittance are being developed for various applications. Among these, recently, as a demand that emphasizes product design, there is a strong demand for a narrower frame that is the periphery of the display area.

These liquid crystal display devices have a liquid crystal display panel forming a display area in which a plurality of pixels are arranged in a matrix. In the liquid crystal display panel, around the display area, there are an area where driver ICs are mounted for outputting gate signals and source signals for driving the liquid crystal to gate wirings and source wirings, respectively, and a display area where signals from the driver ICs are mounted. and a frame region having a region in which a lead-out wiring for transmission to the gate wiring and the source wiring is formed. Since the gate wiring and the source wiring intersect within the display area, the mounting portions of the gate IC and the source IC and each routing wiring are formed on at least two sides of the display area, which makes it difficult to narrow the frame.

Further, even if the gate IC and the source IC are formed only on one side, it is necessary to form the routing wiring on sides other than the one side. (Patent Document 1) Therefore, a structure has been proposed in which the mounting area is concentrated on only one side, and a gate lead-out wiring for transmitting a gate signal is formed in the display area, thereby narrowing the frame other than the IC mounting. there is (Patent Document 2) Furthermore, in order to suppress the influence on the image caused by noise when the gate lead-out wiring and the signal wiring are brought close to each other, the gate lead-out is performed in the pixels corresponding to the colors with high luminosity in the display area. A structure has been proposed in which the wiring and the signal wiring are formed separately. (Patent Document 3)

Japanese Unexamined Patent Publication No. 9-311341 JP-A-10-78761 Japanese Unexamined Patent Publication No. 2001-43774

As in Patent Document 3, in the case of a structure in which the distance between the lead-out line of the scanning line and the signal line is close to the pixel corresponding to the color with low luminosity, although the luminosity is low, the influence on the display image can be completely eliminated. It is difficult to suppress In addition, if the routing lines for the scanning lines are formed without considering the size of the pixel aperture region, the wiring may cause a decrease in the pixel aperture ratio. Furthermore, in order to compensate for the decrease in brightness of the display device due to the decrease in pixel aperture ratio, it becomes necessary to increase the brightness of the backlight, which may increase power consumption.

The present invention has been made in view of the above problems, and provides a liquid crystal display panel that suppresses a decrease in the aperture ratio, reduces the size of the frame, and has a good design, and a liquid crystal display panel equipped with such a liquid crystal display panel. An object of the present invention is to provide a display device.

A display device according to the present invention comprises a first substrate, the first substrate comprising a horizontally extending gate line, a vertically extending source line, and a vertically extending vertical gate connected to the gate line. and a pixel partitioned by an intersection of the gate wiring and the source wiring. A pixel electrode and a thin film transistor connected to the source wiring are formed in the pixel, and a desired display is performed. wherein the pixels have a first pixel, a second pixel, a third pixel and a fourth pixel, wherein the first pixel, the second pixel and the fourth pixel are defined. The third pixel and the fourth pixel are connected in this order to the same gate wiring, and the horizontal width of the aperture region in the first pixel is the same as that in the second pixel. The width of the aperture region in the horizontal direction is narrower than the width of the aperture region in the third pixel in the horizontal direction, and the vertical gate wiring is narrower than the width in the horizontal direction of the aperture region in the first pixel and the width of the aperture region in the third pixel. a non-aperture region between the aperture regions of the two pixels, a non-aperture region between the aperture region of the second pixel and the aperture region of the third pixel, and the A display characterized by being arranged in a non-aperture region other than the narrowest non-aperture region among non-aperture regions between the aperture region of the third pixel and the aperture region of the fourth pixel. It is a device.

According to the present invention, it is possible to provide a liquid crystal display device capable of narrowing the frame without lowering the transmittance.

1 is a plan view of a liquid crystal display panel according to the present invention; FIG. 2 is a plan view of the array substrate according to Embodiment 1; FIG. 1 is a cross-sectional view of a panel according to Embodiment 1; FIG. 2 is a cross-sectional view of the array substrate according to Embodiment 1; FIG. 8 is a plan view of an array substrate according to Embodiment 2; FIG. FIG. 8 is a cross-sectional view of a panel according to Embodiment 2; FIG. 11 is a plan view of an array substrate according to Embodiment 3; FIG. 11 is a cross-sectional view of a panel according to Embodiment 3; FIG. 11 is a plan view of an array substrate according to Embodiment 4; FIG. 11 is a cross-sectional view of a panel according to Embodiment 4; FIG. 11 is a plan view of an array substrate according to Embodiment 5; FIG. 14 is a plan view of an array substrate according to Embodiment 6; FIG. 14 is a cross-sectional view of an array substrate according to Embodiment 6; FIG. 14 is a plan view of an array substrate according to Embodiment 7; FIG. 14 is a cross-sectional view of a panel according to Embodiment 7; FIG. 21 is a plan view of an array substrate according to an eighth embodiment; FIG. 20 is a cross-sectional view of a panel according to Embodiment 8; FIG. 21 is a cross-sectional view of an array substrate according to an eighth embodiment; FIG. 10 is a plan view of an array substrate according to a different form;

<A. Embodiment 1>
<A-1. Configuration>
FIG. 1 is a plan view of a liquid crystal display panel according to Embodiment 1. FIG. As shown in FIG. 1, the liquid crystal display panel according to the first embodiment includes a display area 1 corresponding to a display section on which an image is displayed in a display device, and a frame area 2 around the display area 1. have. FIG. 1 shows a configuration in which the TFT array substrate 100 and the counter substrate 200 overlap each other, and the counter substrate 200 overlaps at least the display area 1 . Although not shown, a liquid crystal, which is an electro-optical material, is enclosed between the two substrates, and is sealed by a known method such as sealing so that the liquid crystal does not leak. Hereinafter, elements formed on the TFT array substrate 100 in FIG. 1 will be mainly described.

In FIG. 1, the gate wiring 4 extends horizontally in the display area 1, and the source wiring 5 and the vertical gate wiring 6 extend vertically. Although the source wiring 5 and the vertical gate wiring 6 are drawn so as to be adjacent and parallel in FIG. 1 for easy understanding, part or all of both wirings may overlap. A pixel PX is a region defined by the intersection of the gate wiring 4 and the source wiring 5 with an insulating film interposed therebetween. The display portion of the display device corresponds to at least part of the area where the pixels PX are gathered. Further, in the present invention, for the sake of convenience, the boundary 3 between the display area 1 and the frame area 2 is shown by dividing by one line, and the display area 1 is regarded as an area where the pixels PX are gathered.

Further, a thin film transistor TFT as a switching element is formed in the vicinity of the intersection of the gate wiring 4 and the source wiring 5 . The thin film transistor TFT contributes to the display of an image (including video) in the display area 1 by turning on/off the image signal.

Each gate wiring 4 is connected to a vertical gate wiring 6 within the display area 1, which will be described later. In addition, for the sake of the following description, an area A is shown as an example of an area including a part of the pixels in which the vertical gate lines 6 are not formed in the display area 1 and the frame area 2 . Similarly, a region B is shown as an example of a region composed of pixels in which the vertical gate lines 6 are formed.

In the frame area 2, a gate IC 41 and a source IC 51 are mounted on one side S parallel to the gate wiring 4. As shown in FIG. In the liquid crystal display device, both are connected to terminals (not shown) formed on the array substrate 1 by COG mounting. The opposing substrate 200 is formed smaller than the TFT array substrate 100 so as to expose the frame area 2 on the side S on which the gate IC 41 and the source IC 51 are mounted. On three sides other than the side S, the ends of the counter substrate 200 and the TFT array substrate 100 are aligned, but if the TFT array substrate 100 is larger, they may not be aligned.

Furthermore, the gate IC 41 and the source IC 51 are electrically connected to the FPC 61, which is a flexible substrate, by wiring (not shown). Gate IC 41 and source IC 51 are also connected to circuit board 62 via FPC 61, which is a flexible board. The liquid crystal display panel exchanges signals with the liquid crystal display device through the circuit board 62 .

Furthermore, on the TFT array substrate 1 , a gate lead-out line 24 is formed between the gate IC 41 and the vertical gate line 6 , and a source lead-out line 25 is formed between the source IC 51 and the source line 5 . These routing lines may be formed integrally and simultaneously with the vertical gate wiring 6 and the source wiring 5, respectively.

Next, signal paths will be described. In the liquid crystal display device, the gate signal output from the gate IC 41 is transmitted to the gate wiring 4 via the vertical gate wiring 6 in the display area 1 and the gate lead-out line 24 in the frame area 2 . On the other hand, the source IC 51 is connected to the source wiring 5 via the source lead-out line 25 and supplies the voltage of the video signal to the source wiring 5 . In other words, signal transmission into the display area 1 can be performed without the need for wiring lines other than the one side S side.

Although not shown, the TFT array substrate 100, which is the first substrate shown in FIG. constitutes a liquid crystal display panel. Further, the liquid crystal display panel and the driving member are connected to each other so that the light from the light source is transmitted through the liquid crystal panel and the optical sheet, and the liquid crystal display panel is attached to the housing together with the optical sheet and the backlight equipped with the light source. The liquid crystal display device is completed by putting them together.

FIG. 2 is a plan view of an array substrate showing patterns formed in area A within display area 1 of FIG. FIG. 3 is a sectional view of the panel taken along line AA' in FIG. FIG. 4 is a cross-sectional view taken along the line BB' in FIG. 2, more specifically, a cross-sectional view of a connecting portion in the array substrate.

In FIG. 2 , vertically extending source wiring 5 and vertical gate wiring 6 cross gate wiring 4 .

Pixels PX are defined by the intersections of the gate lines 4 and the source lines 5, and 4×2=8 pixels are shown in FIG. 2 as an example. Each pixel in this patent corresponds to one of a plurality of colors. A plurality of colors may be appropriately selected from arbitrary colors, but in FIG. 2, each pixel corresponds to one of the three colors of red (R), green (green), and B (blue). drawing.

Two pixels PXR1 and PXR2 are pixels corresponding to red (R). Four pixels PXG1, PXG2, PXG3, and PXG4 are pixels corresponding to green (G). Two pixels PXB1 and PXB2 are pixels corresponding to blue (B). Although only eight pixels are shown in FIG. 2, other pixels are spread out in a similar arrangement within the display area.

In this embodiment, the pixels PXG1, PXG2, PXG3, and PXG4 are called the first pixels, the pixels PXR1 and PXR2 are called the second pixels, and the pixels PXB1 and PXB2 are called the third pixels when comparing the respective colors. Sometimes.

In FIG. 2, a pixel electrode 8 and a slit 7 of a common electrode 15 extending over the entire surface are formed in a pixel, which is a region partitioned by the intersection of the gate wiring 4 and the source wiring 5 . A thin film transistor TFT electrically connected to the pixel electrode 8 and the source line 5 is also formed.

Details will be described later with reference to FIG. Also, in FIG. 2, a connection portion 22 where the vertical gate wiring 6 and the gate wiring 4 overlap is shown as a dotted circle. The connection portion 22, including the contact hole 18 in the connection portion 22, will be described later with reference to FIG. Furthermore, a rectangular pattern is drawn as an opening region OP in the center of each pixel, but this is a region corresponding to a region where no black matrix is formed. .

Next, the structure of the array will be described with reference to FIG. 3, which is a sectional view. As shown in FIG. 3, the TFT array substrate 100 includes an insulating substrate 16, a gate wiring 4, a gate insulating film 13, a channel layer 12, a source electrode 11, a drain electrode 10, a source wiring 5, a pixel electrode 8, and a first interlayer. It has an insulating film 14 , a vertical gate wiring 6 , a second interlayer insulating film 17 and a common electrode 15 .

As will be described later in the description of the manufacturing method, these electrodes and wiring are appropriately selected metal films or transparent conductive films, and the insulating films are, for example, silicon nitride films, silicon oxide films, resin films, and the like. In addition, the channel layer 12 is generally an a-Si film, but may be, for example, a crystalline silicon film or an oxide semiconductor film such as In--Ga--Zn--O.

A transparent substrate such as a glass substrate or a quartz substrate is used for the insulating substrate 16 . A gate wiring 4 is provided on the surface of the insulating substrate 16 . A gate insulating film 13 which is a first insulating film is provided on an insulating substrate 16 including the gate wiring 4 .

A channel layer 12 , a source electrode 11 and a pixel electrode 8 are provided on the gate insulating film 13 . The channel layer 12 is positioned so as to partially overlap the gate wiring 4 with the gate insulating film 13 interposed therebetween. A source electrode 11 branched from the source wiring 5 is provided on the channel layer 12 . A drain electrode 10 is provided over the channel layer 12 and the gate insulating film 13 . As described above, a thin film transistor having an inverted staggered structure is formed as a switching element.

A pixel electrode 8 which is also a transparent pixel electrode is formed on the drain electrode 10 and is also electrically connected to the drain electrode 10 . In FIG. 2, the pixel electrode 8 is represented by a rectangle, and part of the pixel electrode 8 is provided over the gate insulating film 13 where the drain electrode 10 is not formed, and covers most of one pixel. occupy

A first interlayer insulating film 14 is provided on these gate insulating film 13 , pixel electrode 8 , channel layer 12 , source electrode 11 , drain electrode 10 and source line 5 . A vertical gate wiring 6 is formed on the first interlayer insulating film 14 . Although it is necessary to form the vertical gate wiring 6 in a layer different from that of the gate wiring 4, in the first embodiment, it is formed in a layer different from that of the source wiring 5, so that it is formed above the first interlayer insulating film 14. There is a need to.

A second interlayer insulating film 17 is provided on the first interlayer insulating film 14 and the vertical gate wiring 6 . Furthermore, a common electrode 15 which is also a transparent common electrode is formed on the second interlayer insulating film 17 . At this time, the vertical gate wiring 6 is formed in a layer different from that of the pixel electrode 8 and the common electrode 15 .

2 and 3, the common electrode 15 is formed over the entire surface of the display area 1 except for the slit 7, the connection portion 22, and the vicinity of each of the thin film transistors (the area indicated by a rectangle in FIG. 2). It is Therefore, in FIG. 2, the common electrode 15 also covers the source wiring 5 with the first interlayer insulating film 14 and the second interlayer insulating film 17 interposed therebetween. In this way, the structure in which the common electrode 15 covers the source line 5 is effective in suppressing application of an unnecessary electric field from the source line 5 to the liquid crystal. FIG. 2 shows a mode in which the common electrode 15 is not formed in the rectangular region extending over the connection portion 22 and the thin film transistor TFT adjacent to the connection portion. may be

2 and 3, the pixel electrode 8 and the common electrode 15 are insulated from each other through the first interlayer insulating film 14 and the second interlayer insulating film 17, and overlap each other. The part overlaps with the pixel electrode 8 . Therefore, the fringe electric field generated between the common electrode 15 and the pixel electrode 8 in the vicinity of the slit 7 drives the liquid crystal molecules to display an image. A storage capacitor for stabilizing the pixel potential is formed between the pixel electrode 8 and the common electrode 15 . Therefore, the common electrode 15 needs to be formed in a layer different from that of the pixel electrode 8 . Also, in FIG. 2, the pixel electrode 8 is drawn as a rectangle, and the pixel electrode 8 is not formed with a slit.

Next, the connecting portion 22 will be described with reference to FIGS. 2 and 4. FIG. In FIG. 4, a contact hole 18a, which is a first contact hole, is opened in the gate insulating film 13, the first interlayer insulating film 14, and the second interlayer insulating film 17 above the gate wiring 4. As shown in FIG. Similarly, a contact hole 18b, which is a second contact hole, is opened in the second interlayer insulating film 17 above the vertical gate wiring 6. As shown in FIG. A connection film 15a is formed on the second interlayer insulating film 17 so as to cover the contact holes 18a and 18b.

The connection portion 22 indicates a structure for connecting the gate wiring 4 and the vertical gate wiring 6. In FIG. 4, the connection film 15a connects the gate wiring 4 and the vertical gate wiring 6 through the contact holes 18a and 18b. A structure is shown electrically connecting the . In the structure shown in FIG. 4, the gate potential is also applied to the connection film 15a.

The connection film 15 a may be formed of the same material as the common electrode 15 at the same time, but in that case, it must be electrically insulated from the common electrode 15 . For example, the connection film 15a and the common electrode 15 may be formed simultaneously as separate patterns. Alternatively, the connection film 15 a may be formed separately from a material different from that of the common electrode 15 . Also, in the present embodiment, it is possible to directly connect both without the connection film 15a interposed therebetween, but this form will be described later.

2 and 4, since the second contact hole 18b is arranged on the gate line 4, the formation of the contact hole can suppress the decrease in the aperture ratio of light transmission in the pixel. However, if the aperture ratio of the pixel does not matter, the second contact hole 18b may be arranged at a location different from the gate line 4. FIG.

At least one connecting portion 22 described here is provided in each gate wiring 4 as shown in FIG. 2, where each gate wiring 4 is also electrically connected to the vertical gate wiring 6 . In FIG. 2, each vertical gate wiring 6 extends from the frame region 2 to reach the connecting portion 22, but does not extend further. Therefore, in FIG. 2, the lengths of the vertical gate wirings 6 are not the same. Although the vertical gate wiring 6 may be extended beyond the connecting portion 22, the capacitance between the two may increase in such a case, causing a display defect. Therefore, the form as shown in FIG. 2 is adopted.

Although not shown in FIG. 2, one gate wiring 4 may be connected to a plurality of vertical gate wirings 6 via a plurality of connecting portions 22. FIG. In this case, the same gate potential is applied to the plurality of connected vertical gate lines 6 and transmitted to the gate line 4 during the horizontal scanning period of the gate line 4 . This is achieved by connecting only the gate wiring 4 in the region with the long vertical gate wiring 6 to a plurality of vertical gate wirings 6 when there are regions in which the vertical gate wiring 6 is long and regions in which the vertical gate wiring 6 is short in the display area 1 . , is effective when it is desired to reduce the difference in wiring resistance up to each region.

The structure on the TFT array substrate has been mainly described above with reference to FIGS. Next, the correspondence relationship between the TFT array substrate and the counter substrate will be described with reference to FIGS. 2 and 3. FIG. As shown in FIG. 3, a counter substrate 27 is provided with a black matrix 26 and a colored layer 28, which are light shielding materials. While the black matrix is formed, the colored layer 28 is formed in the open area without the black matrix 26 formed, and faces each pixel. Light projected from the backlight is blocked by the black matrix and passes through the colored layer 28 in the area where the black matrix is not formed.

Therefore, a region where no black matrix is formed is sometimes called an open region. The open area is indicated by OP in FIGS. A region indicated by region 0P in FIG. 2 corresponds to a region where the black matrix 26 is not formed. Here, the color of the light after passing through the colored layer 28 facing the pixels PXG1, PXG2, PXG3, and PXG4 is green. The other pixels also face the colored layers 28 that generate transmitted light of corresponding colors.

On the other hand, the area other than the open area may be called a non-open area. In FIG. 2, the non-aperture area is a boundary area between pixels and is almost synonymous with the area where the black matrix 26, which is a light shielding material, is formed. Here, although FIG. 2 is a plan view of the TFT array substrate, the opening region OP is also illustrated in order to make the relative positional relationship with the black matrix 26 formed on the counter substrate 27 easy to understand. there is

In FIG. 2, a black matrix is formed in a region other than the rectangular opening region OP. In other words, the black matrix 26 is formed in a grid pattern so as to face the boundaries between pixels. At this time, the black matrix faces at least part of the gate wiring 4 and part of the source wiring 5 .

Here, in FIG. 2, the first black matrix 26a facing the boundary between the first pixels PXG1 and PXG2 and the third pixels PXB1 and PXGB2, the third pixels PXB1 and PXB2 and the second pixels A second black matrix 26b facing the boundary between PXR1, PXR2 and a third black matrix 26c facing the boundary between the second pixels PXR1, PXR2 and the first pixels PXG3, PXG4 are shown. ing. The black matrix is also formed in a region facing the gate wiring 4, but is not specifically described here, and the width of the formation region is shown based on the direction along the source wiring.

In Embodiment 1, as shown in FIG. 2, the size of the opening regions OP1 in the first pixels PXG1, PXG2, PXG3, and PXG4 is the same as that of the second pixels PXR1, PXR2 and the third pixels PXB1, PXB2. It is made smaller than the opening regions OP2 and OP3. This is because the width of the black matrix 26a formed between the first pixels PXG1, PXG2 and the third pixels PXB1, PXB2 is larger than the widths 26b, 26c of the black matrices formed at other positions. according to. In this way, even if the dimensions of the pixels themselves are the same, it is possible to adjust the size of the aperture region by arranging the black matrix so that the width of each pixel is different.

As an effect of making the width of the aperture region of each pixel different according to the color, it is possible to adjust the color tone of the liquid crystal display panel without changing the optical characteristics of the backlight and the color filter. Specifically, for example, when it is desired to enhance yellow in order to match the color spectrum of the backlight, the aperture area of the third pixel may be made smaller than the aperture areas of the first and second pixels. As shown in FIG. 2, the size of the opening area of the black matrix 26 for each colored layer 28 may be adjusted for the purpose of adjusting the white color of the liquid crystal display panel. Alternatively, if there is a need for the white balance of the image displayed on the liquid crystal display panel, etc., the desired display can be achieved by adjusting the size of the aperture region of each color pixel accordingly.

In the present invention, as shown in FIG. 2, the black matrix 26 and the black matrix 26 between the first pixels PXG1, PXG2 and the third pixels PXB1, PXB2 in the non-aperture area under the black matrix of the counter substrate 27 It is characterized by forming a vertical gate wiring 6 in the overlapping region. In other words, the configuration shown in FIG. 2 is characterized in that the vertical gate wiring 6 is formed under the widest black matrix. It can also be said that the form shown in FIG. 2 is characterized in that the vertical gate wiring is arranged so as to be adjacent to the first pixel having the smaller opening region OP. Also, if the magnitude relationship of the aperture ratio of each pixel is directly related to the magnitude relationship of the non-aperture regions between pixels, the region in which the vertical gate wiring is formed is the aperture ratio smaller than that of the pixel with the highest aperture ratio. It can also be called a non-aperture region located between pixels having . Furthermore, in other words, it can be said that the vertical gate wiring is formed in a region other than the narrowest non-opening region among the non-opening regions.

Originally, from the necessity of the color balance of the display image, in the panel where it is necessary to widen the width of the predetermined black matrix by changing the area of the opening region for each corresponding color, This means that the vertical gate wiring 6 is formed. Such an effect can be achieved by comprehensive optimization that takes into consideration not only the aperture ratio of the TFT array substrate but also the panel design such as the color filter.

Note that in FIG. 2, the area of the opening regions OP1 in the first pixels PXG1 and PXG2 is made smaller than the area of the opening regions OP2 and OP3 in the second pixels PXB1 and PXB2 and the third pixels PXR1 and PXR2. Although formed, it is not limited to this form. For example, if the optical characteristics of the liquid crystal display panel require that the area of the aperture region of the blue pixel be the smallest among the pixels of each color, the black matrix between the second pixel and the third pixel may be formed. The width is made wider than the width of other black matrices, and the area of the aperture region of the second pixel is made smaller than the aperture regions of the pixels of other colors. Then, a vertical gate line may be formed between the second pixel and the third pixel and under the black matrix facing each other.

With such a structure, in Embodiment 1, since the vertical gate wiring 6 is provided in the display area 1, the aperture ratio of the pixel is not lowered and the frame can be narrowed. A display device can be realized.

In addition, as shown in FIG. 2, the vertical gate wiring 6 is arranged in the non-opening region so as not to overlap the source wiring 5 . This is to prevent an increase in capacitance between the source wiring 5 and the vertical gate wiring 6 . If the non-opening area is small and the vertical gate wiring 6 and the source wiring 5 cannot be prevented from overlapping each other, the vertical gate wiring 6 and the source wiring 5 are arranged within the range of the non-opening area in order to reduce the capacitance. It is desirable to install so that the overlapping area of

With the configuration described above, in Embodiment 1, since it is not necessary to arrange the vertical gate wiring 6 and other lead wirings in the frame area 2 around the display area 1, the frame area 2 can be displayed regardless of the resolution. can be narrowed.

Moreover, since the vertical gate wiring 6 arranged in the display area 1 is formed so as to overlap with the black matrix 19, it is possible to ensure the same transmittance as in the conventional case. In other words, according to the first embodiment, it is possible to realize an FFS mode liquid crystal display device capable of narrowing the frame regardless of the resolution without lowering the display performance.

<A-2. Manufacturing process>
Next, the manufacturing process of the TFT array substrate 100 shown in FIG. 2 or 3 will be described. First, a first metal film to be the gate wiring 4 is formed on the insulating substrate 16 by a sputtering method using a DC magnetron. The first metal film may be Mo, Cr, W, Al, Ta, or an alloy film containing these as main components. After that, patterning is performed to obtain the gate wiring 4 . Next, a gate insulating film 13 is formed by plasma CVD. A silicon nitride film is generally used for the gate insulating film 13, but a silicon oxide film, a silicon oxynitride film, or the like may be used. When an oxide semiconductor is used as a semiconductor film, which will be described later, a silicon oxide film is preferable.

After forming the gate insulating film 13, an a-Si film (amorphous silicon film) is formed by plasma CVD. The a-Si film generally has a laminated structure of an intrinsic semiconductor layer forming the channel layer 12 and an impurity semiconductor layer containing phosphorus or the like. The impurity semiconductor layer is for ensuring ohmic contact with the source electrode 11 and the drain electrode 10 which will be described later. After that, patterning is performed to obtain a channel layer 12 as an island-shaped a-Si film. Note that the semiconductor layer may be formed using an oxide semiconductor film formed by sputtering. In this case, formation of the ohmic contact layer is not necessarily required.

Next, a second metal film is formed by a sputtering method using a DC magnetron. The second metal film may be Mo, Cr, W, Al, Ta, or an alloy film containing these as main components. After that, patterning is performed to obtain the source electrode 11 , the drain electrode 10 and the source wiring 5 . Here, the impurity semiconductor layer for obtaining ohmic contact with the source electrode 11 and the drain electrode 10 may be etched using the source electrode 11 and the drain electrode 10 as a mask in order to reduce the mask man-hour.

After the formation of the source electrode 11, the drain electrode 10, and the source wiring 5, a first transparent conductive film, which becomes the pixel electrode 8, is formed by a sputtering method using a DC magnetron. The first transparent conductive film can be made of ITO, IZO (Indium Zinc Oxide), or the like. Patterning is then performed to obtain transparent pixel electrodes 8 .

After forming the pixel electrode 8, a first interlayer insulating film 14 is formed by plasma CVD. The first interlayer insulating film 14 can be formed of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like. Alternatively, the first interlayer insulating film 14 may be formed by applying an acrylic or imide organic resin film in order to secure insulation by increasing the thickness. Furthermore, the first interlayer insulating film 14 may be formed by stacking a silicon nitride film, a silicon oxide film or a silicon oxynitride film and an organic resin film.

Next, a third metal film is formed by a sputtering method using a DC magnetron. The third metal film may be Mo, Cr, W, Al, Ta, or an alloy film containing these as main components. After that, patterning is performed to obtain the vertical gate wiring 6 .

After that, a second interlayer insulating film 17 is formed by plasma CVD. The second interlayer insulating film 17 can be formed of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like. Alternatively, the second interlayer insulating film 17 may be formed by applying an acrylic or imide organic resin film to a thickness of 1 to 3 μm in order to secure insulation by increasing the film thickness. Furthermore, the second interlayer insulating film 17 may be formed by laminating a silicon nitride film, a silicon oxide film or a silicon oxynitride film and an organic resin film.

After that, a contact hole (not shown) is formed for conducting to the first metal film, the second metal film, the third metal film or the first transparent conductive film.

After forming the contact holes, a second transparent conductive film to be the common electrode 15 is formed. The second transparent conductive film can be composed of ITO, IZO, or the like. After that, patterning is performed to obtain the common electrode 15 . During this patterning, slits 7 are formed in the common electrode 15 on the pixel electrode 8 .

The TFT array substrate thus completed is bonded to a counter substrate having a black matrix and colored layers such as RGB as shown in FIG. be done. Gate ICs and source ICs are mounted on the TFT array substrate as shown in FIG. 1, and the gate ICs and source ICs are connected to the driving circuit substrate through FPCs. After that, it is incorporated into a light source such as an LED or a backlight having an optical sheet to complete a liquid crystal display device.

In this embodiment, the structure in which the black matrix and the colored layers are formed on the opposing substrate has been described, but at least one of the black matrix and the colored layers may be formed on the TFT array substrate. . When the black matrix is formed on the TFT array substrate, it is formed so that at least a part thereof overlaps with the gate wiring, the source wiring and the TFT. When the colored layer is formed on the TFT array substrate, it is formed so as to overlap most of the pixel electrodes.
<B. Embodiment 2>

FIG. 5 is a plan view of the array substrate according to the second embodiment, and corresponds to an enlarged plan view of region A in FIG. 6 is a cross-sectional view of the panel taken along line CC' in FIG. In order to avoid duplication and redundancy of description, elements having the same or corresponding functions are given the same reference numerals in each drawing of each embodiment.

Unlike the first embodiment, the second embodiment is characterized in that the source wiring 5 and the vertical gate wiring 6 are at least partially overlapped. Furthermore, as in the first embodiment, the vertical gate wiring 6 formed on the source wiring 5 is provided in a non-aperture region adjacent to a pixel having a smaller aperture region than a pixel having the largest aperture region. and

As shown in the cross-sectional view CC' of FIG. 6, the vertical gate wiring 6 is formed on the first interlayer insulating film 14 and is formed by two types of colored layers adjacent to each other. 28b to overlap. By doing so, even if the width of the non-opening region is narrow, the vertical gate wiring 6 can be arranged without lowering the transmittance.

Within the scope of the invention, the embodiments can be appropriately modified or omitted.
<C. Embodiment 3>

FIG. 7 is a plan view of an array substrate according to Embodiment 3, and corresponds to a plan view in which area A in FIG. 1 is enlarged. FIG. 8 is a sectional view of the panel taken along line DD' in FIG. In order to avoid duplication and redundancy of description, elements having the same or corresponding functions are given the same reference numerals in each drawing of each embodiment.

As shown in FIG. 7, the pixel electrodes 8a in the first pixels PXG1 and PXG2 are formed to be smaller in size than the pixel electrodes 8 in the other pixels. Further, the separation distance between the pixel electrode 8a and the adjacent source line 5 is formed to be larger than the separation distance in other pixels. As described above, the third embodiment is characterized by reducing the size of the transparent pixel electrode 8 and forming it so as not to overlap the vertical gate wiring 6 . That is, there is no overlapping region between the vertical gate wiring 6 and the transparent pixel electrode 8 . Therefore, the capacitance between the vertical gate wiring 6 and the transparent pixel electrode can be reduced. Further, as in the first embodiment, the vertical gate wiring 6 formed on the source wiring 5 is provided in a non-aperture region adjacent to a pixel having a smaller aperture region than a pixel having the largest aperture region. there is

With such a configuration, the gate signal delay caused by the capacitive coupling between the vertical gate wiring 6 and the transparent pixel electrode 8 and the potential fluctuation of the transparent pixel electrode 8 can be suppressed, and the frame can be narrowed while maintaining the transmittance and display quality. It becomes possible.

Within the scope of the invention, the embodiments can be appropriately modified or omitted. For example, in FIG. 7 of Embodiment 3, the edges of the pattern of the pixel electrode 8 are drawn so as to overlap the slits 7, but such a structure is not necessarily required.
<D. Embodiment 4>

FIG. 9 is a plan view of an array substrate according to Embodiment 4, which corresponds to an enlarged plan view of region A in FIG. FIG. 10 is a cross-sectional view of the panel taken along line EE' in FIG. In order to avoid duplication and redundancy of description, elements having the same or corresponding functions are given the same reference numerals in each drawing of each embodiment.

The fourth embodiment is characterized in that the size of the transparent pixel electrode is reduced in the same manner as in the third embodiment, and the length of the slit 7 is reduced. In FIG. 9, in the first pixels PXG1 to PXG4 adjacent to the vertical gate line 6, the length of one slit 7 is shortened. In the third embodiment, the storage capacity formed between the pixel electrode 8a and the common electrode 15 in the first pixels PXG1 to PXG4 is smaller than the storage capacity in other pixels. Here, the area of the slit does not contribute to the storage capacity between the transparent pixel electrode and the common electrode. Therefore, by making the area of the slit 7 in the first pixel smaller than that in the other pixels as in the fourth embodiment, a storage capacity equivalent to that of the other pixels in which the vertical gate line 6 is not provided is formed. be able to.

Furthermore, as in the first embodiment, the vertical gate wiring 6 formed on the source wiring 5 is provided in a non-aperture region adjacent to a pixel having a smaller aperture region than a pixel having the largest aperture region. . With such a form, it is possible to narrow the frame while maintaining the display quality. Further, the present invention can be modified or omitted as appropriate within the scope of the invention.
<E. Embodiment 5>

FIG. 11 is a plan view of an array substrate according to Embodiment 4, and corresponds to a plan view in which area A in FIG. 1 is enlarged. In order to avoid duplication and redundancy of description, elements having the same or corresponding functions are given the same reference numerals in each drawing of each embodiment.

Embodiment 5 is characterized in that the size of the transparent pixel electrode 8 is reduced and the size of the TFT is also reduced in the pixel where the vertical gate wiring is arranged. That is, in the first pixel, the size of the transparent pixel electrode 8 is reduced and the size of the TFT is also reduced.

When the size of the transparent pixel electrode 8 is reduced, the storage capacity formed between the transparent pixel electrode 8 and the common electrode 15 becomes smaller. The characteristics change, and as a result, luminance unevenness occurs. Therefore, for a pixel in which the vertical gate wiring 6 is arranged and the size of the transparent pixel electrode 8 is reduced, the TFT size (for example, the channel width) is reduced so as to correspond to the reduction in the storage capacity. Therefore, the charging characteristics between pixels can be made uniform.

FIG. 11 shows a mode in which the width W1 of the drain electrode 10a in the first pixel is smaller than the width W2 of the drain electrode 10 in the second and third pixels. With this configuration, the channel width of the thin film transistor in the first pixel can be made smaller than the channel width of the thin film transistor in the second pixel. Furthermore, as in the first embodiment, the vertical gate wiring 6 formed on the source wiring 5 is provided in a non-aperture region adjacent to a pixel having a smaller aperture region than a pixel having the largest aperture region. there is With such a form, it is possible to narrow the frame while maintaining the display quality.

Within the scope of the invention, the embodiments can be appropriately modified or omitted. For example, only the channel length in the first pixel may be lengthened.
<F. Embodiment 6>

FIG. 12 is a plan view of an array substrate according to Embodiment 4, which corresponds to an enlarged plan view of region A in FIG. FIG. 13 is a sectional view of the panel taken along line FF' in FIG. In order to avoid duplication and redundancy of description, elements having the same or corresponding functions are given the same reference numerals in each drawing of each embodiment.

In the first embodiment, as shown in FIG. 4, the vertical gate wiring 6 and the gate wiring 4 are electrically connected to each other through the contact holes 18a and 18b formed in each insulating film and the connection film 15a at the connection portion 22. In the above description, the form in which the two terminals are physically connected has been described.

A gate signal is applied to the connection film 15a. If the connection film 15a is formed in the uppermost layer as shown in FIG. 4, the voltage of the applied gate signal may disturb the liquid crystal orientation near the connection film 15a. have a nature. Furthermore, this disturbance may lead to the occurrence of defects such as light leakage that degrade the display quality. Although it is conceivable to cover with an insulating film only as a countermeasure, it causes an increase in manufacturing cost.

Therefore, in the sixth embodiment, as shown in FIG. 13, in the region where the gate wiring 4 and the vertical gate wiring 6 overlap, the gate insulating film 13 and the first interlayer insulating film 14 between them are removed. A structure in which the gate wiring 4 and the vertical gate wiring 6 are directly contacted by opening a penetrating third contact hole 18c is adopted. Further, the contact hole 18 c and the vertical gate wiring 6 are covered with the second interlayer insulating film 17 in the connecting portion 22 . Furthermore, as in the first embodiment, the vertical gate wiring 6 formed on the source wiring 5 is provided in a non-aperture region adjacent to a pixel having a smaller aperture region than a pixel having the largest aperture region. there is

To realize an FFS mode liquid crystal display device which can expect the same effect as the first embodiment by the above structure and can suppress the deterioration of display quality because the conductive film having the potential of the gate signal is covered with the insulating film. can be done. Further, the sixth embodiment can be applied together with the first to fifth embodiments.

Within the scope of the invention, the embodiments can be appropriately modified or omitted. For example, when applying the present embodiment to the fourth or fifth embodiment, the insulating films for opening the third contact hole 18c are the gate insulating film 13 and the first interlayer insulating film 14, as well as the third insulating film. The two-layer insulating film 17 is also targeted.
<G. Embodiment 7>

FIG. 14 is a plan view of an array substrate according to Embodiment 4, and corresponds to a plan view in which area A in FIG. 1 is enlarged. FIG. 15 is a sectional view of the panel taken along the line GG' in FIG. In order to avoid duplication and redundancy of description, elements having the same or corresponding functions are given the same reference numerals in each drawing of each embodiment.

In FIG. 15, the transparent pixel electrode 8 is provided on the first interlayer insulating film 14 and connected to the drain electrode 10 through the contact hole 18d. The vertical gate wiring 6 is provided on the second interlayer insulating film 17 and the common electrode 15 is provided on the third interlayer insulating film 19 . Further, as in the first embodiment, the vertical gate wiring 6 formed on the source wiring 5 is provided in a non-aperture region adjacent to a pixel having a smaller aperture region than a pixel having the largest aperture region. there is

With such a configuration, even in an array substrate in which the pixel electrode and the drain electrode are arranged in different layers, it is possible to narrow the frame while maintaining the display quality. In addition, it may be appropriately combined with the modes described in the second to sixth embodiments. For example, as in the mode described with reference to FIG. 13 in the sixth embodiment, the structure may be such that the gate wiring 4 and the vertical gate wiring 6 are directly contacted through a contact hole opened in the insulating film.
<H. Embodiment 8>

FIG. 16 is a plan view of an array substrate according to Embodiment 8, and corresponds to an enlarged plan view of region A in FIG. 17 is a sectional view of the panel taken along the line HH' in FIG. 16, and FIG. 18 is a sectional view of the panel taken along the line II' in FIG. In order to avoid duplication and redundancy of description, elements having the same or corresponding functions are given the same reference numerals in each drawing of each embodiment.

In FIG. 17, vertical gate wiring 6 is formed in the same layer as source wiring 5 . Specifically, the vertical gate wiring 6 is provided directly on the gate insulating film 13 like the source wiring 5 . A first interlayer insulating film 14 is formed to cover the source wiring 5 and the vertical gate wiring 6 . The first interlayer insulating film 14 is composed of an inorganic insulating film, an organic insulating film, an organic planarizing film, or a laminate thereof. Also, the common electrode 15 is provided on the first interlayer insulating film 14 . Further, as in the first embodiment, the vertical gate wiring 6 is provided so as to overlap the non-aperture region adjacent to the pixel having the smaller aperture region than the pixel having the largest aperture region in which no black matrix is formed. there is

18, a contact hole 18a, which is a first contact hole, is opened in the gate insulating film 13 and the first interlayer insulating film 14 on the gate wiring 4. As shown in FIG. Similarly, a contact hole 18b, which is a second contact hole, is opened in the first interlayer insulating film 14 above the vertical gate wiring 6. As shown in FIG. A connection film 15a is formed on the first interlayer insulating film 14 so as to cover the contact holes 18a and 18b.

In the first embodiment, the stack of the first interlayer insulating film 14 and the second interlayer insulating film 17 is interposed between the pixel electrode 8 and the common electrode 15. Only the insulating film 14 can be used. Therefore, the capacitance between the pixel electrode 8 and the common electrode 15 can be increased.

16 to 18, even in an array substrate in which the source wiring 5 and the vertical gate wiring 6 are formed in the same layer, it is possible to narrow the frame while maintaining the display quality as in the first embodiment. becomes. In addition, it may be appropriately combined with the modes described in other embodiments. For example, as in the mode described with reference to FIG. 13 in the sixth embodiment, the structure may be such that the gate wiring 4 and the vertical gate wiring 6 are directly contacted through a contact hole opened in the insulating film.

In the embodiment described so far, it is assumed that the colored layers 28 formed on the opposing insulating substrate 27 are arranged in stripes of three colors such as red, green, and blue. Four or more colored layers 28 such as green, blue and white may be used.

FIG. 19 shows a configuration in which four color pixels of R (red), G (green), B (blue), and W (white) are arranged in a square grid. In FIG. 19, pixels of each color are indicated by PXG, PXR, PXB, and PXW. Even in such a case, if the aperture regions of the black matrix 26 are different for each color of the colored layer 28, it is possible to apply this structure by using the non-aperture regions of pixels with narrow aperture regions.

In the first to eighth embodiments of the present invention, the color filters and the black matrix are formed on the counter substrate facing the array substrate, but at least one of them is formed on the array substrate. good too. In this case, the color filter and the black matrix may be formed above the TFT with an insulating film interposed therebetween.

In Embodiments 1 to 8 of the present invention, the mode in which the common electrode having slits is disposed above the plate-shaped pixel electrode has been described. It may be arranged in a higher layer than the electrodes.

In Embodiments 1 to 8 of the present invention, the vertical gate wiring does not necessarily have to cross the gate wiring perpendicularly, and may cross the gate wiring diagonally depending on the arrangement of the pixels. Also, the vertical gate wiring does not necessarily have to be formed in a layer above the first interlayer insulating film. For example, it may be formed in a layer below the gate wiring via an insulating film.

In the first to eighth embodiments of the present invention, the reduction in the aperture ratio may be suppressed by using only the first matrix as the matrix that overlaps the vertical gate wiring.

In Embodiments 1 to 8 of the present invention, a mode in which the color of the first pixel is blue (B) has been described, but the present invention is not limited to such a mode. For example, if it is necessary to maximize the area of the red pixel from the viewpoint of optical design, color filter material, etc., red (R) may be selected as the first pixel.

In Embodiments 1 to 8 of the present invention, only the area of the aperture region of the first pixel is smaller than the area of the aperture regions of the other pixels, but the present invention is not limited to such a configuration. For example, let us consider a case where there is a relationship of the first pixel<second pixel<third pixel with respect to the area of the aperture region when there are three types of display colors.

In this case, if there is not a large difference in the area of each pixel, generally, the width of the black matrix formed between the pixels is: 1st to 2nd pixels > 1st to 3rd pixels > 2nd to 3rd pixels between pixels. In this case, it is best to provide the vertical gate wiring between the first and second pixels. good. This is because the decrease in the aperture ratio can be suppressed more than if it is provided between the second and third pixels. In other words, the vertical gate wiring is formed in a region other than the narrowest non-opening region among the non-opening regions.

1 display area, 2 frame area, 3 boundary, 4 gate wiring, 5 source wiring,
6 vertical gate wiring, 7 slit, 8, 8a pixel electrode,
10, 10a drain electrode, 11 source electrode, 12 channel layer,
13 gate insulating film, 14 first interlayer insulating film,
15 common electrode, 15a connection film, 16 insulating substrate, 17 second interlayer insulating film,
18, 18a, 18b, 18c, 18d contact holes,
19 third interlayer insulating film,
22 connection part, 24 gate lead-out line, 25 source lead-out line,
26, 26a, 26b, 26c black matrix 27 opposing insulating substrate, 28 colored layer 41 gate IC, 51 source IC, 61 FPC, 62 circuit board,
100 TFT array substrate 200 counter substrate PX, PXG, PXR, PXB, PXW pixel,
TFT thin film transistor

Claims (14)

comprising a first substrate;
The first substrate is
gate wiring extending in the horizontal direction;
a vertically extending source wire;
a vertical gate line extending vertically and connected to the gate line;
pixels separated by intersections of the gate wiring and the source wiring;
a pixel electrode and a thin film transistor connected to the source line are formed in the pixel, and an opening region for achieving a desired display is defined;
The pixels have a first pixel, a second pixel, a third pixel and a fourth pixel , and the first pixel, the second pixel , the third pixel and the fourth pixel are connected to the same gate wiring in this order ,
The horizontal width of the aperture region in the first pixel is equal to the horizontal width of the aperture region in the second pixel and the horizontal width of the aperture region in the third pixel. narrower than the width
The vertical gate wiring is formed between the non-aperture region between the aperture region of the first pixel and the aperture region of the second pixel, and the aperture region of the second pixel. A non-aperture region between the aperture region of the third pixel and a non-aperture region between the aperture region of the third pixel and the aperture region of the fourth pixel , wherein the display device is arranged outside the narrowest non-aperture region . The first substrate further has a first interlayer insulating film, a second interlayer insulating film and a common electrode,
the first interlayer insulating film covers the pixel electrode;
the second interlayer insulating film covers the vertical gate wiring;
2. The display device according to claim 1, wherein the common electrode is arranged on the second interlayer insulating film. The first substrate further has a first interlayer insulating film, a second interlayer insulating film, a third interlayer insulating film, and a common electrode,
the pixel electrode is disposed on the first interlayer insulating film,
the second interlayer insulating film covers the pixel electrode;
the vertical gate wiring is disposed on the second interlayer insulating film,
the third interlayer insulating film covers the vertical gate wiring;
2. The display device according to claim 1, wherein the common electrode is arranged on the third interlayer insulating film. the first substrate further includes a first insulating film that insulates the gate wiring and the source wiring; and a connecting portion that electrically connects the gate wiring and the vertical gate wiring,
At the connecting portion,
a first contact hole opened in at least the first insulating film, the first interlayer insulating film, and the second interlayer insulating film above the gate wiring;
a second contact hole opened in at least the second interlayer insulating film on the vertical gate line;
a connection film formed above the second interlayer insulating film and connecting the gate wiring and the vertical gate wiring via the first contact hole and the second contact hole; 3. The display device according to claim 2. The first substrate further has a first interlayer insulating film and a common electrode,
the vertical gate wiring and the source wiring are in the same layer,
the first interlayer insulating film is formed over the source wiring and the vertical gate wiring;
2. The display device according to claim 1, wherein the common electrode is formed in a layer above the first interlayer insulating film. the first substrate further includes a first insulating film that insulates the gate wiring and the source wiring; and a connecting portion that electrically connects the gate wiring and the vertical gate wiring,
At the connecting portion,
a first contact hole opened in at least the first insulating film and the first interlayer insulating film above the gate wiring;
a second contact hole opened in the first interlayer insulating film above the vertical gate line;
a connection film formed above the first interlayer insulating film and connecting the gate wiring and the vertical gate wiring through the first contact hole and the second contact hole; 6. The display device according to claim 5. 7. The display device according to claim 4, wherein the connection film is on the same layer as the common electrode and is made of the same material. the first substrate further includes a first insulating film that insulates the gate wiring and the source wiring; and a connecting portion that electrically connects the gate wiring and the vertical gate wiring,
In the connecting portion, the gate wiring and the vertical gate wiring are directly connected via a third contact hole opened in at least the first insulating film and the first interlayer insulating film on the gate wiring. 3. The display device according to claim 2, which is connected. the first substrate further includes a first insulating film that insulates the gate wiring and the source wiring; and a connecting portion that electrically connects the gate wiring and the vertical gate wiring,
6. A display according to claim 5, wherein in said connecting portion, said gate wiring and said vertical gate wiring are directly connected via a third contact hole opened in at least said first insulating film above said gate wiring. Device. 10. The display device according to claim 1, wherein the pixel electrode in the first pixel has a smaller area than the pixel electrode in the second pixel. 11. The display device according to claim 10, wherein the pixel electrode in the first pixel has a larger separation distance between the pixel electrode and the source line than the pixel electrode in the second pixel. The first substrate has a common electrode,
The common electrode is transparent and has a slit,
12. The display device according to claim 10, wherein the area of the slit portion of the common electrode in the first pixel is smaller than the area of the slit portion of the common electrode in the second pixel. 10. The display device according to claim 1, wherein the size of the thin film transistor in the first pixel is smaller than the size of the thin film transistor in the second pixel. 14. The display device according to claim 13, wherein the channel width of the thin film transistor in the first pixel is smaller than the channel width of the thin film transistor in the second pixel.

Images