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JP7256303B2 - Substrates for semiconductor devices and semiconductor devices - Google Patents

Substrates for semiconductor devices and semiconductor devices Download PDF

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Publication number
JP7256303B2
JP7256303B2 JP2022004059A JP2022004059A JP7256303B2 JP 7256303 B2 JP7256303 B2 JP 7256303B2 JP 2022004059 A JP2022004059 A JP 2022004059A JP 2022004059 A JP2022004059 A JP 2022004059A JP 7256303 B2 JP7256303 B2 JP 7256303B2
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Prior art keywords
metal
semiconductor device
resist layer
substrate
semiconductor element
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JP2022036268A (en
Inventor
佑也 五郎丸
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Maxell Ltd
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Maxell Ltd
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Priority claimed from JP2020119330A external-priority patent/JP7011685B2/en
Application filed by Maxell Ltd filed Critical Maxell Ltd
Priority to JP2022004059A priority Critical patent/JP7256303B2/en
Publication of JP2022036268A publication Critical patent/JP2022036268A/en
Priority to JP2023054922A priority patent/JP7542677B2/en
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Description

本発明は、底部に電極等の金属部が露出する形態の半導体装置、および当該半導体装置を製造するのに用いる半導体装置用基板に関する。 The present invention relates to a semiconductor device in which a metal portion such as an electrode is exposed at the bottom, and a semiconductor device substrate used to manufacture the semiconductor device.

半導体素子支持用の基板上に半導体素子を搭載し、半導体素子と外部導出用の金属端子
とを配線接続した上で、樹脂等の保護材で半導体素子を含む基板全体を被覆した旧来の構
造の半導体装置は、その構造上、小型化には限界があった。これに対し、半導体素子搭載
部分や電極部分となる金属部(リード)を形成し、この金属部上に半導体素子を搭載し配
線等の処理後、半導体素子や配線等のある金属部の表面側を樹脂等の封止材で封止し、金
属部が底部に一部露出した構成とされる半導体装置は、その高さを低くして省スペース化
が図れる他、露出した金属部を通じて半導体素子で生じた熱を外部に放出でき、放熱の面
で優れるといった特長を有しており、チップサイズなど超小型の半導体装置の分野で利用
が進んでいる。
A conventional structure in which a semiconductor element is mounted on a substrate for supporting the semiconductor element, wiring is connected between the semiconductor element and metal terminals for external derivation, and then the entire substrate including the semiconductor element is covered with a protective material such as resin. There is a limit to miniaturization of semiconductor devices due to their structure. On the other hand, metal parts (leads) are formed as semiconductor element mounting parts and electrode parts, semiconductor elements are mounted on these metal parts, and after processing such as wiring, the surface side of the metal parts with semiconductor elements, wiring, etc. is formed. is sealed with a sealing material such as resin, and the metal portion is partially exposed at the bottom. It has the advantage of being able to dissipate the heat generated in the outside and is excellent in terms of heat dissipation, and is being used in the field of ultra-small semiconductor devices such as chip size.

こうした半導体装置は、主に、導電性を有する母型基板上に半導体素子搭載部分や電極
部分となる金属部を、メッキを厚く形成する手法、いわゆる電鋳、により、半導体装置の
所望個数分まとめて形成し、半導体素子が搭載され配線等の処理を経た金属部の表面側を
封止材で封止した後、母型基板のみを除去し、一体にまとまった状態の多数の半導体装置
を個別に切り分ける、といった製造過程を経て製造される。このような半導体装置の製造
方法の一例として、特開2002-9196号公報や特開2004-214265号公報
に開示されるものがある。
Such semiconductor devices are manufactured by electroforming, which is a method of forming a thick plating on a conductive matrix substrate to form a semiconductor element mounting portion and an electrode portion. After sealing the surface side of the metal portion on which semiconductor elements are mounted and undergone processing such as wiring with a sealing material, only the mother substrate is removed, and a large number of integrated semiconductor devices are individually separated. It is manufactured through a manufacturing process such as cutting into pieces. An example of such a method for manufacturing a semiconductor device is disclosed in Japanese Unexamined Patent Application Publication No. 2002-9196 and Japanese Unexamined Patent Application Publication No. 2004-214265.

特開2002-9196号公報JP-A-2002-9196 特開2004-214265号公報Japanese Patent Application Laid-Open No. 2004-214265

従来の半導体装置の製造方法は前記特許文献に示される構成となっており、母型基板上
への金属部の形成にあたり、母型基板における金属部の非配置部分にレジスト層をあらか
じめ形成して、金属部が電解メッキの手法により適切な位置に形成されるようにしていた
。この金属部には、メッキによる膜形成に適したニッケル等の金属が使用されており、導
電性や配線用ワイヤの接合性を高めるために、金属部表面には一般に金メッキや銀メッキ
が施されていた。このメッキに対しても、レジスト層が必要箇所以外へのメッキの付着を
防ぐ役割を果していた。そして、このレジスト層を溶剤等で溶解除去した上で、母型基板
とその表面に形成された金属部が、半導体装置用基板として供給された。この半導体装置
用基板を用いて、実際の半導体装置の製造工程において、半導体素子の取付や配線、封止
材による封止等を行うようにしていた。
The conventional method for manufacturing a semiconductor device has the configuration shown in the above-mentioned patent document. In forming the metal portion on the mother mold substrate, a resist layer is formed in advance on the portion of the mother mold substrate where the metal portion is not arranged. , metal parts are formed at appropriate positions by means of electroplating. Metal such as nickel, which is suitable for film formation by plating, is used for this metal part, and the surface of the metal part is generally plated with gold or silver in order to improve conductivity and bondability of wiring wires. was Also for this plating, the resist layer played a role in preventing the plating from adhering to areas other than the required areas. After removing the resist layer by dissolving it with a solvent or the like, the matrix substrate and the metal part formed on the surface thereof were supplied as a semiconductor device substrate. Using this substrate for a semiconductor device, mounting and wiring of a semiconductor element, sealing with a sealing material, etc. have been carried out in the actual manufacturing process of a semiconductor device.

従来の半導体装置用基板では、母型基板上へのレジスト膜の配置で多様な形状の金属部
を得られるものの、基板上に形成する工程上の関係で、金属部は上面が平面状で一様な厚
さとなる板形状とならざるを得ず、上下方向について立体的な変化に富む形状とすること
が難しいという課題を有していた。
In conventional substrates for semiconductor devices, metal parts of various shapes can be obtained by arranging a resist film on a mother mold substrate. Inevitably, a plate shape with various thicknesses is required, and there is a problem that it is difficult to form a shape rich in three-dimensional variation in the vertical direction.

また、製造される半導体装置には、これが用いられる電子機器のさらなる小型化を実現
するために、低背化の要求があるが、これまでの構造では、半導体装置からの半導体素子
搭載部分や電極部分の脱落を防止するために、半導体素子搭載部分や電極部分をなす金属
部の薄型化には限界があり、さらに半導体素子自体も所定の強度を与えるために一定の厚
さを確保する必要があり、さらなる薄型化、低背化が困難であるという課題を有していた
In addition, the manufactured semiconductor devices are required to have a low profile in order to realize further miniaturization of the electronic equipment in which they are used. In order to prevent the parts from falling off, there is a limit to how thin the metal part that forms the semiconductor element mounting part and the electrode part can be made. However, there is a problem that further reduction in thickness and height is difficult.

本発明は前記課題を解消するためになされたもので、金属部の適切な箇所に凹部を設けて、得られる半導体装置各部の構造を最適化できると共に、効率よく半導体装置を製造できる半導体装置用基板、並びに、この半導体装置用基板を用いて製造される半導体装置を提供することを目的とする。 SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. An object of the present invention is to provide a substrate and a semiconductor device manufactured using this semiconductor device substrate.

本発明の開示に係る半導体装置用基板は、装置底部に半導体素子搭載部及び電極部とな
る各金属部が露出する半導体装置の製造に用いられ、母型基板上に前記金属部がそれぞれ
形成される半導体装置用基板において、前記金属部が、表面側に凹部を設けられるもので
ある。
A substrate for a semiconductor device according to the present disclosure is used for manufacturing a semiconductor device in which a semiconductor element mounting portion and metal portions to be electrode portions are exposed at the bottom of the device, and the metal portions are formed on a mother mold substrate. In the semiconductor device substrate according to claim 1, the metal portion has a concave portion on the surface side.

このように本発明の開示によれば、母型基板上に形成される金属部である半導体素子搭
載部及び/又は電極部に凹部が設けられ、半導体素子搭載部及び/又は電極部における凹
部の下側部分の厚さを小さくすることにより、半導体装置用基板を用いた半導体装置の製
造にあたり、凹部で変化を加えた金属部の表面形状に応じて、半導体装置の構造に好まし
い特長を付与でき、例えば凹部で金属部の表面積が増える分、金属部と半導体装置の封止
材との接触面積を増やして、金属部の一体化の強度を高められる。また、半導体素子搭載
部に凹部を設けるようにすれば、半導体素子の配設位置の設定に柔軟性を与えられ、製造
される半導体装置の構造の自由度を大きくすることができる。さらに、半導体装置同士の
切り離し位置に配置される金属部に凹部を設けるようにすれば、半導体装置の切り離しの
際の金属の切断量を減らすことができ、切断装置の損耗を抑えられる。
As described above, according to the disclosure of the present invention, recesses are provided in the semiconductor element mounting portion and/or the electrode portion, which are metal portions formed on the mother mold substrate, and the recesses in the semiconductor element mounting portion and/or the electrode portion are provided. By reducing the thickness of the lower portion, when manufacturing a semiconductor device using a substrate for a semiconductor device, it is possible to impart favorable features to the structure of the semiconductor device according to the surface shape of the metal portion that has been changed by the concave portion. For example, the contact area between the metal part and the encapsulant of the semiconductor device is increased to the extent that the surface area of the metal part is increased by the concave portion, so that the strength of integration of the metal part can be increased. Further, by providing a concave portion in the semiconductor element mounting portion, it is possible to provide flexibility in setting the arrangement position of the semiconductor element, and to increase the degree of freedom in the structure of the manufactured semiconductor device. Furthermore, by providing a concave portion in the metal portion arranged at the separation position between the semiconductor devices, the amount of metal cut when separating the semiconductor devices can be reduced, and the wear of the cutting device can be suppressed.

また、本発明の開示に係る半導体装置用基板は、必要に応じて、前記凹部が、金属部の
うち少なくとも半導体素子搭載部に、凹部内に半導体素子を挿入し且つ凹部底部に半導体
素子を載置可能な大きさとして設けられるものである。
Further, in the substrate for a semiconductor device according to the disclosure of the present invention, if necessary, the recess has at least the semiconductor element mounting portion of the metal portion, the semiconductor element is inserted into the recess, and the semiconductor element is mounted on the bottom of the recess. It is provided as a size that can be placed.

このように本発明の開示によれば、金属部のうち半導体素子搭載部に凹部を設け、この
凹部を半導体装置製造工程で半導体素子を挿入、載置可能な大きさとなるようにすること
により、半導体装置製造の際に、半導体素子を半導体素子搭載部の凹部に挿入配設した場
合、従来のように半導体素子搭載部の上面に搭載される場合と比べて、配設位置を下げる
ことができ、半導体素子上面や、電極部と半導体素子とを接合するワイヤ等の高さも下が
る分、半導体装置の厚さを小さくして製造することができ、半導体装置の低背化を実現で
きる。また、半導体素子の位置が下がって、ワイヤが接合する半導体素子と電極部の各上
面が互いに近付く分、ワイヤ長さも短くすることができ、ワイヤ使用量を削減してコスト
を低減できる。
As described above, according to the disclosure of the present invention, a concave portion is provided in the semiconductor element mounting portion of the metal portion, and the concave portion has a size that allows the semiconductor element to be inserted and mounted in the semiconductor device manufacturing process. When a semiconductor element is inserted into a concave portion of a semiconductor element mounting portion during manufacturing of a semiconductor device, the mounting position can be lowered compared to the conventional case where the semiconductor element is mounted on the upper surface of the semiconductor element mounting portion. Since the height of the upper surface of the semiconductor element and the height of the wire connecting the electrode portion and the semiconductor element are lowered, the thickness of the semiconductor device can be reduced and the height of the semiconductor device can be reduced. In addition, since the position of the semiconductor element is lowered and the upper surfaces of the semiconductor element and the electrode portion to which the wire is bonded are brought closer to each other, the length of the wire can be shortened, and the amount of wire used can be reduced, thereby reducing the cost.

また、本発明の開示に係る半導体装置用基板は、必要に応じて、前記金属部における電
極部の少なくとも一部が、基板上に設計される半導体装置位置のうち、個々の半導体装置
ごとに切り離す切断加工を経て各半導体装置の側端位置となる切断予定箇所に跨って、前
記切断加工時に切断される配置として基板上に形成され、前記凹部が、切断予定箇所に位
置する電極部に、電極部の切断加工により除去される部位を含んで所定の大きさとして設
けられるものである。
Further, in the semiconductor device substrate according to the present disclosure, at least a part of the electrode portion in the metal portion is separated for each semiconductor device among the semiconductor device positions designed on the substrate, if necessary. It is formed on the substrate as an arrangement to be cut during the cutting process, straddling the planned cutting locations that will become the side end positions of each semiconductor device after the cutting process, and the recesses are formed on the electrode portions positioned at the planned cutting locations. It is provided with a predetermined size including the portion to be removed by cutting the portion.

このように本発明の開示によれば、金属部のうち、切断予定箇所に位置する電極部に凹
部を設け、半導体装置の製造工程で半導体装置を切り離す切断加工の際に、電極部の凹部
のある位置を切断するようにしていることにより、電極の凹部深さの分、切断位置が下が
り、切断加工における金属の切断量を減らすことができ、切断に伴う切断加工用装置の負
担を減らし、刃部の劣化を抑えられる。また、切断面の近傍で電極部上面は凹部に伴う段
差のある形状となっており、その分電極部上面と半導体装置の封止材とが広く接触するこ
ととなり、半導体装置における電極部の支持強度が向上し、耐久性を高められる。
As described above, according to the disclosure of the present invention, in the metal portion, the recess is provided in the electrode portion located at the portion to be cut, and the recess of the electrode portion is formed during the cutting process for separating the semiconductor device in the manufacturing process of the semiconductor device. By cutting at a certain position, the cutting position is lowered by the depth of the concave portion of the electrode, the amount of metal cut in the cutting process can be reduced, and the burden on the cutting device associated with cutting can be reduced. Suppresses deterioration of the blade. In addition, in the vicinity of the cut surface, the upper surface of the electrode portion has a stepped shape due to the concave portion, so that the upper surface of the electrode portion and the sealing material of the semiconductor device are in contact with each other widely, and the electrode portion of the semiconductor device is supported. Increased strength and increased durability.

また、本発明の開示に係る半導体装置用基板は、必要に応じて、前記金属部が、少なく
とも上側の表面にメッキによる表面金属層を形成される一方、前記凹部に面する表面には
前記表面金属層を形成されないものである。
Further, in the semiconductor device substrate according to the present disclosure, the metal part has a surface metal layer formed by plating on at least the upper surface, and the surface facing the concave part has the surface metal layer formed thereon, if necessary. A metal layer is not formed.

このように本発明の開示によれば、金属部の上側の表面に形成する表面金属層を、凹部
周囲には形成しないことにより、凹部下側部分の厚さが、金属部の厚さ以上に厚くならな
いようにして、凹部下側部分の厚さ削減を確実なものとすると共に、半導体装置用基板で
製造された半導体装置の側面に切断に伴って電極部が一部露出する場合でも、凹部のある
位置で切断される電極部の切断面には表面金属層が露出することはなく、表面金属層露出
部を起点とするマイグレーションのような信頼性低下につながる事象の発生を未然に防止
できる。
Thus, according to the disclosure of the present invention, the surface metal layer formed on the upper surface of the metal portion is not formed around the recess, so that the thickness of the lower portion of the recess is greater than or equal to the thickness of the metal portion. The thickness of the lower portion of the concave portion can be reliably reduced by preventing the thickness of the concave portion from becoming thicker, and even when the electrode portion is partially exposed due to cutting on the side surface of the semiconductor device manufactured using the semiconductor device substrate, the concave portion can be formed. The surface metal layer is not exposed on the cut surface of the electrode part cut at a certain position, and it is possible to prevent the occurrence of events that lead to reliability deterioration such as migration originating from the surface metal layer exposed part. .

また、本発明の開示に係る半導体装置用基板の製造方法は、母型基板上の所定部位にレ
ジスト層を形成し、レジスト層の非形成部位に、半導体装置の半導体素子搭載部及び電極
部となる各金属部をメッキの手法で形成して、当該金属部が底部に露出する構造の半導体
装置の製造に用いることのできる基板を得る、半導体装置用基板の製造方法において、前
記金属部を、レジスト層を越えない所定高さまで形成する工程と、形成した金属部及び/
又はレジスト層の上側の所定部位に、別のレジスト層を新たに形成する工程と、形成され
た前記別のレジスト層に対し、当該別のレジスト層の非形成部位で金属部の形成を再開し
て、別のレジスト層を越えない所定高さまで金属部を追加で形成する工程と、前記レジス
ト層及び別のレジスト層をそれぞれ除去する工程を備えて、前記別のレジスト層で設定さ
れた所定形状が表面に現れた金属部を得るものである。
Further, in the method of manufacturing a substrate for a semiconductor device according to the present disclosure, a resist layer is formed on a predetermined portion of a mother mold substrate, and a semiconductor element mounting portion and an electrode portion of a semiconductor device are formed on a portion where the resist layer is not formed. A method for manufacturing a substrate for a semiconductor device, wherein each metal portion is formed by a plating method to obtain a substrate that can be used for manufacturing a semiconductor device having a structure in which the metal portion is exposed at the bottom, wherein the metal portion is formed by: A step of forming to a predetermined height that does not exceed the resist layer, and the formed metal part and /
Alternatively, a step of forming a new resist layer on a predetermined portion above the resist layer, and restarting formation of the metal portion on the formed another resist layer at a portion where the another resist layer is not formed. a step of additionally forming a metal portion up to a predetermined height not exceeding another resist layer; and a step of removing the resist layer and the another resist layer, respectively. is to obtain a metal portion exposed to the surface.

このように本発明の開示によれば、金属部の形成において別のレジスト層を用いて金属
部の形成領域を一部規制して、レジスト除去後の金属部表面に別のレジスト層に基づく形
状を付与できることにより、金属部の形成範囲をレジスト層だけでなく上側の別のレジス
ト層も併用してより正確に規定して、金属部を基板上により精細な配置とすることができ
ると共に、金属部の構造の自由度が増すこととなり、半導体装置用基板を用いて製造され
る半導体装置を、金属部の構造に基づいて改良できる。
As described above, according to the disclosure of the present invention, in the formation of the metal portion, another resist layer is used to partially regulate the formation region of the metal portion, and the surface of the metal portion after the resist is removed has a shape based on the other resist layer. By being able to provide the metal The degree of freedom in the structure of the portion is increased, and the semiconductor device manufactured using the semiconductor device substrate can be improved based on the structure of the metal portion.

また、本発明の開示に係る半導体装置用基板の製造方法は、必要に応じて、前記別のレ
ジスト層が、前記中断時点の金属部のうち最終的に半導体素子搭載部となるものの上側所
定部位に形成され、前記別のレジスト層の形成後、金属部の形成再開で、金属部が別のレ
ジスト層の側面に接する部位を伴って形成され、形成終了後、最終的に別のレジスト層を
除去して、金属部の半導体素子搭載部における、別のレジスト層が存在していた部位に、
穴又は溝状の凹部を生じさせるものである。
Further, in the method for manufacturing a substrate for a semiconductor device according to the present disclosure, if necessary, the another resist layer is formed on a predetermined portion above the portion of the metal portion at the time of interruption that will eventually become the semiconductor element mounting portion. After the formation of the another resist layer, the formation of the metal portion is resumed, and the metal portion is formed with a portion in contact with the side surface of another resist layer, and after the formation is completed, another resist layer is finally formed. After removing, in the semiconductor element mounting portion of the metal portion, at the portion where another resist layer was present,
It is intended to produce a hole or groove-like recess.

このように本発明の開示によれば、別のレジスト層を金属部のうち半導体素子搭載部と
なる部位に配設して、最終的に形成された金属部の半導体素子搭載部に、別のレジスト層
の配置範囲に応じた凹部を生じさせることにより、レジスト形状の設定で自由に凹部を配
置できることに加え、得られた半導体装置用基板を用いて半導体装置を製造する際に、半
導体素子を半導体素子搭載部の凹部に挿入配設した場合、半導体素子の配設位置を下げる
ことができ、半導体素子上面や、電極部と半導体素子とを接合するワイヤ等の高さも下が
る分、半導体装置の厚さを小さくして製造することができ、半導体装置の低背化を実現で
きる。
As described above, according to the disclosure of the present invention, another resist layer is disposed on a portion of the metal portion that will be the semiconductor element mounting portion, and another resist layer is formed on the semiconductor element mounting portion of the finally formed metal portion. By forming recesses according to the arrangement range of the resist layer, the recesses can be freely arranged by setting the shape of the resist. When the semiconductor element is inserted and arranged in the concave portion of the semiconductor element mounting portion, the arrangement position of the semiconductor element can be lowered, and the upper surface of the semiconductor element and the height of the wire or the like that joins the electrode portion and the semiconductor element are also lowered. It can be manufactured with a reduced thickness, and a low profile semiconductor device can be realized.

また、本発明の開示に係る半導体装置用基板の製造方法は、必要に応じて、前記別のレ
ジスト層が、前記中断時点の金属部のうち最終的に電極部となるものの上側所定部位に、
複数の電極部にわたる略線状配置で形成され、前記別のレジスト層の形成後、金属部の形
成再開で、金属部が別のレジスト層の側面に接する部位を伴って形成され、形成終了後、
最終的に別のレジスト層を除去して、金属部の電極部における、別のレジスト層が存在し
ていた部位に、複数の電極部にわたって直列に並ぶ配置となる溝状の凹部をそれぞれ生じ
させるものである。
Further, in the method for manufacturing a semiconductor device substrate according to the present disclosure, if necessary, the separate resist layer is applied to a predetermined portion above the metal portion at the time of interruption that will eventually become the electrode portion.
It is formed in a substantially linear arrangement over a plurality of electrode portions, and after the formation of the another resist layer, when the formation of the metal portion is resumed, the metal portion is formed with a portion in contact with the side surface of the another resist layer, and after the formation is completed. ,
Finally, another resist layer is removed, and groove-shaped recesses arranged in series over a plurality of electrode portions are formed in the portions of the electrode portions of the metal portion where the other resist layer was present. It is.

このように本発明の開示によれば、別のレジスト層を金属部のうち電極部となる部位に
配設して、最終的に形成された金属部の電極部の切断加工対象位置に並んだ凹部を生じさ
せることにより、レジスト形状の設定で所望の凹部を配置できることに加え、得られた半
導体装置用基板を用いて半導体装置を製造する際に、凹部のある電極部を切断するように
して各半導体装置を切り離す場合、電極部の凹部下側の部位が薄くされる分、切断加工の
負荷を小さくすることができ、切断装置の損耗を抑えられる。
As described above, according to the disclosure of the present invention, another resist layer is disposed on a portion of the metal portion that will be the electrode portion, and is aligned with the cutting target position of the electrode portion of the finally formed metal portion. By forming the recesses, it is possible to arrange the desired recesses by setting the shape of the resist. In addition, when manufacturing a semiconductor device using the obtained substrate for a semiconductor device, the electrode portions having the recesses are cut off. When separating each semiconductor device, the load of the cutting process can be reduced because the portion of the electrode section below the concave portion is thinned, and the wear of the cutting device can be suppressed.

また、本発明の開示に係る半導体装置は、半導体素子搭載部及び電極部となる各金属部
を有し、当該金属部表面の少なくとも一部にメッキにより表面金属層を形成され、金属部
表面側への半導体素子搭載及び配線、封止材による封止がなされ、装置底部に前記金属部
の裏面側が露出した状態とされる半導体装置において、前記金属部のうち半導体素子搭載
部における表面側に半導体素子より広い大きさの凹部が設けられ、当該凹部に面する表面
には前記表面金属層を形成されない状態とされ、前記凹部が、半導体素子を挿入配置され
、半導体素子ごと封止材により封止されるものである。
In addition, the semiconductor device according to the disclosure of the present invention has a metal portion that serves as a semiconductor element mounting portion and an electrode portion. In a semiconductor device in which a semiconductor element is mounted on a semiconductor device, wiring is performed, and sealing is performed with a sealing material, and the back side of the metal part is exposed at the bottom of the device, a semiconductor A concave portion wider than the element is provided, the surface facing the concave portion is not formed with the surface metal layer, the semiconductor element is inserted into the concave portion, and the semiconductor element is sealed together with the sealing material. It is what is done.

このように本発明の開示によれば、半導体装置を構成する金属部のうち、半導体素子を
搭載する半導体素子搭載部に凹部が設けられていることで、半導体素子を半導体素子搭載
部の凹部に挿入配設した場合、従来のように半導体素子搭載部の上面に搭載される場合と
比べて、配設位置を下げることができ、半導体素子上面や、電極部と半導体素子とを接合
するワイヤ等の高さも下がる分、半導体装置の厚さを小さくすることができ、半導体装置
の低背化を実現できる。また、半導体素子の位置が下がって、ワイヤが接合する半導体素
子と電極部の各上面が互いに近付く分、ワイヤ長さも短くすることができ、ワイヤ使用量
を削減して半導体装置のコストを低減できる。
As described above, according to the disclosure of the present invention, of the metal portions constituting the semiconductor device, the semiconductor element mounting portion for mounting the semiconductor element is provided with the recess, so that the semiconductor element can be placed in the recess of the semiconductor element mounting portion. In the case of inserting and arranging, the arrangement position can be lowered as compared with the conventional case of mounting on the upper surface of the semiconductor element mounting portion, and the upper surface of the semiconductor element, the wire connecting the electrode portion and the semiconductor element, etc. Since the height of the semiconductor device is also reduced, the thickness of the semiconductor device can be reduced, and the height of the semiconductor device can be reduced. In addition, since the position of the semiconductor element is lowered and the upper surfaces of the semiconductor element and the electrode portion to which the wire is bonded are brought closer to each other, the length of the wire can be shortened. .

また、本発明の開示に係る半導体装置は、半導体素子搭載部及び電極部となる各金属部
を有し、当該金属部表面の少なくとも一部にメッキにより表面金属層を形成され、金属部
表面側への半導体素子搭載及び配線、封止材による封止がなされ、装置底部に前記金属部
の裏面側が露出した状態とされる半導体装置において、少なくともいずれかの側面が、複
数の半導体装置の集合形成状態から個々の半導体装置を切り離す切断加工により生じた切
断面であり、切断加工を受けて切断面の一部として露出した電極部を有し、当該側面に露
出した電極部が、前記切断加工での切断予定箇所に位置する電極部の表面側にあらかじめ
凹部を設けられてなり、当該凹部に面する表面には前記表面金属層を形成されず、前記側
面に露出した電極部の表面が、元の凹部のあった位置の下側部分の断面であり、表面金属
層の断面を一切含まないものである。
In addition, the semiconductor device according to the disclosure of the present invention has a metal portion that serves as a semiconductor element mounting portion and an electrode portion. In a semiconductor device in which a semiconductor element is mounted on a semiconductor device, wiring is performed, and sealing is performed with a sealing material, and the back surface side of the metal portion is exposed at the bottom of the device, at least one of the side surfaces is a collective formation of a plurality of semiconductor devices. It is a cut surface generated by cutting to separate individual semiconductor devices from a state, and has an electrode part exposed as a part of the cut surface by cutting, and the electrode part exposed on the side surface is cut by the cutting process. A concave portion is provided in advance on the surface side of the electrode portion located at the planned cutting location, the surface metal layer is not formed on the surface facing the concave portion, and the surface of the electrode portion exposed on the side surface is the original is a cross-section of the lower portion of the position where the recess was, and does not include any cross-section of the surface metal layer.

このように本発明の開示によれば、半導体装置を構成する金属部のうち電極部にあらか
じめ凹部が設けられて、凹部を切断加工対象位置とされて個々の半導体装置に切り離され
た際に、端部に電極部の凹部位置の切断面が現れていることにより、電極部の露出部分は
元の凹部の下側にあたる部分となり、表面金属層が現れないこととなり、表面金属層露出
部分を起点とするマイグレーションを未然に防止できる上、切断加工に伴って側端部に位
置する電極部は凹部のある位置とされた分、封止部分との接触面が増えるので強度を高め
られ、半導体装置としての耐久性や信頼性も高められる。
As described above, according to the disclosure of the present invention, when a concave portion is provided in advance in an electrode portion of a metal portion constituting a semiconductor device, and the concave portion is set as a position to be cut and separated into individual semiconductor devices, Since the cut surface of the concave portion of the electrode portion appears at the end, the exposed portion of the electrode portion corresponds to the lower side of the original concave portion, and the surface metal layer does not appear, and the exposed portion of the surface metal layer is the starting point. In addition, since the electrode portion located at the side edge is made to have a recessed portion due to the cutting process, the contact surface with the sealing portion increases, so the strength is increased, and the strength of the semiconductor device is increased. As a result, durability and reliability are also enhanced.

本発明の第1の実施形態に係る半導体装置用基板の要部拡大図である。1 is an enlarged view of a main part of a semiconductor device substrate according to a first embodiment of the present invention; FIG. 本発明の第1の実施形態に係る半導体装置用基板の製造方法におけるレジスト層形成工程説明図である。FIG. 3 is an explanatory diagram of a resist layer forming process in the method for manufacturing a semiconductor device substrate according to the first embodiment of the present invention; 本発明の第1の実施形態に係る半導体装置用基板の製造方法における最初の金属部形成工程説明図である。FIG. 10 is an explanatory view of the first metal portion formation step in the method of manufacturing a substrate for a semiconductor device according to the first embodiment of the present invention; 本発明の第1の実施形態に係る半導体装置用基板の製造方法における第二レジスト層の形成工程説明図である。FIG. 4 is an explanatory diagram of a step of forming a second resist layer in the method for manufacturing a semiconductor device substrate according to the first embodiment of the present invention; 本発明の第1の実施形態に係る半導体装置用基板の製造方法における後の金属部形成、表面金属層形成、及びレジスト層除去の各工程説明図である。FIG. 4 is an explanatory view of each process of subsequent metal portion formation, surface metal layer formation, and resist layer removal in the method of manufacturing a substrate for a semiconductor device according to the first embodiment of the present invention; 本発明の第1の実施形態に係る半導体装置用基板を用いた半導体装置の製造工程説明図である。1A to 1D are explanatory diagrams of a manufacturing process of a semiconductor device using the semiconductor device substrate according to the first embodiment of the present invention; 本発明の第1の実施形態に係る半導体装置の断面図及び底面図である。1A and 1B are a cross-sectional view and a bottom view of a semiconductor device according to a first embodiment of the present invention; FIG. 本発明の第2の実施形態に係る半導体装置用基板の要部拡大図である。FIG. 5 is an enlarged view of a main part of a semiconductor device substrate according to a second embodiment of the present invention; 本発明の第2の実施形態に係る半導体装置用基板の製造方法における最初の金属部形成工程説明図である。FIG. 10 is an explanatory view of the first metal portion formation step in the method of manufacturing a substrate for a semiconductor device according to the second embodiment of the present invention; 本発明の第2の実施形態に係る半導体装置用基板の製造方法における第二レジスト層の形成工程説明図である。FIG. 10 is an explanatory diagram of a step of forming a second resist layer in the method for manufacturing a substrate for a semiconductor device according to the second embodiment of the present invention; 本発明の第2の実施形態に係る半導体装置用基板の製造方法における後の金属部形成、表面金属層形成、及びレジスト層除去の各工程説明図である。FIG. 10 is an explanatory view of each process of subsequent metal portion formation, surface metal layer formation, and resist layer removal in the method of manufacturing a substrate for a semiconductor device according to the second embodiment of the present invention; 本発明の第2の実施形態に係る半導体装置用基板を用いた半導体装置の製造工程説明図である。8A to 8D are diagrams for explaining a manufacturing process of a semiconductor device using the semiconductor device substrate according to the second embodiment of the present invention; FIG. 本発明の第2の実施形態に係る半導体装置の底面側斜視図及び断面図である。8A and 8B are a perspective view and a cross-sectional view of a semiconductor device according to a second embodiment of the present invention; FIG. 本発明の第3の実施形態に係る半導体装置用基板の製造方法における第二レジスト層の形成工程説明図である。FIG. 10 is an explanatory diagram of a step of forming a second resist layer in the method for manufacturing a semiconductor device substrate according to the third embodiment of the present invention; 本発明の第3の実施形態に係る半導体装置用基板の製造方法における後の金属部形成、表面金属層形成、及びレジスト層除去の各工程説明図である。FIG. 11 is an explanatory view of each process of subsequent metal portion formation, surface metal layer formation, and resist layer removal in the method of manufacturing a substrate for a semiconductor device according to the third embodiment of the present invention; 本発明の第3の実施形態に係る半導体装置用基板による金属部配置間隔の縮小状態説明図である。FIG. 10 is an explanatory diagram of a reduced state of the arrangement interval of the metal portion by the semiconductor device substrate according to the third embodiment of the present invention; 本発明の第3の実施形態に係る半導体装置用基板の他の製造方法における第二レジスト層の形成工程説明図である。FIG. 11 is an explanatory diagram of a step of forming a second resist layer in another method of manufacturing a substrate for a semiconductor device according to the third embodiment of the present invention; 本発明の第3の実施形態に係る半導体装置用基板の他の製造方法における金属部形成工程説明図である。FIG. 11 is an explanatory diagram of a metal portion forming step in another method of manufacturing a substrate for a semiconductor device according to the third embodiment of the present invention; 本発明の第3の実施形態に係る半導体装置用基板の他の製造方法における表面金属層形成及びレジスト層除去の各工程説明図である。10A to 10C are diagrams for explaining steps of forming a surface metal layer and removing a resist layer in another method of manufacturing a substrate for a semiconductor device according to the third embodiment of the present invention; 本発明の他の実施形態に係る半導体装置用基板の製造におけるレジスト層除去工程前後の基板状態説明図、及び、半導体装置用基板を用いて得られた半導体装置の概略断面図である。FIG. 10 is a schematic cross-sectional view of a semiconductor device obtained using the semiconductor device substrate, and an explanatory diagram of substrate states before and after a resist layer removing step in manufacturing a semiconductor device substrate according to another embodiment of the present invention.

(本発明の第1の実施形態)
以下、本発明の第1の実施形態に係る半導体装置用基板を図1ないし図7に基づいて説
明する。
前記各図において本実施形態に係る半導体装置用基板1は、導電性を有する材質からな
る母型基板10と、この母型基板10上に形成され、本基板を用いて製造される半導体装
置70の半導体素子搭載部11a又は電極部11bとなる金属部11と、金属部11表面
にメッキにより形成される表面金属層13とを備える構成である。
(First embodiment of the present invention)
A semiconductor device substrate according to a first embodiment of the present invention will be described below with reference to FIGS. 1 to 7. FIG.
In each of the drawings, the semiconductor device substrate 1 according to the present embodiment includes a matrix substrate 10 made of a conductive material, and a semiconductor device 70 formed on the matrix substrate 10 and manufactured using the substrate. The structure includes a metal portion 11 that serves as the semiconductor element mounting portion 11a or the electrode portion 11b, and a surface metal layer 13 that is formed on the surface of the metal portion 11 by plating.

この半導体装置用基板1を用いて製造される半導体装置70は、図7に示すように、半
導体装置用基板1から得られる金属部11及び表面金属層13に加えて、金属部11のう
ち半導体素子搭載部11aに搭載される半導体素子14と、この半導体素子14と金属部
11のうちの電極部11bとを電気的に接続するワイヤ15と、半導体素子14やワイヤ
15を含む金属部11の表面側を覆って封止する封止材19とを備える構成である。
As shown in FIG. 7, a semiconductor device 70 manufactured using this substrate 1 for a semiconductor device includes a metal portion 11 and a surface metal layer 13 obtained from the substrate 1 for a semiconductor device. The semiconductor element 14 mounted on the element mounting portion 11a, the wire 15 electrically connecting the semiconductor element 14 and the electrode portion 11b of the metal portion 11, and the metal portion 11 including the semiconductor element 14 and the wire 15. It is the structure provided with the sealing material 19 which covers and seals the surface side.

この半導体装置70では、底部に金属部11の裏面側が電極や放熱パッド等として露出
した状態となり(図7(B)参照)、この露出する金属部11の裏面側と、装置外装の一
部として現れる封止材19の裏面側とが略同一平面上に位置する構成である。半導体装置
70における底部以外の各面は、装置外装をなす封止材19のみがそれぞれ現れた状態と
なる。
In this semiconductor device 70, the back side of the metal portion 11 is exposed as an electrode, a heat dissipation pad, etc. on the bottom (see FIG. 7B). It is configured such that the rear surface side of the sealing material 19 that appears is positioned substantially on the same plane. On each surface of the semiconductor device 70 other than the bottom portion, only the sealing material 19 forming the exterior of the device is exposed.

前記半導体装置用基板1は、母型基板10上に金属部11の非配置部分に対応する第一
レジスト層12が形成された後、電解メッキで金属部11を形成され、続いて金属部11
の凹部に対応する前記レジスト層とは別の第二レジスト層16が形成された後、電解メッ
キで金属部11を追加形成され、さらに金属部11表面にメッキにより表面金属層13を
形成された後、第一レジスト層12及び第二レジスト層16を除去することで製造される
ものである。
After the first resist layer 12 is formed on the mother mold substrate 10 corresponding to the portion where the metal portion 11 is not arranged, the semiconductor device substrate 1 is formed with the metal portion 11 by electroplating.
After forming a second resist layer 16 different from the resist layer corresponding to the concave portion, the metal portion 11 is additionally formed by electrolytic plating, and the surface metal layer 13 is formed on the surface of the metal portion 11 by plating. It is manufactured by removing the first resist layer 12 and the second resist layer 16 later.

また、この半導体装置用基板1を用いた半導体装置製造の際は、この半導体装置用基板
1に対し、金属部11表面側への半導体素子14搭載及び配線、封止材19による封止が
なされ、封止の後、半導体装置部分から母型基板10を分離除去して半導体装置70を得
る仕組みである。
Further, when manufacturing a semiconductor device using this semiconductor device substrate 1, the semiconductor element 14 is mounted on the surface side of the metal portion 11 of the semiconductor device substrate 1, and wiring and sealing with a sealing material 19 are performed. After sealing, the semiconductor device 70 is obtained by separating and removing the mother mold substrate 10 from the semiconductor device portion.

前記母型基板10は、ステンレス材(SUS430等)やアルミニウム、銅等の導電性
の金属板(厚さ約0.1mm)で形成され、半導体装置の製造工程で除去されるまで、半
導体装置用基板1の要部をなすものであり、半導体装置用基板製造工程の各段階で、表面
側に第一レジスト層12、金属部11が形成され、また裏面側にレジスト層18が配設さ
れる。金属部11の形成の際には、この母型基板10を介した通電がなされることで、母
型基板10表面の第一レジスト層12に覆われない通電可能な部分に電解メッキで金属部
11が形成されることとなる。また、表面金属層13のメッキの際も、電解メッキとする
場合には、母型基板10を介して通電がなされる。
The matrix substrate 10 is formed of a conductive metal plate (about 0.1 mm thick) such as stainless steel (SUS430, etc.), aluminum, copper, or the like. The first resist layer 12 and the metal portion 11 are formed on the front surface side, and the resist layer 18 is provided on the back surface side at each stage of the semiconductor device substrate manufacturing process. . When the metal part 11 is formed, an electric current is passed through the mother mold substrate 10, so that the metal part is formed by electroplating on the part of the surface of the mother mold substrate 10 that is not covered with the first resist layer 12 and can be energized. 11 will be formed. Also, when the surface metal layer 13 is plated, electricity is passed through the matrix substrate 10 in the case of electroplating.

一方、半導体装置用基板1を用いた半導体装置の製造工程では、母型基板10上の金属
部11表面側が封止材19で覆われ(図6(B)参照)、母型基板10で金属部11及び
封止材19を支持しなくても十分な強度が得られたら、母型基板10がこれらから分離除
去される(図6(C)参照)。母型基板10がステンレス材の場合には、力を加えて半導
体装置側から物理的に引き剥がして除去する方法が採られ、また、母型基板10が銅等の
場合、薬液を用いて溶解除去するエッチングの方法が用いられる。エッチングの場合、母
型基板10は溶解するが金属部11のニッケル等の材質が冒されないような選択エッチン
グ性を有するエッチング液を用いることとなる。
この母型基板10が除去されると、半導体装置底部に、金属部11の半導体素子搭載部
11a及び電極部11b、並びに封止材19の各裏面が同一平面上に露出した状態が得ら
れる。
On the other hand, in the manufacturing process of a semiconductor device using the substrate 1 for a semiconductor device, the surface side of the metal part 11 on the mother mold substrate 10 is covered with the sealing material 19 (see FIG. 6B), and the mother mold substrate 10 is covered with the metal part 11 . When sufficient strength is obtained without supporting the portion 11 and the sealing material 19, the matrix substrate 10 is separated and removed from them (see FIG. 6(C)). If the matrix substrate 10 is made of stainless steel, a method of physically peeling it off from the semiconductor device side by applying force is adopted. A removing etching method is used. In the case of etching, an etchant having a selective etching property that dissolves the matrix substrate 10 but does not affect the material such as nickel of the metal portion 11 is used.
When the mother substrate 10 is removed, the semiconductor element mounting portion 11a and the electrode portion 11b of the metal portion 11 and the back surfaces of the sealing material 19 are exposed on the same plane at the bottom of the semiconductor device.

前記金属部11は、電解メッキに適したニッケルや銅、又はニッケル-コバルト等のニ
ッケル合金からなり、母型基板10上の第一レジスト層12のない部分に、電解メッキで
形成される構成である。半導体装置用基板1において、金属部11は、母型基板10表面
で、半導体素子搭載部11aとその近傍に複数配置される電極部11bの組合わせを一つ
の単位として、製造する半導体装置の数だけ前記組合わせが多数整列状態で並べられた形
態で形成されることとなる。
The metal portion 11 is made of nickel, copper, or a nickel alloy such as nickel-cobalt, which is suitable for electrolytic plating, and is formed by electrolytic plating on a portion of the mother mold substrate 10 where the first resist layer 12 is absent. be. In the semiconductor device substrate 1, the metal portion 11 is formed on the surface of the mother mold substrate 10, and the number of semiconductor devices to be manufactured is determined by using the combination of the semiconductor element mounting portion 11a and the plurality of electrode portions 11b arranged in the vicinity thereof as one unit. Only a large number of the combinations are arranged in an aligned state.

この金属部11は、第一レジスト層12の厚さを越える厚さ(例えば、厚さ約60~8
0μm)で、且つ上端周縁には第一レジスト層12側に張出した略庇状の張出し部11c
を有する形状として形成される。張出し部11cは、電解メッキの際、金属部11を第一
レジスト層12の厚さまで形成した後も電解メッキを継続して、金属部の成長を厚さ方向
に加えて第一レジスト層12による制限のない他の向きにも進行させることで、第一レジ
スト層12を越えた金属部11上端部から第一レジスト層12側へ張出した形状として得
られるものである。この張出し部11cは、封止材19による封止に伴って、封止材19
で挟まれて固定された状態となる。
The metal part 11 has a thickness exceeding the thickness of the first resist layer 12 (for example, a thickness of about 60 to 8 mm).
0 μm), and an overhanging portion 11c extending toward the first resist layer 12 is formed on the upper peripheral edge of the upper end.
is formed as a shape having a During electroplating, the protruding portion 11c continues electroplating even after the metal portion 11 is formed to the thickness of the first resist layer 12, and the metal portion is grown in the thickness direction to form the first resist layer 12. By proceeding in other directions without limitation, a shape projecting from the upper end portion of the metal portion 11 beyond the first resist layer 12 toward the first resist layer 12 can be obtained. This protruding portion 11 c is formed by the sealing material 19 as it is sealed with the sealing material 19 .
It will be in a state of being sandwiched and fixed.

この他、金属部11のうち、半導体素子搭載部11aには、半導体装置製造の際に半導
体素子14を挿入して搭載可能な凹部11eが設けられる。この凹部11eに半導体素子
14が挿入配設されると、凹部深さの分、従来のように半導体素子搭載部の上面に搭載さ
れる場合と比べて、半導体素子14の配設位置を下げることができる。凹部11eは、金
属部11の形成の途中段階で、半導体素子搭載部11aにおける凹部11eに対応する箇
所に第二レジスト層16を配設することで穴又は溝状として生じるものであり、凹部11
eの下側に半導体素子搭載部11aが必要な強度を維持する厚さを十分確保可能な程度の
深さとされる。
In addition, the semiconductor element mounting portion 11a of the metal portion 11 is provided with a concave portion 11e into which the semiconductor element 14 can be inserted and mounted during the manufacture of the semiconductor device. When the semiconductor chip 14 is inserted into the concave portion 11e, the position of the semiconductor chip 14 can be lowered by the depth of the concave portion as compared with the conventional case where the semiconductor chip 14 is mounted on the upper surface of the semiconductor chip mounting portion. can be done. The recess 11e is formed in the form of a hole or groove by disposing the second resist layer 16 in a portion corresponding to the recess 11e in the semiconductor element mounting portion 11a during the formation of the metal portion 11.
The depth is such that the semiconductor element mounting portion 11a can sufficiently secure the thickness necessary for maintaining the required strength below the portion e.

金属部11は、大部分を電解メッキに適したニッケルやニッケル合金等で形成されるが
、金属部11の裏面側には、半導体装置実装時のハンダ付けを適切に行えるようにするた
めに、ニッケル等の主材質部よりハンダぬれ性の良好な金属、例えば金や錫、パラジウム
、ハンダ等の薄膜11dが配設される構成である。この薄膜11dの厚さは0.03~1
μm程度とするのが好ましい。
Most of the metal portion 11 is made of nickel, nickel alloy, or the like, which is suitable for electroplating. A thin film 11d made of metal, such as gold, tin, palladium, or solder, which has better solder wettability than the main material portion such as nickel, is provided. The thickness of this thin film 11d is 0.03 to 1
It is preferable to make it about μm.

金属部11形成の際には、あらかじめ薄膜11dが母型基板10上の第一レジスト層1
2のない部分にメッキ等で形成された後(図3(B)参照)、この薄膜11d上にさらに
電解メッキによりニッケル等の主材質部が形成されることとなる。この薄膜11dには、
母型基板10のエッチングによる除去の際にエッチング液による金属部11の侵食劣化を
防ぐ機能を与えることもでき、その場合、金や銀、錫などの薄膜を配設するのが好ましい
When forming the metal portion 11, the thin film 11d is formed on the first resist layer 1 on the mother mold substrate 10 in advance.
After the portion without 2 is formed by plating or the like (see FIG. 3B), the main material portion such as nickel is further formed on the thin film 11d by electroplating. In this thin film 11d,
A function of preventing corrosion and deterioration of the metal portion 11 due to the etchant can be given when the mother mold substrate 10 is removed by etching.

なお、この金属部11裏面側の薄膜形成は、前記ハンダ付け対策を目的とするものの場
合、電解メッキで金属部11主材質部を形成する前に限られるものではなく、半導体装置
70の完成後、メッキにより金属部11の露出した裏面側に薄膜を形成するようにしても
かまわない。
It should be noted that the formation of the thin film on the back surface side of the metal portion 11 is not limited to before the main material portion of the metal portion 11 is formed by electrolytic plating if the purpose is to prevent soldering, but after the semiconductor device 70 is completed. Alternatively, a thin film may be formed on the exposed rear surface of the metal portion 11 by plating.

前記第一レジスト層12は、金属部11の電解メッキや表面金属層13のメッキで使用
するメッキ液に対する耐溶解性を備えた絶縁性材で形成され、母型基板10上にあらかじ
め設定される金属部11の非配置部分に対応させて配設され、金属部11及び表面金属層
13の形成後には除去されるものである(図5(C)参照)。
The first resist layer 12 is formed of an insulating material that is resistant to dissolution in a plating solution used for electrolytic plating of the metal part 11 and plating of the surface metal layer 13, and is set on the mother board 10 in advance. It is arranged corresponding to the non-arrangement portion of the metal portion 11, and is removed after the formation of the metal portion 11 and the surface metal layer 13 (see FIG. 5(C)).

この第一レジスト層12は、母型基板10上に金属部11の形成に先立って配設され、
詳細には、公知の感光性レジスト剤を母型基板10に所定の厚さ、例えば約50μmの厚
さとなるようにして密着配設し、半導体装置70の金属部11位置に対応する所定パター
ンのマスクフィルム50を載せた状態で、紫外線照射による露光での硬化(図2(C)参
照)、非照射部分の感光性材料を除去する現像等の処理を経て、金属部11の非配置部分
に対応させた形状で形成される。
This first resist layer 12 is disposed on the mother mold substrate 10 prior to the formation of the metal portion 11,
Specifically, a known photosensitive resist agent is adhered to the mother mold substrate 10 to a predetermined thickness, for example, a thickness of about 50 μm, and a predetermined pattern corresponding to the position of the metal portion 11 of the semiconductor device 70 is formed. In the state where the mask film 50 is placed, it is cured by exposure to ultraviolet irradiation (see FIG. 2C), and development is performed to remove the photosensitive material in the non-irradiated portion. It is formed in a corresponding shape.

前記第二レジスト層16は、前記第一レジスト層12同様にメッキ液に対する耐溶解性
を備えた絶縁性材で形成され、金属部11の形成の途中段階で、あらかじめ設定される金
属部11の凹部11eに対応させて配設され、金属部11及び表面金属層13の形成後に
は除去されるものである。この第二レジスト層16としては、第一レジスト層12の場合
と同様、感光性レジスト剤等を用いることができる。このレジスト剤を金属部11と第一
レジスト層12の各表面に所定の厚さ、例えば約60μmを超える厚さとなるようにして
コーティングし、金属部11の凹部11e位置に対応する所定パターンのマスクフィルム
51を載せた状態で、紫外線照射による露光で硬化させる処理を経ると、金属部11上に
固定状態の第二レジスト層16が形成されることとなる。この金属部11上の第二レジス
ト層16により、金属部11の凹部11eに相当する部分で電解メッキが進行せず、金属
部11の欠けた部分、すなわち凹部11eを生じさせられる。
Like the first resist layer 12, the second resist layer 16 is made of an insulating material that is resistant to dissolution in the plating solution. It is disposed corresponding to the recess 11e and is removed after the metal portion 11 and the surface metal layer 13 are formed. As for the second resist layer 16, a photosensitive resist agent or the like can be used as in the case of the first resist layer 12. FIG. This resist agent is coated on each surface of the metal part 11 and the first resist layer 12 to a predetermined thickness, for example, a thickness exceeding about 60 μm, and a mask having a predetermined pattern corresponding to the position of the concave portion 11e of the metal part 11. With the film 51 placed thereon, the second resist layer 16 in a fixed state is formed on the metal part 11 by performing curing by exposure to ultraviolet rays. Due to the second resist layer 16 on the metal portion 11, electroplating does not proceed in the portion corresponding to the recess 11e of the metal portion 11, and the missing portion of the metal portion 11, that is, the recess 11e is generated.

なお、この第一レジスト層12や第二レジスト層16については、感光性レジストに限
られるものではなく、メッキ液に対し変質せず強度の高い塗膜が得られる塗料を、母型基
板10上における金属部11の非配置部分や金属部11の凹部11e位置に、電着塗装等
により必要な塗膜厚さとなるように塗装して形成することもできる。
Note that the first resist layer 12 and the second resist layer 16 are not limited to the photosensitive resist, and a paint that can provide a coating film with high strength without being degraded by the plating solution is used on the mother mold substrate 10. It is also possible to apply a coating such as electrodeposition coating to the portion where the metal portion 11 is not arranged or the position of the concave portion 11e of the metal portion 11 so as to obtain the necessary coating thickness.

一方、この表面側の第一レジスト層12や第二レジスト層16とは別に、母型基板10
の裏面側にも、レジスト層18が形成される構成である(図2参照)。裏面側のレジスト
層18は、硬化状態でメッキ液への耐性のある材質で、且つ不要となったら容易に溶解除
去可能なレジスト材、例えば厚さ約50μmのアルカリ現像タイプの感光性フィルムレジ
ストを熱圧着等により配設し、そのままマスクなしに紫外線照射による露光等の処理を経
て、裏面全面にわたり硬化形成されるものとすることができる。
On the other hand, apart from the first resist layer 12 and the second resist layer 16 on the surface side, the matrix substrate 10
A resist layer 18 is also formed on the rear surface side of (see FIG. 2). The resist layer 18 on the back side is made of a resist material that is resistant to the plating solution in a hardened state and that can be easily dissolved and removed when it becomes unnecessary, for example, an alkali development type photosensitive film resist with a thickness of about 50 μm. It can be disposed by thermocompression bonding or the like, and cured and formed over the entire back surface through treatment such as exposure by ultraviolet irradiation without a mask.

前記表面金属層13は、配線用のワイヤ15をなす金線等との接合性に優れる金や銀等
からなるメッキ膜として形成される。
この表面金属層13は、母型基板10ごとのメッキ浴により金属部11の表面に所定の
厚さ、例えば、金メッキの場合は約0.1~1μm、銀メッキの場合は約1~10μmの
厚さのメッキとして形成される。この表面金属層13のメッキの際、母型基板10の裏面
側はレジスト層18で覆われていることから、メッキの付着等は生じない(図5(B)参
照)。
なお、この表面金属層13へのメッキに際しては、金属部11のメッキの場合とはメッ
キ液を異ならせるなど、メッキの金属に対応するメッキ液を使用することとなる。
The surface metal layer 13 is formed as a plated film made of gold, silver, or the like, which is excellent in bondability with the gold wire or the like forming the wire 15 for wiring.
The surface metal layer 13 is formed on the surface of the metal part 11 by a plating bath for each mother board 10 to a predetermined thickness, for example, approximately 0.1 to 1 μm in the case of gold plating and approximately 1 to 10 μm in the case of silver plating. Formed as a thick plating. At the time of plating the surface metal layer 13, since the back side of the mother board 10 is covered with the resist layer 18, plating does not adhere (see FIG. 5(B)).
When plating the surface metal layer 13, a plating solution corresponding to the metal to be plated is used, such as using a different plating solution from that used for plating the metal portion 11. FIG.

この表面金属層13のメッキを形成する際は、金属部11がニッケルの場合、メッキが
付着しにくいため、通常、表面金属層13のメッキの前にあらかじめ金属部11表面に下
地メッキ(銅ストライクや銀ストライク、又は金ストライク)を行い、表面金属層13の
金属部11への密着性を高めることが望ましい。
When the surface metal layer 13 is plated, if the metal portion 11 is made of nickel, the plating is difficult to adhere. , silver strike, or gold strike) to enhance the adhesion of the surface metal layer 13 to the metal portion 11 .

前記半導体素子14は、微細な電子回路が形成されたいわゆるチップであり、金属部1
1のうち半導体素子搭載部11aの凹部11eに挿入、接着されて搭載される。そして、
金、銅等の導電性線材からなる配線(ボンディング)用のワイヤ15が、半導体素子14
表面に設けられた電極と、金属部11のうち半導体素子搭載部11aと独立させて形成さ
れた電極部11bとにそれぞれ接合され、半導体素子14と電極部11bとを電気的に接
続することとなる。
The semiconductor element 14 is a so-called chip in which a fine electronic circuit is formed.
1, it is inserted into the concave portion 11e of the semiconductor element mounting portion 11a and mounted by bonding. and,
A wiring (bonding) wire 15 made of a conductive wire such as gold or copper is attached to the semiconductor element 14 .
The electrode provided on the surface and the electrode portion 11b formed independently of the semiconductor element mounting portion 11a of the metal portion 11 are respectively joined to electrically connect the semiconductor element 14 and the electrode portion 11b. Become.

この半導体素子14は、半導体素子搭載部11aの凹部11eに挿入配設されることか
ら、従来のように半導体素子搭載部の上面に搭載される場合と比べて、配設位置を下げる
ことができ、半導体素子14上面や接合されるワイヤ15も下がる分、半導体装置70の
厚さを小さくして製造することができ、半導体装置70の低背化を実現できる。また、半
導体素子14の位置が下がって、ワイヤ15が接合する半導体素子14と電極部の各上面
が近付く分、ワイヤ長さも短くすることができ、ワイヤ使用量を削減してコストを低減で
きる。
Since the semiconductor element 14 is inserted into the concave portion 11e of the semiconductor element mounting portion 11a, the position of the semiconductor element 14 can be lowered compared to the conventional case where the semiconductor element 14 is mounted on the upper surface of the semiconductor element mounting portion. Since the upper surface of the semiconductor element 14 and the wires 15 to be bonded are also lowered, the thickness of the semiconductor device 70 can be reduced and the height of the semiconductor device 70 can be reduced. In addition, the position of the semiconductor element 14 is lowered, and the semiconductor element 14 to which the wire 15 is bonded and the upper surfaces of the electrode portions are closer to each other, so that the length of the wire can be shortened, and the amount of wire used can be reduced, thereby reducing the cost.

前記封止材19は、物理的強度の高い熱硬化性エポキシ樹脂等であり、金属部11表面
側の半導体素子14やワイヤ15を覆った状態で封止し、半導体素子14やワイヤ15等
の構造的に弱い部分を外部から隔離した保護状態とするものである。なお、半導体素子1
4がLED等の発光素子の場合、透光性の材質が用いられる。
The sealing material 19 is a thermosetting epoxy resin or the like having high physical strength, and seals the semiconductor element 14 and the wires 15 on the surface side of the metal part 11 while covering the semiconductor element 14 and the wires 15 . This is a protected state in which structurally weak parts are isolated from the outside. In addition, the semiconductor element 1
If 4 is a light-emitting element such as an LED, a translucent material is used.

この封止材19を用いる封止工程は、半導体装置用基板1に対して行われ、母型基板1
0の表面側における金属部11等のある半導体装置となる範囲を、上型となる金型で覆っ
た上で、この金型と母型基板10の間に硬化前の封止材19を圧入し、封止材19を硬化
させることで封止が完了となる。ただし、封止工程では、一つの半導体装置となる半導体
素子搭載部11aと複数の電極部11bとの組合わせが多数整列状態のままで一様に封止
されるため、半導体装置は封止材19を介して多数つながった状態となっている。
The sealing process using this sealing material 19 is performed on the semiconductor device substrate 1, and the mother mold substrate 1
After covering the range of the semiconductor device with the metal part 11 and the like on the surface side of 0 with a mold that will be the upper mold, the sealing material 19 before hardening is press-fitted between this mold and the mother mold substrate 10. Then, the sealing is completed by curing the sealing material 19 . However, in the encapsulation process, a large number of combinations of the semiconductor element mounting portion 11a and the plurality of electrode portions 11b, which constitute one semiconductor device, are uniformly encapsulated while being aligned. 19 are connected to each other.

この封止材19は、十分な物理的強度を有しており、半導体装置70の外装の一部とし
て十分に内部を保護する機能を果し、また母型基板10を半導体装置側から引き剥がすな
ど力を加えて物理的に除去する場合にも、割れ等の破損もなく金属部11との一体化状態
を維持することとなる。
The encapsulant 19 has sufficient physical strength, functions to sufficiently protect the inside as a part of the exterior of the semiconductor device 70, and allows the mother mold substrate 10 to be peeled off from the semiconductor device side. Even when the metal part 11 is physically removed by applying a force such as the above, the integrated state with the metal part 11 is maintained without breakage such as cracking.

次に、本実施形態に係る半導体装置用基板の製造及び半導体装置用基板を用いた半導体
装置製造の各工程について説明する。
半導体装置用基板の製造工程として、まず、母型基板10上にあらかじめ設定される金
属部11の非配置部分に対応させて母型基板10に第一レジスト層12を配設する。具体
的には、母型基板10の表面側に、感光性レジスト剤12aを、形成する金属部11の高
さに対応する所定厚さ(例えば約50μm)となるようにして密着配設する(図2(B)
参照)。感光性レジスト剤に対しては、金属部11の配置位置に対応する所定パターンの
マスクフィルム50を載せた状態で、紫外線照射による露光での硬化(図2(C)参照)
、非照射部分のレジスト剤を除去する現像等の公知の処理を行い、金属部11の非配置部
分に対応させた第一レジスト層12を硬化形成する(図3(A)参照)。また、母型基板
10の裏面側にも、感光性レジスト剤を表面側同様に配設し、これに対してはそのまま全
面に対する露光等の処理を経て、裏面全面にわたりレジスト層18を硬化形成する(図2
(C)参照)。
Next, each process of manufacturing the semiconductor device substrate according to the present embodiment and manufacturing a semiconductor device using the semiconductor device substrate will be described.
As a process for manufacturing a substrate for a semiconductor device, first, a first resist layer 12 is provided on a mother mold substrate 10 corresponding to a predetermined portion on the mother mold substrate 10 where the metal portion 11 is not arranged. Specifically, a photosensitive resist agent 12a is adhered to the surface of the mother mold substrate 10 so as to have a predetermined thickness (for example, about 50 μm) corresponding to the height of the metal portion 11 to be formed ( Figure 2(B)
reference). For the photosensitive resist agent, a mask film 50 having a predetermined pattern corresponding to the arrangement position of the metal portion 11 is put thereon, and cured by exposure to ultraviolet irradiation (see FIG. 2(C)).
Then, a known process such as development is performed to remove the resist agent from the non-irradiated portions, and the first resist layer 12 corresponding to the non-arranged portions of the metal portion 11 is hardened and formed (see FIG. 3A). Also, a photosensitive resist agent is provided on the back side of the mother mold substrate 10 in the same way as on the front side, and the entire back surface is subjected to a treatment such as exposure, and a resist layer 18 is hardened over the entire back surface. (Fig. 2
(C)).

こうして、金属部11のメッキで使用するメッキ液に対する耐溶解性を備えたレジスト
層12、18を形成したら、母型基板10表面の第一レジスト層12で覆われていない露
出部分に対し、必要に応じて表面酸化被膜除去や表面活性化処理を行う。その後、この露
出部分にメッキ等によりハンダぬれ性改善用の金の薄膜11dを、例えば0.03~1μ
m厚で形成する(図3(B)参照)。そして、この薄膜11d上に、電解メッキによりニ
ッケルを積層して金属部11を形成する(図3(C)参照)。
After forming the resist layers 12 and 18 having dissolution resistance against the plating solution used for plating the metal part 11 in this way, the exposed portions of the surface of the mother mold substrate 10 not covered with the first resist layer 12 are covered with the necessary resist layers. Surface oxide film removal and surface activation treatment are performed according to the conditions. After that, a gold thin film 11d for improving solder wettability is applied to the exposed portion by plating or the like to a thickness of, for example, 0.03 to 1 μm.
It is formed with a thickness of m (see FIG. 3B). Then, nickel is laminated on the thin film 11d by electroplating to form the metal portion 11 (see FIG. 3C).

この最初の金属部11の形成工程で、金属部11は、第一レジスト層12の厚さを越え
ない所定厚さ(例えば、厚さ50μm未満)として形成される(図3(C)参照)。金属
部11は、母型基板10表面において、半導体素子搭載部11aとその近傍に複数配置さ
れる電極部11bの組合わせを一つの単位として、製造する半導体装置の数だけ前記組合
わせが多数整列状態で並べられた形態で形成されることとなる。
In this initial step of forming the metal portion 11, the metal portion 11 is formed to have a predetermined thickness (for example, less than 50 μm thick) that does not exceed the thickness of the first resist layer 12 (see FIG. 3C). . In the metal part 11, on the surface of the mother mold substrate 10, a combination of a semiconductor element mounting part 11a and a plurality of electrode parts 11b arranged in the vicinity of the semiconductor element mounting part 11a is set as one unit. It will be formed in a form arranged in a state.

金属部11を所定厚さまで形成したら、いったん電解メッキによる金属部形成作業を中
断し、表面を清浄化した後、所定厚さまで形成された金属部11の上に、金属部11にお
ける半導体素子搭載部11aの凹部11eに対応させて第二レジスト層16を配設する。
具体的には、金属部11と第一レジスト層12の表面側に、感光性レジスト剤16aを、
凹部11eの深さより大きい所定厚さ(例えば約50μm)となるようにして密着配設す
る(図4(A)参照)。この感光性レジスト剤に対し、半導体素子搭載部11aの凹部1
1eの配置位置に対応する所定パターンのマスクフィルム51を載せた状態で、紫外線照
射による露光での硬化(図4(B)参照)、非照射部分のレジスト剤を除去する現像等の
公知の処理を行い、凹部11eを生じさせる箇所に対応させた第二レジスト層16を硬化
形成する(図4(C)参照)。
After forming the metal portion 11 to a predetermined thickness, the operation of forming the metal portion by electroplating is temporarily interrupted, and after cleaning the surface, a semiconductor element mounting portion of the metal portion 11 is formed on the metal portion 11 formed to the predetermined thickness. A second resist layer 16 is provided corresponding to the recess 11e of 11a.
Specifically, a photosensitive resist agent 16a is applied to the surface side of the metal portion 11 and the first resist layer 12,
They are arranged in close contact so as to have a predetermined thickness (for example, about 50 μm) greater than the depth of the recess 11e (see FIG. 4A). With respect to this photosensitive resist agent, the concave portion 1 of the semiconductor element mounting portion 11a
With a mask film 51 having a predetermined pattern corresponding to the arrangement position of 1e placed thereon, known processing such as curing by exposure to ultraviolet irradiation (see FIG. 4(B)) and development to remove the resist agent from non-irradiated portions. to harden and form the second resist layer 16 corresponding to the portion where the concave portion 11e is to be formed (see FIG. 4(C)).

第二レジスト層16を形成したら、この第二レジスト層16で覆われていない金属部1
1の露出部分に対し、必要に応じて公知の表面処理、例えば清浄処理や密着処理等を行っ
た後、電解メッキによりニッケルを積層して金属部11を形成する工程を再度行い、金属
部11をあらかじめ設定された所定厚さ(例えば、厚さ約60μm)に形成する(図5(
A)参照)。
After forming the second resist layer 16, the metal portion 1 not covered with the second resist layer 16 is removed.
After subjecting the exposed portion of 1 to a known surface treatment, such as cleaning treatment and adhesion treatment, as required, the step of forming a metal portion 11 by laminating nickel by electroplating is performed again. is formed to a predetermined thickness (for example, a thickness of about 60 μm) (FIG. 5 (
A)).

金属部11は、第一レジスト層12の厚さを越える一方、第二レジスト層16の上面を
越えない厚さとして形成され、第二レジスト層16の側面に接する部位を伴う一方、第一
レジスト層12寄りの金属部11上端周縁には第一レジスト層12側に張出した略庇状の
張出し部11cが形成される。この新たな電解メッキによる金属部11の形成工程では、
第二レジスト層16の配置された箇所に金属部11は形成されない。
The metal portion 11 is formed to have a thickness that exceeds the thickness of the first resist layer 12 but does not exceed the upper surface of the second resist layer 16, and has a portion in contact with the side surface of the second resist layer 16. A substantially eaves-like overhanging portion 11c overhanging toward the first resist layer 12 is formed on the upper end peripheral edge of the metal portion 11 near the layer 12 . In the process of forming the metal portion 11 by this new electrolytic plating,
The metal part 11 is not formed in the place where the second resist layer 16 is arranged.

所望の厚さ及び形状の金属部11が得られたら、母型基板10ごとのメッキ浴により、
金属部11の表面に、表面金属層13を所定の厚さ、例えば銀メッキの場合、厚さ約0.
3~0.4μmとなるように形成する(図5(B)参照)。メッキ浴に用いられるメッキ
液に対し、第一レジスト層12及び第二レジスト層16は十分な耐性を有しているため、
変質等が生じることはなく、レジスト層としての機能を維持し、金属部11等必要箇所以
外へのメッキ付着を防ぐことができる。また、この表面金属層13のメッキの際、母型基
板10の裏面側はレジスト層18で覆われていることから、メッキの付着はない。
After obtaining the desired thickness and shape of the metal part 11, the plating bath for each mother board 10 is
A surface metal layer 13 is formed on the surface of the metal portion 11 to a predetermined thickness, for example, a thickness of about 0.5 mm in the case of silver plating.
It is formed to have a thickness of 3 to 0.4 μm (see FIG. 5B). Since the first resist layer 12 and the second resist layer 16 have sufficient resistance to the plating solution used in the plating bath,
It is possible to maintain the function as a resist layer and prevent the adhesion of plating to portions other than the necessary portions such as the metal portion 11 without deterioration or the like. In addition, since the back side of the mother board 10 is covered with the resist layer 18 during the plating of the surface metal layer 13, the plating does not adhere.

表面金属層13形成後、母型基板10表面側の第一レジスト層12、第二レジスト層1
6、及び裏面側のレジスト層18を所定の除去剤で溶解させてそれぞれ除去すると(図5
(C)参照)、半導体装置用基板1が完成する。第二レジスト層16を除去した後は、金
属部11の半導体素子搭載部11aにおける、第二レジスト層16が存在していた部位に
、穴又は溝状の凹部11eが生じている。
After forming the surface metal layer 13, the first resist layer 12 and the second resist layer 1 on the surface side of the matrix substrate 10
6 and the resist layer 18 on the back side are dissolved with a predetermined remover and removed respectively (FIG. 5).
(C)), the semiconductor device substrate 1 is completed. After the second resist layer 16 is removed, a hole- or groove-like concave portion 11e is formed in the semiconductor element mounting portion 11a of the metal portion 11 where the second resist layer 16 was present.

続いて、得られた半導体装置用基板1を用いた半導体装置の製造について説明すると、
まず、半導体装置用基板1における金属部11のうち半導体素子搭載部11aの凹部11
eに、接着剤を介在させた上で半導体素子14を挿入して搭載し、接着固定状態とし、さ
らに、半導体素子14表面の電極と、これに対応する各電極部11bとに、金線等のワイ
ヤ15を接合し、半導体素子14と各電極部11bとを電気的接続状態とする(図6(A
)参照)。この配線による電気的接続は、公知の超音波ボンディング装置等により実施さ
れる。電極部11bの表面には表面金属層13が形成されているため、ワイヤ15との接
合を確実なものとすることができ、接続の信頼性を高められる。
Next, the manufacturing of a semiconductor device using the obtained semiconductor device substrate 1 will be described.
First, the concave portion 11 of the semiconductor element mounting portion 11a of the metal portion 11 of the semiconductor device substrate 1 is
e, the semiconductor element 14 is inserted and mounted with an adhesive interposed therebetween to be fixed by bonding, and gold wires or the like are attached to the electrodes on the surface of the semiconductor element 14 and the corresponding electrode portions 11b. wires 15 are joined to electrically connect the semiconductor element 14 and each electrode portion 11b (FIG. 6A
)reference). This electrical connection by wiring is performed by a known ultrasonic bonding apparatus or the like. Since the surface metal layer 13 is formed on the surface of the electrode portion 11b, the connection with the wire 15 can be ensured, and the reliability of the connection can be improved.

半導体素子14と各電極部11bとの接続が完了したら、母型基板10の表面側におけ
る金属部11等のある半導体装置となる範囲を、熱硬化性エポキシ樹脂等の封止材19で
封止し、半導体素子14やワイヤ15を外部から隔離した保護状態とする(図6(B)参
照)。詳細には、母型基板10の表面側を上型となるモールド金型に装着し、母型基板1
0に下型の役割を担わせつつ、モールド金型内に封止材19となる硬化前のエポキシ樹脂
を圧入するという過程で封止が実行され、母型基板10上では、一つの半導体装置となる
半導体素子搭載部11aと複数の電極部11bとの組合わせが多数整列状態のままで一様
に封止され、半導体装置が多数つながった状態で現れることとなる。
After the connection between the semiconductor element 14 and each electrode portion 11b is completed, the area of the semiconductor device including the metal portion 11 on the surface side of the mother board 10 is sealed with a sealing material 19 such as a thermosetting epoxy resin. Then, the semiconductor element 14 and the wire 15 are in a protected state isolated from the outside (see FIG. 6B). Specifically, the surface side of the mother mold substrate 10 is mounted on a molding die serving as an upper mold, and the mother mold substrate 1 is mounted.
0 plays the role of a lower mold, sealing is performed in the process of press-fitting uncured epoxy resin as a sealing material 19 into the molding die, and one semiconductor device is formed on the mother mold substrate 10. A large number of combinations of the semiconductor element mounting portion 11a and the plurality of electrode portions 11b are uniformly sealed in an aligned state, and a large number of semiconductor devices appear in a connected state.

この多数つながった状態の半導体装置が得られたら、母型基板10を除去し、各半導体
装置の底部に金属部11の裏面側が露出した状態を得る(図6(C)参照)。ステンレス
材製である母型基板10の除去には、半導体装置側から母型基板10を物理的に引き剥が
して除去する方法を用いる。母型基板10に強度及び剥離性に優れるステンレス材を用い
ることで、半導体装置側から母型基板10を引き剥がして速やかに分離除去することがで
きる。
After obtaining a large number of connected semiconductor devices, the base substrate 10 is removed to obtain a state in which the back side of the metal portion 11 is exposed at the bottom of each semiconductor device (see FIG. 6C). The mother substrate 10 made of stainless steel is removed by physically peeling off the mother substrate 10 from the semiconductor device side. By using a stainless material excellent in strength and peelability for the mother substrate 10, the mother substrate 10 can be quickly separated and removed by peeling it off from the semiconductor device side.

この他、母型基板が他の金属材である場合には、母型基板を除去する方法として、母型
基板をエッチング液に浸漬して溶解させる方法を用いることもできる。このエッチングの
場合、母型基板は溶解するが金属部11や表面金属層13の材質が冒されないような選択
エッチング性を有するエッチング液を用いることとなる。溶解させて除去する場合では、
半導体装置側に過大な力が加わらないため、母型基板の除去に伴って悪影響が生じる確率
を小さくできる。
In addition, when the matrix substrate is made of another metal material, a method of dissolving the matrix substrate by immersing it in an etchant can be used as a method for removing the matrix substrate. In the case of this etching, an etchant having a selective etching property that dissolves the matrix substrate but does not affect the materials of the metal portion 11 and the surface metal layer 13 is used. When dissolving and removing
Since an excessive force is not applied to the semiconductor device side, the probability of adverse effects due to removal of the base substrate can be reduced.

母型基板10を除去された半導体装置の底部では、露出する金属部11の裏面側と、封
止材19の裏面側とが同一平面上に位置する状態となっている。母型基板10の除去後、
多数つながった状態の半導体装置を一つ一つ切り離せば、半導体装置70としての完成と
なる。
At the bottom of the semiconductor device from which the base substrate 10 has been removed, the exposed back side of the metal portion 11 and the back side of the sealing material 19 are positioned on the same plane. After removing the mother mold substrate 10,
The semiconductor device 70 is completed by separating the connected semiconductor devices one by one.

得られた半導体装置70内部において、金属部11の上端周縁を張出し部11cとして
略庇状に張り出し形成し、封止材19による封止状態で、この張出し部11cが硬化した
封止材19に囲まれて固定されていることから、樹脂同士で密着し強固に一体化した封止
材19に張出し部11が食込んで、金属部11に加わる外力に対する抵抗体の役割を果す
こととなり、母型基板10にステンレス材等を用い、半導体装置側から母型基板10を物
理的に引き剥がして除去する場合など、金属部11裏面側に装置外装から引離そうとする
外力が加わっても、張出し部11が金属部11の移動を妨げ、金属部11の他部分に対す
るずれ等をなくすことができ、製造時における歩留りを向上させられると共に、半導体装
置としての強度を高められ、使用時の耐久性や半導体装置動作の信頼性も高められる。
Inside the obtained semiconductor device 70, the upper end peripheral edge of the metal part 11 is formed as an overhanging portion 11c to protrude in a substantially eave-like shape. Since it is surrounded and fixed, the overhanging portion 11 bites into the sealing material 19 which is tightly integrated with the resins and serves as a resistor against the external force applied to the metal portion 11. When stainless steel or the like is used for the mold substrate 10 and the mother mold substrate 10 is removed from the semiconductor device side by physically peeling it off, even if an external force is applied to the back side of the metal portion 11 to pull it away from the exterior of the device. The protruding portion 11 prevents the movement of the metal portion 11, and the displacement of the metal portion 11 with respect to other portions can be eliminated, so that the yield in manufacturing can be improved, the strength as a semiconductor device can be increased, and the durability in use can be improved. The reliability and reliability of the operation of the semiconductor device are also improved.

このように、本実施形態に係る半導体装置用基板は、母型基板10上に形成される金属
部11である半導体素子搭載部11aに凹部11eを設け、半導体素子搭載部11aにお
ける凹部11eの下側部分の厚さを小さくすると共に、凹部11eを半導体装置製造工程
で半導体素子14を挿入、載置可能な大きさとなるようにすることから、この半導体装置
用基板1を用いた半導体装置70の製造にあたり、凹部11eで変化を加えた金属部11
の表面形状に応じて、半導体装置の構造に好ましい特長を付与でき、例えば、半導体素子
14を半導体素子搭載部11aの凹部11eに挿入配設して、従来のように半導体素子搭
載部の上面に搭載される場合と比べて、配設位置を下げることができ、半導体素子14上
面や、電極部11bと半導体素子14とを接合するワイヤ15等の高さも下がる分、半導
体装置70の厚さを小さくして製造することができ、半導体装置70の低背化を実現でき
る。また、半導体素子14の位置が下がって、ワイヤ15が接合する半導体素子14と電
極部11bの各上面が互いに近付く分、ワイヤ長さも短くすることができ、ワイヤ使用量
を削減してコストを低減できる。
As described above, the substrate for a semiconductor device according to the present embodiment has the concave portion 11e provided in the semiconductor element mounting portion 11a which is the metal portion 11 formed on the mother mold substrate 10, and the semiconductor element mounting portion 11a has the concave portion 11e below the concave portion 11e. Since the thickness of the side portion is reduced and the recess 11e is made large enough to insert and mount the semiconductor element 14 in the semiconductor device manufacturing process, the semiconductor device 70 using this semiconductor device substrate 1 is manufactured. The metal part 11 that has been changed by the concave part 11e in manufacturing
For example, the semiconductor element 14 can be inserted into the concave portion 11e of the semiconductor element mounting portion 11a and placed on the upper surface of the semiconductor element mounting portion 11a as in the conventional art. Compared to the case of mounting, the arrangement position can be lowered, and the height of the upper surface of the semiconductor element 14 and the height of the wire 15 or the like that joins the electrode portion 11b and the semiconductor element 14 can be lowered, so that the thickness of the semiconductor device 70 can be reduced. The semiconductor device 70 can be manufactured in a smaller size, and the height of the semiconductor device 70 can be reduced. In addition, since the position of the semiconductor element 14 is lowered and the upper surfaces of the semiconductor element 14 and the electrode portion 11b to which the wire 15 is bonded are brought closer to each other, the length of the wire can be shortened, thereby reducing the amount of wire used and the cost. can.

(本発明の第2の実施形態)
前記第1の実施形態における半導体装置用基板1においては、金属部11の半導体素子
搭載部11aに凹部11eを設けて、この半導体装置用基板を用いた半導体装置の製造工
程では、凹部11eに半導体素子14を搭載するようにしているが、この他、第2の実施
形態として、図8に示すように、半導体装置用基板2における金属部11の電極部11f
にも凹部11gを設け、半導体装置の製造工程で電極部の凹部位置を切断して、切り分け
られた個々の半導体装置71を得るものとすることもできる。
(Second embodiment of the present invention)
In the semiconductor device substrate 1 according to the first embodiment, the semiconductor element mounting portion 11a of the metal portion 11 is provided with the concave portion 11e. Although the element 14 is mounted thereon, as a second embodiment, as shown in FIG.
It is also possible to provide the recessed portion 11g in the semiconductor device manufacturing process, and cut the recessed portion of the electrode portion to obtain the individual cut semiconductor devices 71 .

本実施形態に係る半導体装置用基板2は、前記第1の実施形態同様、母型基板10と、
金属部11と、表面金属層13とを備えるものであり、異なる点として、金属部11にお
ける電極部11fが、後の半導体装置製造工程で行われる切断加工での切断予定箇所に位
置して、切断加工時に二つに切断される配置として基板上に形成される構成を有するもの
である。そして、この電極部11fには、切断加工の際に除去される部位を含む所定の大
きさとして凹部11gが設けられることとなる。
The semiconductor device substrate 2 according to the present embodiment includes a mother mold substrate 10, as in the first embodiment,
It has a metal portion 11 and a surface metal layer 13, and is different in that the electrode portion 11f of the metal portion 11 is positioned at a portion to be cut in a cutting process performed later in the semiconductor device manufacturing process. It has a configuration formed on the substrate as an arrangement that is cut in two during the cutting process. The electrode portion 11f is provided with a recess 11g having a predetermined size including a portion to be removed during cutting.

この半導体装置用基板2を用いて製造される半導体装置71は、図13に示すように、
前記第1の実施形態同様に金属部11と、表面金属層13と、半導体素子14と、ワイヤ
15と、封止材19とを備える一方、異なる点として、金属部11のうち電極部11fが
、装置底部だけでなく側面にも露出する配置とされる構成を有するものである。
As shown in FIG. 13, a semiconductor device 71 manufactured using this semiconductor device substrate 2 is composed of:
Similar to the first embodiment, the metal portion 11, the surface metal layer 13, the semiconductor element 14, the wire 15, and the sealing material 19 are provided. , is arranged to be exposed not only on the bottom of the device but also on the side.

半導体装置71の各側面は、複数の半導体装置の集合形成状態から個々の半導体装置を
切り離す切断加工により生じた切断面となっている。半導体装置の実装上の必要等から、
電極部を底部だけでなく側面にも露出させる構造を採用する場合、切断面である側面の一
部に位置する関係から、電極部も切断加工を受けることとなる。
Each side surface of the semiconductor device 71 is a cut surface produced by a cutting process that separates individual semiconductor devices from a collective state of a plurality of semiconductor devices. Due to the mounting needs of semiconductor devices,
When adopting a structure in which the electrode portion is exposed not only on the bottom portion but also on the side surface, the electrode portion is also cut because it is positioned on a part of the side surface, which is the cut surface.

よって、半導体装置用基板2では、基板上に設計される半導体装置位置のうち、後の半
導体装置製造の際の切断加工を経て各半導体装置の側端位置となる切断予定箇所Yに、隣
り合う二つの半導体装置位置に跨り、切断加工で二つに切断されて、それぞれの半導体の
側端部で電極部をなすような配置及び大きさとして、電極部としての金属部が基板上に形
成される(図8参照)。
Therefore, in the semiconductor device substrate 2, of the semiconductor device positions designed on the substrate, the planned cutting portion Y, which will become the side end position of each semiconductor device through the cutting process in the subsequent semiconductor device manufacturing, is adjacent to the cutting position Y. A metal portion as an electrode portion is formed on the substrate so as to straddle two semiconductor device positions and be cut into two by a cutting process so that the side end portions of each semiconductor form an electrode portion. (see Figure 8).

なお、電極部を半導体装置のコーナ部に位置させる場合、電極部となる金属部は、半導
体装置用基板上の直線状の切断位置が交差する箇所で四つに切断されて、各々が問題なく
電極部をなすような大きさ及び配置として形成されることとなる。
When the electrode portion is positioned at the corner portion of the semiconductor device, the metal portion to be the electrode portion is cut into four pieces at the intersection of the straight cutting positions on the substrate for the semiconductor device, and each of them can be cut without problems. It is formed to have a size and arrangement that form an electrode portion.

そして、半導体装置用基板2においては、電極部を形成する金属部形成工程で、電極部
の表面側に、切断予定箇所に位置するように溝状の凹部11gが設けられる。この凹部1
1gは、前記第1の実施形態の場合同様、金属部11の形成の途中段階で、凹部11gに
対応させて第二レジスト層16を配設し(図10参照)、金属部11の形成を再開した時
に第二レジスト層16位置で金属部11を形成させないことにより生じるものである。前
記第1の実施形態と同様、表面金属層13の形成工程でも第二レジスト層16は存在して
いることで、金属部11の凹部11gに面する部位には表面金属層は形成されない(図1
1(B)参照)。
Then, in the semiconductor device substrate 2, groove-like recesses 11g are provided on the surface side of the electrode portion so as to be positioned at the planned cutting portion in the step of forming the metal portion for forming the electrode portion. This concave portion 1
1g, as in the case of the first embodiment, the second resist layer 16 is disposed in correspondence with the concave portion 11g (see FIG. 10) during the formation of the metal portion 11 (see FIG. 10), and the formation of the metal portion 11 is completed. This is caused by not forming the metal part 11 at the position of the second resist layer 16 when the process is restarted. As in the first embodiment, since the second resist layer 16 is present even in the step of forming the surface metal layer 13, the surface metal layer is not formed on the portion of the metal portion 11 facing the concave portion 11g (FIG. 1
1(B)).

半導体装置用基板2上で電極部11fとなる金属部11における凹部11gの大きさは
、電極部11fの切断予定箇所に重なり、且つ、切断加工において0でない所定の厚さを
有する切断刃の切削作用により少なからず除去される部位Aが、確実に凹部の範囲に収ま
るように設定される(図12(C)参照)。また、凹部11gは、その下側で電極部11
iが半導体装置製造工程における切断加工時まで必要な強度を維持する厚さを十分確保可
能な程度の深さとされる。
The size of the concave portion 11g in the metal portion 11 to be the electrode portion 11f on the semiconductor device substrate 2 overlaps with the portion to be cut of the electrode portion 11f, and is cut with a cutting blade having a predetermined non-zero thickness in the cutting process. The portion A, which is removed by the action, is set so as to surely fall within the range of the concave portion (see FIG. 12(C)). In addition, the recess 11g has the electrode portion 11 on its lower side.
The depth i is such that a sufficient thickness can be secured to maintain the required strength until cutting in the semiconductor device manufacturing process.

そして、半導体装置製造工程での切断加工を経て各半導体装置71の側面に露出した電
極部11fの表面は、元の凹部11gのあった位置の下側部分の断面であることから、表
面金属層の断面を一切含まないこととなる(図13(B)参照)。
Since the surface of the electrode portion 11f exposed on the side surface of each semiconductor device 71 through the cutting process in the semiconductor device manufacturing process is the cross section of the lower portion of the position where the original recess 11g was, the surface metal layer does not include any cross section (see FIG. 13(B)).

次に、本実施形態に係る半導体装置用基板の製造及び半導体装置用基板を用いた半導体
装置製造の各工程について説明する。
半導体装置用基板の製造工程として、はじめに、母型基板10の表裏にレジスト層12
、18をそれぞれ形成する工程と、母型基板10表面の第一レジスト層12で覆われてい
ない部分に金属部11を所定厚さまで形成する工程とがそれぞれ実行される点は、金属部
11の形成位置が電極部11fの形状に基づいて一部変化することを除いて前記第1の実
施形態の場合と同様であり、詳細な説明を省略する。
Next, each process of manufacturing the semiconductor device substrate according to the present embodiment and manufacturing a semiconductor device using the semiconductor device substrate will be described.
As a manufacturing process of a substrate for a semiconductor device, first, a resist layer 12 is formed on the front and back of a mother mold substrate 10.
, 18 and the step of forming the metal portion 11 up to a predetermined thickness on the portion of the surface of the mother mold substrate 10 not covered with the first resist layer 12, respectively. It is the same as the case of the first embodiment except that the formation position is partially changed based on the shape of the electrode portion 11f, and detailed description thereof will be omitted.

金属部11を所定厚さまで形成したら(図9参照)、金属部形成作業を中断し、表面を
清浄化した後、所定厚さまで形成された金属部11の上に、金属部11における電極部1
1fのあらかじめ設定された凹部11gの位置に対応させて、第二レジスト層16を配設
する(図10参照)。第二レジスト層16は、形成中断時点の金属部11のうち最終的に
電極部11fとなるものの上側所定部位に、複数の電極部11fにわたる略線状配置で形
成される。
After the metal portion 11 is formed to a predetermined thickness (see FIG. 9), the metal portion forming operation is interrupted and the surface is cleaned.
A second resist layer 16 is disposed corresponding to the position of the preset recess 11g of 1f (see FIG. 10). The second resist layer 16 is formed in a substantially linear arrangement extending over the plurality of electrode portions 11f at predetermined portions above the metal portions 11 that will eventually become the electrode portions 11f among the metal portions 11 at the time of interruption of formation.

第二レジスト層16を形成した後の、第二レジスト層16で覆われていない金属部11
の露出部分に対し、金属部11を所定厚さまで形成する工程(図11(A)参照)と、金
属部11の表面に表面金属層13を形成する工程(図11(B)参照)、並びに、母型基
板10表面側の第一レジスト層12、第二レジスト層16、及び裏面側のレジスト層18
をそれぞれ除去する工程(図11(C)参照)を経て、半導体装置用基板2の完成に至る
点も、前記第1の実施形態同様である。
Metal portion 11 not covered with second resist layer 16 after forming second resist layer 16
The step of forming the metal portion 11 to a predetermined thickness on the exposed portion of (see FIG. 11A), the step of forming the surface metal layer 13 on the surface of the metal portion 11 (see FIG. 11B), and , a first resist layer 12, a second resist layer 16, and a resist layer 18 on the front side of the matrix substrate 10
are removed (see FIG. 11C) to complete the semiconductor device substrate 2, as in the first embodiment.

第二レジスト層16を除去した後、金属部11の電極部11fにおける、第二レジスト
層16が存在していた部位には、複数の電極部11fにわたって直列に並ぶ配置となる溝
状の凹部11gがそれぞれ生じている(図8参照)。
After the second resist layer 16 is removed, groove-like recesses 11g arranged in series over the plurality of electrode portions 11f are placed in the electrode portions 11f of the metal portion 11 where the second resist layer 16 was present. are generated respectively (see FIG. 8).

続いて、半導体装置用基板2を用いた半導体装置の製造では、半導体装置用基板2の金
属部11のうち半導体素子搭載部11aに、半導体素子14を搭載、固定する工程と、半
導体素子14表面の電極と各電極部11bの表面金属層13部分とにワイヤ15を接合し
て電気的接続状態とする工程(図12(A)参照)と、母型基板10の表面側における半
導体装置となる範囲を封止材19で封止する工程(図12(B)参照)と、封止で得られ
た多数つながった状態の半導体装置から母型基板10を除去する工程(図12(C)参照
)とが、順次実行される点は、前記第1の実施形態同様であり、詳細な説明を省略する。
Subsequently, in manufacturing a semiconductor device using the semiconductor device substrate 2, a step of mounting and fixing the semiconductor element 14 to the semiconductor element mounting portion 11a of the metal portion 11 of the semiconductor device substrate 2; and the surface metal layer 13 portion of each electrode portion 11b to establish an electrical connection (see FIG. 12A); A step of sealing the range with a sealing material 19 (see FIG. 12B), and a step of removing the mother mold substrate 10 from the semiconductor devices in a state of being connected in a number obtained by sealing (see FIG. 12C). ) are sequentially executed in the same manner as in the first embodiment, and detailed description thereof will be omitted.

母型基板10の除去後、多数つながった状態の半導体装置に対し、あらかじめ設定され
た切断位置に沿って切断加工を実行し、半導体装置71を一つ一つ切り離していく。この
半導体装置を切り分ける工程で、切断位置は電極部11fの凹部11gと重なっており、
切断加工の際、硬化した封止材19が切断されていくと共に、各電極部11fが凹部11
gの位置で順次切断される。
After the mother substrate 10 is removed, the connected semiconductor devices are cut along predetermined cutting positions to separate the semiconductor devices 71 one by one. In this step of cutting the semiconductor device, the cutting position overlaps with the recessed portion 11g of the electrode portion 11f.
During the cutting process, the hardened sealing material 19 is cut, and each electrode portion 11f becomes the concave portion 11.
It is cut sequentially at the position of g.

凹部11gが切断位置となることで、凹部深さの分、切断位置が下がり、従来のように
一様な高さに電極部を形成した場合と比べて、切断加工における金属の切断量を減らすこ
とができ、切断に伴う切断加工用装置の刃部(ダイシングブレード)の摩耗を軽減可能と
なる。
Since the recessed portion 11g serves as the cutting position, the cutting position is lowered by the depth of the recessed portion, and the amount of metal cut in the cutting process is reduced compared to the conventional case where the electrode portion is formed at a uniform height. It is possible to reduce the abrasion of the blade portion (dicing blade) of the cutting device that accompanies cutting.

また、半導体装置の切り分けの際、封止材19で覆われた表面側から切断位置の位置決
めを行って切断を実行する場合、封止材19が透明な材質であれば、封止材19を介して
電極部11fにおける凹部11gを識別できることから、この凹部11gを切断位置の目
印として利用することもでき、精度よく切断加工を実行できる。
Further, when cutting the semiconductor device, if the cutting position is positioned from the surface side covered with the encapsulant 19 and cutting is performed, if the encapsulant 19 is a transparent material, the encapsulant 19 can be used. Since the concave portion 11g of the electrode portion 11f can be identified through the electrode portion 11f, the concave portion 11g can be used as a mark of the cutting position, and the cutting can be performed with high accuracy.

切断されて得られた半導体装置71の側面には、切断された電極部11fが露出する(
図13参照)。この電極部11fの、半導体装置側面に露出した部位は、あらかじめ切断
予定箇所に位置するようにして凹部11gを設けられた箇所の下側部分にあたり、凹部1
1gの位置において電極部11fはその表面に表面金属層を形成されていないことから、
表面金属層の断面は含んでいない(図13(B)参照)。
The cut electrode portion 11f is exposed on the side surface of the semiconductor device 71 obtained by cutting (
See Figure 13). The portion of the electrode portion 11f exposed on the side surface of the semiconductor device corresponds to the lower portion of the portion where the recess 11g is provided so as to be positioned in advance at the portion to be cut.
Since the surface metal layer is not formed on the surface of the electrode portion 11f at the position 1g,
A cross section of the surface metal layer is not included (see FIG. 13(B)).

こうして半導体装置の側面には電極部11fの一部が露出するものの、表面金属層は現
れていないことから、表面金属層が例えば銀メッキ等の場合に、表面金属層露出部を起点
とするマイグレーションのような信頼性低下につながる事象の発生を未然に防止できる。
また、側面における電極部11fの露出部分上側には元は凹部11gがあったことで、そ
の近傍で封止材19で覆われている電極部11f上面は段差11hのある形状となってお
り(図13(B)参照)、その分電極部上面と封止材19との接触面が、単純な平面の場
合より増えるので、電極部の支持強度が向上し、半導体装置としての耐久性も高められる
In this way, although a part of the electrode portion 11f is exposed on the side surface of the semiconductor device, the surface metal layer is not exposed. It is possible to prevent the occurrence of such events that lead to a decrease in reliability.
In addition, since there was originally a concave portion 11g above the exposed portion of the electrode portion 11f on the side surface, the upper surface of the electrode portion 11f covered with the sealing material 19 in the vicinity thereof has a stepped shape 11h ( 13(B)), the contact surface between the upper surface of the electrode portion and the sealing material 19 is increased as compared with the case of a simple flat surface, so that the support strength of the electrode portion is improved, and the durability as a semiconductor device is also enhanced. be done.

(本発明の第3の実施形態)
前記第1の実施形態に係る半導体装置用基板の製造においては、最初の金属部11の形
成工程で、金属部11を第一レジスト層12の厚さを越えない所定厚さまで形成したら、
金属部形成を中断し、金属部11の上に凹部位置に対応させて第二レジスト層16を形成
配設し、さらに、この第二レジスト層16で覆われていない金属部11の露出部分に対し
、金属部11を形成する工程を再度行い、適切に配置した第二レジスト層16により金属
部11の形状を制御しつつ金属部11の最終形状を得るようにしているが、この他、第3
の実施形態として、金属部11を形成する二つの工程の間で、第一レジスト層12の上の
所定範囲に第二レジスト層16を形成し(図14参照)、後の金属部形成工程で、金属部
の形成範囲を第二レジスト層16で制限して(図15参照)、金属部11の上部をあらか
じめ設定された大きさに調整することもできる。
(Third embodiment of the present invention)
In the manufacture of the semiconductor device substrate according to the first embodiment, in the first step of forming the metal portion 11, after forming the metal portion 11 to a predetermined thickness not exceeding the thickness of the first resist layer 12,
Interrupting the formation of the metal portion, forming and disposing a second resist layer 16 on the metal portion 11 so as to correspond to the position of the concave portion, and further, on the exposed portion of the metal portion 11 not covered with the second resist layer 16. On the other hand, the step of forming the metal portion 11 is performed again, and the final shape of the metal portion 11 is obtained while the shape of the metal portion 11 is controlled by the appropriately arranged second resist layer 16 . 3
As an embodiment, between the two steps of forming the metal part 11, the second resist layer 16 is formed in a predetermined range on the first resist layer 12 (see FIG. 14), and in the metal part forming step later Alternatively, the upper portion of the metal portion 11 can be adjusted to a predetermined size by limiting the formation range of the metal portion with the second resist layer 16 (see FIG. 15).

例えば、金属部11が第一レジスト層12の厚さを越えて形成されることで、第一レジ
スト層12寄りの金属部11上端周縁には第一レジスト層12側に張出した略庇状の張出
し部11iが形成される(図15(A)参照)。この時、第一レジスト層12上に第二レ
ジスト層16が配設されていることで、張出し部11iは、その形成範囲を第二レジスト
層16で規制され、第二レジスト層16の側面に接する部位を伴いつつ形成される。結果
として、張出し部11iの張出し量は、あらかじめ設定された第二レジスト層16の配置
に基づいた所定量に管理されることとなる。
For example, by forming the metal part 11 beyond the thickness of the first resist layer 12, the upper edge of the metal part 11 near the first resist layer 12 has a substantially eaves-like shape protruding toward the first resist layer 12 side. A projecting portion 11i is formed (see FIG. 15A). At this time, since the second resist layer 16 is provided on the first resist layer 12, the formation range of the projecting portion 11i is restricted by the second resist layer 16, and the side surface of the second resist layer 16 is formed. It is formed with a contacting part. As a result, the amount of extension of the extension portion 11i is controlled to a predetermined amount based on the preset arrangement of the second resist layer 16 .

この場合、母型基板10上で隣り合う金属部11のそれぞれが上部に張出し部11iを
備えつつ、これら張出し部11i同士があらかじめ設定された適切な間隔をなす状態に調
整できることから、母型基板10上における金属部の配置間隔を従来より小さくすること
ができる。すなわち、従来の工程では金属部11上部の張出し部の張出し量を厳密に管理
できないため、張出し部同士の間隔が後のレジスト除去を妨げる狭小なものとならないよ
うに金属部11の配置間隔を広めにとる必要があったのに対し、本実施形態では張出し部
11iの張出し量を第二レジスト層16の配置で調整できることから、金属部11の配置
間隔を詰めた場合でも、張出し部11iの張出し量をレジスト除去を問題なく行える程度
に抑えて、隣り合う金属部11の最小間隔を適切な量とすることができる。
In this case, each of the metal portions 11 adjacent to each other on the mother mold substrate 10 has an overhanging portion 11i on its upper portion, and these overhanging portions 11i can be adjusted to form a predetermined appropriate interval. The arrangement intervals of the metal parts on 10 can be made smaller than before. That is, in the conventional process, the amount of overhang of the overhanging portion above the metal portion 11 cannot be strictly controlled. However, in the present embodiment, since the amount of protrusion of the overhanging portion 11i can be adjusted by the arrangement of the second resist layer 16, even if the arrangement interval of the metal portion 11 is reduced, the overhanging portion 11i The amount can be suppressed to the extent that the resist can be removed without any problem, and the minimum distance between the adjacent metal portions 11 can be set to an appropriate amount.

なお、金属部の配置間隔は、張出し部11iで抜けに対する十分な強度を得られる必要
最小限の張出し量を確保でき、且つ金属部間に第一レジスト層12の除去剤が到達して第
一レジスト層12が適切に除去できる状態が維持される範囲で、小さくすることができる
(図16参照)。これにより、半導体装置用基板3上で形成される半導体装置の一層の小
型化が図れると共に、半導体装置用基板3上での半導体装置の形成密度を高められ、半導
体装置の製造を効率化できる。
In addition, the arrangement interval of the metal parts is such that the minimum amount of protrusion required to obtain sufficient strength against removal of the protrusions 11i can be secured, and the remover of the first resist layer 12 can reach between the metal parts. The size can be reduced as long as the resist layer 12 can be properly removed (see FIG. 16). As a result, the semiconductor devices formed on the semiconductor device substrate 3 can be further miniaturized, and the formation density of the semiconductor devices on the semiconductor device substrate 3 can be increased, thereby improving the efficiency of manufacturing the semiconductor devices.

こうして第一レジスト層12の上に第二レジスト層16を配設して、第二レジスト層1
6で金属部11の上部形状を調整制御する場合、上記の他に、図17に示すように、母型
基板上に第一レジスト層12を形成するのに続いて、第二レジスト層16を形成し、その
後、金属部を形成する手順で行うこともでき、金属部の形成を一つの工程で行えることで
、製造の能率をさらに高められる。
In this way, the second resist layer 16 is arranged on the first resist layer 12, and the second resist layer 1
6, in addition to the above, as shown in FIG. It is also possible to perform the steps of forming the metal portion and then forming the metal portion. By performing the formation of the metal portion in one step, the efficiency of manufacturing can be further improved.

この場合の半導体装置用基板の製造方法としては、母型基板10の表裏にレジスト層1
2、18をそれぞれ形成する工程と、さらに第一レジスト層12の上側で、張出し部11
iとして形成される金属部11の形成を抑えたい位置に対応させて、第二レジスト層16
を配設する工程と、母型基板10表面の第一レジスト層12や第二レジスト層16で覆わ
れていない部分に金属部11を所定厚さまで形成する工程と、金属部11の表面に表面金
属層13を形成する工程と、母型基板10表面側の第一レジスト層12、第二レジスト層
16、及び裏面側のレジスト層18をそれぞれ除去する工程とを含むものであるといえる
In this case, as a method of manufacturing a substrate for a semiconductor device, resist layers 1 are formed on the front and back of the mother mold substrate 10 .
2 and 18, respectively, and overhanging portion 11 above first resist layer 12.
The second resist layer 16 corresponding to the position where the formation of the metal portion 11 formed as i is desired to be suppressed.
a step of forming the metal portion 11 to a predetermined thickness on a portion of the surface of the mother mold substrate 10 not covered with the first resist layer 12 or the second resist layer 16; It can be said that it includes a step of forming the metal layer 13 and a step of removing the first resist layer 12, the second resist layer 16, and the back side resist layer 18 on the front side of the matrix substrate 10, respectively.

これらの半導体装置用基板製造の各工程について具体的に説明すると、はじめに、母型
基板10の表裏にレジスト層12、18をそれぞれ形成する工程が実行される点は、前記
第1の実施形態同様であり、詳細な説明を省略する。
Specifically, each step of manufacturing these substrates for a semiconductor device will be described. First, the steps of forming resist layers 12 and 18 on the front and back surfaces of a mother mold substrate 10 are executed, respectively, as in the first embodiment. , and detailed description is omitted.

続いて、第二レジスト層16を形成する工程では、最初に形成された第一レジスト層1
2の上に、金属部11の形成を抑えたい範囲に対応させて第二レジスト層16を配設する
。具体的には、母型基板10と第一レジスト層12の表面側に、感光性レジスト剤16a
を、所定厚さ(例えば約50μm)となるようにして密着配設する(図17(B)参照)
。この感光性レジスト剤に対し、張出し部11iとしての金属部11の形成を抑えたい位
置に対応する所定パターンのマスクフィルム51を載せた状態で、紫外線照射による露光
での硬化(図17(C)参照)、非照射部分のレジスト剤を除去する現像等の公知の処理
を行い、金属部11を形成させない箇所に対応させた第二レジスト層16を硬化形成する
(図18(A)参照)。
Subsequently, in the step of forming the second resist layer 16, the first resist layer 1 formed first
2, a second resist layer 16 is disposed corresponding to the range where the formation of the metal portion 11 is desired to be suppressed. Specifically, a photosensitive resist agent 16 a is applied to the surface side of the mother mold substrate 10 and the first resist layer 12 .
are arranged in close contact so as to have a predetermined thickness (for example, about 50 μm) (see FIG. 17(B)).
. A mask film 51 having a predetermined pattern corresponding to a position where it is desired to suppress the formation of the metal portion 11 as the projecting portion 11i is placed on the photosensitive resist agent, and then cured by exposure to ultraviolet light (FIG. 17(C)). (see FIG. 18A), a known process such as development is performed to remove the resist agent from the non-irradiated portions, and the second resist layer 16 corresponding to the portions where the metal portions 11 are not to be formed is cured (see FIG. 18A).

第二レジスト層16を形成したら、母型基板10表面の第一レジスト層12並びに第二
レジスト層16で覆われていない露出部分に対し、必要に応じて公知の表面酸化被膜除去
や表面活性化処理を行う。その後、この露出部分にメッキ等によりハンダぬれ性改善用の
金の薄膜11dを、例えば0.05~1μm厚で形成する(図18(B)参照)。そして
、この薄膜11d上に、電解メッキによりニッケルを積層して金属部11を形成する(図
18(C)参照)
After the second resist layer 16 is formed, exposed portions of the surface of the mother mold substrate 10 not covered with the first resist layer 12 and the second resist layer 16 are subjected to known surface oxide film removal and surface activation as necessary. process. Thereafter, a gold thin film 11d for improving solder wettability is formed on the exposed portion by plating or the like to a thickness of, for example, 0.05 to 1 μm (see FIG. 18B). Then, nickel is laminated on the thin film 11d by electroplating to form the metal portion 11 (see FIG. 18(C)).

この金属部11の形成工程で、金属部11は、第一レジスト層12の厚さを越える一方
、第二レジスト層16の上面を越えない所定厚さ(例えば、厚さ約60μm)として形成
され、第一レジスト層12寄りの金属部11上端周縁には、第一レジスト層12側に張出
した略庇状の張出し部11iが、第二レジスト層16の側面に接する部位を伴いつつ形成
される(図18(C)参照)。この張出し部11iの形成範囲は、金属部11が形成され
ないように配置された第二レジスト層16で規制されることから、張出し部11iの張出
し量はあらかじめ設定されたものとなる。また、金属部11は、前記第1の実施形態同様
、母型基板10表面において、半導体素子搭載部11aとその近傍に複数配置される電極
部11bの組合わせを一つの単位として、製造する半導体装置の数だけ前記組合わせが多
数整列状態で並べられた形態で形成されることとなる。
In this process of forming the metal portion 11, the metal portion 11 is formed to have a predetermined thickness (for example, a thickness of about 60 μm) that exceeds the thickness of the first resist layer 12 but does not exceed the upper surface of the second resist layer 16. At the upper edge of the metal part 11 near the first resist layer 12, a substantially eaves-shaped overhanging part 11i overhanging to the side of the first resist layer 12 is formed with a part in contact with the side surface of the second resist layer 16. (See FIG. 18(C)). Since the formation range of the projecting portion 11i is regulated by the second resist layer 16 arranged so that the metal portion 11 is not formed, the projecting amount of the projecting portion 11i is set in advance. As in the first embodiment, the metal portion 11 is a semiconductor device manufactured by using a combination of a semiconductor element mounting portion 11a and a plurality of electrode portions 11b arranged in the vicinity of the semiconductor element mounting portion 11a on the surface of the mother mold substrate 10 as one unit. The same number of combinations as the number of devices are arranged in an aligned state.

金属部11を所定厚さまで形成した後の、金属部11の表面に表面金属層13を形成す
る工程(図19(A)参照)、並びに、母型基板10表面側の第一レジスト層12、第二
レジスト層16、及び裏面側のレジスト層18をそれぞれ除去する工程(図19(B)参
照)を経て、半導体装置用基板4の完成に至る点は、前記第1の実施形態同様である。
After forming the metal portion 11 to a predetermined thickness, a step of forming a surface metal layer 13 on the surface of the metal portion 11 (see FIG. 19A), and a first resist layer 12 on the surface side of the mother substrate 10, The process of removing the second resist layer 16 and the resist layer 18 on the back surface side (see FIG. 19B) is performed to complete the semiconductor device substrate 4, which is the same as in the first embodiment. .

このように、母型基板10上に第一レジスト層12を形成する工程に続いて、第二レジ
スト層16を形成し、その後に金属部11を形成するようにすることで、前記同様に第一
レジスト層12上側に達する金属部11(張出し部11i)の形成範囲を制御できること
に加え、各レジスト層を先にまとめて形成し、金属部11の形成を一工程で行うことで、
第二レジスト層16形成後の、既存の金属部11に対し清浄化等の処理を行った上で金属
部の形成を再開する工程を省略できるなど、生産効率の向上が図れることとなる。
In this way, following the step of forming the first resist layer 12 on the mother mold substrate 10, the second resist layer 16 is formed, and then the metal portion 11 is formed. In addition to being able to control the formation range of the metal portion 11 (extending portion 11i) reaching the upper side of one resist layer 12, by forming each resist layer collectively first and forming the metal portion 11 in one step,
After the second resist layer 16 is formed, it is possible to omit the step of resuming the formation of the metal portion after cleaning the existing metal portion 11, thereby improving the production efficiency.

なお、母型基板10上に第一レジスト層12を形成する工程に続いて、第二レジスト層
16を形成し、その後に金属部11を形成する前記一連の工程を、半導体素子搭載部や電
極部となる金属部の一部に適用して、金属部に貫通孔を生じさせることもできる。具体的
には、金属部における貫通孔を設けたい箇所に第一レジスト層12を形成し、さらにその
上に第二レジスト層16を配設し、金属部の形成工程で、各レジスト層の周囲に金属部を
形成するようにすれば、適切に配置した第二レジスト層16により上部開口形状を調整さ
れた貫通孔が、レジスト除去後に生じることとなる。孔の大きさが金属部11の第一レジ
スト層12側への張出しの量に比べて十分大きい場合には、第二レジスト層16を設けず
第一レジスト層12のみ孔位置に形成して、孔を生じさせるようにしてもよい。
The series of steps of forming the first resist layer 12 on the matrix substrate 10, followed by forming the second resist layer 16, and then forming the metal portion 11 may be performed on the semiconductor element mounting portion or the electrode. It can also be applied to a part of the metal part that becomes the part to form a through hole in the metal part. Specifically, a first resist layer 12 is formed at a location where a through hole is to be provided in the metal portion, and a second resist layer 16 is disposed thereon. If the metal portion is formed in the through-hole, the through-hole whose upper opening shape is adjusted by the appropriately arranged second resist layer 16 will be formed after the resist is removed. When the size of the hole is sufficiently larger than the amount of protrusion of the metal portion 11 toward the first resist layer 12, the second resist layer 16 is not provided and only the first resist layer 12 is formed at the hole position. You may make it produce a hole.

この他、金属部の凹部を設ける箇所と重なるように貫通孔を設けるようにしてもよく、
例として、隣り合う半導体装置の各電極部となる金属部間に貫通孔を設ける場合を説明す
ると、まず母型基板10上に第一レジスト層12を形成した後、金属部11を所定厚さま
で形成し、凹部及び貫通孔としたい箇所に第二レジスト層16を形成する。凹部と貫通孔
の両方を生じさせる箇所では、第二レジスト層は金属部と第一レジスト層とに跨るように
形成されることとなる。
In addition, a through-hole may be provided so as to overlap with the portion of the metal portion where the concave portion is provided.
As an example, a case of forming through-holes between metal portions that will be electrode portions of adjacent semiconductor devices will be described. Then, a second resist layer 16 is formed on the portions where the recesses and through holes are desired. The second resist layer is formed so as to straddle the metal portion and the first resist layer at locations where both the recess and the through hole are to be formed.

その後、さらに金属部の追加形成、表面金属層形成の各工程を実行し(図20(A)参
照)、最終的に各レジスト層を除去すると、凹部11j及び貫通孔11kの生じた半導体
装置用基板5が得られる(図20(B)参照)。図20に示した例では、半導体装置の製
造工程で、封止後に個々の半導体装置を切り分ける際の切断加工で電極部11l間の除去
される部位に、ちょうど貫通孔11kが位置するようにされており、切断の際に、貫通孔
部分に存在する封止材19が除去される結果、切断されて得られた半導体装置72の側面
に電極部11lの一部が露出する(図20(C)参照)。貫通孔11kが切断位置となる
ことで、前記第2の実施形態と同様に半導体装置の側面に電極部を露出させる構成を得る
場合でも、切断加工において金属の切断を行わずに済むこととなり、切断に伴う切断加工
用装置の刃部(ダイシングブレード)の摩耗を軽減できる。
After that, additional formation of a metal portion and formation of a surface metal layer are further performed (see FIG. 20A), and finally, when each resist layer is removed, a semiconductor device semiconductor device having a concave portion 11j and a through hole 11k is formed. A substrate 5 is obtained (see FIG. 20(B)). In the example shown in FIG. 20, in the manufacturing process of the semiconductor device, the through hole 11k is positioned exactly at the portion to be removed between the electrode portions 11l by cutting when dividing the individual semiconductor devices after sealing. As a result of the removal of the sealing material 19 present in the through-hole portion during cutting, a portion of the electrode portion 11l is exposed on the side surface of the semiconductor device 72 obtained by cutting (FIG. 20(C)). )reference). Since the through hole 11k serves as the cutting position, even when obtaining a configuration in which the electrode portion is exposed on the side surface of the semiconductor device as in the second embodiment, it is not necessary to cut the metal in the cutting process. It is possible to reduce the wear of the blade (dicing blade) of the cutting device that accompanies cutting.

1、2、3、4 半導体装置用基板
10 母型基板
11 金属部
11a 半導体素子搭載部
11b、11f 電極部
11c、11i 張出し部
11d 薄膜
11e、11g 凹部
11h 段差
11j 凹部
11k 貫通孔
11l 電極部
12 第一レジスト層
12a レジスト剤
13 表面金属層
14 半導体素子
15 ワイヤ
16 第二レジスト層
16a レジスト剤
18 レジスト層
19 封止材
50、51 マスクフィルム
70、71、72 半導体装置
Reference Signs List 1, 2, 3, 4 semiconductor device substrate 10 mother mold substrate 11 metal portion 11a semiconductor element mounting portion 11b, 11f electrode portion 11c, 11i projecting portion 11d thin film 11e, 11g recess 11h step 11j recess 11k through hole 11l electrode portion 12 First resist layer 12a Resist agent 13 Surface metal layer 14 Semiconductor element 15 Wire 16 Second resist layer 16a Resist agent 18 Resist layer 19 Sealing material 50, 51 Mask film 70, 71, 72 Semiconductor device

Claims (4)

母型基板上に、半導体素子搭載部及び/又は電極部となる金属部を備える半導体装置用基板であって、
前記金属部の表面に凹部が設けられ、
前記金属部の上端部に張出し部が形成されており、
前記張出し部には前記金属部の表面に連続して形成される上面を有し、
前記金属部の表面には表面金属層が形成され、前記凹部に面する表面には前記表面金属層が形成されておらず、
前記張出し部の高さ位置が前記凹部の深さの範囲内にあることを特徴とする半導体装置用基板。
A semiconductor device substrate comprising a semiconductor element mounting portion and/or a metal portion serving as an electrode portion on a mother mold substrate,
A concave portion is provided on the surface of the metal portion,
A protruding portion is formed at the upper end of the metal portion,
The projecting portion has an upper surface formed continuously with the surface of the metal portion,
A surface metal layer is formed on the surface of the metal portion, and the surface metal layer is not formed on the surface facing the recess,
A substrate for a semiconductor device, wherein the height position of the projecting portion is within the range of the depth of the recess.
前記張出し部は前記金属部の表面と平行な下面を有し、
前記張出し部の前記下面の高さ位置が前記凹部の深さの範囲内にあることを特徴とする請求項1に記載の半導体装置用基板。
The projecting portion has a lower surface parallel to the surface of the metal portion,
2. The semiconductor device substrate according to claim 1, wherein the height position of said lower surface of said projecting portion is within the range of the depth of said recess.
半導体素子と、半導体素子搭載部及び/又は電極部となる金属部と、前記半導体素子および前記金属部の表面側を覆って封止する封止材とを備え、装置底部に前記金属部の裏面が露出する半導体装置であって、
前記金属部の表面に凹部が設けられ、
前記金属部の上端部に張出し部が形成されており、
前記張出し部には前記金属部の表面に連続して形成される上面を有し、
前記金属部の表面には表面金属層が形成され、前記凹部に面する表面には前記表面金属層が形成されておらず、
前記張出し部の高さ位置が前記凹部の深さの範囲内にあることを特徴とする半導体装置。
A semiconductor element, a metal part that serves as a semiconductor element mounting part and/or an electrode part, and a sealing material that covers and seals the surface side of the semiconductor element and the metal part, and the back surface of the metal part is provided on the bottom of the device. A semiconductor device in which is exposed,
A concave portion is provided on the surface of the metal portion,
A protruding portion is formed at the upper end of the metal portion,
The projecting portion has an upper surface formed continuously with the surface of the metal portion,
A surface metal layer is formed on the surface of the metal portion, and the surface metal layer is not formed on the surface facing the recess,
A semiconductor device, wherein the height position of the projecting portion is within the range of the depth of the recess.
前記張出し部は前記金属部の表面と平行な下面を有し、
前記張出し部の前記下面の高さ位置が前記凹部の深さの範囲内にあることを特徴とする請求項3に記載の半導体装置。
The projecting portion has a lower surface parallel to the surface of the metal portion,
4. The semiconductor device according to claim 3, wherein the height position of said lower surface of said protrusion is within the range of the depth of said recess.
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JP2010040679A (en) 2008-08-01 2010-02-18 Kyushu Hitachi Maxell Ltd Semiconductor device and its production process
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JP2002261187A (en) 2000-12-28 2002-09-13 Hitachi Ltd Semiconductor device
JP2002289739A (en) 2001-03-23 2002-10-04 Dainippon Printing Co Ltd Resin sealed type semiconductor device, and circuit member for semiconductor device and its manufacturing method
JP2010040679A (en) 2008-08-01 2010-02-18 Kyushu Hitachi Maxell Ltd Semiconductor device and its production process
JP2011096970A (en) 2009-11-02 2011-05-12 Dainippon Printing Co Ltd Led element placing member, led element placing substrate, method of manufacturing the same, led element package, and method of manufacturing the same
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