JP7251914B2 - semiconductor equipment - Google Patents

Description

The present invention relates to semiconductor devices.

2. Description of the Related Art A semiconductor device including an IGBT (insulated gate bipolar transistor) or the like is known (see Patent Document 1, for example). A dummy trench may be provided in a semiconductor device.
Patent document 1 International publication 2005/109521 pamphlet

When the semiconductor device is turned on, a P-type inversion region may be formed in the N-type region near the bottom of the dummy trench. The formation of a P-type inversion region increases turn-on loss.

A first aspect of the present invention provides a semiconductor device comprising a semiconductor substrate. The semiconductor device may include a first conductivity type drift region formed in a semiconductor substrate. The semiconductor device may include a base region of the second conductivity type formed between the upper surface of the semiconductor substrate and the drift region in the semiconductor substrate. The semiconductor device may comprise an accumulation region of a first conductivity type formed between a drift region and a base region in a semiconductor substrate and having a higher doping concentration than the drift region. The semiconductor device may include a dummy trench section formed in the semiconductor substrate so as to penetrate the base region from the upper surface of the semiconductor substrate. At least one of the accumulation region and the dummy trench portion may have a suppression structure for suppressing the formation of the second conductivity type inversion region in the first conductivity type region adjacent to the dummy trench portion.

The semiconductor device may further include a gate trench portion formed in the semiconductor substrate through the base region and the accumulation region from the upper surface of the semiconductor substrate to the drift region. The gate trench portion may have a gate insulating film formed on the inner wall of the trench. The gate trench portion may have a gate conductive portion covered with a gate insulating film. The dummy trench portion may have a dummy insulating film formed on the inner wall of the trench and thicker than the gate insulating film. The dummy trench portion may have a dummy conductive portion covered with a dummy insulating film.

The film thickness of the dummy insulating film may be twice or more the film thickness of the gate insulating film. The dummy insulating film in the dummy trench portion may have a uniform film thickness.

The dummy trench portion may be filled with an insulating material. The lower end of the dummy trench portion may be arranged above the lower end of the accumulation region.

The semiconductor device may include a gate trench section formed in the semiconductor substrate through the base region and the accumulation region to a position deeper than the dummy trench section. The dummy trench section may have a dummy insulating film formed on the inner wall of the trench. The dummy trench portion may have a dummy conductive portion covered with a dummy insulating film. The doping concentration distribution in the accumulation region may have a peak in the depth direction of the semiconductor substrate. In the depth direction of the semiconductor substrate, the doping concentration distribution peak in the accumulation region may be located between the lower end of the dummy conductive portion and the lower end of the dummy insulating film. In the depth direction of the semiconductor substrate, the lower end of the accumulation region may be arranged between the lower end of the dummy conductive portion and the lower end of the dummy insulating film.

The dummy insulating film on the bottom of the dummy trench may be thicker than the dummy insulating film on the sidewall of the dummy trench. The dummy trench section may have a dummy insulating film formed on the inner wall of the trench. The dummy trench portion may have a dummy conductive portion covered with a dummy insulating film. The dummy insulating film on the bottom of the dummy trench may be thicker than the dummy insulating film on the sidewall of the dummy trench. The lower end of the dummy insulating film at the bottom of the dummy trench portion may be arranged below the accumulation region.

The lower end of the dummy conductive portion may be arranged below the upper end of the accumulation region. In the accumulation region, the doping concentration in the dummy adjacent region adjacent to the dummy trench portion is integrated in the depth direction of the semiconductor substrate. It may be higher than the integrated integral concentration.

The accumulation region may be formed to a deeper position in the dummy adjacent region than in the gate adjacent region. The dummy adjacent region of the accumulation region is arranged in a doping concentration distribution in the depth direction of the semiconductor substrate at a first peak and at a position deeper than the first peak and having a higher doping concentration than the first peak. and a peak of

The accumulation region may have a peak doping concentration in the dummy adjacent region that is higher than a peak doping concentration in the gate adjacent region. In the accumulation region formed between the two dummy trench portions, the central region at the center of the two dummy trench portions may have a lower integrated concentration than the dummy adjacent region adjacent to the dummy trench portions.

A semiconductor device includes a transistor section formed on a semiconductor substrate and including one or more dummy trench sections, a diode section formed on the semiconductor substrate and including one or more dummy trench sections, and a transistor section and a diode section on the semiconductor substrate. and a boundary portion comprising one or more dummy trench portions. A high-concentration region of the second conductivity type having a doping concentration higher than that of the base region may be formed on the upper surface of the semiconductor substrate in the mesa portion sandwiched between the dummy trench portions in the boundary portion.

An accumulation region may not be formed in at least a part of the boundary mesa. An accumulation region may be formed over the entire boundary mesa.

In the mesa portion of the boundary portion, the integrated concentration obtained by integrating the first conductivity type doping concentration in the depth direction of the semiconductor substrate in the region adjacent to the dummy trench portion on the side closer to the transistor portion is the second in the central region of the mesa portion. It may be higher than the integrated concentration obtained by integrating the doping concentration of one conductivity type in the depth direction.

In the mesa portion of the boundary portion, the integrated concentration obtained by integrating the first conductivity type doping concentration in the depth direction of the semiconductor substrate in the region adjacent to the dummy trench portion on the side closer to the diode portion is It may be higher than the integrated concentration obtained by integrating the doping concentration of one conductivity type in the depth direction.

The semiconductor device may include a gate trench portion formed in the semiconductor substrate through the base region and the accumulation region from the upper surface of the semiconductor substrate to the drift region. The semiconductor device may include a mesa portion sandwiched between a gate trench portion and a dummy trench portion inside a semiconductor substrate and having a base region disposed thereon. A base region arranged in at least a part of the mesa portion sandwiched between the gate trench portion and the dummy trench portion may not be connected to the emitter electrode.

The semiconductor device may include a first gate trench portion and a second gate trench portion formed in the semiconductor substrate through the base region and the accumulation region from the upper surface of the semiconductor substrate to the drift region. Each of the first gate trench portion, the second gate trench portion, and the dummy trench portion includes two extending portions extending parallel to a predetermined direction on the upper surface of the semiconductor substrate, and two extending portions. and a tip connecting the tips of the . The dummy trench portion may be arranged inside the first gate trench portion on the upper surface of the semiconductor substrate. The second gate trench portion may be arranged inside the dummy trench portion on the upper surface of the semiconductor substrate.

A semiconductor device includes a gate trench portion formed in a semiconductor substrate through a base region and an accumulation region from the upper surface of the semiconductor substrate to a drift region, and a mesa portion sandwiched between at least one of the dummy trench portion and the gate trench portion. , may also be provided. The accumulation region may comprise a first accumulation region provided below the base region and a second accumulation region provided between the first accumulation region and the drift region.

At least one of the dummy trench portion and the gate trench portion includes a trench thin film portion having an insulating film having a predetermined thickness on the inner wall of the trench and a conductive portion covered with the insulating film; and a trench thick-film portion having an insulating film thicker than the thickness of the insulating film in the thin-film portion.

The conductive portion is provided in the trench thin film portion, but may not be provided in the trench thick film portion.

The conductive portion may be provided in both the trench thin film portion and the trench thick film portion. The conductive portion of the trench thin film portion may be wider in the trench arrangement direction than the conductive portion of the trench thick film portion.

The conductive portion has the same width in the direction in which the trenches are arranged, and may be provided in both the trench thin film portion and the trench thick film portion. At least one of the dummy trench portion and the gate trench portion may have a width in the array direction of the trench thin film portion smaller than that of the trench thick film portion in the array direction.

The trench thick film portion may be provided at a position deeper than the base region.

The accumulation region may further comprise a third accumulation region provided between the first accumulation region and the second accumulation region.

A second aspect of the present invention provides a semiconductor device comprising a semiconductor substrate. The semiconductor device may include a first conductivity type drift region formed in a semiconductor substrate. The semiconductor device may include a base region of the second conductivity type formed between the upper surface of the semiconductor substrate and the drift region in the semiconductor substrate. The semiconductor device may comprise an accumulation region of a first conductivity type formed between a drift region and a base region in a semiconductor substrate and having a higher doping concentration than the drift region. The semiconductor device may include a gate trench portion formed in the semiconductor substrate through the base region and the accumulation region from the upper surface of the semiconductor substrate to the drift region. The semiconductor device may include a dummy trench section formed in the semiconductor substrate so as to penetrate the base region from the upper surface of the semiconductor substrate. The semiconductor device may comprise an emitter electrode provided above the top surface of the semiconductor substrate. The semiconductor device may include a mesa portion sandwiched between a gate trench portion and a dummy trench portion inside a semiconductor substrate and having a base region disposed thereon. A base region arranged in at least a part of the mesa portion sandwiched between the gate trench portion and the dummy trench portion may not be connected to the emitter electrode.

A third aspect of the present invention provides a semiconductor device comprising a semiconductor substrate. The semiconductor device may include a first conductivity type drift region formed in a semiconductor substrate. The semiconductor device may include a base region of the second conductivity type formed between the upper surface of the semiconductor substrate and the drift region in the semiconductor substrate. The semiconductor device may comprise an accumulation region of a first conductivity type formed between a drift region and a base region in a semiconductor substrate and having a higher doping concentration than the drift region. The semiconductor device may include a first gate trench portion and a second gate trench portion formed in the semiconductor substrate through the base region and the accumulation region from the upper surface of the semiconductor substrate to the drift region. The semiconductor device may include a dummy trench section formed in the semiconductor substrate so as to penetrate the base region from the upper surface of the semiconductor substrate. The dummy trench portion may be arranged inside the first gate trench portion on the upper surface of the semiconductor substrate. The second gate trench portion may be arranged inside the dummy trench portion on the upper surface of the semiconductor substrate.

The above summary of the invention is not an exhaustive list of all features of the present invention. Subcombinations of these features can also be inventive.

1 is a diagram partially showing the top surface of a semiconductor device 100 according to an embodiment of the present invention; FIG. FIG. 2 is a diagram showing an example of a cross section taken along line aa in FIG. 1; 3 is an enlarged cross-sectional view of the vicinity of a gate trench portion 40 and a dummy trench portion 30; FIG. FIG. 2 is a diagram showing another example of the aa cross section in FIG. 1; FIG. 2 is a diagram showing another example of the aa cross section in FIG. 1; FIG. 2 is a diagram showing another example of the aa cross section in FIG. 1; 7 is a diagram showing an example of doping concentration distribution in the depth direction of the accumulation region 16 shown in FIG. 6. FIG. FIG. 2 is a diagram showing another example of the aa cross section in FIG. 1; 9 is an enlarged cross-sectional view of the vicinity of a gate trench portion 40 and a dummy trench portion 30 shown in FIG. 8; FIG. FIG. 2 is a diagram showing another example of the aa cross section in FIG. 1; FIG. 11 is a diagram showing an example of doping concentration distribution in the gate adjacent region 72 and the dummy adjacent region 74 shown in FIG. 10; FIG. 10 is a diagram showing another example of doping concentration distribution in the gate adjacent region 72 and the dummy adjacent region 74; 3 is a diagram showing a structural example of an accumulation region 16 sandwiched between dummy trench portions 30; FIG. 3 is a diagram partially showing another example of the top surface of the semiconductor device 100; FIG. 15 is a diagram showing an example of a bb cross section of the semiconductor device 100 shown in FIG. 14; FIG. 4 is a diagram showing an example of a mesa portion 94 of the boundary portion 90. FIG. 8 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. 8 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. 8 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. 3 is a diagram showing another example of the bb cross section of the semiconductor device 100; FIG. 3 is a diagram showing another example of the bb cross section of the semiconductor device 100; FIG. 4 is a diagram showing an example of a mesa portion 94 of the boundary portion 90. FIG. 8 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. 8 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. 8 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. 8 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. 8 is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. 3 is a diagram showing another example of the bb cross section of the semiconductor device 100; FIG. It is a figure which shows an example of a trench part. FIG. 10 is a diagram showing another example of a trench portion; FIG. 10 is a diagram showing another example of a trench portion; FIG. 10 is a diagram showing another example of a trench portion; 1 is a top view showing an example of a semiconductor device 200 according to an embodiment of the invention; FIG. 2 is a diagram showing an example of a cc cross section of the semiconductor device 200; FIG. FIG. 10 is a diagram showing another example of the cc cross section of the semiconductor device 200; 1 is a top view showing an example of a semiconductor device 300 according to an embodiment of the invention; FIG. 3 is a diagram showing an example of a dd cross section of the semiconductor device 300; FIG. FIG. 10 is a diagram showing another example of the dd cross section of the semiconductor device 300; 3 is a diagram showing an example of an ee cross section of the semiconductor device 300; FIG. 1 is a top view showing an example of a semiconductor device 400 according to an embodiment of the invention; FIG. 4 is a diagram showing an example of an ff cross section of the semiconductor device 400; FIG. FIG. 4 is a diagram showing another example of the ff cross section of the semiconductor device 400; 3 is a diagram showing an example of a gg cross section of the semiconductor device 400; FIG.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution of the invention.

In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is called "upper", and the other side is called "lower". One of the two main surfaces of a substrate, layer or other member is called the upper surface and the other surface is called the lower surface. The "up" and "down" directions are not limited to the gravitational direction. In this specification, technical matters may be described using X-, Y-, and Z-axis orthogonal coordinate axes. Let the depth direction of the semiconductor substrate be the Z-axis.

Although the terms "emitter" and "collector" are used in this specification, semiconductor devices are not limited to IGBTs. "Sources" and "drains" in transistors such as MOSFETs may also fall within the scope of the terms "emitter" and "collector" herein.

In each embodiment, an example in which the first conductivity type is the N type and the second conductivity type is the P type is shown, but the first conductivity type may be the P type and the second conductivity type may be the N type. In this case, the conductivity types of substrates, layers, regions, etc. in each embodiment have opposite polarities.

FIG. 1 is a diagram partially showing the top surface of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 of this example is a semiconductor chip including transistors such as IGBTs. FIG. 1 shows the top surface of the chip around the edge of the chip, omitting other regions.

1 shows the active region of the semiconductor substrate in the semiconductor device 100, the semiconductor device 100 may have a breakdown voltage structure surrounding the active region. The active region refers to a region through which current flows when the semiconductor device 100 is controlled to be on. The breakdown voltage structure relaxes electric field concentration on the upper surface side of the semiconductor substrate. The breakdown voltage structure has, for example, a guard ring, a field plate, a RESURF, or a combination of these structures.

The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, an accumulation region 16 and a well region 11 formed inside a semiconductor substrate. The accumulation region 16 is not exposed on the top surface of the semiconductor substrate. In FIG. 1, the region where the accumulation region 16 is formed in the XY plane parallel to the upper surface of the semiconductor substrate is indicated by broken lines. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate electrode 46 provided above the upper surface of the semiconductor substrate. Emitter electrode 52 and gate electrode 46 are provided separately from each other.

An interlayer insulating film is formed between the emitter electrode 52 and the gate electrode 46 and the upper surface of the semiconductor substrate, but is omitted in FIG. A contact hole 54, a contact hole 55, and a contact hole 56 are formed through the interlayer insulating film of this example.

Emitter electrode 52 contacts emitter region 12, contact region 15 and base region 14 on the upper surface of the semiconductor substrate through contact hole 54. FIG. The contact holes 54 of this example are formed between the respective trench portions. Also, the emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through the contact hole 56 . Between the emitter electrode 52 and the dummy conductive portion, a connection portion 57 made of a conductive material such as impurity-doped polysilicon may be provided. The connecting portion 57 is formed on the upper surface of the semiconductor substrate. In this example, the contact hole 56 is arranged at the tip of the dummy trench portion 30 in the X-axis direction. An insulating film is provided between the connection portion 57 and the semiconductor substrate 10 .

Gate electrode 46 is in contact with gate wiring 45 through contact hole 55 . The gate wiring 45 is formed of impurity-doped polysilicon or the like. The gate wiring 45 is connected to the gate conductive portion in the gate trench portion 40 on the upper surface of the semiconductor substrate. Gate wiring 45 is not connected to the dummy conductive portion in dummy trench portion 30 . The gate wiring 45 of this example is formed from below the contact hole 55 to the tip portion 43 of the gate trench portion 40 . The gate conductive portion is exposed on the upper surface of the semiconductor substrate at the tip portion 43 of the gate trench portion 40 and is in contact with the gate wiring 45 . An insulating film is provided between the gate wiring 45 and the semiconductor substrate 10 .

Emitter electrode 52 and gate electrode 46 are formed of a material containing metal. For example, at least a partial region of each electrode is made of aluminum or an aluminum silicon alloy. Each electrode may have a barrier metal made of titanium, a titanium compound, or the like under a region made of aluminum or the like, and may have a plug made of tungsten or the like in the contact hole.

One or more gate trench portions 40 and one or more dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction on the upper surface of the semiconductor substrate. The arrangement direction in FIG. 1 is the Y-axis direction.

The gate trench portion 40 of this example has two extending portions 41 extending in parallel along the extending direction (the X-axis direction in this example) perpendicular to the arrangement direction, and two extending portions 41 at the ends of the extending portions 41 . It may have a connecting tip 43 . At least a part of the tip portion 43 is preferably formed in a curved shape on the upper surface of the semiconductor substrate. By connecting the tips of the two extending portions 41 of the gate trench portion 40, electric field concentration at the ends of the extending portions 41 can be alleviated.

One or more dummy trench portions 30 are provided between each extension portion 41 of the gate trench portion 40 . Like the gate trench portion 40, the dummy trench portion 30 may have a tip portion connecting the tips of the two extension portions. In this example, a dummy trench portion 30 having two extension portions and a tip portion is formed between each extension portion 41 of the gate trench portion 40 . Another example of the dummy trench portion 30 may have a straight shape without a tip portion. The dummy trench portion 30 is provided at a position not overlapping the gate wiring 45 .

Emitter electrode 52 is formed above gate trench portion 40 , dummy trench portion 30 , well region 11 , emitter region 12 , base region 14 and contact region 15 . The well region 11 is formed within a predetermined range from the edge of the active region on the side where the gate electrode 46 is provided. The well region 11 in this example is of P+ type. The diffusion depth of well region 11 may be deeper than the depths of gate trench portion 40 and dummy trench portion 30 . Part of gate trench portion 40 and dummy trench portion 30 on the gate electrode 46 side is formed in well region 11 . The bottom of the end of the dummy trench portion 30 in the extending direction may be covered with the well region 11 .

A base region 14 is formed in the mesa portion sandwiched between the trench portions inside the semiconductor substrate. Base region 14 is of P− type with a lower doping concentration than well region 11 .

A P + -type contact region 15 having a higher doping concentration than the base region 14 is formed on the upper surface of the mesa base region 14 . An N + -type emitter region 12 having a doping concentration higher than that of the semiconductor substrate is selectively formed on the upper surface of the base region 14 .

Each of contact region 15 and emitter region 12 is formed from one adjacent trench portion to the other trench portion. The contact regions 15 and the emitter regions 12 are alternately exposed on the upper surface of the semiconductor substrate along the extending direction (X-axis direction) of the trench portion.

In another example of the mesa portion, the contact region 15 and the emitter region 12 may be formed in stripes along the extending direction. For example, an emitter region 12 is formed in a region adjacent to the trench portion, and a contact region 15 is formed in a region sandwiched between the emitter regions 12 .

A contact hole 54 is formed above each region of contact region 15 and emitter region 12 . Contact hole 54 is not formed in a region corresponding to base region 14 and well region 11 .

FIG. 2 is a diagram showing an example of the aa cross section in FIG. The aa section of this example is the YZ plane. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 26, an emitter electrode 52 and a collector electrode 58 in the cross section. The interlayer insulating film 26 is, for example, silicate glass doped with impurities such as boron and phosphorus. The interlayer insulating film 26 is selectively formed on the upper surface of the semiconductor substrate 10 . Emitter electrode 52 is formed on the upper surfaces of semiconductor substrate 10 and interlayer insulating film 26 . A collector electrode 58 is formed on the bottom surface of the semiconductor substrate 10 .

The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, or the like. The semiconductor substrate 10 of this example is a silicon substrate.

A semiconductor substrate 10 is formed with an N− type drift region 18 . The drift region 18 of this example is a region of the semiconductor substrate 10 that remains without the emitter region 12, the base region 14, the accumulation region 16, the buffer region 20 and the collector region 22 being formed.

A P− type base region 14 is formed between the upper surface of the semiconductor substrate 10 and the drift region 18 . The base region 14 may be formed by implanting a P-type impurity such as boron from the upper surface of the semiconductor substrate 10 .

An N + -type emitter region 12 is formed on the upper surface of the base region 14 . The emitter region 12 may be formed by implanting N-type impurities such as phosphorus from the upper surface of the semiconductor substrate 10 .

An N+ type accumulation region 16 is formed between the drift region 18 and the base region 14 . The accumulation region 16 may be formed by implanting N-type impurities such as phosphorus or protons from the upper surface of the semiconductor substrate 10 .

In this example, the gate trench portion 40 and the dummy trench portion 30 are formed from the upper surface of the semiconductor substrate 10 so as to penetrate the emitter region 12 , the base region 14 and the accumulation region 16 . The bottoms of the gate trench portion 40 and the dummy trench portion 30 of this example are arranged in the drift region 18 . It should be noted that the fact that the trench penetrates through the impurity region is not limited to the order in which the trench is formed after the impurity region is formed. A structure in which an impurity region is formed between the trench portions after the trench portions are formed is also included in the structure in which the trench portion penetrates the impurity region.

Buffer region 20 is formed on the lower surface side of drift region 18 . The doping concentration of buffer region 20 is higher than the doping concentration of drift region 18 . The buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower surface side of the base region 14 from reaching the P + -type collector region 22 . A P+ type collector region 22 is formed on the lower surface side of the buffer region 20 .

The gate trench portion 40 has a gate insulating film 42 and a gate conductive portion 44 . A gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is covered with the gate insulating film 42 inside the gate trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10 from each other. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

The gate conductive portion 44 includes at least a region facing the adjacent base region 14 in the depth direction. The gate trench portion 40 in the cross section is covered with the interlayer insulating film 26 on the upper surface of the semiconductor substrate 10 . When a predetermined voltage is applied to the gate conductive portion 44 , a channel is formed in the surface layer of the interface contacting the gate trench portion 40 in the base region 14 .

The dummy trench portion 30 of this example has a dummy insulating film 32 and a dummy conductive portion 34 . The dummy insulating film 32 is formed covering the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench portion 30 and covered with the dummy insulating film 32 . The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10 . The dummy conductive portion 34 may be made of the same material as the gate conductive portion 44 . For example, the dummy conductive portion 34 is made of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction. The dummy trench portion 30 in the cross section is covered with the interlayer insulating film 26 on the upper surface of the semiconductor substrate 10 .

By providing the dummy trench portion 30, the effect of accumulating carriers can be enhanced, the conductivity modulation can be promoted, and the ON voltage can be lowered. Further, by adjusting the ratio of the dummy trench portion 30 to the gate trench portion 40, the switching speed of the semiconductor device 100 can be adjusted.

When a predetermined on-voltage is applied to the gate conductive portion 44 to turn on the semiconductor device 100 , a reverse bias is applied between the dummy conductive portion 34 and the drift region 18 at the bottom of the dummy trench portion 30 . For example, when the width of the depletion layer in the drift region 18 narrows during turn-on and the lower end of the depletion layer reaches the vicinity of the bottom of the dummy trench portion 30, the voltage of the dummy conductive portion 34 is the ground potential, and the dummy trench portion The voltage near the bottom of 30 is a predetermined positive voltage.

When a reverse bias is applied in the vicinity of the bottom of the dummy trench portion 30, holes may gather in the vicinity of the bottom of the dummy trench portion 30 to form a P-type inversion region. If a P-type inversion region is formed, holes injected into the drift region 18 escape to the emitter side through the inversion region and the base region 14, increasing turn-on loss.

On the other hand, in the semiconductor device 100, at least one of the accumulation region 16 and the dummy trench portion 30 has a P-type region adjacent to the dummy trench portion 30 (the drift region 18 and the accumulation region 16 in this example). has a suppressing structure that suppresses the formation of an inversion region of . In the example shown in FIG. 2, the dummy trench portion 30 has a suppression structure.

In the dummy trench portion 30 of this example, the film thickness of the dummy insulating film 32 is thicker than the film thickness of the gate insulating film 42 . As the film thickness of the dummy insulating film 32, the average film thickness of the entire dummy insulating film 32 may be used. The film thickness of the dummy insulating film 32 may be the average film thickness of the dummy insulating film 32 formed between the dummy conductive portion 34 and the side wall of the dummy trench in the Y-axis direction.

For the film thickness of the gate insulating film 42, the average film thickness of the entire gate insulating film 42 may be used. The film thickness of the gate insulating film 42 may be the average film thickness of the gate insulating film 42 formed between the gate conductive portion 44 and the sidewall of the gate trench in the Y-axis direction.

By forming the dummy insulating film 32 thick, the capacitance between the dummy conductive portion 34 and the drift region 18 can be reduced, and the number of holes collected in the vicinity of the bottom portion of the dummy trench portion 30 can be reduced. Therefore, formation of a P-type inversion region in the vicinity of the bottom of the dummy trench portion 30 can be suppressed.

FIG. 3 is an enlarged sectional view of the vicinity of the gate trench portion 40 and the dummy trench portion 30. As shown in FIG. The film thickness T1 of the dummy insulating film 32 may be twice or more the film thickness T2 of the gate insulating film 42 . The film thickness T1 of the dummy insulating film 32 may be three times or more the film thickness T2 of the gate insulating film 42 or may be four times or more.

Also, the dummy insulating film 32 preferably has a uniform film thickness. A uniform film thickness means, for example, that the error of the film thickness of the dummy insulating film 32 at each position in one dummy trench portion 30 is within a range of ±20%. The error range may be in the range of ±10%. For example, the film thickness T1 of the dummy insulating film 32 formed on the side wall of the dummy trench portion 30 and the film thickness T2 of the dummy insulating film 32 formed on the bottom portion are uniform. However, in the vicinity of the upper end of the dummy trench portion 30, the diameter of the trench tends to fluctuate and the boundary between the interlayer insulating film 26 and the dummy insulating film 32 is unclear. It is sufficient that the dummy insulating film 32 has the above-described uniform film thickness. The gate insulating film 42 may similarly have a uniform film thickness.

Since the dummy insulating film 32 has a uniform film thickness, it becomes easier to inspect whether the thickness of the dummy insulating film 32 is formed as designed. That is, when a predetermined test voltage is applied between the dummy conductive portion 34 and the semiconductor substrate 10 for inspection, if the thickness of the dummy insulating film 32 is not uniform, dielectric breakdown occurs first in the thin region. It becomes difficult to confirm whether the film thickness of the thick region is the specified value. On the other hand, by uniformly increasing the thickness of the entire dummy insulating film 32, the thickness of the dummy insulating film 32 can be easily inspected, and the dummy insulating film 32 having a thickness sufficient to suppress the formation of the P-type inversion region can be obtained. You can easily check if it is formed.

The dummy trench portion 30 may be formed to protrude below the lower end 17 of the accumulation region 16 . The lower end 35 of the dummy conductive portion 34 may be arranged below the lower end 17 of the accumulation region 16 . In another example, the lower end 35 of the dummy conductive portion 34 may be arranged above the lower end of the accumulation region 16 .

FIG. 4 is a diagram showing another example of the aa cross section in FIG. The semiconductor device 100 in this example differs from the example shown in FIG. 2 in the structure of the dummy trench portion 30 . Other structures may be the same as the example shown in FIG.

In the dummy trench portion 30 of this example, the inside of the trench is filled with an insulating material. The insulating material may be the dummy insulating film 32 formed by oxidizing or nitriding the inner wall of the trench, or may be an insulating film formed by a CVD method or the like, and may include a plurality of types of these insulating films. . Further, no conductive material is provided inside the trench of the dummy trench portion 30 . However, a cavity surrounded by an insulating material may be formed in the trench of the dummy trench portion 30 . By filling the inside of the trench of the dummy trench portion 30 with an insulating material, it is possible to suppress the collection of holes in the vicinity of the bottom portion of the dummy trench portion 30 .

FIG. 5 is a diagram showing another example of the aa cross section in FIG. The semiconductor device 100 in this example differs from the example shown in FIG. 4 in the length of the dummy trench portion 30 in the depth direction (Z-axis direction). Other structures may be the same as the example shown in FIG.

In the dummy trench portion 30 of this example, the inside of the trench is filled with an insulating material as in the example shown in FIG. The dummy trench portion 30 shown in FIG. 4 is formed through the accumulation region 16 . That is, the lower end of the dummy trench portion 30 shown in FIG. 4 is arranged below the lower end of the accumulation region 16 .

On the other hand, the dummy trench portion 30 of this example does not penetrate the accumulation region 16 . The lower end of the dummy trench portion 30 is arranged above the lower end of the accumulation region 16 . In this example, the lower end of the dummy trench portion 30 is arranged within the accumulation region 16 . By arranging the lower end of the dummy trench portion 30 in the high-concentration N+ type accumulation region 16 , it is possible to further suppress the formation of the P-type inversion region near the lower end of the dummy trench portion 30 .

In still another example, the length of the dummy trench portion 30 in the depth direction may be shorter than that of the gate trench portion 40 while the dummy trench portion 30 penetrates the accumulation region 16 . That is, the distance between the lower end of the dummy trench portion 30 and the accumulation region 16 is shorter than the distance between the lower end of the gate trench portion 40 and the accumulation region 16 . Such a structure can also suppress the formation of a P-type inversion region in the vicinity of the lower end of the dummy trench portion 30 .

FIG. 6 is a diagram showing another example of the aa cross section in FIG. In the semiconductor device 100 of this example, the length of the dummy trench portion 30 in the depth direction is different from the examples shown in FIGS. Other structures may be the same as any of the examples shown in FIGS.

The dummy trench portion 30 of this example is formed to penetrate the emitter region 12 , the base region 14 and the accumulation region 16 and reach a position shallower than the gate trench portion 40 . The gate trench portion 40 is formed through the emitter region 12 , the base region 14 and the accumulation region 16 to a position deeper than the dummy trench portion 30 .

The structure inside the trench of the dummy trench portion 30 may be the same as the example in any one of FIGS. 2 to 5, or may have another structure. The dummy trench portion 30 shown in FIG. 6 has a dummy insulating film 32 and a dummy conductive portion 34 . The film thickness of the dummy insulating film 32 may be the same as that of the gate insulating film 42, or may be different as shown in FIG.

By forming the dummy trench portion 30 shallow, the bottom portion of the dummy trench portion 30 can be brought closer to the accumulation region 16 . Thereby, formation of a P-type inversion region in the vicinity of the bottom of the dummy trench portion 30 can be suppressed.

The distance in the depth direction between the lower end of the base region 14 and the lower end of the dummy trench portion 30 is L1, and the distance in the depth direction between the lower end of the base region 14 and the lower end of the gate trench portion 40 is L2. The distance L1 may be 3/4 or less, 2/3 or less, half or less, 1/3 or less, or 1/4 or less of the distance L2. .

The dummy trench portion 30 of this example may have a smaller width in the Y-axis direction than the gate trench portion 40 . Thereby, the shallow dummy trench portion 30 can be easily formed. The polysilicon of the dummy conductive portion 34 and the polysilicon of the gate conductive portion 44 may be formed in the same step or in separate steps. By forming polysilicon in a separate process, the height positions of polysilicon formed in trenches having different depths can be easily aligned. Both the upper end of the dummy conductive portion 34 and the upper end of the gate conductive portion 44 may be arranged at the same level as the upper surface of the semiconductor substrate 10 .

When the dummy conductive portion 34 and the gate conductive portion 44 are formed in separate processes, it is preferable to form one conductive portion and then form the trench for the other trench portion. As a result, it is possible to prevent the resist or the like used for forming one of the conductive portions from remaining in the other trench.

FIG. 7 is a diagram showing an example of doping concentration distribution in the depth direction of the accumulation region 16 shown in FIG. In FIG. 7, the positions in the depth direction of the lower ends 35 of the dummy conductive portions 34 and the lower ends 33 of the dummy trench portions 30 are shown together. The horizontal axis of FIG. 7 indicates the position in the depth direction with reference to the upper surface position of the semiconductor substrate 10, and the vertical axis indicates the doping concentration in logarithm.

The doping concentration profile of the accumulation region 16 has a peak 19 indicating a maximum value. In this example, the peak 19 is arranged between the lower end 33 of the dummy insulating film 32 and the lower end 35 of the dummy conductive portion 34 in the depth direction of the semiconductor substrate 10 . The peak 19 may be arranged in the center between the lower end 33 of the dummy insulating film 32 and the lower end 35 of the dummy conductive portion 34, may be arranged above the center, or may be arranged below the center. may be placed in

As a result, the position where the concentration of the N-type impurity peaks can be located near the bottom of the dummy trench portion 30 . Therefore, formation of a P-type inversion region in the vicinity of the bottom of the dummy trench portion 30 can be suppressed.

In addition, in the depth direction of the semiconductor substrate 10 , the lower end of the accumulation region 16 (that is, the boundary with the drift region 18 ) is arranged between the lower end 35 of the dummy conductive portion 34 and the lower end 33 of the dummy insulating film 32 . you can In this case, the dummy trench portion 30 penetrates the accumulation region 16 . In addition, when each member in each embodiment has a downwardly convex shape, the lower end of each member refers to the tip of the convex shape.

FIG. 8 is a diagram showing another example of the aa cross section in FIG. In the semiconductor device 100 of this example, the film thickness distribution of the dummy insulating film 32 in the dummy trench portion 30 is different from the examples shown in FIGS. Other structures may be the same as any of the examples shown in FIGS. In this example, the dummy insulating film 32 on the bottom of the dummy trench portion 30 is thicker than the dummy insulating film 32 on the side wall of the dummy trench portion 30 .

FIG. 9 is an enlarged sectional view of the vicinity of the gate trench portion 40 and the dummy trench portion 30 shown in FIG. In this example, the gate insulating film 42 has a uniform film thickness T3. On the other hand, the dummy insulating film 32 has a film thickness T5 larger at the bottom than a film thickness T4 at the sidewall. The film thickness T5 may be twice or more the film thickness T4, or may be three times or more. The film thickness T4 may be the same as the film thickness T3.

The bottom portion of the dummy trench portion 30 may have a curved shape that is convex downward. In this case, the film thickness T5 at the bottom of the dummy insulating film 32 may be the film thickness at the lowermost end of the convex shape. Also, the film thickness T4 on the side wall of the dummy insulating film 32 may be the average film thickness in the range facing the base region 14 .

By increasing the film thickness of the dummy insulating film 32 at the bottom portion of the dummy trench portion 30 in this way, it is possible to suppress the collection of holes in the vicinity of the bottom portion of the dummy trench portion 30 . Therefore, formation of a P-type inversion region in the vicinity of the bottom of the dummy trench portion 30 can be suppressed.

As described above, the film thickness distribution of the dummy insulating film 32 shown in FIG. 9 and the shallowly formed dummy trench portion 30 shown in FIG. 6 may be combined. Thereby, it is possible to further suppress the formation of the P-type inversion region. Further, the structure of the doping concentration distribution shown in FIG. 7 may be further combined. As shown in FIG. 9, by increasing the film thickness of the dummy insulating film 32 at the bottom of the dummy trench portion 30, the peak 19 of the doping concentration of the accumulation region 16 is aligned with the lower end 35 of the dummy conductive portion 34 and the dummy insulating film 32. Arrangement between the lower end 33 of the membrane 32 is facilitated.

The lower end of the dummy insulating film 32 at the bottom of the dummy trench portion 30 in this example is arranged below the lower end 17 of the accumulation region 16 . Also, the lower end 35 of the dummy conductive portion 34 is arranged below the upper end of the accumulation region 16 . A lower end 35 of the dummy conductive portion 34 may be arranged between the upper end and the lower end of the accumulation region 16 . In another example, the lower end 35 of the dummy conductive portion 34 may be arranged between the upper and lower ends of the base region 14 and may be arranged below the lower end 17 of the accumulation region 16 .

FIG. 10 is a diagram showing another example of the aa cross section in FIG. The semiconductor device 100 in this example differs from the examples shown in FIGS. 2 to 9 in the structure of the accumulation region 16 . Other structures may be the same as any of the examples shown in FIGS.

In this example, in the accumulation region 16 , a region adjacent to the dummy trench portion 30 is defined as a dummy adjacent region 74 , and a region adjacent to the gate trench portion 40 is defined as a gate adjacent region 72 . Assuming that the width of the accumulation region 16 in the Y-axis direction is W, the gate adjacent region 72 and the dummy adjacent region 74 may refer to regions having a width of about W/4 from the position in contact with the corresponding trench portion. .

In this example, the integrated concentration obtained by integrating the doping concentration in the dummy adjacent region 74 in the depth direction of the semiconductor substrate 10 is higher than the integrated concentration obtained by integrating the doping concentration in the depth direction in the gate adjacent region 72 . The integrated concentration in the dummy adjacent region 74 may be 1.5 times or more the integrated concentration in the gate adjacent region 72, or may be 2 times or more.

In the example shown in FIG. 10, the dummy adjacent region 74 is formed to a position deeper than the gate adjacent region 72 . That is, the dummy adjacent region 74 is longer than the gate adjacent region 72 in the depth direction. The length of the dummy adjacent region 74 in the depth direction may be 1.5 times or more, or may be twice or more than the length of the gate adjacent region 72 in the depth direction. The length of the dummy adjacent region 74 in the depth direction may be the length of the portion in contact with the dummy trench portion 30 . The length of the gate adjacent region 72 in the depth direction may be the length of the portion in contact with the gate trench portion 40 . Thereby, the integrated concentration of the dummy adjacent region 74 can be made higher than the integrated concentration of the gate adjacent region 72 .

By increasing the integrated concentration in the accumulation region 16 adjacent to the dummy trench portion 30 , it is possible to suppress the collection of holes in the vicinity of the bottom portion of the dummy trench portion 30 . This can suppress the formation of a P-type inversion region.

In FIG. 10, the depth positions of the lower surfaces of the gate adjacent regions 72 and the dummy adjacent regions 74 are schematically shown in steps, but the lower surfaces of the gate adjacent regions 72 and the dummy adjacent regions 74 are curved. may be Further, the accumulation region 16 sandwiched between the dummy trench portions 30 may be formed to have the same depth as the dummy adjacent region 74 as a whole.

FIG. 11 is a diagram showing an example of doping concentration distribution in gate adjacent region 72 and dummy adjacent region 74 shown in FIG. The horizontal axis of FIG. 11 indicates the position in the depth direction with reference to the upper surface position of the semiconductor substrate 10, and the vertical axis indicates the doping concentration in logarithm. Note that FIG. 11 shows the doping concentration distribution of the portions in contact with the respective trench portions.

In this example, the dummy adjacent region 74 is formed to a deeper position than the gate adjacent region 72 . The dummy adjacent region 74 in this example has more peaks than the gate adjacent region 72 in the doping concentration distribution. In the example of FIG. 11, the gate adjacent region 72 has one peak 76, and the dummy adjacent region 74 has a first peak 77 and a second peak 78 located deeper than the first peak 77. and

Each peak can be formed by implanting impurities such as protons at a plurality of depth positions with different ranges. The depth position of the peak 76 in the gate adjacent region 72 and the first peak 77 in the dummy adjacent region 74 may be the same. The doping concentration D1 of the peak 76 and the doping concentration D2 of the first peak 77 may also be the same.

The doping concentration D3 of the second peak 78 may be greater than both the doping concentration D1 of the peak 76 and the doping concentration D2 of the first peak 77 . By increasing the doping concentration of the second peak 78 located closer to the bottom of the dummy trench portion 30, the formation of the P-type inversion region near the bottom of the dummy trench portion 30 can be efficiently suppressed. . The doping concentration D3 may be 1.5 times or more the doping concentration D2, or may be 2 times or more.

FIG. 12 is a diagram showing another example of doping concentration distribution in the gate adjacent region 72 and the dummy adjacent region 74. In FIG. In this example, the dummy adjacent region 74 and the gate adjacent region 72 have the same length in the depth direction. The dummy adjacent region 74 in this example has the same number of peaks in the doping concentration profile as the gate adjacent region 72 . In the example of FIG. 12, gate adjacent region 72 and dummy adjacent region 74 each have one peak.

However, the peak doping concentration in dummy adjacent region 74 is higher than the peak doping concentration in gate adjacent region 72 . Such a structure can also increase the integrated concentration in the dummy adjacent region 74 and suppress the formation of the P-type inversion region near the bottom of the dummy trench portion 30 .

The peak doping concentration in the dummy adjacent region 74 may be 1.5 times or more, or 2 times or more, the peak doping concentration in the gate adjacent region 72 . The peak in the dummy adjacent region 74 and the peak in the gate adjacent region 72 may be arranged at the same depth position.

FIG. 13 is a diagram showing a structural example of the accumulation region 16 sandwiched between the dummy trench portions 30. As shown in FIG. The accumulation region 16 has two dummy adjacent regions 74 adjacent to each dummy trench portion 30 and a central region 79 sandwiched between the two dummy adjacent regions 74 . The central region 79 is arranged centrally between the two dummy trench portions 30 in the Y-axis direction.

In this example, the integrated concentration obtained by integrating the doping concentration in the depth direction in the central region 79 is lower than the integrated concentration in the dummy adjacent region 74 . As the integrated concentration in the central region 79, the integrated concentration at the center between the two dummy trench portions 30 in the Y-axis direction may be used. As the integrated concentration in the dummy adjacent region 74, the integrated concentration in the portion in contact with the dummy trench portion 30 may be used. With such a structure, holes can be extracted to the emitter side through the central region 79 at the time of turn-off or the like.

The integrated density in the central region 79 may be 1.5 times or more the integrated density in the dummy adjacent region 74, or may be 2 times or more. In the example of FIG. 13, the length of the central region 79 in the depth direction is shorter than the length of the dummy adjacent region 74 in the depth direction. The length of the central region 79 may be two-thirds or less of the length of the dummy adjacent region 74, or may be half or less. Also, the peak doping concentration in the central region 79 may be lower than the peak doping concentration in the dummy adjacent region 74 . The central region 79 may have the same doping concentration distribution in the depth direction as the gate adjacent region 72 .

FIG. 14 is a diagram partially showing another example of the top surface of the semiconductor device 100. As shown in FIG. The semiconductor device 100 of the present example has a transistor section 70 including transistors such as IGBTs and a diode section 80 including diodes such as FWD (Free Wheel Diode) provided on the semiconductor substrate 10 . A boundary portion 90 is provided between the transistor portion 70 and the diode portion 80 on the upper surface of the semiconductor substrate 10 . The structure of the transistor section 70 may be the same as that of any one of the semiconductor devices 100 described with reference to FIGS.

One or more dummy trench portions 30 are arranged along the Y-axis direction in each of the diode portion 80 and the boundary portion 90 . The dummy trench portions 30 in the diode portion 80 and the boundary portion 90 may have the same shape and structure as the dummy trench portions 30 in the transistor portion 70 .

A base region 14 is formed in the mesa portion of the diode portion 80 and the boundary portion 90 . A contact region 15 is selectively formed in a part of the base region 14 in the mesa portion of the boundary portion 90 . The contact region 15 of the boundary portion 90 is an example of a high concentration region of the second conductivity type. In the boundary portion 90 , the contact region 15 may be formed in a region facing the emitter region 12 and the contact region 15 of the adjacent transistor portion 70 with the dummy trench portion 30 interposed therebetween. Contact region 15 at boundary portion 90 is electrically connected to emitter electrode 52 through contact hole 54 .

Although emitter region 12 and contact region 15 are not formed in the mesa portion of diode portion 80 in the example of FIG. 14, at least one of emitter region 12 and contact region 15 may be formed in the mesa portion. The base region 14 of the diode section 80 is connected to the emitter electrode 52 through the contact hole 54 .

Contact hole 54 is formed above contact region 15 and base region 14 in diode portion 80 and boundary portion 90 . In this example, the contact holes 54 of the transistor portion 70, the diode portion 80 and the boundary portion 90 have the same length in the longitudinal direction of each trench portion.

The diode portion 80 is a region that overlaps the cathode region 82 in the direction perpendicular to the bottom surface of the semiconductor substrate 10 . Further, the transistor portion 70 is a region in which predetermined unit configurations including the emitter region 12 and the contact region 15 are regularly arranged in the region overlapping the collector region 22 in the direction perpendicular to the lower surface of the semiconductor substrate 10 . In addition, the boundary portion 90 is defined as a region where predetermined unit structures including the emitter region 12 and the contact region 15 are not regularly arranged in the region overlapping the collector region 22 in the direction perpendicular to the lower surface of the semiconductor substrate 10 . .

FIG. 15 is a diagram showing an example of a bb cross section of the semiconductor device 100 shown in FIG. The bb cross section is a cross section parallel to the YZ plane and passing through the emitter region 12 of the transistor section 70 , the contact region 15 of the boundary section 90 and the base region 14 of the diode section 80 . The structure of the transistor section 70 may be the same as that of any one of the semiconductor devices 100 described with reference to FIGS. The transistor section 70 shown in FIG. 15 has the same structure as the semiconductor device 100 shown in FIG.

A region sandwiched between the trench portions is called a mesa portion 94 . In FIG. 15, only the mesa portion 94 of the boundary portion 90 is denoted by reference numerals.

In this example, the transistor portion 70 refers to a region in which the emitter region 12 is provided in the mesa portion 94 on the upper surface side of the semiconductor substrate 10 and the collector region 22 is provided on the lower surface side of the semiconductor substrate 10 . The boundary portion 90 refers to a region in which the emitter region 12 is not provided in the mesa portion 94 on the upper surface side of the semiconductor substrate 10 and the collector region 22 is provided on the lower surface side of the semiconductor substrate 10 . In the mesa portion 94 of the boundary portion 90 of this example, the contact region 15 and the base region 14 are provided in order from the upper surface side of the semiconductor substrate 10 .

The diode portion 80 refers to a region provided with a cathode region 82 of the first conductivity type on the lower surface side of the semiconductor substrate 10 . Cathode region 82 in this example is of the N+ type. In the example shown in FIG. 15, the base region 14 is formed in the mesa portion 94 of the diode portion 80, and the emitter region 12 is not formed. The cathode region 82 in the diode section 80 of this example is formed at the same depth position as the collector region 22 . A buffer region 20 may be formed above the cathode region 82 .

Since the transistor section 70 and the diode section 80 have different layer structures including pn junctions, the electric field distribution tends to become unbalanced. Therefore, if carriers are accumulated near the boundary between the transistor section 70 and the diode section 80, the avalanche resistance of the semiconductor device 100 is lowered. By providing the boundary portion 90 in the semiconductor device 100 , carriers (for example, holes) can be easily extracted to the emitter electrode 52 between the transistor portion 70 and the diode portion 80 . Therefore, the avalanche resistance of the semiconductor device 100 can be improved. Further, since the distance between the transistor portion 70 and the cathode region 82 can be increased, carrier injection from the transistor portion 70 to the diode portion 80 can be suppressed when the semiconductor device 100 is turned on or turned off.

The accumulation region 16 may not be formed in at least a part of the mesa portion 94 of the boundary portion 90 . That is, the accumulation region 16 may be selectively formed below the base region 14 in the mesa portion 94 of the boundary portion 90, or the accumulation region 16 may not be formed at all. When the accumulation region 16 is selectively formed, it is preferable that the accumulation region 16 be formed adjacent to the dummy trench portion 30 closer to the transistor portion 70 among the dummy trench portions 30 sandwiching the mesa portion 94 . . As a result, formation of a p-type inversion region at the bottom of the dummy trench portion 30 near the transistor portion 70 can be suppressed, and the effect on the operation of the transistor portion 70 can be reduced.

FIG. 16A is a diagram showing an example of the mesa portion 94 of the boundary portion 90. FIG. In this example, of the dummy trench portions 30 sandwiching the mesa portion 94, the one closer to the transistor portion 70 is referred to as a dummy trench portion 30-1, and the one closer to the diode portion 80 is referred to as a dummy trench portion 30-2. In the mesa portion 94 of this example, the accumulation region 16 is formed in the region adjacent to the dummy trench portion 30-1, and the accumulation region 16 is not formed in the region adjacent to the dummy trench portion 30-2.

With such a structure, holes can be easily extracted through the mesa portion 94 while suppressing formation of a hole inversion region at the bottom of the dummy trench portion 30-1. Further, since the accumulation region 16 is not provided in the region adjacent to the dummy trench portion 30-2, even if the semiconductor device 100 is miniaturized and the width of the mesa portion 94 is reduced, the region in which the accumulation region 16 is not provided can be easily removed. can be secured to The width of the accumulation region 16 in the Y-axis direction at the mesa portion 94 of the boundary portion 90 may be half or less of the width of the mesa portion 94, or may be one-third or less.

FIG. 16B is a diagram showing another example of the mesa portion 94 of the boundary portion 90. As shown in FIG. The accumulation region 16 in the mesa portion 94 of this example has the same shape as the accumulation region 16 shown in FIG. In the mesa portion 94 of the boundary portion 90 of this example, the accumulation region 16 is formed covering the entire lower surface of the base region 14 . However, the accumulation region 16 has dummy adjacent regions 74 for each of the dummy trench portions 30-1 and 30-2. Moreover, it has a central region 79 in the central region of the mesa portion 94 in the Y-axis direction.

Dummy adjacent region 74 and central region 79 are the same as dummy adjacent region 74 and central region 79 shown in FIG. That is, the integrated density in the dummy adjacent region 74 is higher than the integrated density in the central region 79 . The dummy adjacent region 74 in the example of FIG. 16B is formed below the central region 79 . The accumulation region 16 may have two dummy adjacent regions 74 and no central region 79 . In this case, at least one of base region 14 and drift region 18 is formed in the region where central region 79 is provided in FIG. 16B.

With such a structure, it is possible to suppress the formation of an inversion region even in the dummy trench portion 30 of the boundary portion 90 . Further, by reducing the integral concentration of impurities in the vicinity of the center of the mesa portion 94, the extraction of carriers in the boundary portion 90 becomes easier.

16C is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. The accumulation region 16 in the mesa portion 94 of this example has the dummy adjacent region 74 adjacent to the dummy trench portion 30-1, and does not have the dummy adjacent region 74 in the region adjacent to the dummy trench portion 30-2. . A central region 79 extends to a region adjacent to the dummy trench portion 30-2. With such a structure, holes can be easily extracted through the mesa portion 94 while suppressing the formation of an inversion region at the bottom of the dummy trench portion 30-1.

16D is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. In this example, the accumulation region 16 is not provided in the mesa portion 94 of the boundary portion 90 . With such a structure, holes can be easily extracted at the boundary portion 90 .

FIG. 17 is a diagram showing another example of the bb cross section of the semiconductor device 100. As shown in FIG. The boundary 90 in this example has a plurality of mesas 94 . Each mesa 94 may have any of the structures described in FIGS. 16A-16D. One of the mesa portions 94 may have a smaller width in the Y-axis direction of the provided accumulation region 16 than the mesa portion 94 closer to the transistor portion 70 . As an example, the width of the accumulation region 16 of the mesa portion 94-3 adjacent to the diode portion 80 (zero in the example of FIG. 17) is smaller than the width of the accumulation region 16 of the mesa portion 94-1 adjacent to the transistor portion .

With such a structure, formation of an inversion region at the bottom of the dummy trench portion 30 in the mesa portion 94 in the vicinity of the transistor portion 70 can be suppressed. Further, carriers can be efficiently extracted from the mesa portion 94 away from the transistor portion 70 .

15 to 17, the doping concentration of the accumulation region 16 in the boundary portion 90 may be higher than the doping concentration of the accumulation region 16 in the center of the transistor portion 70 in the Y-axis direction. The doping concentration of accumulation region 16 may be a peak concentration. This reduces carrier accumulation in the region of the transistor portion 70 away from the boundary portion 90 , thereby facilitating extraction of carriers through the boundary portion 90 .

FIG. 18 is a diagram showing another example of the bb cross section of the semiconductor device 100. As shown in FIG. The transistor section 70 of this example has the same structure as the semiconductor device 100 shown in FIG. That is, the dummy trench portion 30 in the transistor portion 70 is formed shallower than the gate trench portion 40 .

In this example, at least a portion of dummy trench portion 30 in boundary portion 90 and diode portion 80 is also formed shallower than gate trench portion 40 . In the example of FIG. 18 , all the dummy trench portions 30 in the boundary portion 90 and the diode portion 80 are formed shallower than the gate trench portion 40 . The dummy trench portions 30 in the boundary portion 90 and the diode portion 80 may be formed to the same depth as the dummy trench portions 30 in the transistor portion 70 .

FIG. 19A is a diagram showing an example of the mesa portion 94 of the boundary portion 90. FIG. The dummy trench portion 30-1 and the dummy trench portion 30-2 of this example are formed shallower than the gate trench portion 40. As shown in FIG. In the mesa portion 94 of this example, the accumulation region 16 is formed so as to cover the entire bottom surface of the base region 14 . Such a structure can suppress the formation of reversed regions at the bottoms of the dummy trench portions 30-1 and 30-2.

FIG. 19B is a diagram showing another example of the mesa portion 94 of the boundary portion 90. As shown in FIG. The boundary portion 90 of this example is the same as the boundary portion 90 shown in FIG. 19A except that the dummy trench portion 30-2 is formed deeper than the dummy trench portion 30-1. The dummy trench portion 30 - 2 may be formed to the same depth as the gate trench portion 40 . It should be noted that the deeper each trench is formed, the larger the width in the Y-axis direction. Such a structure can also suppress the formation of reversed regions at the bottoms of the dummy trench portions 30-1 and 30-2.

19C is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. The boundary 90 of this example is the same as the boundary 90 shown in FIG. 19A except that the accumulation region 16 is selectively formed. The accumulation region 16 of this example is formed in a region adjacent to the dummy trench portion 30-1 and is not formed in a region adjacent to the dummy trench portion 30-2. With such a structure, formation of an inversion region at the bottom of the dummy trench portion 30 - 1 can be suppressed, and carriers can be easily extracted at the boundary portion 90 .

19D is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. The boundary portion 90 of this example is the same as the boundary portion 90 shown in FIG. 19C except that the accumulation region 16 is also formed in the region adjacent to the dummy trench portion 30-2. The accumulation region 16 is not formed in the region near the center of the mesa portion 94 in the Y-axis direction. With such a structure, formation of an inversion region at the bottom of each dummy trench portion 30 can be suppressed, and carriers can be easily extracted at the boundary portion 90 .

19E is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. The boundary portion 90 of this example is the same as the boundary portion 90 shown in FIG. 19C except that the dummy trench portion 30-2 is formed deeper than the dummy trench portion 30-1. With such a structure as well, formation of an inversion region at the bottom of the dummy trench portion 30 - 1 can be suppressed, and carriers can be easily extracted at the boundary portion 90 .

19F is a diagram showing another example of the mesa portion 94 of the boundary portion 90. FIG. The boundary portion 90 of this example is the same as the boundary portion 90 shown in FIG. 19D except that the dummy trench portion 30-2 is formed deeper than the dummy trench portion 30-1. With such a structure as well, it is possible to suppress the formation of an inversion region at the bottom of each dummy trench portion 30 and to easily extract carriers at the boundary portion 90 . Note that the mesa portion 94 of the boundary portion 90 may have the same structure as any of the examples shown in FIGS. 16A to 16D. Also, each example shown in FIGS. 19A to 19F may be applied to the semiconductor device 100 shown in FIG.

FIG. 20 is a diagram showing another example of the bb cross section of the semiconductor device 100. As shown in FIG. In the semiconductor device 100 of this example, the dummy trench portion 30 provided in the diode portion 80 has a larger width in the Y-axis direction than the dummy trench portion 30 provided in the transistor portion 70 . Other structures are the same as any of the semiconductor devices 100 described with reference to FIGS. 14 to 19F. The pitch at which the respective trench portions are arranged is uniform.

With such a structure, the width of the mesa portion 94 in the diode portion 80 is reduced. Therefore, carrier injection into the mesa portion 94 can be suppressed. The dummy trench portion 30 in the diode portion 80 may have the same width as the gate trench portion 40 . Note that even if the dummy trench portion 30 in the diode portion 80 is formed deep and a hole inversion region is likely to be formed at the bottom, the operation of the semiconductor device 100 is affected because the dummy trench portion 30 is distant from the transistor portion 70 . is small.

FIG. 21A is a diagram showing an example of a trench portion. The dummy trench portion 30 of this example includes a trench thin film portion 37 and a trench thick film portion 38 . Two storage regions 16-1 and 16-2 are formed below the base region 14. As shown in FIG. The accumulation region 16-1 is an example of a first accumulation region provided below the base region 14, and the accumulation region 16-2 is a first accumulation region provided between the accumulation region 16-1 and the drift region . 2 is an example of an accumulation area.

The trench thin film portion 37 has a dummy insulating film 32 having a predetermined thickness on the inner wall of the trench portion. Further, the trench thin film portion 37 has a dummy conductive portion 34 covered with the dummy insulating film 32 in the dummy trench portion 30 . The bottom end of the trench thin film portion 37 is formed deeper than the bottom end of the base region 14 . The lower end of the trench thin film portion 37 in this example is located at the same depth as at least part of the region in which the accumulation region 16-1 is formed. In the trench thin film portion 37, the dummy conductive portion 34 has a uniform width in the Y-axis direction. That is, the lower end of the trench thin film portion 37 corresponds to the lower end of the dummy conductive portion 34 .

The trench thick film portion 38 has a dummy insulating film 32 having a film thickness thicker than that of the trench thin film portion 37 on the inner wall of the trench portion. The dummy conductive portion 34 is provided in the trench thin film portion 37 but is not provided in the trench thick film portion 38 . The trench thick film portion 38 is formed at a position deeper than the base region 14 . By providing the trench thick film portion 38, the capacitance between the dummy conductive portion 34 and the drift region 18 can be reduced, and the number of holes collected near the bottom portion of the dummy trench portion 30 can be reduced. Thereby, formation of a P-type inversion region in the vicinity of the bottom portion of the dummy trench portion 30 can be suppressed. Therefore, turn-on loss is reduced.

In this example, since a plurality of accumulation regions 16 are formed in the mesa portion 94 between the dummy trench portions 30, extraction of carriers via the P-type inversion region at the bottom portion of the dummy trench portion 30 can be suppressed during turn-on. . Also, the increase in turn-on loss can be reduced while maintaining the reduction in Von voltage due to miniaturization.

FIG. 21B is a diagram showing another example of the trench portion. This example is different from the case of FIG. 21A in that dummy conductive portions 34 are provided in both trench thin film portion 37 and trench thick film portion 38 .

The trench thin film portion 37 and the trench thick film portion 38 of the dummy conductive portion 34 have different widths in the Y-axis direction. In the trench thin film portion 37 , the dummy conductive portion 34 of this example has a larger width in the Y-axis direction than the trench thick film portion 38 . As a result, the dummy insulating film 32 of the trench thin film portion 37 becomes thinner than the dummy insulating film 32 of the trench thick film portion 38 . The trench thick film portion 38 is formed at a position deeper than the base region 14 . Also, the lower end of the dummy conductive portion 34 is formed deeper than the lower end of the accumulation region 16-2. Therefore, the effect of suppressing the formation of the P-type inversion region in the vicinity of the bottom of the dummy trench portion 30 and reducing the turn-on loss is high.

FIG. 21C is a diagram showing another example of the trench portion. In the dummy trench portion 30 of this example, the trench thin film portion 37 and the trench thick film portion 38 have different widths in the Y-axis direction. Dummy conductive portion 34 is provided in both trench thin film portion 37 and trench thick film portion 38 .

The dummy trench portion 30 has a width in the Y-axis direction smaller than that of the trench thick film portion 38 in the trench thin film portion 37 . On the other hand, the dummy conductive portion 34 has a uniform width in the Y-axis direction in the trench thin film portion 37 and the trench thick film portion 38 . That is, the dummy insulating film 32 of the trench thick film portion 38 is thicker than the dummy insulating film 32 of the trench thin film portion 37 . This suppresses the formation of a P-type inversion region in the vicinity of the bottom of the dummy trench portion 30, thereby reducing the turn-on loss. Note that the trench thick film portion 38 is formed at a position deeper than the base region 14 .

FIG. 21D is a diagram showing another example of the trench portion. This example differs from the case of FIG. 21C in that the mesa portion 94 sandwiched between the dummy trench portions 30 has three accumulation regions 16-1, 16-2 and 16-3. The accumulation area 16-3 is an example of a third accumulation area provided between the accumulation areas 16-1 and 16-2.

Note that the dummy trench portion 30 has been described with reference to FIGS. 21A to 21D. However, the gate trench portion 40 may similarly comprise the structure of the dummy trench portion 30 disclosed in FIGS. 21A-21D.

21A to 21D, the mesa portion 94 sandwiched between adjacent dummy trench portions 30 has been described. However, the mesa portion 94 sandwiched between the dummy trench portion 30 and the gate trench portion 40 may similarly have the structure of the mesa portion 94 disclosed in FIGS. 21A-21D. The same applies to the mesa portion 94 sandwiched between adjacent gate trench portions 40 .

FIG. 22 is a top view showing an example of a semiconductor device 200 according to an embodiment of the invention. The semiconductor device 200 may include the gate trench portion 40 and the dummy trench portion 30 arranged in the same manner as the semiconductor device 100 .

In semiconductor device 200 , base region 14 arranged in at least part of mesa portion 94 sandwiched between gate trench portion 40 and dummy trench portion 30 is not directly connected to emitter electrode 52 . . In the example of FIG. 22, the base region 14 in a part of the mesa portion 94-2 of the mesa portion 94 sandwiched between the gate trench portion 40 and the dummy trench portion 30 is connected to the emitter electrode 52 on the upper surface of the semiconductor substrate 10. not. In this example, no contact hole 54 is arranged in the interlayer insulating film 26 between the emitter electrode 52 and the base region 14 in the mesa portion 94-2. As an example, the mesa portion 94-2 is the mesa portion 94 arranged on both sides in the Y-axis direction with respect to one of the mesa portions 94-1 sandwiched between the two dummy trench portions 30. FIG.

The emitter region 12 may not be formed in the mesa portion 94-2. In the mesa portion 94-2 of this example, the base region 14 is provided in the entire region inside the well region 11 on the upper surface of the semiconductor substrate 10. As shown in FIG.

Contact holes 54 are arranged in the mesa portion 94-1 and the mesa portion 94-3. The structure of the mesa portion 94-1 and the mesa portion 94-3 on the upper surface of the semiconductor substrate 10 may be the same as or different from that of the semiconductor device 100 shown in FIGS. 1 to 21D. In this example, the mesa portion 94-1 and the mesa portion 94-3 are arranged on the upper surface of the semiconductor substrate 10 so that the emitter region 12 extends in the X-axis direction between the contact hole 54 and each trench portion. there is The contact region 15 is arranged to extend in the X-axis direction below the contact hole 54, but is omitted in FIG.

Of the mesa portions 94 sandwiched between the gate trench portion 40 and the dummy trench portion 30, the base regions 14 arranged in some of the mesa portions 94-2 are not brought into direct contact with the emitter electrode 52, so that the mesa portion 94- The extraction of holes in 2 can be suppressed, and carrier accumulation can be promoted. Therefore, the ON voltage of the semiconductor device 200 can be reduced.

Moreover, it is preferable that two or less dummy trench portions 30 are arranged between the two gate trench portions 40 . In addition, among the respective trench portions, each extended portion linearly extending in the X-axis direction on the upper surface of the semiconductor substrate 10 is defined as one trench portion. In the example of FIG. 22 , two dummy trench portions 30 are arranged between two gate trench portions 40 .

In this example, the gate trench portion 40 is directly connected to the gate electrode 46 through the contact hole 55 . Also, the dummy trench portion 30 is directly connected to the emitter electrode 52 through the contact hole 56 . In other words, the semiconductor device 200 of this example does not include the connecting portion 57 and the gate wiring 45 . Such a structure eliminates a step due to the connecting portion 57 and the like, and facilitates miniaturization of the semiconductor device 200 .

FIG. 23 is a diagram showing an example of a cc cross section of the semiconductor device 200. As shown in FIG. The dummy trench portion 30 and the gate trench portion 40 in this example have the same structure as the gate trench portion 40 shown in FIG. Alternatively, the dummy trench portion 30 may have the same structure as any of the dummy trench portions 30 shown in FIGS. 1-21D. Also, each doping region in mesa portion 94-1 and mesa portion 94-3 may have the same structure as each doping region in mesa portion 94 shown in FIGS.

The mesa portion 94-1 and the mesa portion 94-3 of this example have the contact region 15 below the contact hole 54. FIG. Emitter regions 12 are provided on both sides of the contact region 15 .

Contact region 15 and emitter region 12 are electrically connected to emitter electrode 52 . The mesa portion 94-1 and the mesa portion 94-3 of this example have a connection portion 96 provided from the upper surface of the semiconductor substrate 10 to the inside. Connection portion 96 is in contact with each of contact region 15 , emitter region 12 and emitter electrode 52 . The connection portion 96 has a lower electrical resistance than the contact region 15 . As an example, the connection portion 96 is made of metal such as tungsten. The emitter region 12 is in contact with the side surface of the connecting portion 96, and the contact region 15 is in contact with the bottom surface. Such a structure facilitates electrical connection between the emitter electrode 52 and the contact region 15 and the emitter region 12 even if the semiconductor device 200 is miniaturized.

Also, the connection portion 96 may be provided in the dummy conductive portion 34 of the dummy trench portion 30 . The connecting portion 96 is provided below the contact hole 56 . The connecting portion 96 connects with the emitter electrode 52 through the contact hole 56 .

FIG. 24 is a diagram showing another example of the cc cross section of the semiconductor device 200. As shown in FIG. In this example, the dummy trench portion 30 has the same structure as the dummy trench portion 30 shown in FIG. Other structures are the same as those of the semiconductor device 200 shown in FIG.

The semiconductor device 200 may have dummy trench portions 30 as shown in FIGS. 1 to 21D. That is, the structure shown in FIGS. 22 to 24 in which the base region 14 is not connected to the emitter electrode 52 in any mesa portion 94 may be applied to each of the semiconductor devices 100 shown in FIGS. 1 to 21D.

FIG. 25 is a top view showing an example of a semiconductor device 300 according to an embodiment of the invention. The semiconductor device 300 of this example differs from each of the semiconductor devices shown in FIGS. Other structures may be similar to any of the semiconductor devices shown in FIGS.

In the semiconductor device 300 , one or less dummy trench portions 30 are arranged between each gate trench portion 40 . The dummy trench portion 30 of this example extends linearly in the X-axis direction on the upper surface of the semiconductor substrate 10 . In this example, one linear dummy trench portion 30 is arranged between two extending portions 41 connected by a tip portion 43 in the gate trench portion 40 .

By sandwiching the respective dummy trench portions 30 between the gate trench portions 40, it is possible to promote the disappearance of the depletion layer in the vicinity of the dummy trench portions 30 at the time of turn-on. Therefore, the conductivity can be efficiently modulated at the time of turn-on, and the turn-on loss can be reduced.

FIG. 26 is a diagram showing an example of a dd cross section of the semiconductor device 300. As shown in FIG. The dummy trench portion 30 and the gate trench portion 40 in this example have the same structure as the gate trench portion 40 shown in FIG. Alternatively, the dummy trench portion 30 may have the same structure as any of the dummy trench portions 30 shown in FIGS. 1-21D. Also, each doping region in the mesa portion 94 may have the same structure as each doping region in the mesa portion 94 shown in FIGS.

FIG. 27 is a diagram showing another example of the dd cross section of the semiconductor device 300. As shown in FIG. In this example, the dummy trench portion 30 has the same structure as the dummy trench portion 30 shown in FIG. Other structures are the same as those of the semiconductor device 200 shown in FIG. The structure in which one or less dummy trench portions 30 are provided between each gate trench portion 40 shown in FIGS. 25 to 27 may be applied to each of the semiconductor devices shown in FIGS. 1 to 24 .

FIG. 28 is a diagram showing an example of an ee cross section of the semiconductor device 300. As shown in FIG. The ee section is the XZ plane passing through the vicinity of the dummy trench portion 30 . Contact regions 15 and emitter regions 12 are alternately arranged on the upper surface of semiconductor substrate 10 in the range in which contact hole 54 is provided in the X-axis direction. Base region 14 and well region 11 are arranged on the upper surface of semiconductor substrate 10 in a range where contact hole 54 is not provided.

A gate trench portion 40 is arranged so as to be surrounded by the well region 11 . The gate trench portion 40 is connected to a gate electrode 46 via a gate wiring 45 arranged above the upper surface of the semiconductor substrate 10 . An insulating film is formed between gate line 45 and the upper surface of semiconductor substrate 10 .

FIG. 29 is a top view showing an example of a semiconductor device 400 according to an embodiment of the invention. The semiconductor device 400 of this example differs from the semiconductor devices shown in FIGS. 1 to 24 in the shape and arrangement of the dummy trench portion 30 and the gate trench portion 40 on the upper surface of the semiconductor substrate 10 . Other structures may be the same as those of the respective semiconductor devices shown in FIGS.

The semiconductor device 400 includes a first gate trench portion 40-1, a second gate trench portion 40-2 and a dummy trench portion 30. FIG. The semiconductor device 400 includes a plurality of trench sets each including a first gate trench portion 40-1, a second gate trench portion 40-2 and a dummy trench portion 30 along the Y-axis direction on the upper surface of the semiconductor substrate 10. good.

Each of the first gate trench portion 40-1 and the second gate trench portion 40-2 has an extension portion 41-1, an extension portion 41-2 and a tip portion 43. As shown in FIG. The extending portion 41-1 and the extending portion 41-2 are provided on the upper surface of the semiconductor substrate 10 so as to extend in parallel with the X-axis direction. The distal end portion 43 connects the distal ends of the two extending portions 41 .

The dummy trench portion 30 has an extension portion 31-1, an extension portion 31-2 and a tip portion . The extending portion 31-1 and the extending portion 31-2 are provided on the upper surface of the semiconductor substrate 10 so as to extend in parallel with the X-axis direction. The distal end portion 36 connects the distal ends of the two extending portions 31 .

On the upper surface of the semiconductor substrate 10, the dummy trench portion 30 is arranged inside the first gate trench portion 40-1. That is, on the upper surface of the semiconductor substrate 10, the two extending portions 31 of the dummy trench portion 30 are arranged in a region sandwiched between the two extending portions 41 of the first gate trench portion 40-1.

The second gate trench portion 40 - 2 is arranged inside the dummy trench portion 30 on the upper surface of the semiconductor substrate 10 . That is, on the upper surface of the semiconductor substrate 10, the two extending portions 41 of the second gate trench portion 40-2 are arranged in a region sandwiched between the two extending portions 31 of the dummy trench portion 30. As shown in FIG. Moreover, on the upper surface of the semiconductor substrate 10, the tip portion 36 of the dummy trench portion 30 is located between the tip portion 43 of the first gate trench portion 40-1 and the tip portion 43 of the second gate trench portion 40-2. are placed in

With such a structure, while the number of extension portions 31 of the dummy trench portion 30 sandwiched between the two extension portions 41 of the gate trench portion 40 is one, the respective extension portions (31, 41) in the X-axis direction are The tips can be connected at tips (36, 43). Therefore, electric field concentration at the tips of the extensions (31, 41) can be alleviated while promoting conductivity modulation.

Structures other than the gate trench portion 40 and the dummy trench portion 30 may be the same as those of the semiconductor device according to any one of the modes shown in FIGS. The semiconductor device 400 of this example does not have the connecting portion 57 and the gate wiring 45, like the semiconductor device 200 shown in FIG.

Each of the first gate trench portion 40 - 1 , the second gate trench portion 40 - 2 and the dummy trench portion 30 has a portion overlapping the gate electrode 46 on the upper surface of the semiconductor substrate 10 . A contact hole 55 is provided in a portion overlapping with the gate electrode 46 for the first gate trench portion 40-1 and the second gate trench portion 40-2.

Each of the first gate trench portion 40 - 1 , the second gate trench portion 40 - 2 and the dummy trench portion 30 has a portion overlapping the emitter electrode 52 on the upper surface of the semiconductor substrate 10 . A contact hole 56 is provided in a portion of the dummy trench portion 30 overlapping the emitter electrode 52 .

FIG. 30 is a diagram showing an example of the ff section of the semiconductor device 400. As shown in FIG. The dummy trench portion 30 and the gate trench portion 40 in this example have the same structure as the gate trench portion 40 shown in FIG. Alternatively, the dummy trench portion 30 may have the same structure as any of the dummy trench portions 30 shown in FIGS. 1-21D. Also, each doping region in the mesa portion 94 may have the same structure as each doping region in the mesa portion 94 shown in FIGS.

FIG. 31 is a diagram showing another example of the ff cross section of the semiconductor device 400. As shown in FIG. In this example, the dummy trench portion 30 has the same structure as the dummy trench portion 30 shown in FIG. Other structures are the same as those of the semiconductor device 400 shown in FIG. The shape and arrangement of dummy trench portion 30 and gate trench portion 40 shown in FIG. 29 may be applied to each of the semiconductor devices shown in FIGS.

FIG. 32 is a diagram showing an example of a gg section of the semiconductor device 400. As shown in FIG. In the semiconductor device 400, each trench portion is directly connected to each electrode. Therefore, the semiconductor device 400 does not include the connecting portion 57 and the gate wiring 45 .

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the scope of claims that forms with such modifications or improvements can also be included in the technical scope of the present invention.

DESCRIPTION OF SYMBOLS 10... Semiconductor substrate 11... Well area 12... Emitter area 14... Base area 15... Contact area 16... Accumulation area 17... Lower end 18. Drift region 19 Peak 20 Buffer region 22 Collector region 26 Interlayer insulating film 30 Dummy trench portion 31 Extension portion 32. Dummy insulating film 33 Lower end 34 Dummy conductive portion 35 Lower end 36 Tip portion 37 Trench thin film portion 38 Trench thick film portion 40 Gate trench portion 41 Extension portion 42 Gate insulating film 43 Tip portion 44 Gate conductive portion 45 Gate wiring 46 Gate Electrodes 52 Emitter electrode 54, 55, 56 Contact hole 57 Connection portion 58 Collector electrode 70 Transistor portion 72 Gate adjacent region 74 ... dummy adjacent region, 76 ... peak, 77 ... first peak, 78 ... second peak, 79 ... central region, 80 ... diode part, 82 ... cathode Area 90 Boundary 94 Mesa 96 Connection 100, 200, 300, 400 Semiconductor device

Claims (32)

a semiconductor substrate;
a drift region of a first conductivity type formed in the semiconductor substrate;
a base region of a second conductivity type formed between the upper surface of the semiconductor substrate and the drift region in the semiconductor substrate;
an accumulation region of a first conductivity type formed between the drift region and the base region in the semiconductor substrate and having a doping concentration higher than that of the drift region;
a gate trench portion formed in the semiconductor substrate from the upper surface of the semiconductor substrate to the drift region through the base region and the accumulation region; and a gate trench portion formed in the semiconductor substrate from the upper surface of the semiconductor substrate to the base region a dummy trench portion formed by
a suppression structure for suppressing formation of a second conductivity type inversion region in the first conductivity type drift region and the accumulation region adjacent to the dummy trench portion;
with
The dummy trench portion is
a dummy insulating film formed on the inner wall of the trench;
a dummy conductive portion covered with the dummy insulating film;
the suppressing structure includes the dummy trench portion formed shallower than the gate trench portion;
The semiconductor device, wherein a lower end of the accumulation region is arranged between a lower end of the dummy conductive portion and a lower end of the dummy insulating film in a depth direction of the semiconductor substrate. The gate trench portion is
a gate insulating film formed on the inner wall of the trench;
a gate conductive portion covered with the gate insulating film;
The suppression structure is
the dummy insulating film formed on the inner wall of the trench and thicker than the gate insulating film;
2. The semiconductor device according to claim 1 , comprising said dummy trench portion having said dummy conductive portion covered with said dummy insulating film. 3. The semiconductor device according to claim 2, wherein the thickness of said dummy insulating film is at least twice the thickness of said gate insulating film. 4. The semiconductor device according to claim 2, wherein said dummy insulating film in said dummy trench portion has a uniform film thickness. a semiconductor substrate;
a drift region of a first conductivity type formed in the semiconductor substrate;
a base region of a second conductivity type formed between the upper surface of the semiconductor substrate and the drift region in the semiconductor substrate;
an accumulation region of a first conductivity type formed between the drift region and the base region in the semiconductor substrate and having a doping concentration higher than that of the drift region;
a dummy trench portion formed in the semiconductor substrate by penetrating the base region from an upper surface of the semiconductor substrate; and a position deeper than the dummy trench portion in the semiconductor substrate by penetrating the base region and the accumulation region. a gate trench formed up to
a suppression structure for suppressing formation of a second conductivity type inversion region in the first conductivity type drift region and the accumulation region adjacent to the dummy trench portion;
with
The dummy trench portion is
a dummy insulating film formed on the inner wall of the trench;
a dummy conductive portion covered with the dummy insulating film;
A doping concentration distribution in the accumulation region has a peak in the depth direction of the semiconductor substrate,
In the suppression structure, the peak of the doping concentration distribution in the accumulation region is arranged between the lower end of the dummy conductive portion and the lower end of the dummy insulating film in the depth direction of the semiconductor substrate. contains area
semiconductor device. 6. The semiconductor device according to claim 5, wherein a lower end of said accumulation region is arranged between a lower end of said dummy conductive portion and a lower end of said dummy insulating film in the depth direction of said semiconductor substrate. The suppression structure includes the dummy trench portion in which the dummy insulating film is thicker at the bottom than at the sidewall.
7. The semiconductor device according to claim 6. The suppression structure includes the dummy trench portion in which the dummy insulating film is thicker at the bottom than at the sidewall.
A semiconductor device according to claim 1 . 9. The semiconductor device according to claim 8, wherein a lower end of said dummy insulating film in a bottom portion of said dummy trench portion is arranged below said accumulation region. a semiconductor substrate;
a drift region of a first conductivity type formed in the semiconductor substrate;
a base region of a second conductivity type formed between the upper surface of the semiconductor substrate and the drift region in the semiconductor substrate;
an accumulation region of a first conductivity type formed between the drift region and the base region in the semiconductor substrate and having a doping concentration higher than that of the drift region;
a gate trench portion formed in the semiconductor substrate from the upper surface of the semiconductor substrate to the drift region through the base region and the accumulation region; and a gate trench portion formed in the semiconductor substrate from the upper surface of the semiconductor substrate to the base region a dummy trench portion formed shallower than the gate trench portion;
a suppression structure for suppressing formation of a second conductivity type inversion region in the first conductivity type drift region and the accumulation region adjacent to the dummy trench portion;
with
The dummy trench portion is
a dummy insulating film formed on the inner wall of the trench;
a dummy conductive portion covered with the dummy insulating film;
the suppression structure includes the dummy trench portion in which the dummy insulating film is thicker at the bottom than at the sidewall;
A semiconductor device, wherein a lower end of the dummy insulating film at a bottom portion of the dummy trench portion is arranged below the accumulation region. 11. The semiconductor device according to claim 10, wherein the lower end of said dummy conductive portion is arranged below the upper end of said accumulation region. In the suppressing structure, an integral concentration obtained by integrating a doping concentration in a dummy adjacent region adjacent to the dummy trench portion in a depth direction of the semiconductor substrate corresponds to a doping concentration in a gate adjacent region adjacent to the gate trench portion. including the accumulation region formed to be higher than the integral concentration integrated in the depth direction of
A semiconductor device according to claim 1 . 13. The semiconductor device according to claim 12, wherein said dummy adjacent region of said accumulation region is formed to a deeper position than said gate adjacent region. a semiconductor substrate;
a drift region of a first conductivity type formed in the semiconductor substrate;
a base region of a second conductivity type formed between the upper surface of the semiconductor substrate and the drift region in the semiconductor substrate;
an accumulation region of a first conductivity type formed between the drift region and the base region in the semiconductor substrate and having a doping concentration higher than that of the drift region;
a dummy trench portion formed in the semiconductor substrate by penetrating the base region from the upper surface of the semiconductor substrate; a gate trench formed up to
a suppression structure for suppressing formation of a second conductivity type inversion region in the first conductivity type drift region and the accumulation region adjacent to the dummy trench portion;
with
The suppressing structure is the accumulation region, and the integrated concentration obtained by integrating the doping concentration in the dummy adjacent region adjacent to the dummy trench portion in the depth direction of the semiconductor substrate is the gate adjacent region adjacent to the gate trench portion. higher than the integral concentration obtained by integrating the doping concentration in the depth direction of the semiconductor substrate in
the dummy adjacent region is formed to a deeper position than the gate adjacent region;
In the dummy adjacent region, the doping concentration distribution in the depth direction of the semiconductor substrate includes a first peak and a doping concentration higher than the first peak. a second peak and
including said storage region formed to
semiconductor device. 13. The semiconductor device according to claim 12, wherein, in the accumulation region, a doping concentration peak in the dummy adjacent region is higher than a doping concentration peak in the gate adjacent region. In the accumulation region formed between the two dummy trench portions, the integrated concentration is lower in the central region at the center of the two dummy trench portions than in the dummy adjacent region adjacent to the dummy trench portions. 16. The semiconductor device according to any one of Items 12 to 15. a transistor section formed on the semiconductor substrate and including one or more of the dummy trench sections;
a diode section formed on the semiconductor substrate and including one or more of the dummy trench sections;
a boundary portion formed between the transistor portion and the diode portion in the semiconductor substrate and including one or more of the dummy trench portions;
17. A high-concentration region of a second conductivity type having a doping concentration higher than that of the base region is formed on the upper surface of the semiconductor substrate in the mesa portion sandwiched between the dummy trench portions in the boundary portion. The semiconductor device according to any one of 1. 18. The semiconductor device according to claim 17, wherein the accumulation region is not formed in at least a partial region of the mesa portion of the boundary portion. 18. The semiconductor device according to claim 17, wherein the accumulation region is formed in the entirety of the mesa portion of the boundary portion. a semiconductor substrate;
a drift region of a first conductivity type formed in the semiconductor substrate;
a base region of a second conductivity type formed between the upper surface of the semiconductor substrate and the drift region in the semiconductor substrate;
an accumulation region of a first conductivity type formed between the drift region and the base region in the semiconductor substrate and having a doping concentration higher than that of the drift region;
a dummy trench portion formed in the semiconductor substrate so as to penetrate the base region from the upper surface of the semiconductor substrate; a transistor portion formed in the semiconductor substrate and including one or more of the dummy trench portions;
a diode section formed on the semiconductor substrate and including one or more of the dummy trench sections;
a boundary portion formed between the transistor portion and the diode portion in the semiconductor substrate and including one or more of the dummy trench portions;
a suppression structure for suppressing formation of a second conductivity type inversion region in the first conductivity type drift region and the accumulation region adjacent to the dummy trench portion;
with
A high-concentration region of a second conductivity type having a doping concentration higher than that of the base region is formed on the upper surface of the semiconductor substrate in the mesa portion sandwiched between the dummy trench portions in the boundary portion,
The accumulation region is not formed in at least a partial region of the mesa portion of the boundary portion,
The suppressing structure has an integral concentration obtained by integrating the doping concentration of the first conductivity type in the region adjacent to the dummy trench portion on the side closer to the transistor portion in the mesa portion of the boundary portion in the depth direction of the semiconductor substrate. includes the mesa portion formed so as to be higher than the integrated concentration obtained by integrating the doping concentration of the first conductivity type in the central region of the mesa portion in the depth direction
semiconductor device. In the mesa portion of the boundary portion, the integrated concentration obtained by integrating the doping concentration of the first conductivity type in the region adjacent to the dummy trench portion on the side closer to the diode portion in the depth direction of the semiconductor substrate is the mesa portion. 21. The semiconductor device according to claim 20, wherein the doping concentration of the first conductivity type in the central region of is higher than the integrated concentration obtained by integrating the doping concentration in the depth direction. a mesa portion provided sandwiched between the gate trench portion and the dummy trench portion inside the semiconductor substrate and having the base region disposed thereon;
an emitter electrode provided above the upper surface of the semiconductor substrate;
2. The semiconductor device according to claim 1, wherein said base region arranged in at least a part of said mesa portion sandwiched between said gate trench portion and said dummy trench portion is not connected to said emitter electrode. . a semiconductor substrate;
a drift region of a first conductivity type formed in the semiconductor substrate;
a base region of a second conductivity type formed between the upper surface of the semiconductor substrate and the drift region in the semiconductor substrate;
an accumulation region of a first conductivity type formed between the drift region and the base region in the semiconductor substrate and having a doping concentration higher than that of the drift region;
a gate trench portion formed in the semiconductor substrate from the upper surface of the semiconductor substrate to the drift region through the base region and the accumulation region; and a gate trench portion formed in the semiconductor substrate from the upper surface of the semiconductor substrate to the base region a dummy trench portion formed by
a mesa portion provided sandwiched between the gate trench portion and the dummy trench portion inside the semiconductor substrate and having the base region disposed thereon;
an emitter electrode provided above the upper surface of the semiconductor substrate;
a suppression structure for suppressing formation of a second conductivity type inversion region in the first conductivity type drift region and the accumulation region adjacent to the dummy trench portion;
with
the suppressing structure includes the dummy trench portion formed shallower than the gate trench portion;
The semiconductor device, wherein the base region arranged in at least a part of the mesa portion sandwiched between the gate trench portion and the dummy trench portion is not connected to the emitter electrode. a semiconductor substrate;
a drift region of a first conductivity type formed in the semiconductor substrate;
a base region of a second conductivity type formed between the upper surface of the semiconductor substrate and the drift region in the semiconductor substrate;
an accumulation region of a first conductivity type formed between the drift region and the base region in the semiconductor substrate and having a doping concentration higher than that of the drift region;
a dummy trench portion formed through the base region from an upper surface of the semiconductor substrate in the semiconductor substrate;
a suppression structure for suppressing formation of a second conductivity type inversion region in the first conductivity type drift region and the accumulation region adjacent to the dummy trench portion;
with
The semiconductor substrate further includes a first gate trench portion and a second gate trench portion formed through the base region and the accumulation region from the upper surface of the semiconductor substrate to the drift region,
each of the first gate trench portion, the second gate trench portion and the dummy trench portion,
two extending portions extending parallel to a predetermined direction on the upper surface of the semiconductor substrate;
a tip connecting the tips of the two extensions;
The dummy trench portion is arranged inside the first gate trench portion on the upper surface of the semiconductor substrate,
The semiconductor device, wherein the second gate trench portion is arranged inside the dummy trench portion on the upper surface of the semiconductor substrate. a semiconductor substrate;
a drift region of a first conductivity type formed in the semiconductor substrate;
a base region of a second conductivity type formed between the upper surface of the semiconductor substrate and the drift region in the semiconductor substrate;
an accumulation region of a first conductivity type formed between the drift region and the base region in the semiconductor substrate and having a doping concentration higher than that of the drift region;
a first gate trench portion and a second gate trench portion formed in the semiconductor substrate from an upper surface of the semiconductor substrate to the drift region through the base region and the accumulation region;
a dummy trench portion formed in the semiconductor substrate so as to penetrate the base region from the upper surface of the semiconductor substrate;
The dummy trench portion is arranged inside the first gate trench portion on the upper surface of the semiconductor substrate,
The semiconductor device according to claim 1, wherein the second gate trench portion is arranged inside the dummy trench portion on the upper surface of the semiconductor substrate. a mesa portion sandwiched between at least one of the dummy trench portion and the gate trench portion;
further comprising
The storage area is
a first accumulation region provided below the base region;
2. The semiconductor device according to claim 1, further comprising: a second accumulation region provided between said first accumulation region and said drift region. at least one of the dummy trench portion and the gate trench portion,
a trench thin film portion having an insulating film having a predetermined thickness and a conductive portion covered with the insulating film on the inner wall of the trench;
a trench thick-film portion having an insulating film thicker than the insulating film in the trench thin-film portion on the inner wall of the trench;
has
The trench thick film portion is provided at a deeper position than the trench thin film portion,
27. The semiconductor device according to claim 26. 28. The semiconductor device according to claim 27, wherein said conductive portion is provided in said trench thin film portion but not provided in said trench thick film portion. The conductive portion is provided in both the trench thin film portion and the trench thick film portion,
28. The semiconductor device according to claim 27, wherein the conductive portion of the trench thin film portion has a larger width in the trench arrangement direction than the conductive portion of the trench thick film portion. the conductive portion has the same width in the direction in which the trenches are arranged, and is provided in both the trench thin film portion and the trench thick film portion;
28. The semiconductor device according to claim 27, wherein at least one of said dummy trench portion and said gate trench portion has a width in said array direction in said trench thin film portion smaller than a width in said array direction in said trench thick film portion. The semiconductor device according to any one of claims 27 to 30, wherein said trench thick film portion is provided at a position deeper than said base region. 32. The semiconductor device according to any one of claims 26 to 31, wherein said accumulation region further comprises a third accumulation region provided between said first accumulation region and said second accumulation region.

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