JP7234843B2 - DETECTION DEVICE AND CHARGE-VOLTAGE CONVERSION CIRCUIT - Google Patents

Description

The present invention relates to a detection device such as a temperature detection device and a charge-voltage conversion circuit.

2. Description of the Related Art As a detection device, for example, a humidity detection device is of a capacitance type that uses, as a dielectric, a moisture-sensitive film formed of a polymer material whose dielectric constant changes according to the amount of absorbed moisture. In this capacitance-type humidity detector, a humidity-sensitive film is arranged between electrodes, and humidity (relative humidity) is obtained by measuring the capacitance between the electrodes (see, for example, Patent Document 1).

In the humidity detection device described in Patent Document 1, a sensor unit whose capacitance changes with humidity and a reference unit (reference unit) that maintains a constant capacitance regardless of humidity are provided, and the capacitance difference between the two is calculated. Humidity is measured by converting it into voltage. The sensor section and the reference section are arranged side by side on the substrate.

As a circuit unit used in such a capacitance-type humidity detection device, a configuration is known in which a charge output from a sensor unit is converted into a voltage by a charge amplifier (see, for example, Patent Document 2). In addition to the charge amplifier, this circuit section is provided with a drive circuit and the like for driving the sensor section with a square-wave AC drive signal.

Patent No. 5547296 Patent No. 6228865

It is conceivable that leakage current may occur due to the provision of an electrostatic discharge protection circuit or the like to the terminal of the detection device. If a leak current occurs at the capacitance detection terminal, the output voltage from the charge amplifier fluctuates, resulting in an error in the measured value.

SUMMARY OF THE INVENTION An object of the present invention is to suppress errors in measured values due to leakage current.

The disclosed technique has a first electrode connected to a first drive terminal and a second electrode connected to a signal terminal, and a detection capacitor whose capacitance changes according to a physical quantity is connected to the first electrode. and the second electrode, and a drive unit for applying a first AC drive signal to the first drive terminal, wherein the first drive signal is detected during a first period and a second period. A drive unit for inverting a voltage, and a charge-voltage conversion unit for converting a charge generated at the signal terminal into a voltage, wherein the first output voltage is generated during the first period, and the first output voltage is generated during the second period. is a charge-voltage conversion unit that generates a second output voltage whose voltage is inverted; and a difference processing unit that is a differential input AD converter that generates a difference value between the first output voltage and the second output voltage. , a first sample and hold circuit connected to one input terminal of the AD converter, and a second sample and hold circuit connected to the other input terminal of the AD converter, wherein the first sample and hold circuit and the second sample-and-hold circuit selectively samples and holds the first output voltage and the second output voltage, and the AD converter samples the output voltage of the first sample-and-hold circuit and the second sample-and-hold circuit. It is a detection device that converts the difference in output voltage of a circuit into a digital signal and outputs it.

According to the present invention, errors in measured values due to leak current can be suppressed.

It is a figure which illustrates schematic structure of the humidity detection apparatus which concerns on one Embodiment of this invention. FIG. 2 is a cross-sectional view schematically showing a cross section taken along line AA in FIG. 1; FIG. 3 is a plan view of the humidity detection device with the mold resin removed; It is a schematic plan view showing the configuration of a sensor chip. 1 is a circuit diagram illustrating the configuration of an ESD protection circuit; FIG. FIG. 3 is a diagram illustrating a layer structure of an NMOS transistor that constitutes an ESD protection circuit; 4 is a circuit diagram illustrating the configuration of a humidity detection unit; FIG. 4 is a circuit diagram illustrating the configuration of a temperature detection unit; FIG. It is a schematic sectional view for explaining the element structure of the sensor chip. It is a schematic plan view which illustrates the planar shape of a heating part. FIG. 4 is a schematic plan view illustrating the planar shape of each electrode of the humidity detection unit; FIG. 4 is a plan view illustrating a layout pattern of a second wiring layer; FIG. 13 is a schematic cross-sectional view showing a cross-sectional structure taken along line AA of FIG. 12; 1 is a block diagram illustrating the configuration of an ASIC chip; FIG. It is a figure which illustrates the structure of a humidity measurement process part. 4 is a timing chart for explaining a measurement sequence; It is a figure explaining the cancellation effect of leakage current. FIG. 4 is a diagram showing an equivalent circuit of an electrode structure including parasitic capacitance; It is a figure which shows the equivalent circuit of the conventional electrode structure. It is a figure explaining the effect by pad arrangement|positioning of this embodiment. It is a top view which shows the 1st modification of a shield layer. It is a top view which shows the 2nd modification of a shield layer. It is a figure which shows the structure of the humidity measurement process part which concerns on a modification. It is a timing chart explaining a measurement sequence of a humidity measurement processing part concerning a modification. It is a figure which shows roughly the layout of the humidity measurement process part in an ASIC chip. FIG. 26 is a cross-sectional view taken along line AA in FIG. 25;

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In each drawing, the same components are denoted by the same reference numerals, and redundant description may be omitted. In addition, in the present disclosure, humidity when simply described as humidity means relative humidity.

[Outline configuration]
A configuration of the humidity detection device 10 according to one embodiment of the present invention will be described.

FIG. 1 is a diagram illustrating a schematic configuration of a humidity detection device 10 according to one embodiment of the invention. FIG. 1A is a top plan view of the humidity detection device 10. FIG. FIG. 1B is a bottom view of the humidity detection device 10 viewed from below. FIG. 1(C) is a side view of the humidity detection device 10 viewed from the lateral direction. FIG. 2 is a cross-sectional view schematically showing a cross section taken along line AA in FIG. 1(A).

The humidity detection device 10 has a substantially rectangular planar shape, and one of two pairs of opposing sides is parallel to the X direction and the other is parallel to the Y direction. The X direction and the Y direction are orthogonal to each other. Also, the humidity detection device 10 has a thickness in the Z direction perpendicular to the X and Y directions. The planar shape of the humidity detection device 10 is not limited to a rectangular shape, and may be circular, elliptical, polygonal, or the like.

The humidity detection device 10 includes a sensor chip 20 as a first semiconductor chip, an ASIC (Application Specific Integrated Circuit) chip 30 as a second semiconductor chip, a mold resin 40 as a sealing member, and a plurality of lead terminals 41. have

The sensor chip 20 is laminated on the ASIC chip 30 via a first DAF (Die Attach Film) 42 . That is, the sensor chip 20 and the ASIC chip 30 have a stack structure.

The sensor chip 20 and the ASIC chip 30 are electrically connected by a plurality of first bonding wires 43 . The ASIC chip 30 and the plurality of lead terminals 41 are electrically connected by a plurality of second bonding wires 44 .

The sensor chip 20, the ASIC chip 30, the plurality of first bonding wires 43, the plurality of second bonding wires 44, and the plurality of lead terminals 41 laminated in this manner are sealed with the mold resin 40 and packaged. ing. This package method is called a PLP (Plating Lead Package) method.

In this PLP method, it is preferable that the thickness T1 of the sensor chip 20 and the thickness T2 of the ASIC chip 30 are each 200 μm or more.

On the bottom surface of the ASIC chip 30, the second DAF 45 used for packaging by the PLP method remains, although the details will be described later. The second DAF 45 has a role of insulating the bottom surface of the ASIC chip 30 . A second DAF 45 and a plurality of lead terminals 41 are exposed on the lower surface of the humidity detection device 10 .

Each lead terminal 41 is made of nickel or copper. The first DAF 42 and the second DAF 45 are each made of an insulating material such as a mixture of epoxy, silicon and silica. The mold resin 40 is a black resin having a light shielding property such as an epoxy resin.

An opening 50 is formed on the upper surface side of the humidity detection device 10 to expose a part of the sensor chip 20 from the mold resin 40 . The opening 50 has, for example, a tapered wall, and the opening area becomes smaller downward. The lowermost portion of the opening 50 that actually exposes the sensor chip 20 is called an effective opening 51 .

FIG. 3 is a plan view of the humidity detection device 10 with the mold resin 40 removed. As shown in FIG. 3, the sensor chip 20 and the ASIC chip 30 each have a substantially rectangular planar shape and have two sides parallel to the X direction and two sides parallel to the Y direction. The sensor chip 20 is smaller than the ASIC chip 30 and is stacked on the surface of the ASIC chip 30 with the first DAF 42 interposed therebetween.

The sensor chip 20 is provided with a humidity detection section 21 , a temperature detection section 22 and a heating section 23 in a region exposed by the effective opening 51 . The heating portion 23 is formed on the lower surface side of the humidity detection portion 21 so as to cover the formation area of the humidity detection portion 21 .

A plurality of bonding pads (hereinafter simply referred to as pads) 24 are formed at the end of the sensor chip 20 . Six pads 24 are formed in this embodiment. The pads 24 are made of, for example, aluminum or an aluminum silicon alloy (AlSi).

The ASIC chip 30 is a semiconductor chip for signal processing and control, and includes a humidity measurement processing unit 31, a temperature measurement processing unit 32, a heating control unit 33, and a failure determination unit 34 (see FIG. 14 for all), which will be described later. It is

A plurality of first pads 35 and a plurality of second pads 36 are provided in a region of the surface of the ASIC chip 30 that is not covered with the sensor chip 20 . The first pads 35 and the second pads 36 are made of, for example, aluminum or an aluminum silicon alloy (AlSi).

The first pads 35 are connected to corresponding pads 24 of the sensor chip 20 via first bonding wires 43 . The second pads 36 are connected to corresponding lead terminals 41 via second bonding wires 44 . The lead terminals 41 are arranged around the ASIC chip 30 .

[Configuration of sensor chip]
Next, the configuration of the sensor chip 20 will be described.

FIG. 4 is a schematic plan view showing the configuration of the sensor chip 20. As shown in FIG. The aforementioned pad 24 is a terminal used for external voltage application and potential detection. In FIG. 4, the plurality of pads 24 shown in FIG. 3 are shown separately from the pads 24a-24f. The pads 24a to 24f are simply referred to as pads 24 when there is no need to distinguish between them.

The pad 24a functions as a ground electrode terminal (GND) grounded to ground potential. The pad 24a is electrically connected to each part such as the temperature detection part 22 and the heating part 23 through wiring and a substrate. Pad 24a is electrically connected to p-type semiconductor substrate 70 (see FIG. 9) that constitutes sensor chip 20. As shown in FIG.

Pad 24 b is a signal terminal (TS) electrically connected to lower electrode 83 of humidity detector 21 . Pad 24c is a first drive terminal (T1) electrically connected to upper electrode 84 of humidity detector 21 . The pad 24d is a second drive terminal (T2) electrically connected to the reference electrode 82 (see FIG. 9) of the humidity detector 21. As shown in FIG. The lower electrode 83 functions as a capacitance detection electrode for a charge amplifier 301 (see FIG. 15), which will be described later, to detect capacitance.

The pad 24 e is a temperature detection terminal (TMP) electrically connected to the temperature detection section 22 . The pad 24e is used to acquire a temperature detection signal. The pad 24 f is a heating terminal (HT) electrically connected to the heating section 23 . Pad 24f is used to supply a drive voltage for driving heating unit 23 .

An electrostatic discharge (ESD) protection circuit 60 is connected to each of the pads 24b to 24f other than the pad 24a. Each ESD protection circuit 60 is connected between each of the pads 24b to 24f as input terminals or output terminals and the pad 24a as a ground electrode terminal. In this embodiment, the ESD protection circuit 60 is composed of one diode 61 . The diode 61 has an anode connected to the pad 24a and a cathode connected to one of the pads 24b to 24f.

The ESD protection circuit 60 is preferably arranged near the pads 24b-24f so as to be as far away from the effective opening 51 as possible. Since the ESD protection circuit 60 is covered with the mold resin 40, unnecessary current due to the photoelectric effect does not flow.

[Configuration of ESD protection circuit]
Next, the configuration of the ESD protection circuit 60 will be described.

FIG. 5 is a circuit diagram illustrating the configuration of the ESD protection circuit 60. As shown in FIG. As shown in FIG. 5, the diode 61 forming the ESD protection circuit 60 is formed of, for example, an N-channel MOS (Metal-Oxide-Semiconductor) transistor (hereinafter referred to as an NMOS transistor). Specifically, the diode 61 short-circuits the source, gate, and back gate of the NMOS transistor. This short circuit functions as an anode. The drain of this NMOS transistor functions as the cathode.

FIG. 6 is a diagram illustrating the layer structure of the NMOS transistor that constitutes the ESD protection circuit 60. As shown in FIG. This NMOS transistor has two n-type diffusion layers 71 and 72 formed on the surface layer of a p-type semiconductor substrate 70 for constituting the sensor chip 20 , a contact layer 73 and a gate electrode 74 . A gate electrode 74 is formed on the surface of the p-type semiconductor substrate 70 with a gate insulating film 75 interposed therebetween. A gate electrode 74 is arranged between the two n-type diffusion layers 71 and 72 .

For example, the n-type diffusion layer 71 functions as a source and the n-type diffusion layer 72 functions as a drain. Contact layer 73 is a low-resistance layer (p-type diffusion layer) for electrical connection with p-type semiconductor substrate 70 as a back gate. The n-type diffusion layer 71, the gate electrode 74 and the contact layer 73 are commonly connected and short-circuited. This short-circuit portion functions as an anode, and the n-type diffusion layer 72 functions as a cathode.

The p-type semiconductor substrate 70 is, for example, a p-type silicon substrate. The gate electrode 74 is made of, for example, polycrystalline silicon (polysilicon). The gate insulating film 75 is made of, for example, an oxide film such as silicon dioxide.

[Configuration of Humidity Detector]
Next, the configuration of the humidity detector 21 will be described.

FIG. 7 is a circuit diagram illustrating the configuration of the humidity detection section 21. As shown in FIG. As shown in FIG. 7 , the humidity detection unit 21 includes a parallel plate type humidity detection capacitor 80 and a parallel plate type reference capacitor 81 .

One electrode (lower electrode 83) of the humidity detector 21 is connected to a pad 24b as a signal terminal TS. The other electrode (upper electrode 84) of the humidity detector 21 is connected to the pad 24c as the first drive terminal T1. One electrode of the reference capacitor 81 is shared with one electrode (lower electrode 83 ) of the humidity detection section 21 . The other electrode (reference electrode 82) of the reference capacitor 81 is connected to the pad 24d as the second drive terminal T2.

The humidity detection capacitor 80 is provided with a humidity sensitive film 86, which will be described later, between electrodes. The humidity sensitive film 86 is made of a polymeric material such as polyimide that absorbs moisture in the air and changes its dielectric constant according to the amount of moisture absorbed. Therefore, the capacitance of the humidity detection capacitor 80 changes according to the amount of moisture absorbed by the humidity sensitive film 86 .

The reference capacitor 81 is provided with a second insulating film 111 (see FIG. 9), which will be described later, between electrodes. The second insulating film 111 is made of an insulating material such as silicon dioxide (SiO ₂ ) that does not absorb moisture. Therefore, the capacitance of the reference capacitor 81 does not change according to humidity. It should be noted that the fact that the capacitance does not change also includes a very slight change.

Since the amount of moisture contained in the humidity sensitive film 86 corresponds to the humidity around the humidity detection device 10, by detecting the difference between the capacitance of the humidity detection capacitor 80 and the capacitance of the reference capacitor 81, , relative humidity can be measured. This relative humidity measurement is performed by the humidity measurement processor 31 (see FIG. 14) in the ASIC chip 30 .

[Configuration of Temperature Detector]
Next, the configuration of the temperature detection section 22 will be described.

FIG. 8 is a circuit diagram illustrating the configuration of the temperature detection section 22. As shown in FIG. The temperature detection unit 22 is a bandgap type temperature sensor that detects temperature by utilizing the characteristic that the electrical characteristics of the semiconductor bandgap change proportionally with changes in temperature. For example, the temperature detection unit 22 includes one or a plurality of bipolar transistors having two terminals by connecting any two of a base, an emitter, and a collector. The temperature can be measured by detecting the voltage value between these two terminals.

As shown in FIG. 8, in this embodiment, the temperature detection unit 22 is configured by connecting in parallel a plurality (e.g., eight) of npn-type bipolar transistors 90 whose bases and collectors are connected. By connecting a plurality of bipolar transistors 90 in parallel in this way, the junction area of the pn junction is increased and the ESD resistance is improved.

The emitter of bipolar transistor 90 is connected to pad 24a as a ground electrode terminal. The base and collector of the bipolar transistor 90 are connected to the pad 24e as a terminal for temperature detection.

The temperature is measured by the temperature measurement processor 32 (see FIG. 14) in the ASIC chip 30 based on the potential of the pad 24e.

[Sensor chip element structure]
Next, the element structure of the sensor chip 20 will be described.

FIG. 9 is a schematic cross-sectional view for explaining the element structure of the sensor chip 20. As shown in FIG. In FIG. 9, the pads 24a, 24b, 24c, and 24e are shown in the same cross section as the humidity detection section 21, the temperature detection section 22, and the heating section 23, which facilitates understanding of the structure. It does not mean that they actually exist within the same cross section. The cross sections of the humidity detection unit 21, the temperature detection unit 22, and the heating unit 23 are also simplified in order to facilitate understanding of the structure, and the positional relationship and the like of each unit are different from the actual ones.

As shown in FIG. 9, the sensor chip 20 is formed using the p-type semiconductor substrate 70 described above. This p-type semiconductor substrate 70 is formed with a first deep n-well 100a and a second deep n-well 100b. A temperature detector 22 is formed in the first deep n-well 100a. A heating portion 23 is formed in the second deep n-well 100b.

P-wells 103a and 103b are formed in the surface layer of the p-type semiconductor substrate 70 where neither the first deep n-well 100a nor the second deep n-well 100b are formed. Contact layers 104a and 104b made of p-type diffusion regions are formed on the surface layers of the p-wells 103a and 103b, respectively. The contact layers 104a and 104b are low-resistance layers (p-type diffusion layers) for electrical connection between a predetermined wiring layer formed on the p-type semiconductor substrate 70 and the p-type semiconductor substrate 70. FIG.

A p-well 101 and an n-well 102 are formed on the surface of the first deep n-well 100a. An n-type diffusion layer 91 and a p-type diffusion layer 92 are formed in the surface layer of the p-well 101 . An n-type diffusion layer 93 is formed in the surface layer of the n-well 102 . The n-type diffusion layer 91, the p-type diffusion layer 92, and the n-type diffusion layer 93 constitute the aforementioned npn-type bipolar transistor 90, functioning as an emitter, a base, and a collector, respectively.

A p-well 105 is formed on the surface of the second deep n-well 100b. One or more n-type diffusion layers 106 are formed in the surface layer of the p-well 105 . In this embodiment, a plurality of n-type diffusion layers 106 are formed. For example, each n-type diffusion layer 106 extends in a direction orthogonal to the plane of the drawing, and forms a one-dimensional lattice as a whole (see FIG. 11). The n-type diffusion layer 106 has a predetermined resistance value (for example, a sheet resistance value of about 3.3Ω) and functions as a resistor that generates heat when current flows. That is, the n-type diffusion layer 106 constitutes the heating portion 23 described above.

Each layer in the p-type semiconductor substrate 70 is formed using a normal semiconductor manufacturing process (CMOS process). Therefore, n-type diffusion layer 106 as a resistor is formed in the same manufacturing process as n-type diffusion layers 91 and 93 included in part of temperature detection section 22 . The n-type diffusion layers 106, 91 and 93 are simultaneously formed by an ion implantation process of doping the substrate with an n-type impurity (for example, phosphorus) by ion implantation. That is, the n-type diffusion layer 106 as a resistor has the same depth from the surface of the p-type semiconductor substrate 70 as the n-type diffusion layers 91 and 93 included in a part of the temperature detection section 22 . Further, the n-type diffusion layer 106 may have the same depth from the surface of the p-type semiconductor substrate 70 as the p-type diffusion layer 92 included in a part of the temperature detection section 22 .

The n-type diffusion layers 106, 91 and 93 can be formed by a thermal diffusion process in which impurities are added by heat treatment instead of the ion implantation process.

Also, the n-type diffusion layers 71 and 72 of the ESD protection circuit 60 described above are formed by the same manufacturing process (ion implantation process or thermal diffusion process) as the n-type diffusion layers 106, 91 and 93. The contact layer 73 is formed in the same manufacturing process (ion implantation process or thermal diffusion process) as the p-type diffusion layer 92, the contact layers 104a and 104b, and the like.

Other layers in the p-type semiconductor substrate 70 mainly function as contact layers, so description thereof is omitted.

A first insulating film 110 , a second insulating film 111 and a third insulating film 112 are laminated in this order on the surface of the p-type semiconductor substrate 70 . These are made of an insulating material such as silicon dioxide (SiO ₂ ) or silicon nitride (SiN).

A first wiring layer 120 is formed on the first insulating film 110 . A second wiring layer 121 is formed on the second insulating film 111 . The second insulating film 111 covers the first wiring layer 120 . The third insulating film 112 covers the second wiring layer 121 . The first wiring layer 120 and the second wiring layer 121 are made of a conductive material such as aluminum.

A first plug layer 122 having a plurality of first plugs for connecting the first wiring layer 120 to the p-type semiconductor substrate 70 is formed in the first insulating film 110 . A second plug layer 123 having a plurality of second plugs for connecting the first wiring layer 120 and the second wiring layer 121 is formed in the second insulating film 111 . The first plug layer 122 and the second plug layer 123 are made of a conductive material such as tungsten.

For example, the wiring 94 for connecting the base and collector of the bipolar transistor 90 described above is formed by the first wiring layer 120 and is connected to the p-type diffusion layer 92 and the n-type diffusion layer 93 via the first plug layer 122. Connected. Also, the wiring 94 is connected to the pad 24e as a terminal for temperature detection through the second plug layer 123 and the second wiring layer 121. As shown in FIG. Also, the n-type diffusion layer 91 as the emitter of the bipolar transistor 90 is connected through the first plug layer 122, the first wiring layer 120 and the second wiring layer 121 to the pad 24a as the ground electrode terminal.

A wiring 107 for grounding one end of the heating portion 23 to the ground potential is formed of the first wiring layer 120 and connected via the first plug layer 122 to the n-type diffusion layer 106 and the contact layer 104b. The wiring 107 is hereinafter referred to as a ground wiring 107 .

A wiring 108 for connecting the other end of the heating portion 23 to a pad 24f as a heating terminal is connected to the n-type diffusion layer 106 via the first plug layer 122, and is connected to the second plug layer 123 and It is connected to the pad 24 f through the second wiring layer 121 . Note that the wiring 108 is preferably wider than the other signal wirings in order to prevent electromigration due to a large current flowing through the heating portion 23 . The wiring 108 is hereinafter referred to as a power supply wiring 108 .

The reference electrode 82 of the reference capacitor 81 is formed of the first wiring layer 120, and is connected to the pad 24d (not shown in FIG. 9) as the second drive terminal T2 via the second plug layer 123 and the second wiring layer 121. ).

The lower electrode 83 of the humidity detection capacitor 80 is formed of the second wiring layer 121 and connected to the pad 24b as the signal terminal TS. Furthermore, the wiring 85 for connecting the upper electrode 84 of the humidity detection capacitor 80 to the pad 24c as the first drive terminal T1 is formed of the second wiring layer 121. As shown in FIG. Note that the lower electrode 83 is arranged at a position facing the reference electrode 82 with the second insulating film 111 interposed therebetween.

The pads 24a to 24f are formed on the third insulating film 112 with a conductive material such as aluminum, and are connected to the second wiring layer 121 through the third insulating film 112. FIG.

A humidity sensitive film 86 is formed on the third insulating film 112 . The moisture-sensitive film 86 is made of a polymeric material having a thickness of 0.5 μm to 1.5 μm and which easily adsorbs water molecules. The moisture sensitive film 86 is, for example, a polyimide film with a thickness of 1 μm. The polymeric material forming the moisture-sensitive film 86 is not limited to polyimide, and may be cellulose, polymethylmethacrylate (PMMA), polyvinyl alcohol (PVA), or the like.

The upper surface of the humidity sensitive film 86 is flat, and a planar upper electrode 84 is formed on this upper surface. The upper electrode 84 is formed at a position facing the lower electrode 83 with the humidity sensitive film 86 interposed therebetween. A portion of the upper electrode 84 is connected to the wiring 85 . The upper electrode 84 is, for example, a conductive film made of aluminum or the like with a thickness of 200 nm. In addition, the upper electrode 84 is formed with a plurality of openings 84a so that water molecules in the air are efficiently taken into the humidity sensitive film 86. As shown in FIG.

An overcoat film 87 is provided on the humidity sensitive film 86 so as to cover the upper electrode 84 . The overcoat film 87 is made of a polymeric material, for example, the same material as the moisture sensitive film 86 . The thickness of the overcoat film 87 is, for example, 0.5 μm to 10 μm.

The humidity sensitive film 86 and the overcoat film 87 are formed with openings for exposing the pads 24a to 24f.

Thus, the lower electrode 83 and the upper electrode 84 constitute the parallel-plate humidity detection capacitor 80 . The lower electrode 83 and the reference electrode 82 constitute a parallel-plate reference capacitor 81 . The humidity detection capacitor 80 and the reference capacitor 81 are arranged above the heating section 23 .

Therefore, when the heating part 23 generates heat, the moisture sensitive film 86 between the lower electrode 83 and the upper electrode 84 is heated, the moisture evaporates, and the moisture content in the moisture sensitive film 86 changes. As a result, the dielectric constant of the humidity sensitive film 86 changes, and the capacitance of the humidity detection capacitor 80 changes. Also, the temperature detection unit 22 detects temperature changes caused by the heating unit 23 .

[Planar shape of heating part]
FIG. 10 is a schematic plan view illustrating the planar shape of the heating unit 23. As shown in FIG. FIG. 10 schematically shows wiring shapes and the like, and differs from an actual layout pattern.

As shown in FIG. 10, the n-type diffusion layer 106 forming the heating portion 23 is formed in a one-dimensional grid pattern in which a plurality of elongated strip-shaped regions are arranged in parallel. One end of the one-dimensional grid-like n-type diffusion layer 106 is connected to the ground wiring 107 described above, and the other end is connected to the power supply wiring 108 described above. The heating unit 23 is positioned below the temperature detection unit 22 so as to cover the entire temperature detection unit 22 .

Although details will be described later, the ground wiring 107 does not actually have a linear shape, but has a shape extending in the XY plane, and functions as a shield layer for shielding signal lines and the like.

[Planar shape of electrode]
FIG. 11 is a schematic plan view illustrating the planar shape of each electrode of the humidity detection section 21. As shown in FIG.

As shown in FIG. 11, the reference electrode 82, upper electrode 84, and lower electrode 83 all have substantially the same shape and are rectangular. The upper electrode 84 is formed so as to cover the lower electrode 83 and the reference electrode 82 . The reference electrode 82, lower electrode 83, and upper electrode 84 are laminated in this order from the p-type semiconductor substrate 70 side.

The reference electrode 82 and the upper electrode 84 are preferably approximately the same size. The bottom electrode 83 is preferably smaller than the reference electrode 82 and the top electrode 84 .

It is preferable that the opening 84a is as small as possible. The smaller the opening 84a, the smaller the leakage of the electric field into the air, and the more the capacitance change between the lower electrode 83 and the upper electrode 84 is suppressed when foreign matter adheres (FIG. 13). reference). Actually, a large number of minute openings 84a are formed. It should be noted that the opening 84a is not limited to a square shape, and may be an elongated rectangular shape or a circular shape.

The signal lines 201 to 203 are wirings formed by the first wiring layer 120 and the second wiring layer 121 . The signal line 201 is a wiring connected between the lower electrode 83 of the humidity detection section 21 and the pad 24b. The signal line 202 is a wiring connected between the upper electrode 84 of the humidity detection section 21 and the pad 24c.

Note that the wiring 85 described above is part of the signal line 202 .

[Planar shape of electrode]
FIG. 12 is a plan view illustrating a layout pattern of the second wiring layer 121. FIG. As shown in FIG. 12, the lower electrode 83, the ground wiring 107, the wiring 85, and the like are formed of the second wiring layer 121. As shown in FIG.

The ground wiring 107 is adjacent to other wirings such as the ground wiring 107 and the wiring 85 via minute slits. The ground wiring 107 is provided almost over the entire surface. Therefore, the ground wiring 107 covers the signal lines 201 to 203 and the signal line 204 connected to the temperature detection section 22, and functions as a shield layer.

[Laminated structure of electrode]
FIG. 13 is a schematic cross-sectional view showing a cross-sectional structure taken along line AA of FIG. As shown in FIG. 13 , the lower electrode 83 as the capacitance detection electrode is arranged above the reference electrode 82 and is not close to the p-type semiconductor substrate 70 . The resulting parasitic capacitance is suppressed.

In addition, since the upper electrode 84 is arranged above the lower electrode 83 and the ground wiring 107 is provided close to the lower electrode 83 around the lower electrode 83, the electric field is confined by these shield effects. Therefore, as shown in FIG. 13, for example, even if foreign matter such as water droplets having a large relative dielectric constant adheres to the opening 50 and changes the capacitance, the ground wiring 107 shields the electric field. As a result, the influence on the lower electrode 83 is suppressed.

By making the area of the lower electrode 83 smaller than the areas of the reference electrode 82 and the upper electrode 84, the electric field confinement effect on the lower electrode 83 is improved.

In addition, the humidity detection capacitor 80 and the reference capacitor 81 share the lower electrode 83, and the reference electrode 82, the upper electrode 84, and the lower electrode 83 are formed in a laminated structure. 10 can be made smaller.

Further, in FIG. 13, the wiring arranged adjacent to the reference electrode 82 is formed of the first wiring layer 120 and is set to the ground potential.

[Configuration of ASIC chip]
Next, the configuration of the ASIC chip 30 will be described.

FIG. 14 is a block diagram illustrating the configuration of the ASIC chip 30. As shown in FIG. As shown in FIG. 14, the ASIC chip 30 includes a humidity measurement processing section 31, a temperature measurement processing section 32, a heating control section 33, and a failure determination section .

Although details will be described later, the humidity measurement processing unit 31 applies the first drive signal and the second drive signal in opposite phases to the first drive terminal T1 and the second drive terminal T2, respectively, and the pad 24b as the signal terminal TS. Relative humidity is measured by converting the electric charge output from the to a voltage.

The temperature measurement processing unit 32 detects the potential of the pad 24e as the temperature detection terminal HT, and calculates the temperature corresponding to the detected potential.

The heating control unit 33 applies a predetermined driving voltage (for example, the power supply voltage VDD described above) to the pad 24f as the heating terminal HT, thereby causing a current (for example, about 10 mA) to flow through the heating unit 23 to generate heat. The heating controller 33 controls the amount of heat generated by controlling the voltage applied to the pad 24f.

The failure determination section 34 performs failure determination based on the relative humidity measured by the humidity measurement processing section 31 and the temperature measured by the temperature measurement processing section 32 . The failure determination unit 34 provides the heating control unit 33 with instructions regarding the start and end of heating by the heating unit 23 at the time of failure determination.

For example, the failure determination unit 34 acquires the humidity H1 from the humidity measurement processing unit 31 and acquires the temperature T1 from the temperature measurement processing unit 32 in an initial state in which the heating unit 23 does not generate heat. Then, the failure determination unit 34 causes the heating unit 23 to start heating, and acquires the humidity H2 from the humidity measurement processing unit 31 and the temperature T2 from the temperature measurement processing unit 32 again after a certain period of time has elapsed.

When the temperature rises due to heating (T2>T1) and the humidity decreases due to heating (H2<H1), the failure determination unit 34 determines that the humidity detection device 10 is normal. , it is determined that the humidity detection device 10 is in a failed state.

[Configuration of Humidity Measurement Processing Unit]
Next, the configuration of the humidity measurement processing section 31 will be described.

FIG. 15 is a diagram illustrating the configuration of the humidity measurement processing unit 31. As illustrated in FIG. As shown in FIG. 15 , the humidity measurement processing section 31 has a drive section 300 , a charge amplifier 301 , a sample hold circuit 302 , an AD converter (ADC) 303 and a control section 304 . 15 shows the ESD protection circuit 60 connected to the pad 24b as the signal terminal TS of the sensor chip 20. As shown in FIG.

The driving section 300 includes a first driving circuit DRV1 and a second driving circuit DRV2. The charge amplifier 301 is a switched-capacitor type charge-voltage conversion (CV conversion) circuit including a capacitor C1, an operational amplifier OP1, and a switch circuit SW1.

The first drive circuit DRV<b>1 applies a first drive signal, which is a square-wave AC drive signal, to the first drive terminal T<b>1 of the sensor chip 20 under the control of the control unit 304 . Under the control of the control unit 304, the second drive circuit DRV2 supplies a second drive signal, which is a square-wave AC drive signal having a phase opposite to that of the first drive signal, to the second drive terminal T2 of the sensor chip 20. Apply a signal. When the first drive signal is at high level, the second drive signal is at low level, and when the first drive signal is at low level, the second drive signal is at high level.

The high level of the first drive signal and the second drive signal is equal to, for example, power supply voltage VDD, and the low level thereof is equal to, for example, ground potential GND.

The capacitor C1 has one end connected to the signal terminal TS of the sensor chip 20 and the other end connected to the output of the operational amplifier OP1.

The operational amplifier OP1 has an inverting input terminal connected to the signal terminal TS, and a non-inverting input terminal to which the reference voltage Vref is input. The reference voltage Vref is, for example, an intermediate value between the high level and the low level of the first drive signal and the second drive signal.

Since the operational amplifier OP1 has a very large voltage gain, the voltage at the signal terminal TS is substantially equal to the reference voltage Vref. Further, since the input impedance of the inverting input terminal of the operational amplifier OP1 is very high, almost no current flows into the inverting input terminal. The operational amplifier OP1 outputs a voltage Vo obtained by amplifying the difference between the voltage of the signal terminal TS and the reference voltage Vref.

The switch circuit SW1 is a circuit for discharging charges accumulated in the capacitor C1, and is connected in parallel with the capacitor C1. The switch circuit SW1 is turned on or off under the control of the control section 304. FIG.

The sample and hold circuit 302 includes a first sample and hold circuit (first S/H) 302a and a second sample and hold circuit (second S/H) 302b. The first S/H 302 a and the second S/H 302 b are connected in parallel between the driving section 300 and the ADC 303 . The first S/H 302a and the second S/H 302b selectively sample and hold the output voltage Vo from the charge amplifier 301 under the control of the control unit 304, and output the held voltage.

The ADC 303 is a differential input AD converter, and has two input terminals, one of which is connected to the output terminal of the first S/H 302a and the other of which is connected to the output terminal of the second S/H 302b. The ADC 303 converts the difference value ΔV between the output voltage Vsh1 of the first S/H 302a and the output voltage Vsh2 of the second S/H 302b into a digital signal Ds and outputs the digital signal Ds. That is, the ADC 303 functions as a differential processing unit.

A control unit 304 controls each unit in the ASIC chip 30 . The control unit 304 executes the generation of the drive signal by the drive unit 300, the discharge of the capacitor C1 by the switch circuit SW1, the sample hold by the sample hold circuit 302, and the AD conversion operation by the ADC 303 based on a predetermined measurement sequence.

[Measurement sequence]
Next, the measurement sequence will be explained.

FIG. 16 is a timing chart explaining the measurement sequence. In the measurement sequence, the control section 304 controls each section to repeat the first period T1 and the second period T2. The first period T1 consists of a first reset period Tr1 and a first charge transfer period Tc1. The second period T2 consists of a second reset period Tr2 and a second charge transfer period Tc2.

The first reset period Tr1 and the second reset period Tr2 are periods during which the switch circuit SW1 is turned on and the capacitor C1 is discharged. The first charge transfer period Tc1 and the second charge transfer period Tc2 are periods in which the switch circuit SW1 is turned off to set the capacitor C1 in a chargeable state, and the charge output from the signal terminal TS of the sensor chip 20 is transferred to the capacitor C1. be.

In the first reset period Tr1, the first drive signal is set to high level and the second drive signal is set to low level. In the first charge transfer period Tc1, the first drive signal is at low level and the second drive signal is at high level. In the second reset period Tr2, the first drive signal is set to low level and the second drive signal is set to high level. In the second charge transfer period Tc2, the first drive signal is set to high level and the second drive signal is set to low level. In this manner, the voltages of the first drive signal and the second drive signal are inverted between the first period T1 and the second period T2, that is, they are in opposite phases. Inverting the voltage means that the voltage is inverted with respect to the reference voltage Vref.

As a result, the output voltage Vo from the operational amplifier OP1 is inverted between the first charge transfer period Tc1 and the second charge transfer period Tc2. The output voltage Vo (first output voltage) in the first charge transfer period Tc1 is sample-held by the first S/H 302a. The output voltage Vo (second output voltage) in the second charge transfer period Tc2 is sample-held by the second S/H 302b.

Each period will be described in detail below. First, in the first reset period Tr1, the switch circuit SW1 is turned on, thereby discharging the capacitor C1 and virtual shorting the operational amplifier OP1. At this time, the high level (VDD) of the first drive signal is applied to the first drive terminal T1, and the low level (GND) of the second drive signal is applied to the second drive terminal T1. As a result, electric charges are accumulated in the humidity detection capacitor 80 and the reference capacitor 81 of the sensor chip 20 with reference to the reference voltage Vref. These total electric charges Q1 are represented by the following formula (1).

Q1=-Cs*(VDD-Vref)+Cr*Vref (1)
Here, Cs is the capacitance of the humidity detection capacitor 80 and Cr is the capacitance of the reference capacitor 81 .

Also, since the switch circuit SW1 is turned on during the first reset period Tr1, the accumulated charge Q2 of the capacitor C1 is zero.

Next, in the first charge transfer period Tc1, the switch circuit SW1 is turned off, the first drive signal is changed to low level (GND), and the second drive signal is changed to high level (VDD). When the switch circuit SW1 is turned off and the inverting input terminal of the operational amplifier OP1 becomes a high impedance (HiZ) state, the total charge of the humidity detection capacitor 80, the reference capacitor 81, and the capacitor C1 is changed based on the law of conservation of charge. The volume remains constant.

As the voltages of the first drive signal and the second drive signal change, the voltage Vi of the inverting input terminal of the operational amplifier OP1 changes. After that, the feedback of the operational amplifier OP1 increases the output voltage Vo until the differential input voltages are balanced.

At this time, the total electric charge Q3 of the humidity detection capacitor 80 and the reference capacitor 81 is represented by the following equation (2).

Q3=-Cr×(VDD-Vref)+Cs×Vref (2)
Also, in the first charge transfer period Tc1, the accumulated charge Q4 of the capacitor C1 is represented by the following equation (3).

Q4=C1×(Vref−Vo) (3)
Since the relationship "Q1+Q2=Q3+Q4" holds according to the law of conservation of charge, the output voltage Vo in the first charge transfer period Tc1 is expressed by the following equation (4).

Vo=VDD×(Cs−Cr)/C1+Vref (4)
The sample hold by the first S/H 302a captures the signal at the end of the first charge transfer period Tc1 when the output voltage Vo has sufficiently increased, and the first S/H 302a receives the output voltage Vo expressed by Equation (4). retained.

Next, the second reset period Tr2 is the same as the first reset period Tr1, but since the voltages of the first drive signal and the second drive signal are inverted from those of the first reset period Tr1, the second reset period Tr2 The total electric charge Q1' of the humidity detection capacitor 80 and the reference capacitor 81 at is represented by the following equation (5).

Q1′=−Cr×(VDD−Vref)+Cs×Vref (5)
The stored charge Q2' of capacitor C1 is zero.

Similarly, in the second charge transfer period Tc2, the voltages of the first drive signal and the second drive signal are inverted from those in the first charge transfer period Tc1. The total electric charge Q3' with the capacitor 81 is expressed by the following equation (6).

Q3′=−Cs×(VDD−Vref)+Cr×Vref (6)
The accumulated charge Q4' of the capacitor C1 in the second charge transfer period Tc2 is the same as the above equation (3).

Since the relationship of "Q1'+Q2'=Q3'+Q4'" is established by the law of conservation of charge, the output voltage Vo in the second charge transfer period Tc2 is expressed by the following equation (7).

Vo=−VDD×(Cs−Cr)/C1+Vref (7)
The second S/H 302b samples and holds the signal at the end of the second charge transfer period Tc2 when the output voltage Vo has sufficiently increased, and the second S/H 302b receives the output voltage Vo represented by Equation (7). retained.

Since the first S/H 302a and the second S/H 302b maintain the current held voltages until the next sample hold time, the ADC 303 outputs the output voltage Vsh1 that matches the output voltage Vo of the above equation (4) and the above equation ( An output voltage Vsh2 that matches the output voltage Vo of 7) is input.

Therefore, the difference value ΔV generated by the ADC 303 as the difference processing unit is represented by the following equation (8).

ΔV=2×VDD×(Cs−Cr)/C1 (8)
In this way, by inverting the voltages of the first drive signal and the second drive signal between the first period T1 and the second period T2, the amplitude of the measurement signal can be doubled.

[Cancellation effect of leakage current]
FIG. 17 is a diagram for explaining the canceling effect of leak currents. In this embodiment, since the ESD protection circuit 60 is connected to the signal terminal TS of the sensor chip 20, a reverse voltage is applied to the PN junction of the ESD protection circuit 60 to generate a reverse current (leak current). there is a possibility. Also, in the switch circuit SW1 included in the operational amplifier OP1 and the switch circuit (not shown) connected to the signal terminal TS, a reverse voltage is applied to the PN junction, and a reverse current (leak current) may occur. have a nature.

Such a leakage current is, for example, the output terminal of the charge amplifier 301, the capacitor C1, the input terminal of the charge amplifier 301, and the ESD current during the first charge transfer period Tc1 and the second charge transfer period Tc2 in which the switch circuit SW1 is in the OFF state. Protection circuit 60, flows in the path of ground. A leak current flows through the switch circuit SW1 to vary the output voltage Vo. The variation δ of the output voltage Vo is expressed by the following equation (9).

δ=I×t/C1 (9)
Here, I represents the magnitude of the leakage current, and t represents the length of each of the first charge transfer period Tc1 and the second charge transfer period Tc2.

When the leakage current flows from the input terminal of the charge amplifier 301 to the ground as shown in the above path, the fluctuation amount δ becomes positive and the output voltage Vo increases. Conversely, when a leak current flows from a high voltage such as VDD to the input terminal of the charge amplifier 301, the amount of variation δ becomes negative, causing the output voltage Vo to drop.

The leakage current path is the same regardless of whether it is the first charge transfer period Tc1 or the second charge transfer period Tc2. This is the same regardless of whether it is the transfer period Tc2.

Therefore, as shown in FIG. 17, when a leak current occurs, the polarity of the variation δ between the output voltage Vo in the first charge transfer period Tc1 and the output voltage Vo in the second charge transfer period Tc2 is the same. , are offset by differential processing by the ADC 303, and the output voltage error of the charge amplifier 301 due to leakage current is suppressed.

In the measurement sequences shown in FIGS. 16 and 17, it is also possible to set the high level of the voltages of the first drive signal and the second drive signal to the low level and the low level to the high level.

[Effect of reducing power consumption]
Next, the effect of reducing power consumption by the laminated structure of the electrodes shown in FIGS. 9 and 13 will be described.

FIG. 18 is a diagram showing an equivalent circuit of an electrode structure including parasitic capacitance. As shown in FIGS. 9 and 13, in this embodiment, the reference electrode 82 is close to the p-type semiconductor substrate 70 , so parasitic capacitance Cp is generated between the reference electrode 82 and the p-type semiconductor substrate 70 . This parasitic capacitance Cp is added between the reference capacitor 81 and the second drive terminal T2, as shown in FIG.

FIG. 19 is a diagram showing an equivalent circuit of a conventional electrode structure as a comparative example for this embodiment. For example, as shown in FIG. 4 of Patent Document 1, a lower electrode as a capacitance detection electrode is provided close to the substrate, so parasitic capacitance Cp is generated between the lower electrode and the substrate. This parasitic capacitance Cp is added to the signal terminal TS as shown in FIG.

Therefore, in this embodiment, the parasitic capacitance Cp generated between the substrate and the substrate is added to the reference capacitor 81 without being added to the signal terminal TS. The drive load connected to the input terminal is reduced, and power consumption is reduced.

[Effect of Pad Arrangement]
Next, the effects of the pad arrangement of this embodiment will be described.

FIG. 20 is a diagram for explaining the effects of the pad arrangement of this embodiment. As shown in FIG. 20, in this embodiment, the pads 24 of the sensor chip 20 are arranged so that the first drive terminal T1 and the second drive terminal T2 are symmetrical about the signal terminal TS. Similarly, the first pads 35 of the ASIC chip 30 are arranged so that the output terminal for the first drive signal and the output terminal for the second drive signal are symmetrical about the input terminal of the charge amplifier 301 .

As a result, the first bonding wires 43 connected to the signal terminal TS, the first drive terminal T1, and the second drive terminal T2 are substantially symmetrical. A parasitic capacitance Cp is generated between the two first bonding wires 43 , and this parasitic capacitance Cp may change due to the moisture absorption of the mold resin 40 .

If the current flowing through the parasitic capacitance Cp were to flow to the input terminal of the charge amplifier 301, the time constant of the signal would deteriorate. However, in the present embodiment, by symmetrically disposing the pads, the sizes of the respective parasitic capacitances Cp are made substantially equal, and the voltages of the first drive signal and the second drive signal are inverted. A first current component flowing into the input terminal of the charge amplifier 301 and a second current component flowing out are generated at the same time. Since the first current component and the second current component are substantially equal in magnitude, they cancel each other out. As a result, the current flow is only Ip in FIG. 20, the current flow to the input terminal of the charge amplifier 301 is suppressed, and deterioration of the time constant is suppressed.

Further, as expressed by the above-described formula (8), the humidity measurement processing unit 31 calculates a value proportional to the difference between the capacitance Cs of the humidity detection capacitor 80 and the capacitance Cr of the reference capacitor 81. Humidity is measured as Therefore, when the parasitic capacitance Cp occurs as shown in FIG. 20, the parasitic capacitance Cp is canceled by measuring the humidity as the difference value between "Cs+Cp" and "Cr+Cp". Therefore, the pad arrangement shown in FIG. 20 prevents deterioration of the measurement accuracy due to the parasitic capacitance Cp.

Note that the signal terminal TS and the first drive terminal T1, and the signal terminal TS and the second drive terminal T2 may not be adjacent to each other. ) may be placed. In FIG. 4, the temperature detection terminal TMP is arranged between the signal terminal TS and the first drive terminal T1, and the ground electrode terminal GND is arranged between the signal terminal TS and the second drive terminal T2. However, since these are substantially fixed potentials, the magnitudes of the respective parasitic capacitances Cp are maintained substantially equal.

[Modified example of shield layer]
Next, modified examples of the shield layer will be described.

In FIG. 12, the ground wiring 107 functions as a shield layer by arranging the ground wiring 107 close to the periphery of the lower electrode 83. In the modification below, however, a separate shield layer is provided around the lower electrode 83. .

FIG. 21 is a plan view showing a first modification of the shield layer. As shown in FIG. 21, in the first modification, a shield layer 400 is formed so as to surround the lower electrode 83 . The shield layer 400 is preferably at a fixed potential (for example, power supply voltage VDD, ground potential GND). Also, the shield layer 400 may be configured to be fixed in potential by the first drive signal or the second drive signal.

FIG. 22 is a plan view showing a second modification of the shield layer. As shown in FIG. 22, in the second modification, a first shield layer 401 and a second shield layer 402 are formed so as to surround the lower electrode 83 .

The first shield layer 401 surrounds a portion (approximately half) of the periphery of the lower electrode 83, and the second shield layer 402 surrounds the other portion (approximately half). The first shield layer 401 and the second shield layer 402 have substantially the same length, width, thickness, and distance from the lower electrode 83 . Therefore, the parasitic capacitance generated between the first shield layer 401 and the lower electrode 83 is substantially equal to the parasitic capacitance generated between the second shield layer 402 and the lower electrode 83 .

The first shield layer 401 is connected to the signal line 202 and is applied with the first drive signal. The second shield layer 402 is connected to the signal line 203 and is applied with the second drive signal.

When the first drive signal and the second drive signal are applied to the first shield layer 401 and the second shield layer 402, respectively, the absolute values of the capacitances of the humidity detection capacitor 80 and the reference capacitor 81 deviate. There is a possibility, but since this deviation is a value that can be estimated, it can be canceled by correcting the output voltage Vo or the like.

The shield layer surrounding the lower electrode 83 may be further divided into three or more.

[Modification of Humidity Measurement Processing Unit]
Next, a modified example of the humidity measurement processing section will be described.

FIG. 23 is a diagram showing the configuration of the humidity measurement processing section 31a according to the modification. As shown in FIG. 23, it differs from the humidity measurement processing section 31 of the above embodiment in that it has a first charge amplifier 301a, a second charge amplifier 301b, and a demultiplexer (DEMUX) 305 .

The first charge amplifier 301a and the second charge amplifier 301b have the same configuration as the charge amplifier 301 of the above embodiment.

A first S/H 302a is connected to the output terminal of the first charge amplifier 301a, and a second S/H 302b is connected to the output terminal of the second charge amplifier 301b. A DEMUX 305 is connected to each input terminal of the first charge amplifier 301a and the second charge amplifier 301b. DEMUX 305 is connected to signal terminal TS of sensor chip 20 . DEMUX 305 includes a switch circuit SW3 and a switch circuit SW4. The signal terminal TS is connected to the first charge amplifier 301a through the switch circuit SW3. The signal terminal TS is connected to the second charge amplifier 301b through the switch circuit SW4.

The DEMUX 305 selectively connects the first charge amplifier 301a and the second charge amplifier 301b to the signal terminal TS under the control of the control unit 304 . Specifically, the DEMUX 305 turns on the switch circuit SW3 during the first period T1 to connect the first charge amplifier 301a to the signal terminal TS, and turns on the switch circuit SW4 during the second period T2. It is turned on to connect the second charge amplifier 301b to the signal terminal TS.

Therefore, in the humidity measurement processing unit 31a according to the present modification, CV conversion is performed by the first charge amplifier 301a in the first period T1, sample-held by the first S/H 302a, and in the second period T2, by the second charge amplifier 301b. CV conversion is performed and sample-and-hold is performed by the second S/H 302b.

Other configurations and operations of the humidity measurement processing unit 31a are the same as those of the humidity measurement processing unit 31 of the above embodiment.

FIG. 24 is a timing chart for explaining the measurement sequence of the humidity measurement processing section 31a according to the modification. In FIG. 24, Vo1 indicates the output voltage (hereinafter referred to as first output voltage) output from the first charge amplifier 301a. Vo2 indicates the output voltage (hereinafter referred to as the second output voltage) output from the second charge amplifier 301b.

In this modification, the first charge amplifier 301a is driven during the first period T1, and the second charge amplifier 301b is driven during the second period T2. That is, the first charge amplifier 301a and the second charge amplifier 301b are driven at different timings. In this modification, the first output voltage Vo1 rises from the reference voltage Vref in the first charge transfer period Tc1 (Phase2) of the first period T1, and the second output voltage Vo1 rises from the reference voltage Vref in the second charge transfer period Tc2 (Phase4) of the second period T2. The output voltage Vo2 drops from the reference voltage Vref.

Ideally, the second output voltage Vo2 should be maintained at the output voltage Vsh2 during the first reset period Tr1 (Phase1), and the first output voltage Vo1 should be maintained at the output voltage Vsh1 during the second reset period Tr2 (Phase3). is.

In order to improve the humidity measurement accuracy, it is desirable that the first capacitor C1 included in the first charge amplifier 301a and the second capacitor C2 included in the second charge amplifier 301b have the same capacitance value. In order to equalize the capacitance values of the first capacitor C1 and the second capacitor C2, it is preferable to place them close to each other in the layout (circuit layout) of the ASIC chip 30 in which the humidity measurement processing section 31a is formed. . By arranging the first capacitor C1 and the second capacitor C2 close to each other, the influence of in-plane variations occurring during manufacturing is reduced, and the difference in capacitance value is reduced.

However, when the first capacitor C1 and the second capacitor C2 are placed close to each other, coupling occurs between them, causing output fluctuations between them. Specifically, the second output voltage Vo2 fluctuates from the output voltage Vsh2 in the first reset period Tr1. Also, the first output voltage Vo1 fluctuates from the output voltage Vsh1 in the second reset period Tr2. When such an output fluctuation occurs, the humidity measurement accuracy is lowered.

Arranging the first capacitor C1 and the second capacitor C2 close to each other in this manner is effective in terms of equalizing the capacitance values, but causes a detrimental effect of fluctuation in the output voltage due to coupling. A configuration for suppressing variations in output voltage due to coupling will be described below.

FIG. 25 is a diagram schematically showing the layout of the humidity measurement processing section 31a in the ASIC chip 30. As shown in FIG. 25, the pad 35a is connected to the pad 24a of the sensor chip 20 as a ground electrode terminal (GND). The pad 35b is connected to the pad 24b of the sensor chip 20 as a signal terminal (TS). The pad 35b is connected to the DEMUX 305 via wiring.

Symbol IN1 indicates the inverting input terminal of the operational amplifier OP1 included in the first charge amplifier 301a. A symbol IN2 indicates an inverting input terminal of the operational amplifier OP2 included in the second charge amplifier 301b.

The first capacitor C1 and the second capacitor C2 each have a rectangular shape and the same size, and are arranged adjacent to each other in the X direction. A shield wiring SL is arranged between the first capacitor C1 and the second capacitor C2. This shield wiring SL extends in the Y direction. The shield wiring SL is connected to the ground wiring 504a connected to the pad 35a.

Also, the first capacitor C1 and the second capacitor C2 are arranged closer to the pad 35b than the inverting input terminals IN1 and IN2.

26 is a cross-sectional view taken along line AA in FIG. 25. FIG. As shown in FIG. 26, the ASIC chip 30 is formed using a p-type semiconductor substrate 500 as a base. First to sixth wiring layers 501 to 506 are formed on a p-type semiconductor substrate 500 . Further, on the p-type semiconductor substrate 500, the p-type semiconductor substrate 500 and wiring layers, and first to sixth plug layers 511 to 516 for connecting between the wiring layers are formed.

The operational amplifiers OP1 and OP2 are composed of CMOS transistors formed of source/drain regions and gate electrodes formed in the p-type semiconductor substrate 500, first to fourth wiring layers 501 to 504, and first to fourth plugs. It is composed of layers 511-514. Further, a ground wiring 504a formed of the fourth wiring layer 504 is arranged on the uppermost layer of the operational amplifiers OP1 and OP2.

The first capacitor C1, the second capacitor C2, and the shield line SL are located above the operational amplifiers OP1 and OP2. The first capacitor C<b>1 , the second capacitor C<b>2 and the shield line SL are composed of the fifth and sixth wiring layers 505 and 506 and the sixth plug layer 516 .

The first capacitor C<b>1 is a parallel plate type capacitor composed of a lower electrode 505 a formed of the fifth wiring layer 505 and an upper electrode 506 a formed of the sixth wiring layer 506 . Similarly, the second capacitor C2 is a parallel plate type capacitor composed of a lower electrode 505b formed of the fifth wiring layer 505 and an upper electrode 506b formed of the sixth wiring layer 506. FIG.

The shield wiring SL is composed of a lower wiring 505c formed of the fifth wiring layer 505 and an upper wiring 506c formed of the sixth wiring layer 506. As shown in FIG. The lower wiring 505 c and the upper wiring 506 c are connected through the sixth plug layer 516 . In addition, the lower wiring 505c is connected to the ground wiring 504a through the fifth plug layer 515. As shown in FIG.

Thus, the shield wiring SL is formed by stacking the lower wiring 505c and the upper wiring 506c with the sixth plug layer 516 interposed therebetween, and is arranged between the first capacitor C1 and the second capacitor C2. Also, the shield wiring SL is set to a fixed potential (ground potential). The shield wiring SL acts to block electrical interaction between the first capacitor C1 and the second capacitor C2 to suppress coupling.

Therefore, according to this modified example, since the first capacitor C1 and the second capacitor C2 are arranged close to each other, the influence of in-plane variations occurring during manufacturing is reduced, and the difference in capacitance value is reduced. In addition, since the fixed-potential shield line SL is arranged between the first capacitor C1 and the second capacitor C2, fluctuations in the output voltage due to coupling between the two can be suppressed.

Note that the potential of the shield line SL is not limited to the ground potential, and may be another fixed potential.

[Other Modifications]
Other various modifications will be described below.

In the above embodiments, the ESD protection circuit is composed of NMOS transistors, but may be composed of P-channel MOS transistors (PMOS transistors).

Further, in the above embodiment, the substrate of the sensor chip 20 is the p-type semiconductor substrate 70, but it is also possible to use an n-type semiconductor substrate.

Further, in the above embodiment, the humidity detection device 10 has a stack structure in which the sensor chip 20 and the ASIC chip 30 are laminated, but the present invention can be applied to humidity detection devices other than the stack structure.

Further, although the humidity detection capacitor 80 and the reference capacitor 81 are provided in the above embodiment, the reference capacitor 81 is not essential and may be omitted. In this case, the second drive circuit DRV2 that outputs the second drive signal is unnecessary. Even in this case, the measurement sequence shown in FIG. 17 suppresses the output voltage error of the charge amplifier 301 due to the leakage current.

In the above-described embodiment, the humidity detection unit 21 is a capacitance change type humidity sensor. good too.

Further, in the above embodiment, the humidity detection device 10 that detects humidity is exemplified as a detection device, but the present invention is also applicable to detection devices that detect physical quantities other than humidity. That is, instead of the humidity detector 21, it is possible to provide a detector that outputs a signal corresponding to a physical quantity other than humidity. That is, instead of the humidity sensitive film 86, it is possible to use a physical quantity detection film whose dielectric constant changes according to a physical quantity other than humidity.

In addition, in the present disclosure, the positional relationship between two elements represented by the words “cover” and “on” means that the first element is indirectly provided on the surface of the second element via another element. It includes both cases where it is provided and cases where it is provided directly.

Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications can be made to the above-described embodiments without departing from the scope of the present invention. and substitutions can be added.

10 humidity detector, 20 sensor chip (first semiconductor chip), 21 humidity detector, 22 temperature detector, 23 heating unit, 24 bonding pad, 30 ASIC chip (second semiconductor chip), 40 mold resin, 50 opening , 60 electrostatic discharge protection circuit, 70 p-type semiconductor substrate, 80 humidity detection capacitor (detection capacitor), 81 reference capacitor, 82 reference electrode (third electrode), 83 lower electrode (second electrode), 84 upper electrode (first electrode), 84a opening, 86 moisture-sensitive film, 107 ground wiring, 300 driving unit, 301 charge amplifier (charge-voltage conversion unit), 301a first charge amplifier (first charge-voltage conversion unit), 301b second charge Amplifier (second charge-voltage conversion unit), 303 AD converter (difference processing unit), 504a ground wiring

Claims (14)

a detection capacitor having a first electrode connected to a first drive terminal and a second electrode connected to a signal terminal, the first electrode and the second electrode having a capacitance that varies according to a physical quantity; and a detection unit composed of
a driving unit for applying a first AC drive signal to the first drive terminal, the driving unit for inverting the voltage of the first drive signal between a first period and a second period;
A charge-voltage converter that converts the charge generated at the signal terminal into a voltage, wherein a first output voltage is generated during the first period, and a second output voltage is inverted during the second period from that of the first period. a charge-voltage converter that generates a voltage;
a difference processing unit that is a differential input AD converter that generates a difference value between the first output voltage and the second output voltage;
a first sample and hold circuit connected to one input terminal of the AD converter;
a second sample and hold circuit connected to the other input terminal of the AD converter;
has
the first sample-and-hold circuit and the second sample-and-hold circuit selectively sample and hold the first output voltage and the second output voltage;
The detection device, wherein the AD converter converts the difference between the output voltage of the first sample-and-hold circuit and the output voltage of the second sample-and-hold circuit into a digital signal and outputs the digital signal. a detection capacitor having a first electrode connected to a first drive terminal and a second electrode connected to a signal terminal, the first electrode and the second electrode having a capacitance that varies according to a physical quantity; and a detection unit composed of
a driving unit for applying a first AC drive signal to the first drive terminal, the driving unit for inverting the voltage of the first drive signal between a first period and a second period;
A charge-voltage converter that converts the charge generated at the signal terminal into a voltage, wherein a first output voltage is generated during the first period, and a second output voltage is inverted during the second period from that of the first period. a charge-voltage converter that generates a voltage;
a difference processing unit that generates a difference value between the first output voltage and the second output voltage;
has
The charge-voltage converter is
a capacitor connected between an input terminal and an output terminal of the charge-voltage converter;
a switch connected in parallel with the capacitor,
the first period includes a first reset period and a first charge transfer period;
the second period includes a second reset period and a second charge transfer period;
During the first reset period and the second reset period, the switch is turned on to discharge the capacitor, and during the first charge transfer period and the second charge transfer period, the switch is turned off to discharge the capacitor. A detection device that is chargeable and transfers charge output from the signal terminal to the capacitor . a detection capacitor having a first electrode connected to a first drive terminal and a second electrode connected to a signal terminal, the first electrode and the second electrode having a capacitance that varies according to a physical quantity; and a detection unit composed of
a driving unit for applying a first AC drive signal to the first drive terminal, the driving unit for inverting the voltage of the first drive signal between a first period and a second period;
A charge-voltage converter that converts the charge generated at the signal terminal into a voltage, wherein a first output voltage is generated during the first period, and a second output voltage is inverted during the second period from that of the first period. a charge-voltage converter that generates a voltage;
a difference processing unit that generates a difference value between the first output voltage and the second output voltage;
has
The charge-voltage converter includes a capacitive element that accumulates charges generated at the signal terminal for generating the first output voltage or the second output voltage,
the first period includes a first charge transfer period for transferring charges generated at the signal terminal to the capacitive element;
the second period includes a second charge transfer period for transferring the charge generated at the signal terminal to the capacitive element;
The detection device , wherein the first charge transfer period and the second charge transfer period are set to the same length . The first charge transfer period and the second charge transfer period are defined by the variation amount of the first output voltage generated by the difference processing section during the first charge transfer period and the variation amount of the first output voltage generated during the second charge transfer period. 4. The detection device according to claim 3, wherein the lengths are set to be the same so as to cancel the fluctuation amount of the second output voltage . The charge-voltage converter has a first charge-voltage converter driven during the first period and a second charge-voltage converter driven during the second period,
A first capacitor included in the first charge-voltage converter and a second capacitor included in the second charge-voltage converter are arranged adjacent to each other and fixed between the first capacitor and the second capacitor. 5. A detection device according to any one of claims 1 to 4, wherein a potential shield wiring is arranged . a detection capacitor having a first electrode connected to a first drive terminal and a second electrode connected to a signal terminal, the first electrode and the second electrode having a capacitance that varies according to a physical quantity; and a detection unit composed of
a driving unit for applying a first AC drive signal to the first drive terminal, the driving unit for inverting the voltage of the first drive signal between a first period and a second period;
A charge-voltage converter that converts the charge generated at the signal terminal into a voltage, wherein a first output voltage is generated during the first period, and a second output voltage is inverted during the second period from that of the first period. a charge-voltage converter that generates a voltage;
a difference processing unit that generates a difference value between the first output voltage and the second output voltage;
has
The charge-voltage converter has a first charge-voltage converter driven during the first period and a second charge-voltage converter driven during the second period,
A first capacitor included in the first charge-voltage converter and a second capacitor included in the second charge-voltage converter are arranged adjacent to each other and fixed between the first capacitor and the second capacitor. A detection device in which a potential shield wiring is arranged . The detection device according to any one of claims 2 to 6 , wherein the difference processing unit is a differential input AD converter. 8. The detection device according to any one of claims 2 to 7, comprising a sample-and-hold circuit for sampling and holding the first output voltage and the second output voltage. The detection unit further includes a third electrode connected to a second drive terminal, and a reference capacitor whose capacitance does not change according to the physical quantity is composed of the second electrode and the third electrode,
The detecting device according to any one of claims 1 to 8, wherein the driving section applies to the second driving terminal a second AC driving signal having a phase opposite to that of the first driving signal. The detection device according to any one of claims 1 to 9, wherein the physical quantity is humidity. The third electrode is provided above the substrate,
The second electrode is provided above the third electrode via an insulating film,
10. The detection device according to claim 9 , wherein the first electrode is provided above the second electrode via a humidity sensitive film. a first semiconductor chip including the detection capacitor and the reference capacitor;
a second semiconductor chip including the driver and the charge-voltage converter;
12. The detection device of claim 11 , comprising: 13. The detection device according to claim 12 , wherein said first semiconductor chip is laminated on said second semiconductor chip. A switched-capacitor charge-voltage conversion circuit that converts a charge generated at a signal terminal into a voltage ,
The signal terminal is connected to a second electrode forming a detection capacitor between the first electrode and the first electrode connected to a drive terminal to which an AC drive signal whose voltage is inverted between the first period and the second period is applied. is a terminal with
a first charge-voltage conversion unit including a first capacitor and driven during the first period;
a second charge-voltage converter including a second capacitor arranged adjacent to the first capacitor and driven during the second period;
The first charge-voltage converter generates a first output voltage during the first period,
The second charge-voltage converter generates a second output voltage in the second period, the voltage of which is inverted from that in the first period, and
A charge-voltage conversion circuit , wherein a fixed-potential shield wiring is arranged between the first capacitor and the second capacitor.

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