JP7220264B1 - Cell balance circuit, cell balance device, charge/discharge control circuit, charge/discharge control device, and battery device - Google Patents

Abstract

A cell balance circuit and the like in which energy loss associated with cell balance operation is reduced is provided. A cell balance circuit (15) is connected in parallel to a secondary battery including an assembled battery in which a first cell to an nth (n is a plurality) cells are connected in series from a positive electrode to a negative electrode, and n cells are connected in parallel. a switch circuit 16 that can open and close paths connected to each of the n cells; and a depletion type FET 17 as a connected cell discharge resistor. The switch circuit 16 switches the first cell when at least one of the charger non-connected state in which the charger is not connected to the external terminal and the discharge from the secondary battery to the load device is detected. to n-th cells are switched to a cell balance stop state in which they are not connected to the depletion type FET 17 . [Selection drawing] Fig. 3

Description

The present invention relates to a cell balance circuit, a cell balance device, a charge/discharge control circuit, a charge/discharge control device, and a battery device.

There is an assembled battery configured by connecting a plurality of rechargeable secondary battery cells in series. In the assembled battery as a secondary battery, the voltage of each battery cell becomes different as the charging and discharging are repeated many times. In an assembled battery, if the voltages of each battery cell are significantly different, when the assembled battery is charged, the battery cell with the higher voltage will be overcharged and charging will stop, and when the battery is discharged, the battery cell with the lower voltage will be overcharged. There is a risk that the battery will discharge and stop discharging, and that charging and discharging will only be possible for a short period of time. Therefore, in the assembled battery, it is preferable that the voltage of each battery cell is adjusted to be substantially uniform.

Therefore, from the viewpoint of suppressing the voltage deviation between battery cells within a predetermined range, there is a cell balancing technology that operates (hereinafter referred to as "cell balancing operation") to equalize the voltages between battery cells in the assembled battery ( For example, see Patent Document 1).

The cell balance operation disclosed in Patent Literature 1 is an operation in which a current flows through a discharge path from a battery cell with a relatively high voltage. In this cell balancing operation, by discharging a battery cell with a relatively high voltage, the voltage is aligned with the voltage of other battery cells with a relatively low voltage. In the charge/discharge control circuit disclosed in Patent Document 1, the cell balancing operation is performed until the voltage difference between the battery cell with the maximum voltage and the battery cell with the minimum voltage falls within a predetermined range.

JP 2020-124094 A

However, in the above-described conventional cell balancing device that performs the cell balancing operation, if the voltage difference between the battery cell with the maximum voltage and the battery cell with the minimum voltage is not within a predetermined range, the cell balancing operation is continued and the individual No consideration is given to the state of the battery, such as whether the battery cell is overcharged, whether the charger is connected, or whether the assembled battery is discharging to the device. Therefore, in the conventional cell balancing device described above, the cell balancing operation cannot be performed according to the state of the battery or the connection with the charger or the load device, and there is room for improvement from the viewpoint of energy saving. .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a cell balancing circuit, a cell balancing device, a charging/discharging control circuit, a charging/discharging control device, and a battery device that reduce the energy loss accompanying the cell balancing operation. With the goal.

In the cell balance circuit according to the present invention, in order to solve the above-described problems, the first cell to the n-th cell are connected in series from the positive electrode to the negative electrode, where n is a natural number of 2 or more, and the number of cells to be connected in series is n. A circuit that is connected in parallel to a secondary battery including a assembled battery and adjusts the individual voltages of n cells from the first cell to the n-th cell, wherein each of the n cells: A switch circuit including at least one switch in a path connecting its own positive terminal and its own negative terminal, and capable of opening and closing each of the n paths based on a control signal supplied to the at least one switch and cell discharge resistors respectively connected to the n cells from the first cell to the n-th cell via the switch circuit, and k, which is a natural number equal to or less than n, is connected from the positive electrode to the negative electrode. In the case where the cells are connected in series toward each other, the switch circuit detects that the secondary battery is discharging to the load device connected to the external positive electrode terminal and the external negative electrode terminal. , based on the supplied control signal, each of the first cell to the n-th cell is switched to a cell balance stop state in which the cell discharge resistor is not connected, and the k-th cell is switched from the positive electrode to the negative electrode. The voltage of the k-th cell, which is a cell, is equal to or higher than the overcharge detection voltage at which the overcharge protection operation is started, and the charger for charging the secondary battery is connected to the external positive terminal and the external negative terminal. When any one of the charger connected state, the overcharge detection voltage or higher, and the discharge from the secondary battery to the load device being not started is detected, the It is characterized by switching to a k-th cell discharge state in which the k-th cell is discharged through the cell discharge resistor based on a control signal.
Further, a cell balance device, a charge/discharge control circuit, a charge/discharge control device, and a battery device according to the present invention include the cell balance circuit in order to solve the above-described problems.

ADVANTAGE OF THE INVENTION According to this invention, the energy loss accompanying cell balance operation|movement can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic which shows the structural example of the cell balance circuit, charge/discharge control circuit, charge/discharge control apparatus, and battery apparatus which concern on the 1st Embodiment of this invention. 2 is a schematic diagram showing a detailed configuration example of a charge/discharge control circuit according to the first embodiment; FIG. 3 is a schematic diagram showing a detailed configuration example of a cell balance circuit according to the first embodiment; FIG. It is a schematic diagram showing an example of composition of a cell balance circuit, a cell balance device, a charge and discharge control circuit, a charge and discharge control device, and a battery device concerning a 2nd embodiment of the present invention. FIG. 5 is a schematic diagram showing a detailed configuration example of a charge/discharge control circuit according to a second embodiment; It is a schematic diagram showing a detailed configuration example of a cell balance circuit and a cell balance device according to the second embodiment.

Hereinafter, a cell balance circuit, a cell balance device, a charge/discharge control circuit, a charge/discharge control device, and a battery device according to embodiments of the present invention will be described with reference to the drawings.

[First embodiment]
FIG. 1 is a schematic diagram showing a configuration example of a cell balance circuit, a charge/discharge control circuit, a charge/discharge control device, and a battery device according to the first embodiment.

The battery device 1 and the charge/discharge control circuit 10 are examples of the battery device and the charge/discharge control circuit according to the first embodiment, respectively. The battery device 1 includes a secondary battery 2 including a so-called multi-cell assembled battery, an external positive terminal P+ and an external negative terminal P-, a discharge control FET (Field Effect Transistor) 3, a charge control FET 4, a secondary and a charge/discharge control circuit 10 for controlling charge/discharge of the battery 2 . From the viewpoint of simplifying the description, the external positive terminal P+ and the external negative terminal P- may be collectively referred to as "external terminals" in the following description.

The charge/discharge control device 20 is an example of the charge/discharge control device according to the first embodiment. The charge/discharge control device 20 includes an external positive terminal P+, an external negative terminal P−, a discharge control FET3, a charge control FET4, and a charge/discharge control circuit . That is, the charge/discharge control device 20 is a device obtained by omitting the secondary battery 2 from the battery device 1 .

The secondary battery 2 is a so-called multi-cell battery including an assembled battery in which a plurality of battery cells (hereinafter simply referred to as "cells") are connected in series. That is, if the number of cells connected in series is "n", n is a natural number of 2 or more, that is, plural. n cells 2_1, .

The external positive terminal P+ and the external negative terminal P- are terminals for connecting to external devices (not shown) such as a charger and a load. In the battery device 1, a path connecting the external positive terminal P+ and the external negative terminal P- (hereinafter referred to as "path between external terminals") includes, for example, the secondary battery 2 in order from the external positive terminal P+ side. , an overcurrent detection resistor 5, a discharge control FET3 and a charge control FET4 are connected.

The battery device 1 and the charge/discharge control device 20 are provided with a discharge control FET3 and a charge control FET4 on the external negative terminal P- side, that is, on the low side. Both the discharge control FET3 and the charge control FET4 are NMOS transistors, and their drains are connected to each other.

The discharge control FET3 has a gate connected to the discharge control signal output terminal DO, a drain as one end connected to the drain of the charge control FET4, and a source as the other end connected to one end of the overcurrent detection resistor 5. and includes

The charge control FET4 has a gate connected to the charge control signal output terminal CO, a source connected to the external negative terminal P−, and a drain connected to the drain of the discharge control FET3. contains.

The charge/discharge control circuit 10 is composed of, for example, one semiconductor chip, that is, a semiconductor integrated circuit. The charge/discharge control circuit 10 includes positive power supply terminals VDD and VDD2, a negative power supply terminal VSS, cell connection terminals VC1a, . It has a charge control signal output terminal CO, a discharge control signal output terminal DO, an external negative voltage input terminal VM, and an overcurrent detection terminal VINI.

The positive power supply terminal VDD is connected to the positive electrode 2a via a resistor R1, and is supplied with voltage from the positive electrode 2a of the secondary battery 2. As shown in FIG. The positive power supply terminal VDD2 is connected to the external positive terminal P+ and the positive electrode 2a, and is supplied with the voltage from the positive electrode 2a of the secondary battery 2. The negative power supply terminal VSS is connected to the negative electrode 2b and supplied with voltage from the negative electrode 2b.

The cell connection terminal VC1a is connected to the contact points of the adjacent first cell 2_1 and second cell 2_2, that is, the negative terminal of the first cell 2_1 and the positive terminal of the second cell 2_2 via a resistor R2. , VC(n-1)a are connected to the negative terminal of the second cell 2_2 via resistors R3, . and the positive terminal of the third cell 2_3, .

Here, the ends (left ends in FIG. 1) of the resistors R1, . , . . , VC(n−1)a and the negative power supply terminal VSS, that is, the end opposite to the first end is referred to as the second end (the right end in FIG. 1).

A capacitor C1 for suppressing voltage fluctuation is connected between the contact point between the second end of the resistor R1 and the positive power supply terminal VDD and the contact point between the negative electrode 2b and the negative power supply terminal VSS. , Cn connect the second terminals of the resistors R2, . . . , Rn and the cell connection terminals VC1a, . and a contact between the negative electrode 2b and the negative power supply terminal VSS.

The charge control signal output terminal CO is a terminal for outputting to the outside of the charge/discharge control circuit 10 a charge control signal that is generated in the charge/discharge control circuit 10 and controls the stop and permission of charging of the secondary battery 2 . A charge control signal output terminal CO is connected to the gate of the charge control FET4.

The discharge control signal output terminal DO is a terminal for outputting to the outside of the charge/discharge control circuit 10 a discharge control signal that is generated within the charge/discharge control circuit 10 and controls whether to stop or permit the discharge of the secondary battery 2 . A discharge control signal output terminal DO is connected to the gate of the discharge control FET3.

The external negative voltage input terminal VM is connected via a resistor 6 to the external negative terminal P− and the source of the charge control FET4.

The overcurrent detection terminal VINI is connected to one end of the overcurrent detection resistor 5 and the source of the discharge control FET3.

FIG. 2 is a schematic diagram showing a more detailed configuration example of the charge/discharge control circuit 10 as the charge/discharge control circuit according to the first embodiment.

The charge/discharge control circuit 10 includes positive power supply terminals VDD and VDD2, a negative power supply terminal VSS, cell connection terminals VC1a, . In addition to the charge control signal output terminal CO, the discharge control signal output terminal DO, the external negative voltage input terminal VM, and the overcurrent detection terminal VINI, a battery voltage detection circuit 11, an overcurrent detection and cancellation circuit 12, and a control circuit. 13 and a cell balance circuit 15 .

The battery voltage detection circuit 11 is a circuit that detects the voltage between terminals included in the secondary battery 2 . The battery voltage detection circuit 11 is connected to a terminal connected to the positive power supply terminal VDD, a terminal connected to the negative power supply terminal VSS, and cell connection terminals VC1a, . . . , VC(n−1)a. and a terminal connected to the control circuit 13 .

The overcurrent detection and release circuit 12 has an overcurrent detection circuit for detecting an overcurrent state and an overcurrent release circuit for releasing the overcurrent state and transitioning from the overcurrent state to the normal state. there is The overcurrent detection and cancellation circuit 12 includes a terminal connected to the positive power supply terminal VDD, a terminal connected to the overcurrent detection terminal VINI, a terminal connected to the external negative voltage input terminal VM, and the control circuit 13. and a terminal connected to the

The control circuit 13 is connected to a terminal connected to the positive power supply terminal VDD, a terminal connected to the negative power supply terminal VSS, a terminal connected to the charge control signal output terminal CO, and a discharge control signal output terminal DO. a terminal connected to the external negative voltage input terminal VM; a terminal connected to the battery voltage detection circuit 11; a terminal connected to the overcurrent detection and cancellation circuit 12; a terminal;

Further, the control circuit 13 controls charging and discharging of the secondary battery 2 based on detection signals of the voltage of the secondary battery 2 from the battery voltage detection circuit 11 and the voltages of the cells 2_1, . A first control circuit (not shown in FIG. 2) that generates a control signal and supplies it to the charge control signal output terminal CO and the discharge control signal output terminal DO, and the voltage of the secondary battery 2 from the battery voltage detection circuit 11 and each . . , 2_n, the voltage of the negative power supply terminal, and the voltage of the external negative voltage input terminal. and a second control circuit (not shown in FIG. 2) that generates a control signal and supplies it to the cell balance circuit 15 .

The cell balance circuit 15 is a circuit that performs a cell balance operation to adjust individual voltages of the first cell 2_1 to the n-th cell 2_n. The cell balance circuit 15 includes a terminal connected to the positive power supply terminal VDD2, a terminal connected to the negative power supply terminal VSS, a terminal connected to the control circuit 13, and cell connection terminals VC1b, . -1) terminals respectively connected to b;

FIG. 3 is a schematic diagram showing a more detailed configuration example of the cell balance circuit 15 as the cell balance circuit according to the first embodiment.

The cell balance circuit 15 includes a switch circuit 16 and a depletion type FET 17 as a cell discharge resistor.

The switch circuit 16 is provided between the positive power supply terminal VDD2, the negative power supply terminal VSS, the cell connection terminals VC1b, .

The switch circuit 16 has at least one switch in each of the n paths connecting the positive terminal and the negative terminal of the cells 2_1, . . . , 2_n. It has 2n switches 16_1, 16_2, . The switch circuit 16 includes switches 16_1, 16_2, . It is configured to be able to open and close individual paths.

Here, in the switches 16_1, 16_2, . Terminals, that is, ends connected to the positive terminals of the cells 2_1, . . . , 2_n are referred to as first ends. An end connected to the drain or source of the depletion type FET 17 is called a second end.

The switches 16_1, 16_2, . . . , 16_(2n-1), 16_2n each include a first end, a second end, and a control end. Each of the switches 16_1, 16_2, . ) can be switched.

Among the switches 16_1, 16_2, . is connected to the drain of the depletion type FET 17 . The remaining half (n pieces) of switches 16_3, .

Here, a group of switches 16_1 and switches 16_2, . It is called a first switch group. Also, a group of switches 16_3, . It is called a second switch group.

The n switches 16_1 and switches 16_2, . . The n switches 16_3, . .

The depletion type FET 17 as a cell discharge resistor is, for example, an N-type depletion type MOSFET. The depletion type FET 17 has its gate and source connected (short-circuited).

Next, operations of the cell balance circuit 15, the charge/discharge control circuit 10, the charge/discharge control device 20, and the battery device 1 configured as described above will be described.

The charge/discharge control circuit 10, the charge/discharge control device 20, and the battery device 1 are in a normal state, a discharge prohibited state, a charge prohibited state, and an overcurrent detection state, similarly to the conventional charge/discharge control circuit, charge/discharge control device, and battery device. , that is, the charging/discharging control operation of the secondary battery 2 is performed. The overcurrent detection state includes a discharge overcurrent detection state in which an overcurrent is detected during discharging of the secondary battery 2 and a charge overcurrent detection state in which an overcurrent is detected during charging of the secondary battery 2 . In addition, the charge/discharge control circuit 10, the charge/discharge control device 20, and the battery device 1 perform a cell balance operation for adjusting individual voltages of the first cell 2_1 to the n-th cell 2_n.

In the charge/discharge control circuit 10, the power supply voltage, that is, the voltage domain corresponding to the voltage difference between the voltage Vdd of the positive power supply terminal VDD2 and the voltage Vss of the negative power supply terminal VSS is divided into n+1 voltage domains. Here, the n+1 voltage regions are referred to as a first voltage region, a second voltage region, .

Further, the charge/discharge control circuit 10 (more specifically, the control circuit 13) has an overcharge detection voltage and an overcharge detection voltage for starting an overcharge protection operation for each of the first cell 2_1 to the n-th cell 2_n. An overcharge release voltage is set to release (stop) the protection operation. In addition, the charging/discharging control circuit 10 (more specifically, the control circuit 13) has the following conditions for canceling the overcharge protection operation: 2 to start discharge to the load connected between the external terminals.

First, the charge/discharge control operation of the secondary battery 2 will be described. In the charge/discharge control circuit 10 , the charge/discharge control device 20 and the battery device 1 , the battery voltage detection circuit 11 detects the voltage between its terminals and supplies a signal indicating the detected voltage to the control circuit 13 .

The overcurrent detection and release circuit 12 detects the presence or absence of overcurrent based on the voltage input from the overcurrent detection terminal VINI, and supplies a signal indicating the overcurrent detection state or overcurrent release state to the control circuit 13. . The overcurrent detection and cancellation circuit 12 detects an overcurrent, and outputs an overcurrent detection signal when a predetermined time has passed since the transition from the overcurrent non-detection state to the overcurrent detection state.

On the other hand, the overcurrent detection and release circuit 12 outputs a signal for releasing the overcurrent state based on the voltage input from the external negative voltage input terminal VM in the overcurrent detection state. A signal indicating the determination result by the overcurrent detection and release circuit 12 is supplied to the control circuit 13 .

The control circuit 13 controls the discharge control FET 3 and the charge control based on at least one of the signal output from the battery voltage detection circuit 11, the determination result determined by the overcurrent detection and release circuit 12, and the voltage Vm of the external negative voltage input terminal VM. By generating a charge/discharge control signal for controlling ON/OFF of the FET4 and supplying the generated charge/discharge control signal to the discharge control signal output terminal DO and the charge control signal output terminal CO, the discharge control FET3 and the charge control FET4 are controlled. Control on/off. Generation of the charge/discharge control signal is performed by the first control circuit of the control circuit 13 .

Next, the cell balance operation of the first cell 2_1 to the n-th cell 2_n will be described. An operation start condition and an operation stop condition for the cell balance operation are set in the control circuit 13 . In the charge/discharge control circuit 10, the cell balance operation is started when the operation start condition is satisfied, and the cell balance operation is stopped when the operation stop condition is satisfied.

The operation start condition of the cell balance operation is that a charger is connected to the external positive terminal P+ and the external negative terminal P-, charging of the secondary battery 2 is started, and any of the first cell 2_1 to the n-th cell 2_n is overcharged. In addition to being in an overcharge state in which the voltage is higher than the charge detection voltage, the following condition (I) is a state in which the charger is connected to the external positive terminal P+ and the external negative terminal P- (hereinafter referred to as "charging or (II) the charger is disconnected from the external positive terminal P+ and the external negative terminal P- and is not connected to the external positive terminal P+ and the external negative terminal P-. (hereinafter referred to as "charger disconnected state"), but the discharge from the secondary battery 2 to the load connected to the external positive terminal P+ and the external negative terminal P- has not started,
is to satisfy

Whether or not the overcharge state exists and whether or not the condition (I) or (II) is satisfied is determined by the control circuit 13 based on the voltage detected by the battery voltage detection circuit 11 and the determination made by the overcurrent detection and cancellation circuit 12. As a result, determination is made based on at least one of the voltage Vss of the negative power supply terminal VSS and the voltage Vm of the external negative voltage input terminal VM.

When the charge/discharge control circuit 10 detects an overcharge state, the charge control FET 4 is turned off to stop charging the secondary battery 2 . Furthermore, if the condition (I) or (II) for starting the cell balance operation is satisfied, transition to the cell balance operation state is permitted.

That is, the charge/discharge control circuit 10 determines that the voltage of the secondary battery 2 detected by the battery voltage detection circuit 11 is any of the first voltage region to the (n+1)th voltage region after the condition for starting the cell balance operation is satisfied. depending on whether the voltage region of In either case, the state transitions to the cell balance stop state in which the depletion type FET 17 is not connected.

Here, if the order of the first cell 2_1 to the n-th cell 2_n from the positive electrode 2a to the negative electrode 2b is "k", k is a natural number that satisfies 1≤k≤n, that is, a natural number equal to or less than n. Using this k, the relationship between the divided n+1 voltage regions and the cell balance operating state and cell balance stopped state will be described more specifically.

When the voltage of the secondary battery 2 is in the k-th voltage region, the depletion type FET 17 is connected in parallel with the k-th cell 2_k (hereinafter referred to as "k-th cell discharge state"). That is, the cell balance operation state includes n cell discharge states from the first cell discharge state to the nth cell discharge state. Moreover, when the voltage of the secondary battery 2 exists in the (n+1)-th voltage region, the cell balance is stopped.

The control signal for transitioning between the cell balancing operating state and the cell balancing stopped state, that is, the control signal for adjusting the individual voltages of the first cell 2_1 to the n-th cell 2_n is generated by the second control circuit of the control circuit 13. done.

When the voltage of the k-th cell 2_k exceeds the overcharge release voltage after satisfying the operation start condition of the cell balancing operation, the second control circuit of the control circuit 13 puts the charge/discharge control circuit 10 into the k-th cell discharge state. , 16_(2n-1), and 16_2n.

Switches 16_1, 16_2, . A path in the switch circuit 16 is switch-controlled, and the depletion type FET 17 is connected in parallel with the k-th cell 2_k. When the depletion type FET 17 is connected in parallel with the k-th cell 2_k, a cell balance current flows so as to lower the voltage of the k-th cell 2_k.

In the k-th cell discharging state, two of the 2n switches 16_1, 16_2, . , the remaining 2n−2 are opened. Any one of the first cell 2_1 to the n-th cell 2_n and the depletion type FET 17 are connected in parallel by such open/close control of the switches 16_1 to 16_2n.

For example, when the charge/discharge control circuit 10 is caused to transition to the first cell discharge state (when k=1), the switches 16_1 and 16_3 are closed while the remaining switches 16_2, 16_4, . . . , 16_2n are opened. . . , 16_2n, the cell balance circuit 15 is connected to the first cell 2_1 via the positive power supply terminal VDD2 and the cell connection terminal VC1b. That is, the depletion type FET 17 is connected in parallel with the first cell 2_1.

When the charge/discharge control circuit 10 transitions to the n-th cell discharge state (when k=n), two switches 16_(2n−2) and 16_2n out of the switches 16_1 to 16_2n are closed, while the remaining switches 16_(2n−2) and 16_2n are closed. n-2 switches 16_1, . . . , 16_(2n-3), 16_(2n-1) are opened. The depletion type FET 17 is connected in parallel with the n-th cell 2_n by such open/close control of the switches 16_1 to 16_2n.

When the voltage of the secondary battery 2 is in the (n+1)th voltage region, the charge/discharge control circuit 10 enters the cell balance stop state, but the next cell balance operation stop condition (i) does not exceed the overcharge detection voltage. or (ii) (a) discharge from the secondary battery 2 to the load device has started and (b) the charger is not connected. If at least one of the conditions is satisfied, regardless of the voltage of the secondary battery 2, the charge/discharge control circuit 10 enters the cell balance stop state.

Condition (i) and condition (ii) are examples of timing when it is preferable to suppress the discharge of the cells 2_1 to 2_n. The charge/discharge control circuit 10 is configured to enter the cell balance stop state at the timing when it is preferable to suppress the discharge of the cells 2_1 to 2_n. Whether the condition (i) or (ii) is satisfied is determined by the control circuit 13 based on at least one of the voltage detected by the battery voltage detection circuit 11, the voltage Vss of the negative power supply terminal VSS, and the voltage Vm of the external negative voltage input terminal VM. decision based on

When the charge/discharge control circuit 10 is in the cell balance stop state, the switches 16_1, 16_2, . ), 16_2n are controlled. For example, while the switch 16_2n is closed, the remaining switches 16_1, . . . , 16_(2n-1) are opened.

Of the conditions (i) and (ii), the conditions (i) and (ii)(a) are also conditions for canceling the operation of the overcharge protection. When condition (i) and condition (ii)(a) are satisfied, the charge control FET 4 transitions from off to on, and the charge/discharge control circuit 10 enters a cell balance operation stop state. In addition, when the conditions (ii) and (b) are satisfied, the charge/discharge control circuit 10 enters the cell balance operation stop state without canceling the overcharge protection operation.

As described above, in the charge/discharge control circuit 10, the charge/discharge control device 20, and the battery device 1, the cell balance operation state is controlled by controlling the opening/closing of the switches 16_1, 16_2, . (from the first cell discharge state to the nth cell discharge state) and the cell balance stop state.

Also, when switching to the cell balance stop state, for example, when it is determined that the secondary battery 2 is discharging to the load device or the charger is not connected, discharge of the cells 2_1 to 2_n is suppressed. At the preferred timing, even if the voltage difference between the cell with the maximum voltage and the cell with the minimum voltage is not within the predetermined range, the cell balancing operation is interrupted to stop the cell balancing operation.

According to the present embodiment, the cell balance circuit 15 changes the state of the secondary battery 2 (the first cell 2_1 to the n-th cell 2_n) or the connection with the charger to determine the cell balance operation state and the cell balance stop state. You can switch between states. When the voltage difference between the maximum voltage cell and the minimum voltage cell is not within a predetermined range, the cell balance is stopped until the voltage difference between the maximum voltage cell and the minimum voltage cell is within the predetermined range. This is a major difference from the conventional cell balance device that cannot switch between states.

As described above, the cell balance circuit 15, the charge/discharge control circuit 10 including the cell balance circuit 15, the charge/discharge control device 20, and the battery device 1 stop the cell balance operation at the timing when it is desired to suppress the discharge of the cells 2_1 to 2_n. It has a switch circuit 16 that can Therefore, according to the present embodiment, even when the voltage difference between the cell with the maximum voltage and the cell with the minimum voltage does not fall within a predetermined range, at the timing when it is preferable to suppress the discharge of the cells 2_1 to 2_n. The cell balance operation can be stopped, and the energy loss associated with the cell balance operation can be reduced.

On the other hand, the cell balance circuit 15, the charge/discharge control circuit 10 including the cell balance circuit 15, the charge/discharge control device 20, and the battery device 1 are in a state such as a charger connection state or a state in which the secondary battery 2 has not started discharging. In addition, the cell balancing operation is permitted, that is, the cell balancing operation is executed without stopping at the timing when it is not necessary to suppress the discharge of the cells 2_1 to 2_n. For example, by leaving the charger connected for a long time, or by leaving only the secondary battery 2 without connecting the device to the external terminal after charging, the cell balance operation is executed, thereby suppressing excessive energy loss. can also reduce the voltage difference between the maximum voltage cell and the minimum voltage cell.

As described above, the cell balance circuit 15, the charge/discharge control circuit 10 including the cell balance circuit 15, the charge/discharge control device 20, and the battery device 1 include the n positive terminals of the first cell 2_1 to the n-th cell 2_n and the switches. A depletion type FET 17 having a first end connected via a circuit 16 and a second end connected via a switch circuit 16 to n negative terminals of the first cell 2_1 to the n-th cell 2_n. there is In the cell balance circuit 15, the charge/discharge control circuit 10 including the cell balance circuit 15, the charge/discharge control device 20, and the battery device 1, if there is one depletion type FET 17, the switches 16_1 to 16_2n can be opened/closed (opened or shorted). By switching, each of the first cell 2_1 to the n-th cell 2_n can be alternatively discharged.

Therefore, in the cell balance circuit 15, the charge/discharge control circuit 10 including the cell balance circuit 15, the charge/discharge control device 20, and the battery device 1, the configuration of the cell discharge resistance can be simplified, and the heat generating portion can be limited to one portion. can be done.

[Second embodiment]
FIG. 4 is a schematic diagram showing a configuration example of a cell balance device, a charge/discharge control circuit, a charge/discharge control device, and a battery device according to the second embodiment.

The battery device 61, charge/discharge control device 60, and charge/discharge control circuit 50 are examples of the battery device, charge/discharge control device, and charge/discharge control circuit, respectively, according to the second embodiment. The battery device 61 and the charge/discharge control device 60 are different from the battery device 1 and the charge/discharge control device 20 in that they include a charge/discharge control circuit 50 instead of the charge/discharge control circuit 10, but other points are is similar.

In contrast to the charge/discharge control circuit 10, the charge/discharge control circuit 50 has the first control circuit and the cell balance circuit 15 formed on two different semiconductor chips 30 and 40. The control circuit 33 having the first control circuit and the control circuit 43 having the second control circuit are provided instead of the control circuit 13 having the first control circuit and the second control circuit, and the control circuit 43 and the cell balance circuit 15 are independent. It is different in that it is configured as a cell balance device 41 and that an output circuit 34 that connects the control circuit 33 and the control circuit 43 is further provided in the semiconductor chip 30, except for the above differences. is configured in the same manner as the charge/discharge control circuit 10 .

Therefore, in the present embodiment, differences between the charge/discharge control circuit 50 and the charge/discharge control circuit 10 will be mainly described, and the cell balance circuit 15, the charge/discharge control circuit 10, the charge/discharge control device 20, and the battery device 1 will be described. Description is omitted.

The charge/discharge control circuit 50 is dispersedly formed on a plurality of semiconductor chips 30 and 40, for example two. That is, the charge/discharge control circuit 50 includes a circuit formed on the semiconductor chip 30 (see FIG. 5) and a circuit formed on the semiconductor chip 40 (see FIG. 6).

A semiconductor chip 30 as a first semiconductor chip includes a positive power supply terminal VDD, a negative power supply terminal VSS, cell connection terminals VC1a, . In addition to the signal output terminal CO, discharge control signal output terminal DO, external negative voltage input terminal VM, and overcurrent detection terminal VINI, a cell balance control signal terminal CB_CTL is provided.

A semiconductor chip 40 as a second semiconductor chip includes a positive power supply terminal VDD corresponding to the positive power supply terminal VDD2 in the charge/discharge control circuit 10, cell connection terminals VC1b, . )b, a negative power supply terminal VSS and a signal input terminal CTL are provided.

In the semiconductor chip 30, a positive power supply terminal VDD, a negative power supply terminal VSS, cell connection terminals VC1a, . The connection destinations of the terminals VM and the overcurrent detection terminal VINI are the same as those of the charge/discharge control circuit 10 . The cell balance control signal terminal CB_CTL is connected to the signal input terminal CTL.

In the semiconductor chip 40, the positive power supply terminal VDD is connected to the positive electrode 2a and the external positive terminal P+. The cell connection terminals VC1, . connected to the terminal. The negative power supply terminal VSS is connected to the negative electrode 2b.

FIG. 5 is a schematic diagram showing a more detailed configuration example of a circuit formed in the semiconductor chip 30 in the charge/discharge control circuit 50 as the charge/discharge control circuit according to the second embodiment.

FIG. 6 shows a circuit formed in a semiconductor chip 40 in a charge/discharge control circuit 50 as a charge/discharge control circuit according to the second embodiment, that is, a cell balance circuit and a cell balance device according to the second embodiment. is a schematic diagram showing a detailed configuration example of.

The charge/discharge control circuit 50 includes a positive power supply terminal VDD, a negative power supply terminal VSS, cell connection terminals VC1a, . A voltage input terminal VM, an overcurrent detection terminal VINI, a cell balance control signal terminal CB_CTL, a battery voltage detection circuit 11, an overcurrent detection and release circuit 12, a control circuit 33, an output circuit 34, and a signal input terminal CTL. , a control circuit 43, a cell balance circuit 15, and cell connection terminals VC1, . . . , VC(n−1).

In the charge/discharge control circuit 50, the semiconductor chip 30 includes a positive power supply terminal VDD, a negative power supply terminal VSS, cell connection terminals VC1a, . Signal output terminal DO, external negative voltage input terminal VM, overcurrent detection terminal VINI, cell balance control signal terminal CB_CTL, battery voltage detection circuit 11, overcurrent detection and release circuit 12, control circuit 33, and output circuit 34 and are formed.

The control circuit 33 is connected to a terminal connected to the positive power supply terminal VDD, a terminal connected to the negative power supply terminal VSS, a terminal connected to the charge control signal output terminal CO, and a discharge control signal output terminal DO. a terminal connected to the external negative voltage input terminal VM; a terminal connected to the battery voltage detection circuit 11; a terminal connected to the overcurrent detection and cancellation circuit 12; and have

In addition, the control circuit 33 generates a control signal for controlling charging and discharging of the secondary battery 2 and supplies it to the charging control signal output terminal CO and the discharging control signal output terminal DO, and a first control circuit (not shown). , and a determination circuit (not shown) that determines a path between terminals connected in the cell balance circuit 15, that is, a path in the switch circuit 16. FIG.

The output circuit 34 is a circuit for outputting a signal representing a path between terminals connected in the cell balance circuit 15 from the semiconductor chip 30 to the semiconductor chip 40 . The output circuit 34 includes a terminal connected to the positive power supply terminal VDD, a terminal connected to the negative power supply terminal VSS, terminals connected to the cell connection terminals VC1a, . 33 and a terminal connected to the cell balance control signal terminal CB_CTL.

On the other hand, a cell balance device 41 is formed in the semiconductor chip 40 . The cell balance device 41 is an example of the cell balance device according to the second embodiment. In the charge/discharge control circuit 50, the cell balance device 41 includes a positive power supply terminal VDD, a negative power supply terminal VSS, a cell balance circuit 15, cell connection terminals VC1, . It has an input terminal CTL and a control circuit 43 .

In the cell balance device 41, the positive power supply terminal VDD is connected to the drain of the depletion type FET 17 via the switch 16_1. Focusing on the switch 16_1, the switch 16_1 has a first end connected to the positive power supply terminal VDD, a second end connected to the drain of the depletion type FET 17, and a control end connected to the control circuit 43. and includes

The negative power supply terminal VSS is connected to the source of the depletion type FET 17 via the switch 16_2n. Focusing on the switch 16_2n, the switch 16_2n has a first end connected to the negative power supply terminal VSS, a second end connected to the source of the depletion type FET 17, and a control end connected to the control circuit 43. and includes

The cell connection terminals VC1 to VC(n−1) are connected to the drain of the depletion type FET 17 through switches forming the first switch group, and are connected to the depletion type FET 17 through switches forming the second switch group. source.

For example, the cell connection terminal VC1 is connected to the drain of the depletion FET 17 via the switch 16_2 and to the source of the depletion FET 17 via the switch 16_3. Thereafter, the cells up to the cell connection terminal VC(n-1) are connected to the drain and source of the depletion type FET 17 via switches in the same manner as the cell connection terminal VC1. The cell connection terminal VC(n-1) is connected to the source of the depletion type FET 17 via the switch 16_(2n-1).

A control circuit 43 as a cell balance control circuit or a second control circuit is connected to the signal input terminal CTL. Also, the control circuit 43 is connected to each control terminal of the switches 16_1, 16_2, .

The cell balance circuit 15 is an example of the cell balance circuit according to the second embodiment. The cell balance circuit 15 in the charge/discharge control circuit 50 differs from the cell balance circuit 15 in the charge/discharge control circuit 10 in that it is formed on the semiconductor chip 40 different from the semiconductor chip 30 on which the first control circuit is formed. , and other points are the same.

Next, operations of the cell balance device 41, the charge/discharge control circuit 50, the charge/discharge control device 60, and the battery device 61 configured as described above will be described.

The charging/discharging control circuit 50, the charging/discharging control device 60, and the battery device 61 perform cell balancing operations in the cell balancing device 41 for the charging/discharging control circuit 10, the charging/discharging control device 20, and the battery device 1, respectively. Although different, there is no substantial difference in the charge/discharge control operation and the cell balance operation of the secondary battery 2 described above. Therefore, in the present embodiment, the cell balance operation in the charge/discharge control circuit 50, the charge/discharge control device 60, and the battery device 61 will be mainly described. The description of the charging/discharging control operation of the secondary battery 2 in the charging/discharging control device 20 and the battery device 1 is omitted.

In the cell balancing operation in the charge/discharge control circuit 50, the charge/discharge control device 60, and the battery device 61, first, the control circuit 33 detects the voltage detected by the battery voltage detection circuit 11, the voltage Vss of the negative power supply terminal VSS, and the external negative voltage input. Based on the voltage Vm of the terminal VM, it is determined which of the first cell discharge state to the nth cell discharge state and the cell balance stop state, and a signal indicating the determination result is supplied to the output circuit 34 .

The signal indicating the determination result is a signal representing the path between the terminals connected in the cell balance circuit 15. For example, the switch 16_1, 16_2, . A signal indicating whether or not a transition of the open/closed state is necessary to make the open/closed state to be transitioned can be applied.

The output circuit 34 converts the signal indicating the determination result, that is, the signal indicating the path between the terminals connected in the cell balance circuit 15, into a format that can be transmitted from the cell balance control signal terminal CB_CTL to the signal input terminal CTL of the semiconductor chip 40. and supplied to the cell balance control signal terminal CB_CTL.

The signal supplied to the cell balance control signal terminal CB_CTL of the semiconductor chip 30 is transmitted to the signal input terminal CTL of the semiconductor chip 40 and supplied to the control circuit 43 from the signal input terminal CTL. The control circuit 43 generates control signals for controlling opening/closing of the switches 16_1, 16_2, . The control circuit 43 supplies the generated control signal to each control terminal of the switches 16_1, 16_2, . The switch circuit 16 receives a control signal from the control circuit 43 to execute or stop the cell balancing operation.

Thus, according to the cell balance circuit 15, the cell balance device 41 including the cell balance circuit 15, the charge/discharge control circuit 50, the charge/discharge control device 60, and the battery device 61, the control circuit 13 in the charge/discharge control circuit 10 is Although there is a difference that the control circuit 33 and the control circuit 43 and the output circuit 34 connecting the control circuit 33 and the control circuit 43 are separately configured, their operations are substantially the same. Therefore, according to the cell balance circuit 15, the cell balance device 41, the charge/discharge control circuit 50, the charge/discharge control device 60, and the battery device 61, the same effect as the charge/discharge control circuit 10, the charge/discharge control device 20, and the battery device 1 is obtained.

In the charge/discharge control circuit 50, the charge/discharge control device 60, and the battery device 61, the cell balance device 41 that performs the cell balance operation is a semiconductor chip 40 different from the semiconductor chip 30 responsible for the charge/discharge control operation of the secondary battery 2. is formed in The charge/discharge control circuit 50, the charge/discharge control device 60, and the battery device are not easily affected by the heat generated by the cell balance operation because the depletion type FET 17 that generates heat due to the cell balance operation is arranged outside the semiconductor chip 30. 61 can be provided.

In addition, the present invention is not limited to the above-described embodiment as it is, and in the implementation stage, it is possible to implement it in various forms other than the above-described example, and within the scope of the invention, Various omissions, substitutions and alterations may be made.

The charge/discharge control device 20 and the battery device 1 described above are configuration examples in which the discharge control FET 3 and the charge control FET 4 are provided on the external negative terminal P− side of the path between the external terminals, that is, on the low side. Not limited. The charge/discharge control device and the battery device according to the embodiment may include the discharge control FET3 and the charge control FET4 on the external positive terminal P+ side, that is, on the high side.

The charge/discharge control circuit 10 described above is a configuration example including the overcurrent detection terminal VINI, but is not limited to this configuration example. Also, the charge/discharge control device 20 and the battery device 1 described above are configuration examples including the overcurrent detection resistor 5 and the overcurrent detection terminal VINI, but are not limited to this configuration example. In the charge/discharge control circuit according to the embodiment, the overcurrent detection terminal VINI is an optional component and may be omitted. In the charge/discharge control device and the battery device according to the embodiment, the overcurrent detection resistor 5 and the overcurrent detection terminal VINI are arbitrary components and may be omitted.

The charge/discharge control circuits 10, 50, the charge/discharge control devices 20, 60, and the battery devices 1, 61 described above are configuration examples including the depletion type FET 17 as the cell discharge resistance, but the cell discharge resistance is not limited to the depletion type FET 17. . The cell discharge resistance may be any element that has a current limiting function, such as the on-resistance of a transistor, a resistive element, or a combination thereof.

When forming the cell balance device, the charge/discharge control circuit, the charge/discharge control device, and the battery device according to the present embodiment, the charge/discharge control circuit 10 is divided into the cell balance circuit 15, the other battery voltage detection circuit 11, and the overcurrent detection circuit. , and the release circuit 12 and the control circuit 13 may be separately formed on different semiconductor chips.

Moreover, although the charge/discharge control circuit 50, the charge/discharge control device 60, and the battery device 61 described above are examples in which the cell balance device 41 includes the control circuit 43, the present invention is not limited to this example. When forming the cell balance device, charge/discharge control circuit, charge/discharge control device, and battery device according to the present embodiment, the control circuit 43 does not necessarily have to be provided in the cell balance device 41 . If a desired control signal can be supplied to the switch circuit 16 in the cell balance device 41, the control circuit 43 as the second control circuit is provided outside the cell balance device 41 such as the semiconductor chip 30, for example. good too.

These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

1, 61 battery device 2 secondary battery 2_1, ..., 2_n cell 2a positive electrode 2b (of secondary battery) negative electrode 3 (of secondary battery) discharge control FET
4 charge control FET
10, 50 charge/discharge control circuit 13 control circuit (first control circuit and second control circuit)
15 cell balance circuit 16 switch circuit 16_1, . . . , 16_2n switch 17 depletion type FET (cell discharge resistance)
20, 60 charge/discharge control devices 30, 40 semiconductor chip 33 control circuit (first control circuit)
34 output circuit 41 cell balance device 43 control circuit (cell balance control circuit or second control circuit)
P+ External positive terminal P- External negative terminal

Claims (9)

A secondary battery including an assembled battery in which a first cell to an n-th cell are connected in series in order from the positive electrode to the negative electrode, wherein n is a natural number of 2 or more, is connected in parallel to the secondary battery. A circuit for adjusting individual voltages of n cells from cell 1 to cell n, comprising:
Each of the n cells includes at least one switch in a path connecting its own positive terminal and its own negative terminal, and n based on a control signal supplied to the at least one switch a switch circuit capable of opening and closing the paths of
a cell discharge resistor connected to each of the n cells from the first cell to the n-th cell via the switch circuit;
When k, which is a natural number equal to or less than n, is the order of the cells connected in series from the positive electrode to the negative electrode,
When it is detected that the secondary battery is being discharged to a device serving as a load connected to the external positive electrode terminal and the external negative electrode terminal , the switch circuit controls the first switch circuit based on the supplied control signal. Each of the n-th cells is switched from the cell to the cell balance stop state in which the cell discharge resistor is not connected, and the voltage of the k-th cell, which is the k-th cell from the positive electrode to the negative electrode, operates for overcharge protection. and the charger for charging the secondary battery is connected to the external positive electrode terminal and the external negative electrode terminal, and the overcharge detection voltage or more and that discharge from the secondary battery to the load device is not started, the k-th cell is discharged based on the supplied control signal. A cell balance circuit characterized by switching to a k-th cell discharge state in which discharge is performed via a resistor. When it is detected that the voltage of the k-th cell has changed from the overcharge detection voltage or more to the overcharge release voltage or less, the switch circuit discharges the k-th cell based on the supplied control signal. 2. The cell balance circuit according to claim 1, wherein the cell balance circuit switches from a state to the cell balance stop state. When k, which is a natural number less than or equal to n, is the order of the cells connected in series from the positive electrode to the negative electrode, the positive terminal of the k-th cell and the negative terminal of the k-th cell are connected. at least one switch included in the path connecting the
a k_1-th switch capable of switching between connection and non-connection with the positive terminal of the k-th cell based on the supplied control signal;
a k_2-th switch capable of switching between connection and non-connection with the negative terminal of the k-th cell based on the supplied control signal;
has
the k_1-th switch includes a control terminal supplied with the control signal, a first terminal connected to the positive terminal of the k-th cell, and a second terminal connected to the cell discharge resistor;
the k_2 switch includes a control terminal supplied with the control signal, a first terminal connected to the negative terminal of the kth cell, and a second terminal connected to the cell discharge resistor;
The cell discharge resistance is
a first terminal connected to positive terminals of n cells from the first cell to the n-th cell through the k_1th switch;
3. The cell balancing circuit according to claim 1 or 2, further comprising a second end connected to each negative terminal of n cells from the first cell to the n-th cell through the k_2th switch. A cell balance operation state in which any one of the n cells is connected to the cell discharge resistor, and a cell balance stop state in which the cell discharge resistor is disconnected from any of the n cells. The cell balance circuit according to any one of claims 1 to 3 , further comprising a cell balance control circuit that controls switching between and. A secondary battery including an assembled battery in which a first cell to an n-th cell are connected in series in order from the positive electrode to the negative electrode, wherein n is a natural number of 2 or more, is connected in parallel to the secondary battery. A device for adjusting the individual voltages of n cells, from cell 1 to cell n, comprising:
Each of the n cells includes at least one switch in a path connecting its own positive terminal and its own negative terminal, and n based on a control signal supplied to the at least one switch a switch circuit capable of opening and closing the paths of
a cell discharge resistor connected to each of the n cells from the first cell to the n-th cell via the switch circuit;
A cell balance operation state in which any one of the n cells is connected to the cell discharge resistor, and a cell balance stop state in which the cell discharge resistor is disconnected from any of the n cells. A cell balance control circuit for switching and controlling the
a positive power supply terminal connected to the first end of the cell discharge resistor via the switch circuit;
a negative power supply terminal connected to the second terminal of the cell discharge resistor via the switch circuit;
a cell connection terminal respectively connected to a first end and a second end of the cell discharge resistor via the switch circuit;
a signal input terminal connected to the cell balance control circuit,
When k, which is a natural number equal to or less than n, is the order of the cells connected in series from the positive electrode to the negative electrode,
When it is detected that the secondary battery is being discharged to a device serving as a load connected to the external positive electrode terminal and the external negative electrode terminal , the switch circuit controls the first switch circuit based on the supplied control signal. Each of the n-th cells is switched from the cell to the cell balance stop state in which the cell discharge resistor is not connected, and the voltage of the k-th cell, which is the k-th cell from the positive electrode to the negative electrode, operates for overcharge protection. and the charger for charging the secondary battery is connected to the external positive electrode terminal and the external negative electrode terminal, and the overcharge detection voltage or more and that discharge from the secondary battery to the load device is not started, the k-th cell is discharged based on the supplied control signal. A cell balance device characterized by switching to a k-th cell discharge state in which discharge is performed via a resistor. A charge/discharge control circuit for controlling charge/discharge of the secondary battery,
a positive electrode power supply terminal to which a voltage from the positive electrode of the secondary battery is supplied;
a negative power supply terminal to which a voltage from the negative electrode of the secondary battery is supplied;
a cell connection terminal supplied with voltage from contacts of two adjacent cells;
an external negative voltage input terminal connected to the external negative terminal;
a charging control signal output terminal for outputting a charging control signal for controlling suspension and permission of charging of the secondary battery;
a discharge control signal output terminal for outputting a discharge control signal for controlling discharge stop and permission of the secondary battery;
It is connected to the positive power terminal, the cell connection terminal, and the negative power terminal, respectively, and the voltage of the secondary battery and the voltage supplied from the positive power terminal, the cell connection terminal, and the negative power terminal a battery voltage detection circuit that detects the voltage of each cell;
a first control circuit that generates the charge control signal and the discharge control signal based on detection signals of the voltage of the secondary battery and the voltage of each cell from the battery voltage detection circuit;
A control signal to be supplied to the at least one switch is generated based on a detection signal of the voltage of the secondary battery and the voltage of each cell, and the voltage of the negative power supply terminal and the voltage of the external negative voltage input terminal. a second control circuit;
a cell balance circuit according to any one of claims 1 to 3 ;
a signal output terminal connected to the output terminal of the cell balance circuit;
A charge/discharge control circuit, comprising: The charge/discharge control circuit is formed on a plurality of semiconductor chips,
7. The charge/discharge control circuit according to claim 6 , wherein said cell balance circuit is formed on a second semiconductor chip different from a first semiconductor chip on which said first control circuit is formed. A charge/discharge control circuit according to claim 6 or 7 ,
the external positive terminal and the external negative terminal;
a charge control FET including a gate connected to the charge control signal output terminal and one end connected to the external negative terminal;
A charge/discharge control device comprising a discharge control FET including a gate connected to the discharge control signal output terminal and one end connected to the other end of the charge control FET. A charge/discharge control circuit according to claim 6 or 7 ,
the secondary battery;
the external positive terminal and the external negative terminal;
a charge control FET including a gate connected to the charge control signal output terminal and one end connected to the external negative terminal;
A battery device comprising a discharge control FET including a gate connected to the discharge control signal output terminal and one end connected to the other end of the charge control FET.

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