JP7200651B2 - Semiconductor wafer, infrared detector, imaging device using same, method for manufacturing semiconductor wafer, and method for manufacturing infrared detector - Google Patents

Description

The present invention relates to a semiconductor wafer, an infrared detector, an imaging device using the same, a semiconductor wafer manufacturing method, and an infrared detector manufacturing method.

The InAs/GaS superlattice structure on the GaSb substrate has a type II band lineup, and by adjusting at least one of the thickness and period of the superlattice, it is possible to obtain sensitivity in the mid-infrared to far-infrared wavelength band. It can be applied to infrared detectors with The type II superlattice structure is called "T2SL" and is expected to be applied to optoelectronic devices such as infrared detectors, laser light sources for optical communication, solar cells, and oxygen generating electrodes for water splitting systems. ing.

The T2SL type infrared detector has a longer minority carrier lifetime than quantum dot or quantum well type infrared detectors that utilize light absorption between subbands, and is expected to reduce dark current and increase sensitivity. ing.

JP 2016-009716 A

In an epitaxial laminated structure applied to an optoelectronic device, a contact layer for making electrical contact with the outside is often formed above or below T2SL, as described in Patent Document 1, for example. The inventors found that when a bulk InAs layer is grown on GaSb at a growth temperature of around 400° C., pits are generated due to excessive As. Furthermore, it was found that the pits did not disappear in this temperature range even if the V/III ratio conditions were changed.

The pits in the bulk InAs layer act as carrier traps, causing a decrease in the sensitivity of infrared detectors, a decrease in the luminous efficiency of lasers, and the like. The same problem arises when an etching stopper layer such as InAs containing a trace amount of Sb is placed under T2SL.

An object of the present invention is to provide a semiconductor wafer in which dislocations, defects, and the like are suppressed, and a technique for applying the same.

In one aspect of the invention, a semiconductor wafer comprises:
a GaSb underlayer;
an InAs layer disposed on the underlayer in the stacking direction;
and the InAs layer contains Sb having a predetermined concentration distribution in the film thickness direction,
The Sb concentration decreases in the film thickness direction with a slope of 41 ppm/nm or more and 43 ppm/nm or less.

A semiconductor wafer in which dislocations, defects, etc. are suppressed, and its application technology are realized.

1 is a schematic diagram of a semiconductor wafer according to an embodiment; FIG. 4A-4C are AFM images of InAs layers grown on GaSb under different conditions; FIG. 4 is a diagram showing the Sb distribution profile in the depth direction of a bulk InAs(Sb) layer on GaSb; It is a manufacturing-process figure of the infrared detector to which the semiconductor wafer of embodiment is applied. It is a manufacturing-process figure of the infrared detector to which the semiconductor wafer of embodiment is applied. It is a manufacturing-process figure of the infrared detector to which the semiconductor wafer of embodiment is applied. It is a manufacturing-process figure of the infrared detector to which the semiconductor wafer of embodiment is applied. 1 is a schematic diagram of an imaging device using an infrared detector according to an embodiment; FIG.

FIG. 1 is a schematic diagram of a semiconductor wafer 100 of the embodiment. A semiconductor wafer 100 has an InAs layer 102 on a GaSb underlayer 101 in the stacking direction. Underlayer 101 may be a GaSb substrate or a GaSb layer.

The InAs layer 102 contains a small amount of Sb, and the concentration distribution of Sb changes in the film thickness direction of the InAs layer 102 as indicated by the dashed line in the figure. As will be described later with reference to FIG. 3, the slope of the Sb concentration profile in the film thickness direction of the InAs layer 102 is within a predetermined range.

The Sb contained in the InAs layer 102 diffuses from the GaSb underlayer 101 during the film formation process of the InAs layer 102, and the Sb concentration decreases from the interface with the underlayer 101 toward the surface of the InAs layer 102. . The slope of the Sb concentration profile correlates with the growth temperature of the InAs layer 102, but even if the slope changes, the Sb composition at the interface between the GaSb underlayer 101 and the InAs layer 102 is constant.

In a preferred embodiment, the initial Sb concentration in the InAs layer 102 at which the Sb concentration starts to decrease with a predetermined slope is about 3000 ppm, and decreases in the film thickness direction at a rate of about 41 ppm/nm to 43 ppm/nm. .

In this specification and claims, when the initial Sb concentration is "3000 ppm" or "about 3000 ppm", it does not mean strictly 3000 ppm, but measurement variation, manufacturing equipment variation, condition control variation, etc. It shall include a certain range of variation around 3000 ppm due to

The InAs layer 102 is formed under predetermined temperature conditions and V/III ratio, and dislocations, pits, etc. are reduced. Specifically, the InAs layer 102 on the GaSb underlayer 101 has a V/III ratio of mol. It is formed in the range of 15 or more and less than 20 in terms of fraction. The InAs layer 102 formed under these conditions has an Sb concentration distribution within the above-described slope range, and defects such as dislocations and pits are reduced.

FIG. 2 shows AFM (Atomic Force Microscope) images of InAs layers grown at various growth temperatures and V/III ratios. The horizontal direction indicates the growth temperature of the InAs layer, and the vertical direction indicates the V/III ratio (molar ratio) of the InAs layer.

In order to specify preferable growth conditions for an InAs layer in which crystal defects such as pits are suppressed, a plurality of samples are produced under different growth conditions and the surfaces of the samples are observed by AFM. A sample is prepared as follows.

An InAs layer is grown to a thickness of 100 nm on a GaSb (001) substrate at a growth rate of 0.2 μm/h by MBE. With these conditions fixed, the growth temperature is varied in the range of 400°C to 520°C. Also, the V/III ratio is varied in the range of 11-20.

As a general trend, pitting occurs in areas where the growth temperature is low or the V/III ratio is high. When the growth temperature is 430° C. or less, many pits are observed on the surface of the InAs layer. Pits appear as fine black dots in the observed image.

When the growth temperature is 460°C, pits are greatly reduced compared to 430°C, but some pits remain on the surface. Moreover, when the V/III ratio reaches 20 at the growth temperature of 460° C., pits are observed on the surface.

Relatively large black spots observed on the surface when the growth temperature is 430° C. and 460° C. and the V/III ratio is 11 or 13 are not pits but aggregation of In due to As deficiency. Such agglomeration also causes stress concentration and is undesirable.

From this AFM image, it can be seen that when the growth temperature is higher than 460° C. and 520° C. or lower and the V/III ratio is 15 or more and less than 20, a good surface with suppressed pits can be obtained. The growth temperature is more preferably in the range of 490°C to 520°C.

FIG. 3 shows the Sb concentration profile in the depth direction when the InAs layer 102 is formed on the GaSb underlayer 101 at a V/III ratio of 15 and at different growth temperatures of 460° C. and 520° C. FIG. The dark black circle data points are the Sb secondary ion intensity at 520°C, and the gray data points are the Sb secondary ion intensity at 460°C.

The horizontal axis is the depth from the surface of the InAs layer 102, and the interface with the GaSb underlayer 101 is at a depth of 100 nm. The vertical axis is the count number of Sb secondary ions per second.

In a film thickness region of approximately 15 nm from the interface with the GaSb underlayer 101, the Sb concentration is substantially constant regardless of the growth temperature. This film thickness region is called an "interface region". The term "constant Sb concentration" in the interface region does not strictly refer to a single value, but includes concentration variations within a certain range due to variations in measurement, variations in manufacturing equipment, and the like.

Beyond the interface region, the Sb concentration abruptly drops, and after the drop, the Sb concentration gradually decreases in the film thickness direction with a predetermined slope. The Sb concentration when the Sb concentration starts to decrease with a predetermined slope at the film thickness position beyond the interface region is defined as the "initial Sb concentration". The initial Sb concentration is approximately 3000 ppm regardless of the growth temperature.

The change rate of the Sb concentration from the initial Sb concentration varies depending on the growth temperature. At the growth temperature of 520° C., the slope of the Sb concentration is larger, about 43 ppm/nm. The Sb concentration slope at a growth temperature of 460° C. is about 41 ppm/nm.

When an InAs layer is formed on GaSb under growth conditions in which crystal defects such as dislocations and pits are suppressed, Sb diffuses from the GaSb underlayer 101 into the InAs layer, forming a predetermined concentration profile in the film thickness direction. be. The well epitaxially grown InAs layer 102 has an initial Sb concentration of 3000 ppm at the film thickness where the Sb concentration drops sharply beyond the interface region, and the Sb concentration gradient from the initial concentration is in the range of 41 ppm/nm to 43 ppm/nm. It is in.

The semiconductor wafer 100 having this Sb concentration profile can be favorably applied to infrared detectors, lasers for communication, and the like. An InAs layer containing a small amount of Sb may be called an "InAs(Sb) layer".

Even if the InAs layer 102 contains n-type or p-type impurities in the semiconductor wafer 100 of FIG. It has the Sb concentration profile of FIG. 3 in the thickness direction. Defects such as dislocations and pits are also suppressed in the InAs layer 102 containing n-type or p-type impurities.

4 to 7 are manufacturing process diagrams of an infrared detector using the semiconductor wafer 100 of FIG. First, in FIG. 4, on an n-type GaSb substrate 11, a GaSb buffer layer 12, a p-type GaSb contact layer 13, a p-type InAs _0.91 Sb _0.09 etching stopper layer 14, an InAs/GaSb T2SL layer 15, and an n-type An InAs cap layer 16 is laminated in this order.

As the n-type GaSb substrate 11, a substrate slightly inclined by 0.35° from the (001) plane is used. This GaSb substrate 11 is introduced into a solid source molecular beam epitaxy (MBE) apparatus, and the substrate temperature is raised by heater heating.

Standard cells are used for the In, Ga, As, and Sb sources used in the MBE apparatus. Alternatively, group V As and Sb may use a valved cracker cell.

When the substrate temperature of the GaSb substrate 11 reaches 400° C., the GaSb substrate 11 is irradiated with Sb. The Sb beam flux is, for example, 5.0×10 ⁻⁷ Torr. As the substrate temperature continues to rise, the GaSb surface oxide film dissociates when the substrate temperature reaches around 550°C. After that, the substrate temperature is raised to 570° C. under Sb beam irradiation and held for 10 minutes to completely remove the surface oxide film.

Thereafter, the substrate temperature is set to 520° C. under Sb beam irradiation, and Ga is irradiated to form a GaSb buffer layer 12 with a thickness of 100 nm. A beam flux of Ga is, for example, 5.0×10 ⁻⁸ Torr. The V/III ratio is 10. Under these conditions the GaSb growth rate is 0.30 μm/h.

When the GaSb buffer layer 12 has grown to 100 nm, additional Be irradiation is performed. Irradiation with Ga and Be is continued to form a p-type GaSb contact layer 13 with a thickness of 500 nm. The Be cell temperature is adjusted such that the carrier concentration is, for example, 5.0×10 ¹⁸ cm ⁻³ .

When the p-type GaSb contact layer 13 has grown to a thickness of 500 nm, the irradiation of Be and Ga is stopped, and the growth temperature is lowered to 480° C. in an Sb atmosphere. When the temperature stabilizes, the supply of Sb is stopped and the growth is interrupted for 3 seconds.

Subsequently, Be, In, As, and Sb are irradiated to form an etching stopper layer 14 of p-type InAs _0.91 Sb _0.09 with a thickness of 100 nm. The Be cell temperature is adjusted such that the carrier concentration is, for example, 5.0×10 ¹⁸ cm ⁻³ . The In beam flux is, for example, 5.0×10 ⁻⁸ Torr, the As beam flux is, for example, 7.5×10 ⁻⁷ Torr, and the Sb beam flux is 1.0×10 ⁻⁸ Torr.

The growth temperature of the etching stopper layer 14 of InAs _0.91 Sb _0.09 formed on the p-type GaSb contact layer 13 is 480 to 490° C., and as described with reference to FIG. is suppressed.

When the etching stopper layer 14 of p-type InAs _0.91 Sb _0.09 has grown to 100 nm, the Be, In, As, and Sb irradiation is stopped and the temperature is lowered to 400°C.

Subsequently, an InAs/GaSb T2SL layer 15 is formed. As an example, an InAs thin film 151 with a thickness of 2 nm and a GaSb thin film 152 with a thickness of 2 nm are formed 200 cycles to form a T2SL layer 15 with a thickness of 800 nm. The uppermost layer of the T2SL layer 15 is the GaSb thin film 152 .

Specifically, while the Sb beam irradiation is stopped, In and As are irradiated. The In beam flux is 5.0×10 ⁻⁸ Torr, and the As beam flux is 7.5×10 ⁻⁷ Torr. The V/III ratio is 15. The growth rate of InAs is, for example, 0.30 μm/h.

When 2 nm of InAs is formed, the supply of In and As is stopped, and the growth is interrupted for 3 seconds under vacuum.

Subsequently, Ga and Sb are irradiated. The Ga beam flux is 5.0×10 ⁻⁸ Torr, and the Sb beam flux is 5.0×10 ⁻⁷ Torr. The V/III ratio is 10. The GaSb growth rate is, for example, 0.30 μm/h.

When 2 nm of GaSb is formed, the supply of Ga and Sb is stopped, and the growth is interrupted for 3 seconds under vacuum.

The formation of the InAs thin film 151 and the GaSb thin film 152 described above is regarded as one cycle, and 200 cycles are repeated to form the T2SL layer 15 with a total thickness of 800 nm. This T2SL layer 15 functions as a light absorption layer in the application example of FIG. Since dislocations, pits, and the like are suppressed by the underlying etching stopper layer 14, defects in the T2SL layer 15 are also suppressed, and causes of carrier traps are reduced.

Subsequently, the growth temperature is raised to 490° C. under Sb irradiation. After the growth temperature is stabilized at 490° C., the Sb irradiation is stopped and In, As, and Si are irradiated to form an n-type InAs cap layer 16 with a thickness of 100 nm. At this time, the In beam flux is 5.0×10 ⁻⁸ Torr, and the As beam flux is 7.5×10 ⁻⁷ Torr. The V/III ratio is 15 in mole fraction. The growth rate of InAs is, for example, 0.30 μm/h. The Si cell temperature is adjusted such that the carrier concentration is, for example, 5.0×10 ¹⁸ cm ⁻³ .

When the n-type InAs cap layer 16 grows to 100 nm, the supply of In is stopped. Thereafter, the temperature is lowered under the As beam irradiation, and when the substrate temperature reaches 400° C., the As beam irradiation is stopped to obtain the lamination shown in FIG. A GaSb substrate having the laminated structure of FIG. 4 is removed from the MBE apparatus.

In this laminated structure, when the Sb composition rapidly decreases at the film thickness position beyond the interface region of the cap layer 16, the initial Sb concentration is about 3000 ppm, and the Sb concentration in the film thickness direction from the initial concentration is 41 ppm/ It is reduced in the range of nm to 43 ppm/nm.

In FIG. 5, the stack of FIG. 4 is formed with a mesa 20 for each pixel. A resist pattern having a predetermined opening pattern is formed _on the upper portion of the stack shown in FIG. The grating T2SL layer 15 and the p-type InAs _0.91 Sb _0.09 etching stopper layer 14 are etched away. The size of the mesa 20 serving as a pixel is, for example, 50 μm×50 μm, the width of the groove separating the pixels is about 10 μm, and the number of pixels is, for example, 256×256. In this design, the total pixel area is 15.36 mm x 15.36 mm.

In FIG. 6, the etched substrate is introduced into a plasma CVD apparatus, and SiN passivation film 21 is formed on the entire surface using SiH ₄ and NH ₃ based gases. The film thickness of passivation film 21 is, for example, 100 nm. A resist pattern having predetermined openings is formed on the passivation film 21, and predetermined portions of the passivation film 21 are etched with a CF ₄ -based gas to form openings 23 and 24 for electrodes.

An opening 23 is formed on the top surface of the mesa 20 to expose the n-type InAs cap layer 16 in the opening 23 . An opening 24 is formed at the bottom of the groove separating adjacent pixels 110 such that a portion of the p-type GaSb contact layer 13 is exposed in the opening 24 . After that, the resist pattern is removed.

In FIG. 7, a resist is patterned into opening shapes corresponding to the electrode openings 23 and 24, a Ti/Pt/Au electrode film is formed by sputtering, and electrodes 25 and 26 are formed by lift-off. The electrode 25 is connected to the n-type InAs cap layer 16 . The n-type InAs cap layer 16 also functions as an n-type contact layer. The cap layer 16 is formed in a predetermined temperature range and a predetermined V/III ratio as described above, and defects such as pits are suppressed. The electrode 26 is connected to the contact layer 13 of the p-type GaSb layer.

Infrared detector 10 is manufactured by forming bump electrodes of, for example, In on electrodes 25 .

FIG. 8 is a schematic diagram of an imaging device 1 in which the infrared detector 10 of FIG. 7 is flip-chip connected to a signal readout circuit 50. As shown in FIG. The infrared detector 10 detects infrared rays incident from the back surface of the GaSb substrate 11 . The bump electrode 108 connected to the electrode 25 of each pixel 110 formed by the mesa 20 is joined to the corresponding bump electrode 54 provided to the electrode 52 of the signal readout circuit 50 to electrically connect with the signal readout circuit 50. It is connected.

Dummy pixels 105 are formed at the ends of the infrared detector 10 , surface wirings 106 for bias application are formed in the dummy pixels 105 , and the surface wirings 106 are connected to bump electrodes 109 of the dummy pixels 105 .

A bias voltage is applied to the contact layer 13 from the signal readout circuit 50 via the bump electrode 54 , the bump electrode 109 and the surface wiring 106 . When a voltage is applied to the bump electrode 108 of each pixel 110 by the signal readout circuit 50, a photocurrent proportional to the amount of infrared light absorbed by the T2SL layer 15 of each pixel 110 flows. A photocurrent obtained from each pixel 110 is input to the signal readout circuit 50 as an analog electric signal. The signal readout circuit 50 may have a noise canceller, an amplifier, and the like.

An image signal may be obtained by subjecting the output signal of the signal readout circuit 50 to A/D conversion, image conversion processing, or the like. A part of the electrode 52 provided in the signal readout circuit 50 may be used to input a control signal to the signal readout circuit 50 or extract an output signal from the signal readout circuit 50 .

In the infrared detector 10 of the embodiment, at least one of the cap layer 16 and the etching stopper layer 14 sandwiching the T2SL layer 15 between the mesas 20 of each pixel 110 is grown under a predetermined temperature condition to prevent dislocations, pits, and the like. Crystal defects are suppressed.

By applying the growth method of the embodiment to the etching stopper layer 14, dislocations and defects in the T2SL layer 15 can be reduced. By applying the growth method of the embodiment to the InAs cap layer 16, dislocations and defects in the cap layer can be reduced.

As a result, carrier traps and generated current due to dislocations and defects in the T2SL layer 15 and the cap layer 16 can be suppressed. The sensitivity can be improved by reducing the dark current of the infrared detector 10 .

Although the invention has been described with reference to specific embodiments, the invention is not limited to the configurations illustrated in the embodiments. The electrode material that makes ohmic contact with the n-type InAs cap layer 16 is not limited to the stack of Ti/Pt/Au. Suitable good conductors can be used as appropriate, such as stacked electrodes.

The material of the passivation film 21 is not limited to SiN, and may be an insulating protective film such as SiO2, SiON, Al2O3, or the like. The conductivity type of the cap layer 16 is not limited to n-type, and may be p-type. In this case, cap layer 16 may be used as a p-type contact. The conductivity type of the contact layer 13 under the T2SL layer 15 is not limited to p-type, and may be an n-type contact layer. The conductivity type of the GaSb substrate 11 is not limited to n-type, and a p-type substrate may be used.

An infrared imaging system may be constructed by combining the imaging device 1 of FIG. 8 with an optical system and a display device. Using an optical system such as a lens, infrared light is efficiently incident on the back surface of the GaSb substrate 11 of the infrared detector 10, and the detected value obtained from each pixel 110 is converted into an image signal to display the image on a display device. may Such an infrared imaging system can be applied to security systems, unmanned exploration systems, etc., and since it detects infrared light, it can also be effectively applied to nighttime monitoring systems.

When the semiconductor wafer 100 of the embodiment and its growth method are applied to a surface emitting laser for optical communication or the like, light generated in the active layer of the T2SL can be efficiently extracted.

To the above description, the following remarks are presented.
(Appendix 1)
a GaSb underlayer;
an InAs layer disposed on the underlayer in the stacking direction;
and the InAs layer contains Sb having a predetermined concentration distribution in the film thickness direction,
A semiconductor wafer, wherein the Sb concentration decreases in the film thickness direction with a slope of 41 ppm/nm or more and 43 ppm/nm or less.
(Appendix 2)
2. The semiconductor wafer according to claim 1, wherein, in the InAs layer, the initial Sb concentration at which the Sb concentration starts to decrease along the slope is 3000 ppm.
(Appendix 3)
The concentration distribution includes the Sb at a constant concentration in the interface region from the interface with the underlayer to the predetermined film thickness of the InAs layer, and the concentration of Sb at the film thickness position beyond the interface region is the initial Sb 3. The semiconductor wafer according to claim 2, wherein the semiconductor wafer is reduced to a concentration of
(Appendix 4)
4. The semiconductor wafer according to any one of appendices 1 to 3, wherein the InAs layer containing Sb in the concentration distribution is doped with an n-type or p-type impurity.
(Appendix 5)
a superlattice layer having repeating cycles of InAs and GaSb and sensitive to the infrared band;
an InAs layer disposed on the superlattice layer in the stacking direction;
has
The top layer of the superlattice layer is a GaSb thin film,
The InAs layer contains Sb present in a predetermined concentration distribution in the film thickness direction,
The infrared detector, wherein the concentration of Sb decreases in the film thickness direction with a slope of 41 ppm/nm or more and 43 ppm/nm or less.
(Appendix 6)
6. The infrared detector according to claim 5, wherein in the InAs layer, the initial Sb concentration at which the concentration of Sb starts to decrease along the slope is 3000 ppm.
(Appendix 7)
a GaSb contact layer arranged below the superlattice layer in the stacking direction;
an InAs(Sb) etching stopper layer disposed between the GaSb contact layer and the superlattice layer and containing Sb having a predetermined composition;
has
The InAs (Sb) etching stopper layer according to Supplementary Note 5 or 6, wherein the concentration of Sb atoms decreases in the thickness direction of the InAs etching stopper layer with a slope of 41 ppm/nm or more and 43 ppm/nm or less. Infrared detector as described.
(Appendix 8)
an infrared detector according to any one of Appendices 5 to 7;
a signal readout circuit joined to the infrared detector;
An imaging device having
(Appendix 9)
An InAs layer or an InAs(Sb) layer containing Sb with a predetermined composition is formed on GaSb under the conditions of a growth temperature of 460° C. or higher and 520° C. or lower and a V/III molar ratio of 15 or more and less than 20. grow epitaxially,
A method for manufacturing a semiconductor wafer, characterized by:
(Appendix 10)
9. The method of manufacturing a semiconductor wafer according to appendix 9, wherein the growth temperature is set to 490° C. or higher and 520° C. or lower.
(Appendix 11)
forming a superlattice layer having repeated cycles of InAs and GaSb on a GaSb substrate;
epitaxially growing an InAs layer on the uppermost GaSb thin film of the superlattice layer under the conditions that the growth temperature is higher than 460° C. and 520° C. or lower and the V/III ratio is 15 or more and less than 20 in terms of mole fraction;
forming a pixel region having a plurality of pixels by processing a laminate including the superlattice layer and the InAs layer;
A method for manufacturing an infrared detector.
(Appendix 12)
12. The method of manufacturing an infrared detector according to appendix 11, wherein the growth temperature is set to 490° C. or higher and 520° C. or lower.
(Appendix 13)
forming a GaSb contact layer on the GaSb substrate prior to forming the superlattice layer;
On the GaSb contact layer, an InAs (Sb) etching stopper layer containing Sb having a predetermined composition is formed at a temperature range of higher than 460° C. and lower than or equal to 520° C. and a V/III ratio of 15 or more and less than 20 in terms of mole fraction. epitaxially grown at
forming the superlattice layer on the InAs(Sb) etching stopper layer;
13. A method for manufacturing an infrared detector according to appendix 11 or 12.
(Appendix 14)
14. The method of manufacturing an infrared detector according to appendix 13, wherein the temperature range of the InAs(Sb) etching stopper layer is set to 490° C. or more and 520° C. or less.
(Appendix 15)
the GaSb contact layer contains impurities of a first conductivity type;
the InAs layer contains impurities of a second conductivity type;
15. A method for manufacturing an infrared detector according to appendix 13 or 14.

1 imaging device 10 infrared detector 11 GaSb substrate 12 buffer layer 13 contact layer 14 etching stopper layer 15 T2SL layer (superlattice layer)
151 InAs thin film 152 GaSb thin film 16 Cap layer (InAs layer)
50 signal readout circuit 100 semiconductor wafer 101 base (GaSb)
102 InAs layer

Claims (8)

a GaSb underlayer;
an InAs layer disposed on the underlayer in the stacking direction;
and the InAs layer contains Sb having a predetermined concentration distribution in the film thickness direction,
A semiconductor wafer, wherein the Sb concentration decreases in the film thickness direction with a slope of 41 ppm/nm or more and 43 ppm/nm or less. 2. The semiconductor wafer according to claim 1, wherein, in said InAs layer, an initial Sb concentration at which said concentration of Sb starts to decrease along said slope is 3000 ppm. The concentration distribution includes the Sb at a constant concentration in the interface region from the interface with the underlayer to the predetermined film thickness of the InAs layer, and the concentration of Sb at the film thickness position beyond the interface region is the initial Sb 3. The semiconductor wafer of claim 2, wherein the concentration is reduced to a superlattice layer having repeated cycles of an InAs thin film and a GaSb thin film and having sensitivity in the infrared band;
an InAs layer disposed on the superlattice layer in the stacking direction;
has
the uppermost layer of the superlattice layer is the GaSb thin film;
The InAs layer contains Sb present in a predetermined concentration distribution in the film thickness direction,
The infrared detector, wherein the concentration of Sb decreases in the film thickness direction with a slope of 41 ppm/nm or more and 43 ppm/nm or less. 5. An infrared detector according to claim 4, wherein in said InAs layer, the initial Sb concentration at which said concentration of Sb starts to decrease along said slope is 3000 ppm. An infrared detector according to claim 4 or 5;
a signal readout circuit joined to the infrared detector;
An imaging device having An InAs layer is formed on GaSb under the conditions that the growth temperature is higher than 460° C. and is lower than or equal to 520° C., and the V/III ratio between the As beam flux and the In beam flux at the time of epitaxial growth is 15 or more and less than 20 in terms of mole fraction. or epitaxially growing an InAs (Sb) layer containing Sb with a predetermined composition;
A method for manufacturing a semiconductor wafer, characterized by: forming a superlattice layer having repeated cycles of InAs thin films and GaSb thin films on a GaSb substrate;
epitaxially growing an InAs layer on the GaSb thin film as the uppermost layer of the superlattice layer under the conditions of a growth temperature higher than 460° C. and 520° C. or lower and a V/III ratio of 15 or more and less than 20 in terms of mole fraction;
forming a pixel region having a plurality of pixels by processing a laminate including the superlattice layer and the InAs layer;
A method for manufacturing an infrared detector.

Images