JP7199493B2 - Non-sequential page read - Google Patents

Description

PRIORITY APPLICATION This application claims the benefit of U.S. Provisional Patent Application No. 62/746,911 (MXIC2271-0) filed October 17, 2018, which application is incorporated herein by reference. .

The present invention relates to integrated circuit memory devices such as NAND flash devices that support continuous read operations, and more particularly to continuous page read operations.

Read latency, which may be designated as tR, is the time between receipt of a read command and the time the data requested by the read command is available at the output.

This type of latency can be relatively long in NAND flash devices. As a result, NAND flash can be significantly slower than other types of memory such as NOR flash for some operations.

To address this latency in NAND flash devices, command sequences known as cache read and sequential read have been developed.

In a cache read command sequence, the latency tR can be reduced by overlapping some of the procedures, such as error detection and correction, with a cache or other buffer memory structure on the device. The latency seen in a cache read command sequence may be designated as tRCBSY. This can improve the throughput of systems using NAND flash. In a sequential command sequence, the NAND flash device is configured to output sequential pages after an initial latency (tR) such that the sequential pages are available without delay between pages. A NAND flash sequential read operation can include three basic steps as follows.
(Step 1) Start Phase: The host needs to issue a page read (C1) command to read the data at the new page address into the cache. Read latency tR is required to read page data.
(Step 2) Sequential Continuous Read Phase: The host continuously reads data from the interface on the memory device during this phase.
(Step 3) Terminate Phase: Depending on the read protocol, the host issues a "terminate" (C3) command (some common NAND flash devices) or raises the chip select control signal CS from 0 to 1 (SPI NAND flash devices) to terminate the sequential continuous read operation. A reset latency tRST is required to terminate a sequential read operation.

However, if non-sequential pages are requested, a new command sequence must be introduced, with the attendant latency associated with starting the new sequence.

It would be desirable to provide techniques that can overcome long latencies between non-sequential pages for NAND flash and other types of memory devices.

Memory devices such as page-mode NAND flash, which include page buffers and input/output interfaces for I/O data units with I/O widths less than the page width, support sequential page reads with non-sequential addresses. The input/output interface can comprise a serial interface (eg SPI) or a parallel interface.

A command protocol is provided to support sequential reads with non-sequential addresses. The command protocol consists of a first command to initiate successive reads of a stream of pages having a starting address followed by a sequential address, a second command or control event to initiate a cache read of the stream of pages; and an in-stream command to provide a non-sequential address before the preceding page in sequence is output. As a result, continuous reads, including transitions from sequential to non-sequential pages, can be performed with little or no wait states at the interface during the output of the stream of pages.

A controller controls successive page read operations to output a stream of pages at the I/O interface. A continuous read operation involves responding to a series of commands to output a stream of continuous pages. The series of commands includes a first command and one or more in-stream commands received prior to completing the output of the preceding page in the stream, the in-stream commands directing the output of the stream of pages. Received and decoded so that it can be interleaved. In a non-sequential continuous page read operation, the first command may include an address to initiate a continuous page read operation of multiple pages with sequential addresses, and at least one in-stream command is a stream of pages. contains non-sequential addresses for providing pages with non-sequential addresses in the .

A memory device has a controller that initiates a read to transfer a non-sequential page to a page buffer and continuously or quickly following the last I/O cycle of an in-stream command that includes a non-sequential address. Techniques are described for responding to in-stream commands that include non-sequential addresses by providing the preceding page to the input/output interface as possible. Also, a non-sequential page command can follow a previous page in the stream, where the previous page is the page address contained in the previous in-stream command in the series of in-stream commands that precede it in the stream by one page. have In other embodiments, a non-sequential page may follow a preceding page in the stream that precedes it in the stream by two pages, where it is provided to the input/output interface after an in-stream command containing a non-sequential address. The preceding page to be read has the page address carried by the preceding in-stream command that precedes the in-stream command containing the non-sequential address by two commands in the series of commands.

A controller initiates a continuous page read operation to a device containing three-level buffering in response to a first command, transferring the first addressed page in the stream from the memory array to the page buffer, addressing first. An example technique for moving a specified page through a datapath circuit to an interface is described. The controller also transfers the next addressed page in the stream from the memory array to the page buffer in response to the first in-stream command after the first read latency including the next page address, to move the page addressed to the interface through the datapath circuitry. Also, the controller can respond to a second in-stream command after a second read latency including a second next page address before outputting the first addressed page from the interface.

In embodiments described herein, the datapath circuitry may include buffer memory. The device may also include error detection and correction ECC circuitry coupled to the datapath circuitry. The ECC circuit performs the ECC function on a page in the datapath circuit before making that page available for output at the input/output interface of the device. The ECC circuit can operate using data chunks that have an ECC chunk width that is less than the page width and greater than the I/O width.

A datapath circuit alternately connects the first portion of the buffer memory to the ECC circuit and the I/O interface, and alternately connects the second portion of the buffer memory to the ECC circuit. and data paths that alternately connect to the circuits and I/O interfaces.

The datapath circuit can also include a multi-level buffer memory including a second buffer level and a third buffer level in addition to a page buffer having a page width (X). A third buffer level alternately connects the first portion and the second portion, the first portion of the third buffer level to the ECC circuitry and the I/O interface, and connects the second portion of the third buffer level to the I/O interface. A data path that alternately connects to an ECC circuit and an I/O interface. The first and second portions of the third buffer level may have a buffer width (Y) that is less than the page width (eg, a multiple of the width of the ECC chunk), and the datapath connects to the first portion of the third buffer level. and the second portion alternately to the ECC circuit and the I/O interface may have a bus width (Z) less than the buffer width.

A method for operating a memory to read a stream of pages comprising non-sequential pages, the method being responsive to a series of commands for outputting the stream of pages from the memory, the series being a first command. and one or more in-stream commands, and using the first command for the first page address and the one or more in-stream commands for subsequent page addresses; determining an address of a page in a stream of pages; and receiving at least one in-stream command in the one or more in-stream commands prior to completing output of a preceding page in the stream. , at least one in-stream command in the one or more in-stream commands includes an address that is not sequential with respect to a preceding page.

Embodiments are described in which the memory array comprises page-mode NAND flash. The techniques described herein can also be applied to other types of memory devices.

Other aspects and advantages of the invention can be understood upon review of the following drawings, detailed description, and claims.

1 is a simplified block diagram of an integrated circuit memory device supporting non-sequential page sequential reads as described herein; FIG. FIG. 4 is a command sequence diagram for non-sequential page sequential reads as described herein; FIG. 4 is a diagram of an alternative command sequence for non-sequential page sequential reads as described herein; FIG. 4 is a block diagram illustrating two-level buffering for devices supporting non-sequential page sequential reads as described herein using ECC; FIG. 4 is a pipeline dataflow diagram of one embodiment of non-sequential page sequential reads described herein using two-level buffering; FIG. 4 is a pipeline dataflow diagram of an alternative embodiment of non-sequential page sequential reads described herein using two-level buffering; FIG. 3 is a block diagram illustrating three-level buffering for devices supporting non-sequential page sequential reads as described herein using ECC; FIG. 4 is a pipeline dataflow diagram of one embodiment of non-sequential page sequential read described herein using three-level buffering; FIG. 4 is a pipeline dataflow diagram of an alternative embodiment of non-sequential page sequential reads described herein using three-level buffering; FIG. 10 is a pipeline dataflow diagram of another alternative embodiment of non-sequential page sequential reads described herein using three-level buffering; 11 is a diagram of a command sequence for non-sequential page sequential reads described herein for the alternative shown in FIG. 10; FIG.

Detailed descriptions of embodiments of the present invention are provided with reference to FIGS. 1-11.

FIG. 1 is a simplified chip block diagram of an integrated circuit memory device according to one embodiment. Integrated circuit memory device 100 includes a memory array 160, eg, a NAND flash array, that stores data with ECC on a single integrated circuit substrate. The memory devices described herein can also be implemented using multi-chip modules, stacked chips, and other configurations.

Control logic 110 with command decoder 108 generates a random page address as described in more detail below in response to receiving a command to perform the non-sequential page sequential read operations described herein. Logic such as a state machine is included on the integrated circuit memory device 100 to support sequential reads. Control logic 110 outputs control signals, represented by arrows in the figure, and addresses on bus 130 . Addresses provided on bus 130 may include, for example, the output of an address counter within control logic 110 (eg, sequential addresses), or addresses carried within received commands, which may include non-sequential addresses.

Decoder 140 is coupled to a plurality of word lines 145 arranged along rows in memory array 160 with ECC and is coupled to page buffer 171 . Page buffer 171 is coupled to a plurality of bit lines 165 arranged along columns in memory array 160 with ECC for reading and writing data to memory array 160 with ECC.

Page buffer 171 may include one or more storage elements for each bit line. Address decoder 140 can select a particular memory cell in array 160 to couple to page buffer 171 via a bit line for the respective connection. Page buffer 171 can store data that is read and written in parallel to these particular memory cells. The page buffer 171 can have a page width of several thousand bits, eg, 2K bits or 4K bits or more, with additional bits containing the associated ECC code. A page can contain multiple ECC chunks, which contain a segment of data and an associated ECC code (ie, one calculated for the ECC for the segment of data). In embodiments, each page includes two ECC chunks with an ECC width equal to a half page or quarter page plus the size of the associated ECC code. In some embodiments, there may be more than two ECC chunks per page.

In this embodiment, the buffer memory structure in the page buffer to interface datapath circuit is a two-level buffer including a page buffer having a second buffer level which in this example includes two portions named buffer BUF_A181 and buffer BUF_B182. Including a ring, each portion of the second buffer level can store a portion, e.g., one-half, of the page buffer content, the portion of the page buffer content including one or more ECC chunks. is preferred. Also, each portion of the second buffer level can be read and written independently. In some embodiments, buffers BUF_A, BUF_B can be implemented using dual-port or multi-port memory technology that allows independent reading and writing to different addresses, or separate address decoding and reading circuits. can be implemented using multiple banks of memory with

Page buffer 171 is coupled to memory array 160 via X data lines, where X is the width of the page plus ECC code, and the second level of the buffer structure via Y-bit buses 175, 176, respectively. Buffers 181 , 182 (BUF_A, BUF_B), where Y may be equal to or greater than half the width X of page buffer 171 . Each of the second level buffers BUF_A, BUF_B may be implemented by a cache memory using, for example, an SRAM (Static Random Access Memory) memory structure having a one row by multiple columns architecture. For example, one page may contain 2048 bits+ECC code, and BUF_A may have one row of 1024 (+ECC bits) columns, ie, it may have a width of 1024+ECC bits. Buffers BUF_A and BUF_B may be operated such that pages of data in the page buffers may be transferred in parallel to buffers BUF_A and BUF_B using one buffer memory cycle. Buffers BUF_A and BUF_B can also be operated such that a portion of a page of data in the page buffers can be transferred in parallel to each of buffers BUF_A and BUF_B, thereby within the same or different buffer memory cycles: A first portion of a page can be transferred to a first portion of a second buffer level (eg BUF_A) and a second portion of a page can be transferred to a second portion of a second buffer level (eg BUF_B). become.

Other embodiments may include a three-level buffer structure including page buffer 171 and two additional buffer levels. Also, other arrangements of buffer memory structures within the data path circuitry between the page buffer and the interface can be used.

The third level buffer can be implemented using an SRAM-based cache memory structure with a multiple row by multiple column architecture. The first and second memory units of the third level buffer described below can have a width equal to the width of the datapath.

Error detection and correction ECC circuit 190 is coupled to buffer memory structures (181, 182) by data bus 184 and data bus 185. FIG. Data buses 184 and 185 can have a bus width less than an ECC chunk, such as 1 byte or 1 word, and are used by ECC circuit 190 to cyclically switch between ECC chunks for error detection and error detection. Perform error correction ECC operations (eg, syndrome computation, key computation, Chien search). The ECC circuitry is coupled to the buffer memory structures (181, 182) by a data bus 191 to move data back and forth as needed.

I/O interface 105 is coupled by data bus 191 to ECC circuitry and buffer memory structures (181, 182).

Input/output data and control signals are passed between interface 105, command decoder 108 and control logic 110, and input/output ports 195 on integrated circuit memory device 100, or other data sources internal or external to integrated circuit memory device 100. move. In some embodiments, port 195 may connect to on-chip host circuitry, such as a general-purpose processor or special-purpose circuitry, or a combination of modules that provide system-on-chip functionality supported by memory array 160 .

In one embodiment, interface 105 is a serial interface that includes a set of I/O ports 195 through which commands, addresses, and data are communicated. The serial interface can be based on or conform to the Serial Peripheral Interface (SPI) bus specification, where the command channel shares I/O pins used by address and data. For example, integrated circuit memory device 100 may include input/output ports that use pins to send and receive SPI bus signals. A pin can be connected to an input data line carrying a serial input data/address signal SI that can also be used for commands. One or more other pins may be connected to one or more output data lines carrying the serial output data signal SO. Another pin can be connected to a clock line carrying the serial clock signal SCLK. Still other pins can be connected to control lines carrying chip enable or chip select signals CS#.

Other types of interfaces can also be used, such as parallel interfaces and other types of serial interfaces. An I/O port 195 on a particular integrated circuit memory device 100 can be configured to provide output data having an I/O data width, which in some examples is interface width. There can be 1, 4, 8, 16, 32 or more bits in parallel per clock (eg, SCLK) cycle. The I/O interface 105 may include a FIFO buffer, shift register buffer, or other support circuitry along with a transmitter for transmitting data received at the interface at a port clock rate, such as the SCLK rate of an SPI interface. can.

In the example shown in FIG. 1, control logic 110, which uses a bias arrangement state machine, controls read, program, and erase voltages, including page reads, which transfer data from pages in the memory array to page buffers. , control the application of bias adjustment supply voltages generated or provided via one or more voltage sources of block 120, such as; Control logic 110 is coupled to multi-level buffer structure, ECC circuitry 190 and memory array with ECC 160 .

Control logic 110 and command decoder 108 form a controller that can be implemented using dedicated logic circuitry including state machines and support logic. In alternative embodiments, the control logic comprises a general-purpose processor, which can be implemented on the same integrated circuit, executing computer programs to control the operation of the device. In still other embodiments, a combination of dedicated logic circuitry and a general purpose processor may be used to implement the control logic.

The command decoder 108 and control logic 110 of the controller are configured to perform sequential read operations of non-sequential pages, which allows shifting to random page addresses during sequential reads. In the embodiments described herein, the controller controls memory operations including consecutive page read operations for outputting a stream of pages at the I/O interface in response to commands received at the input/output interface. do. Execution of the continuous read operation includes responding to a series of commands, the series including a first command and one or more in-stream commands, where in-stream commands are herein referred to as A later command is defined as a command received while the previous page in the stream is passing through the datapath circuitry containing the buffer memory structure, prior to completing the output of the previous page in the stream. An in-stream command can be received in a clock cycle that follows or immediately follows the last output byte of the preceding page in the stream before the page has passed through the buffer memory structure, for example less than four interface clock cycles. .

FIG. 2 shows a non-sequential page sequential read with two levels. The upper level shows a series of commands interleaved with pages of data in a stream of pages at the I/O interface for non-sequential page sequential reads. The series of commands includes a first command C1 and multiple in-stream commands C2 and C3. The lower level shows the behavior of the page buffer during non-sequential page sequential reads.

In this example, a non-sequential page sequential read is initiated by receiving the first command C1 within interval 200 at the I/O interface. The first command C1 initiates a continuous read and provides the starting address of page X. In response to decoding command C1, the array operates to read page X during interval 201 and the data for page X becomes available in the page buffer during interval 202. FIG. A second command C2 providing the next page address is received during interval 203 after a read latency tR for page X data to be loaded from the memory array into the page buffer and through the datapath circuitry towards the interface. . At the time of the second command, the data for the initial page (the first page in the stream of pages) has passed through the datapath circuitry including the buffer memory structure towards the I/O interface. In this embodiment, the first page will be available at the interface in the I/O cycle following the end of the second command C2 in interval 203 at the beginning of interval 204 . In this example, the next page address carried in C2 during interval 203 is page X+1, which is a sequential address.

After outputting the data for page X during interval 204, a second command C2 containing the next page address is received during interval 206 without an interface wait idle cycle at the interface. Following the second command, the previous page X+1 (ie, the page addressed by the previous command) is output. In this example, the next page address received during interval 206 is page Y, which is a non-sequential address. Command C2 during interval 206 is received before page X+1 data is output at the interface during interval 205 . During interval 207, the memory operates to move data from page Y to the page buffer. The preceding page available at the I/O interface during the interval following command C2 in interval 206 is page X+1.

After outputting the data for page X+1 and before outputting the previous page, page Y, the next command C2 providing the next page address, page Y+1, is received at the I/O interface. After the next page address Y+1 is received, the array operates during interval 208 to move the data for page Y+1 into the page buffer. This sequence can continue indefinitely. To terminate the continuous read sequence, a third command C3 in this example is received during interval 209 in this example at the end of the output of page Y's data at the I/O interface. The third command C3 provides no address and allows data from the previous page Y+1 to be moved to the I/O interface in the interval 210 thereafter.

In the embodiments described herein, an integrated circuit memory device includes ECC circuitry coupled to data path circuitry including buffer memory structures and I/O interfaces. ECC circuitry is utilized to perform error detection and correction during the transfer of data from the page buffer to the I/O interface. The time required for the ECC circuitry to perform its function is hidden by buffering to the datapath circuitry. This buffering can be provided by moving data into and out of the buffer memory of the datapath circuit.

In the example shown in FIG. 2, in-stream command C2 (continuous page cache read command) identifies the next address in the sequence and includes an address to output the preceding page of each page in the stream of pages. Thus, in this embodiment, receiving in-stream commands with addresses consumes at least a portion of the resources of the I/O interface during continuous read operations. However, with the continuous read procedure, if the host providing the command is waiting at the end of the output of one page in sequence, the command for the next page can be provided without idle cycles in the interface and the command Pages in the buffer can be output either continuously (ie, without an idle cycle on the I/O interface) or immediately following the last cycle of .

An alternative is shown in FIG. Like FIG. 2, FIG. 3 includes two levels. The upper level shows a series of commands interleaved with pages of data in a stream of pages at the I/O interface for non-sequential page sequential reads. The series of commands includes a first command C1 and multiple in-stream commands C2 and C3. The lower level shows the behavior of the page buffer during non-sequential page sequential reads. As shown, for sequential pages in this example, there is no need to provide an in-stream command to output each page. Instead, the controller can check for commands that carry the next address, and if none are present at that time, automatically using the address counter, continue to serve pages in the stream with sequential addresses. be able to. The time required to check for commands between page outputs can be very short, eg, less than one interface clock cycle, or less than four interface clock cycles.

In the example of FIG. 3, the non-sequential page sequential read is initiated by receiving the first command C1 within interval 300 at the I/O interface. The first command C1 indicates a continuous read and provides the starting address of page X. In response to decoding command C1, the array operates to read page X during interval 301 and the data for page X becomes available in the page buffer during interval 302. FIG. A second command C2 providing the next page address is received during interval 303 after a read latency tR in which a page of data is loaded from the memory array into the page buffer and moved through the buffer memory system to the interface. , followed by the first page of data being output by the I/O interface during successive intervals 304 . In this example, the next page has a sequential address, page X+1. After receiving the second command C2 during interval 303, the memory operates during interval 305 to load page X+1 data into the page buffer, which data passes through the datapath circuitry to the I/O interface. It is moved and output during interval 306 , which continues interval 304 . In this example, the next address to be output is the sequential address, page X+2, which can be loaded into the page buffer within interval 307 . Since addresses X+1 and X+2 are sequential, the addresses can be provided by the address counter in the controller rather than by additional commands, thus saving resources in the I/O interface. The controller is operable to monitor the command interface for in-stream commands before initiating a page read from the array to move the next page to the page buffer. If a page address was provided by the in-stream command, that address is used. If there are no in-stream commands, the controller can use the output of the address counter to select sequential pages.

To provide a non-sequential address, the next in-stream command C2 is provided during interval 308 at the end of interval 306, prior to outputting previous page X+2. In this example, the next command C2 in interval 308 carries page Y, which is a non-sequential address. Data for page Y is loaded into the page buffer during interval 309 and moved to the I/O interface for output during interval 310, which is contiguous to the preceding page, page X+2. While page Y is being output during interval 310 , the memory is operable to load the next page Y+1 of data into the page buffer during interval 311 . The pages are then serialized in this manner until a third command C3, which terminates the sequential read, is received during interval 312 in this example, and the last page in the sequence, page Y+1 in this example, is output during interval 313. can be output as desired.

FIG. 4 illustrates a memory array operable for non-sequential page consecutive reads described with reference to FIGS. 2 and 3 using two-level buffering (page buffer/buffer BUF_A, buffer BUF_B); FIG. 4 is a block diagram showing data path circuitry including ECC circuitry; This is an example of circuitry available in integrated circuit memory device 100 such as that shown in FIG.

In FIG. 4, a memory array 400 , eg, a NAND flash array, is coupled to page buffer 401 . Data can be moved in parallel from memory array 400 to page buffer 401 during a single page read operation. Page buffer 401 is coupled by bus 404 and bus 405 to datapath circuitry including buffer BUF_A 402 and buffer BUF_B 403, respectively. To transfer half a page from page buffer 401 to buffer BUF_A in a single cycle, bus 404 can have a data width that is half the width of page buffer 401 plus ECC. Similarly, bus 405 can have a data width that is half the width of page buffer 401 in order to transfer half a page from page buffer 401 to buffer BUF_B in a single cycle. The ECC bits can be included in BUF_A and buffer BUF_B, or additional memory elements in parallel with BUF_A and buffer BUF_B can be used for the ECC bits.

Buffer BUF_A and buffer BUF_B are configured in an advantageous embodiment to hold at least one ECC chunk containing data and an ECC code associated with the data, such that ECC is performed independently of data in other buffers. It can be acted upon by circuit 416 .

As shown, the datapath circuitry includes a bus 410 connected to buffer BUF_A and a bus 411 connected to buffer BUF_B. Bus 410 is connected to multiplexer 412 and multiplexer 413 . Similarly, bus 411 is connected to multiplexer 412 and multiplexer 413 . The output of multiplexer 412 is connected by line 414 to ECC circuit 416 . The output of multiplexer 413 is connected by line 415 to I/O interface 417, which provides the addressed page of output data. Data can be used by ECC circuit 416 by moving data on buses 410 and 411 in addressable units, such as bytes or words, which can be supported by buses 410 and 411, and can be used by ECC circuit 416 and I/O by interface 417. It can be output to O port 418 .

FIG. 5 illustrates a state machine and state machine in the controller for the device for non-sequential page sequential read utilizing a datapath circuit with two buffer levels (page buffer/buffer BUF_A, buffer BUF_B) as in FIG. Figure 3 illustrates a pipeline data flow for non-sequential page sequential reads as in Figure 2, implemented using support logic; In this diagram, the horizontal axis represents time and each vertical level corresponds to detailed data movement as follows.
0-1: Receive a page read command C1 for a new page.
0-2: Receive read from cache in-stream command C2 for reading data.
1: Move page data and ECC from memory array to page buffer (both halves).
2-1: Move data from the first half of the page buffer to buffer BUF_A.
2-2: Move data from the latter half of the page buffer to buffer BUF_B.
3-1: Apply ECC logic for error detection and correction in buffer BUF_A.
3-2: Apply ECC logic for error detection and correction in buffer BUF_B.
4-1: Move the data from the buffer BUF_A to the data path of the I/O interface.
4-2: Move the data from the buffer BUF_B to the data path of the I/O interface.

The End of Sequence command is not shown in FIG. This can be implemented as described above. Other embodiments may also signal the end of the sequence by control signals other than commands.

In FIG. 5, a first command C1 providing the starting address of page X is received at the start of level 0-1. Moving diagonally down to level 4-2 as indicated by the elements in area 500 for page X, at level 1 the data for page X is loaded into the page buffer. From the page buffer, the first half X(1) of the page is loaded into buffer BUF_A at level 2-1. Also later (or at the same time) the second half of the page X(2) is loaded into buffer BUF_B at level 2-2.

In the drawings, the notations (1) and (2) represent the first and second portions of the page, respectively. Thus, X(1) is the first portion of page X and X(2) is the second portion of page X.

For the first page in the sequence, assuming buffer BUF_B is available, this transfer of the second half of the first page to BUF_B at level 2-2 is transferred to BUF_A at level 2-1 as indicated by box 509. , or can be done later as indicated by box 510. At level 3-1, while the first half of page X is in buffer BUF_A, the ECC circuit operates on one or more ECC chunks in the first half of the page. Then at level 3-2, while the second half of page X is in buffer BUF_B, ECC operates on one or more ECC chunks in the second half of the page. Finally, when cache read command C2 is received at level 0-2, the first half of page X is provided to the I/O interface at level 4-1 to be provided as output. At level 4-2, the second half of the page is presented to the I/O interface in succession to the first half.

As described herein, in-stream command C2 (read from cache) can carry the address of the next page in a continuous read sequence. A sequence of consecutive reads (regions 501, 502, 503, 504...) can be executed in that order in response to a series of commands to output a stream of pages. Before starting to output data from page X to the interface at level 4-1, the flow receives command C2 containing address X+1 at level 0-2. Also, the output of data from page X to the interface at level 4-1 begins immediately following the end of the C2 command.

This use of in-stream command C2 allows non-sequential addresses to be provided while maintaining a continuous read sequence. In FIG. 5 this is illustrated by the address sequence starting at page X (500), the next C2 command providing address X+1 (501) and the next C2 command providing non-sequential address Y (502). A subsequent C2 command provides address Y+1 (503) in this example. The continuous read in this example continues with the next C2 command which provides address Y+2 (504). A continuous read can continue until the end.

The procedure shown in FIG. 5 is an example of how the controller responds to a series of commands to output a stream of pages. The controller initiates a continuous page read operation in response to the first command to transfer the first addressed page in the stream from the memory array to the page buffer and transfer the first addressed page to the datapath circuit. to navigate to the interface via The controller, in response to a first in-stream command received after the read latency and containing the next page address, accesses the memory to obtain the next page and passes it through the datapath circuitry while: Output the first addressed page from the I/O data unit interface. The controller accesses memory during output of the previous page from the interface in response to subsequent in-stream commands that may include the next page address. In this example using two-level buffering, the preceding page is the page address contained in the preceding in-stream command in multiple in-stream commands that precedes the in-stream command containing the non-sequential address by one page in the stream of pages. have.

FIG. 6 illustrates the state machine and the Figure 3 shows a pipeline data flow for a non-sequential page sequential read as in Figure 2, implemented using support logic, in which in-stream commands after the first in-stream command 601 address sequential addresses; Not used to provide. In this diagram, the horizontal axis represents time and each vertical level corresponds to detailed data movement as follows.
0-1: Receive a page read command C1 for a new page.
0-2: Receive a read-from-cache in-stream command C2 for reading data.
1: Move page data and ECC from memory array to page buffer (both halves).
2-1: Move data from the first half of the page buffer to buffer BUF_A.
2-2: Move data from the latter half of the page buffer to buffer BUF_B.
3-1: Apply ECC logic for error detection and correction in buffer BUF_A.
3-2: Apply ECC logic for error detection and correction in buffer BUF_B.
4-1: Move the data from the buffer BUF_A to the data path of the I/O interface.
4-2: Move the data from the buffer BUF_B to the data path of the I/O interface.

The End of Sequence command is not shown in FIG. This can be implemented as described above, including a page read command 600 followed by one or more in-stream commands 601 , 602 , 603 , 604 , 605 . Other embodiments may also signal the end of the sequence by control signals other than commands.

FIG. 6 differs from FIG. 5 in that after the C2 command 602 the stream of pages contains sequential addresses Y, Y+1, and Y+2 followed by a non-sequential address 605Z. Thus, after the C2 command 602 providing address Y, the controller uses the internal address counter to access the page at address Y+1 without a command, then accesses the page at address Y+2 using the internal address counter without a command. visit the page. This allows for better throughput because the data flow is not interrupted or interrupted long enough to receive commands at times 609 and 610 .

FIG. 7 illustrates a memory operable for non-sequential page consecutive reads as described herein using three-level buffering (page buffer/buffer BUF_2_A, buffer BUF_2_B/buffer BUF_3_A, buffer BUF_3_B). FIG. 4 is a block diagram showing an array and datapath circuitry including ECC circuitry; This is another example of circuitry available in integrated circuit memory device 100 such as that of FIG. The second and third buffer levels can be implemented using the SRAM and cache techniques described above in connection with FIG.

In FIG. 7, a memory array 700 , eg, a NAND flash array, is coupled to page buffer 701 . Data can be moved in parallel from memory array 700 to page buffer 701 during a single read operation. Page buffer 701 is coupled by bus 704 and bus 705 to data path circuitry including second level buffers including buffer BUF_2_A (702) and buffer BUF_2_B (703). To transfer half a page from page buffer 701 to buffer BUF_2_A in a single cycle, bus 704 can have a data width that is half the width of page buffer 701 (including ECC bits). Similarly, bus 705 can have a data width that is half the width of page buffer 701 in order to transfer half a page from page buffer 701 to buffer BUF_2_B in a single cycle.

A second level buffer, buffer BUF_2_A, is coupled to a third level buffer, buffer BUF_3_A (711), by a data path that may have the same width as bus 704 (i.e., half a page), thereby It is possible to transfer data from buffer BUF_2_A to buffer BUF_3_A in a single cycle. Similarly, buffer BUF_2_B is coupled to buffer BUF_3_B (712) by a data path that may have the same width as bus 705 (i.e., half a page), thereby allowing buffer BUF_2_B to buffer BUF_3_B to be transferred in one cycle. data can be transferred to In some embodiments, the second level buffer may have the same width as the page buffer and may include a single buffer structure rather than the split structure shown here.

As shown, the datapath circuitry includes a bus 720 connected to buffer BUF_3_A and a bus 721 connected to buffer BUF_3_B. Bus 720 is connected to multiplexer 714 and multiplexer 715 . Similarly, bus 721 is connected to multiplexer 714 and multiplexer 715 . The output of multiplexer 714 is connected by line 716 to ECC circuit 718 . The output of multiplexer 715 is connected by line 717 to I/O interface 719 which provides the addressed page's output data to port 725 . Data can be used by ECC circuitry 718 by moving data on buses 720 and 721 in addressable units, such as bytes or words, which can be supported by buses 720 and 721, and can be used by ECC circuit 718 and by interface 719 to port 725. can be output to ECC circuitry 718 may include a first ECC function circuit and a second ECC function circuit, which may be alternately utilized using a buffer BUF_2_A/buffer BUF_2_B, buffer BUF_3_A/buffer BUF_3_B structure. In some embodiments, bus 720 and bus 721 may be coupled to both second and third buffer levels including buffer BUF_2_A/buffer BUF_2_B and buffer BUF_3_A/buffer BUF_3_B structures.

A three-level buffering system such as that of FIG. 7 can perform a three-stage non-sequential page sequential read operation as shown in FIG. it becomes possible to

FIG. 8 is a diagram for devices for non-sequential page sequential read utilizing a datapath circuit with three buffer levels (page buffer/buffer BUF_2_A, buffer BUF_2_B/buffer BUF_3_A, buffer BUF_3_B) as in FIG. Figure 8 shows the data flow for a non-sequential page sequential read such as Figure 7 implemented using state machines and support logic in the controller; In this diagram, the horizontal axis represents time and each vertical level corresponds to detailed data movement as follows.
0-1: Receive the first page read command C1 for the first page.
0-2: Receive an in-stream page read command C2 having a page address.
1: Move page data and ECC from memory array to page buffer (both halves).
2: Move page data from page buffer to buffer BUF_2_A and buffer BUF_2_B.
3-1: Move data from the first half of the page in buffer BUF_2_A to buffer BUF_3_A.
3-2: Move data from the second half of the page in buffer BUF_2_B to buffer BUF_3_B.
4-1: Apply ECC logic for error detection and correction in buffer BUF_3_A.
4-2: Apply ECC logic for error detection and correction in buffer BUF_3_B.
5-1: Move the data from the buffer BUF_3_A to the data path of the I/O interface.
5-2: Move the data from the buffer BUF_3_B to the data path of the I/O interface.

The End of Sequence command is not shown in FIG. This can be implemented as described above.

In FIG. 8, a first consecutive read command C1 identifying page X, the first page in the sequence, is received in interval 800 at level 0-1. Going diagonally down to level 5-2 for page X, at level 1 the data for page X is loaded into the page buffer. In this embodiment, at level 2 of the figure, before the data from the next page is loaded into the page buffers, the data for page X is loaded once from the page buffers into the second buffer level containing buffers BUF_2_A and BUF_2_B. is loaded with the transfer of Subsequently, at level 3-1, at the second buffer level, data X(1) is transferred from buffer BUF_2_A to buffer BUF_3_A. Subsequently or simultaneously, at level 3-2, data X(2) is transferred from buffer BUF_2_B to buffer BUF_3_B at the second buffer level.

At level 4-1, the ECC circuit operates on ECC chunk X(1) of page X in buffer BUF_3_A. At level 4-2, the ECC circuit operates on ECC chunk X(2) of page X in buffer BUF_3_B.

Then, at level 5-1, the data X(1) of page X in buffer BUF_3_A is made available at the interface, in this example synchronous with the receipt of in-stream command C2 at interval 802 .

At level 5-2, page X data X(2) in buffer BUF_3_B is made available at the interface synchronously with the output of page X data from buffer BUF_3_A.

After the first consecutive read command C1 of interval 800, the data of page X is quickly moved to the second level buffer at level 2, and then the first half of page X is moved to the third level buffer at level 3-1. This clears the page buffer and receives page X+1 which is accessed using the sequential addresses provided by the controller.

A plurality of consecutive read commands C2 follows, including C2 commands within intervals 802, 803, 804 and 805. The second consecutive read command C2 in interval 802 in this example carries the sequential page addresses of page X+2. After the data for page X+1 is moved from the page buffer to the datapath circuit, the data for page X+2 is moved to the page buffer.

After the second sequential read command C2 is received, a third sequential read command C2 is received at interval 803, including the next address (in this example, the non-sequential address of page Y). After the C2 command, the first part of the page addressed by the first consecutive read command C1 (the one that precedes Y in the stream by two pages) is read from buffer BUF_3_A. Page X+1 is still in the datapath.

As shown in FIG. 8, the data for page X+1 passes through the datapath circuitry and becomes available at the I/O interface synchronously with the C2 command received in interval 803 after the action of the ECC circuitry. .

This procedure continues in pipeline fashion through the datapath circuitry as shown in FIG. 8 until the continuous read operation is terminated.

FIG. 8 shows the latency tR that the host waits after issuing a C1 command or a C2 command with a non-sequential address before issuing the C2 command, and the interval tread1 required to output a page to the interface. show. In some embodiments, tR may be longer than tread1, in which case the introduction of non-sequential addresses may slightly hurt throughput.

FIG. 9 illustrates a pipe implemented using state machines and support logic within the controller for the device for non-sequential page sequential reads utilizing a datapath circuit with three buffer levels as in FIG. 902, 903, 904, 906, after the first in-stream command 902 or non-in-stream commands 901, 902, 903, 904, 906. No in-stream commands after the in-stream command 904 following the sequential address are used to provide the sequential address. Thus, page Y+2 is loaded into the page buffer in interval 905 without an in-stream command. In this diagram, the horizontal axis represents time and each vertical level corresponds to detailed data movement as follows.
0-1: Receive the first page read command C1 for the first page.
0-2: Receive an in-stream page read command C2 having a page address.
1: Move page data and ECC from memory array to page buffer (both halves).
2: Move page data from page buffer to buffer BUF_2_A and buffer BUF_2_B.
3-1: Move data from the first half of the page in buffer BUF_2_A to buffer BUF_3_A.
3-2: Move data from the second half of the page in buffer BUF_2_B to buffer BUF_3_B.
4-1: Apply ECC logic for error detection and correction in buffer BUF_3_A.
4-2: Apply ECC logic for error detection and correction in buffer BUF_3_B.
5-1: Move the data from the buffer BUF_3_A to the data path of the I/O interface.
5-2: Move the data from the buffer BUF_3_B to the data path of the I/O interface.

The End of Sequence command is not shown in FIG. This can be implemented as described above. Other embodiments may also signal the end of the sequence by control signals other than commands.

9 differs from FIG. 8 in that after the C2 command 903 the stream of pages contains sequential addresses Y, Y+1, and Y+2 followed by non-sequential address 906Z. Thus, after the C2 command 903 providing address Y, the controller uses the internal address counter to access the page at address Y+1 before command C2 containing address Y+1, and then uses the internal address counter without a command to access the page at address Y+1. to access the page at address Y+2. This is better because the data flow is not interrupted or interrupted long enough to receive commands at time 909 and other times between sequentially addressed pages in the stream. throughput is possible.

FIG. 10 is a pipeline data flow for yet another embodiment of non-sequential page sequential read utilizing a datapath circuit with three buffer levels as in FIG. 7, using three command levels to increase throughput can be improved. In this diagram, the horizontal axis represents time and each vertical level corresponds to detailed data movement as follows.
0-1: A first page read command C1 for the first page is issued by the host and received by the controller.
0-2: The host issues an intra-stream continuous page read command C2 having the address of the second page, and the controller receives it.
0-3: The host issues an in-stream continuous page read command C3 having the page address of the next succeeding page address, and the controller receives it.
1: Move page data and ECC from memory array to page buffer (both halves).
2: Move page data from page buffer to buffer BUF_2_A and buffer BUF_2_B.
3-1: Move data from the first half of the page in buffer BUF_2_A to buffer BUF_3_A.
3-2: Move data from the second half of the page in buffer BUF_2_B to buffer BUF_3_B.
4-1: Apply ECC logic for error detection and correction in buffer BUF_3_A.
4-2: Apply ECC logic for error detection and correction in buffer BUF_3_B.
5-1: Move the data from the buffer BUF_3_A to the data path of the I/O interface.
5-2: Move the data from the buffer BUF_3_B to the data path of the I/O interface.

In this pipeline flow, which is implemented using state machines and support logic in the controller for the device, a first read command C1 1000 carrying address X is received, and after latency tR, a second read command C1 1000 carrying address X+1 is received. Two consecutive read commands C2 1002 are received. Thus, the array is not accessed for page X+1 until command C2 1002 is received and decoded. The host then waits for latency tR2 and issues a third consecutive read command C3 1003 carrying the next address in the stream. Command C3 can be repeatedly issued by the host at times 1004, 1005 and 1006 with intervals tread1 between commands, even with non-sequential addresses, to obtain the next address in the stream until completion.

FIG. 11 shows the data flow of an embodiment, such as the embodiment of FIG. 10, of a non-sequential page sequential read operation for a three-level buffering system, formatted as in FIGS. Therefore, FIG. 11 contains two levels. The upper level shows a series of commands for non-sequential page sequential reads. The lower level shows the behavior of the page buffer during non-sequential page sequential reads.

In the example of FIG. 11, a non-sequential continuous read is initiated by receiving the first command within interval 1100 at the I/O interface. The first command C1 initiates a continuous read and provides the starting address of page X. In response to decoding command C1, the array operates to read page X during interval 1101 and the data for page X becomes available in the page buffer during interval 1102. FIG. In-stream command C2 is received during interval 1103 using the I/O interface after the read latency tR at which the data for page X is loaded from the memory array into the page buffer. In this example, before the array is accessed for the next page in the sequence, the next page address is carried by in-stream command C2 pointing to page X+1. After receiving in-stream command C2 during interval 1103, the memory operates during interval 1105 to load page X+1 of data into the page buffer. Meanwhile, page X data passes through the datapath circuits (eg, buffer BUF_2_A, buffer BUF_2_B, buffer BUF_3_A, buffer BUF_3_B). A second in-stream command C3 (cache read) is received using the I/O circuitry at interval 1104 after a second latency tR2 to allow data to pass through the tri-level datapath circuitry. The second in-stream command C3 carries the next page address in a consecutive page operation, which in this example is page X+2, sequential to the previous page. Meanwhile, at interval 1105, the data for page X+1 is moved to the page buffer. After the second in-stream command C3, a cache read operation is performed at interval 1106 to provide the data for page X to the I/O interface. At the end of interval 1106, the next in-stream command C3 (cache read) containing the next address (page Y) is received at the I/O interface at interval 1108 before the array is accessed for the next page in sequence. and begins outputting page X+1 of data, which was addressed by the command in interval 1103 received two commands before the current command.

In this example, the next address carried in the command in cache read stream for interval 1108 is non-sequential page Y. While page X+1 data is being output to the interface, the next page X+2 data is loaded into the page buffer at interval 1107 and begins passing through the datapath circuitry. Data for page Y is loaded into the page buffer during interval 1109 . Thus, the next command C3 can carry the address of page Y+1 and the data of page Y+1 can be loaded into the page buffer during interval 1111 .

As shown in FIG. 11, during the output of a page, the next in-stream command C3 (cache read) containing the next page address (eg, page Y+1) is preceded (by two pages) in the stream of pages. A page (eg, page X+1) is provided in succession for output to the I/O interface. In this example, the previous page has the page address included in the previous in-stream command in the plurality of in-stream commands that precedes the in-stream command containing the non-sequential address by two commands in the series of commands.

This procedure continues until the first end command is received (not shown).

Described herein are devices and methods having controllers that respond to command sequences for sequential reads that include non-sequential pages.

A device and method having a controller for sequential read of non-sequential pages, receiving a first command specifying a starting address and outputting sequential pages starting at the first starting address in response. , outputting sequential pages in response to the first starting address, receiving a second command specifying a second out-of-order starting address for the sequential pages of the first command, and receiving the second command. Devices and methods are described including outputting sequential pages starting from a second starting address in response to completion of pages from a first sequence.

Devices and methods with controllers are described that include sequential read operations that include commands with page address inputs that can be inserted into sequential reads (similar to cache reads) to eliminate read latency between non-sequential pages.

A device and method having a controller that includes a continuous read operation including a command with a page address input that can be inserted into the continuous read, the command having the next page address downloaded to the page buffer. explain.

A device and method having a controller that includes a continuous read operation including a command with a page address input that can be inserted into a continuous read, the command having the next page address downloaded to a page buffer, the command The devices and methods published for each page are described.

A device and method having a controller that includes a continuous read operation including a command with a page address input that can be inserted into a continuous read, the command having the next page address downloaded to a page buffer, the command A device and method are described that are issued only for non-sequential pages.

While the present invention has been disclosed with reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than a restrictive sense. sea bream. Modifications and combinations will readily occur to those skilled in the art and are intended to be within the spirit of the invention and the scope of the following claims.

100 integrated circuit memory device 105, 417, 719 I/O interface 108 command decoder 110 control logic 120 block 140 decoder 145 word line 160 memory array 165 bit line 171, 401, 701 page buffer 184, 185, 191 data bus 190, 416 , 718 ECC circuit 400, 700 memory array 418 I/O ports

Claims (16)

a memory array including a plurality of bitlines;
a page buffer coupled to the plurality of bitlines having a page width;
an input/output interface for an I/O data unit having an I/O width less than the page width;
a data path circuit including a cache coupled between said page buffer and said input/output interface;
A controller for controlling memory operations including consecutive page read operations for outputting a stream of pages at said input/output interface in response to commands received at said input/output interface, said consecutive page read operations. includes responding to a series of commands, said series being a first command for initiating said consecutive page read operation and one or more streams for moving data from said cache to said input/output interface. wherein the first command sequentially loads a page from a page address into the page buffer, moves the page into the cache, and loads the next page from the next page address into the page buffer. the page address for initiating the consecutive page read operation, wherein the controller uses a non-sequential address as the next page address to provide a non-sequential page in the stream of pages. wherein the non-sequential address is provided in one in-stream command in the one or more in-stream commands to read data from the cache of a previous page in the stream of pages; a controller ;
The cache includes a second buffer level coupled to the page buffer and a third buffer level coupled to the second buffer level, and the data path circuit inputs/outputs the third buffer level. A memory device that connects to an interface . 2. The controller of claim 1 , wherein the controller is configured to provide the stream of pages using a sequential address as the next page address unless the in-stream command containing the non-sequential address is received. device. ECC circuitry coupled to the datapath circuitry for performing an ECC function on a page in the datapath circuitry prior to allowing the page to be output at the input/output interface. 2. The device of claim 1, comprising: 4. The device of claim 3 , wherein the ECC circuit operates using data chunks having an ECC chunk width less than the page width and greater than the I/O width. an ECC circuit coupled to the datapath circuit, the ECC circuit performing an ECC function using data chunks having an ECC chunk width less than the page width and greater than the I/O width;
said third buffer level alternately connecting a first portion and a second portion and said first portion of said third buffer level to said ECC circuit and said input/output interface ; and a data path alternately connecting said second portion of to said ECC circuit and said input/output interface. 2. The device of claim 1, wherein the input/output interface comprises serial input lines configured to carry both addresses and data. a memory array including a plurality of bitlines;
a page buffer coupled to the plurality of bitlines having a page width;
an input/output interface for an I/O data unit having an I/O width less than the page width;
a data path circuit connected between said page buffer and said input/output interface and including a cache;
A controller for controlling memory operations including consecutive page read operations for outputting a stream of pages at said input/output interface in response to commands received at said input/output interface, said consecutive page read operations. comprises responding to a series of commands, said series comprising a first command and one or more in-stream commands, wherein said in-stream commands within said one or more in-stream commands correspond to said in-stream at least one in-stream command in the one or more in-stream commands is received before completing the output of the previous page of the includes a non-sequential address of said non-sequential page in said stream of pages for providing a non-sequential page in said stream of pages; and
with
an ECC circuit coupled to the datapath circuit, the ECC circuit performing an ECC function using data chunks having an ECC chunk width less than the page width and greater than the I/O width;
The datapath circuitry includes a second buffer level coupled to the page buffer and a third buffer level coupled to the second buffer level, the third buffer level comprising a first portion and a second buffer level. and said first portion of said third buffer level to said ECC circuit and said input/output interface, and said second portion of said third buffer level to said ECC circuit and said input /output interface. a data path that alternately connects to the output interface;
Said first and second portions of said third buffer level have a buffer width less than said page width, and said first and second portions of said third buffer level are combined with said ECC circuit and said input/output interface. said data paths alternately connecting to has a bus width less than said buffer width. a memory array including a plurality of bit lines for storing data and associated error checking and correcting (ECC) code;
a page buffer coupled to the plurality of bit lines having a page width for storing pages of data and associated ECC code;
an input/output interface for an I/O data unit having an I/O width less than the page width;
a data path circuit including a cache coupled between said page buffer and said input/output interface;
a controller for controlling memory operations including consecutive page read operations for outputting a stream of pages at the input/output interface in response to commands received at the input/output interface; A read operation includes responding to a series of commands, said series including a first command for initiating said consecutive page read operation and one or more for moving data from said cache to said input/output interface. wherein the first command sequentially loads a page from a page address into the page buffer, moves the page into the cache, and loads the next page from the next page address into the page buffer and the controller uses a non-sequential address as the next page address to read a non-sequential page in the stream of pages. wherein said non-sequential address is one in said one or more in-stream commands to move data from said cache to said input/output interface of a previous page in said stream of pages. an error detection and correction (ECC) circuit coupled to the controller and the datapath circuit, provided in one in-stream command, for a page in the stream of pages, the ECC function prior to outputting the page; and operating using data chunks having an ECC chunk width less than the page width and greater than the I/O width;
The cache includes a second buffer level coupled to the page buffer and a third buffer level coupled to the second buffer level, the third buffer level having a first portion and a second portion. and alternately connecting said first portion of said third buffer level to said ECC circuit and said input/output interface, and connecting said second portion of said third buffer level to said ECC circuit and said input/output interface. a data path that alternately connects to
Said first and second portions of said third buffer level have a buffer width less than said page width, and said first and second portions of said third buffer level are combined with said ECC circuit and said input/output interface. said data paths alternately connecting to an integrated circuit memory device having a bus width less than said buffer width . the second buffer level includes a first portion coupled to a first portion of the page buffer and a second portion coupled to a second portion of the page buffer; said first and second portions of levels having a buffer width less than said page width, said data path alternately connecting said first portion to said ECC circuit and said input/output interface; 9. The device of claim 8 , wherein two portions are alternately connected to said ECC circuit and said input/output interface. 9. The device of Claim 8 , wherein said memory array comprises NAND flash memory. 9. The device of Claim 8 , wherein said input/output interface comprises a serial peripheral interface port. 9. The device of claim 8, wherein said input/output interface includes serial input lines configured to carry both addresses and data. A method for operating a memory device to read a stream of pages, comprising:
in response to a series of commands for outputting a stream of pages of data from memory to an input/output interface of said memory device , said series sequentially loading pages into a page buffer from page addresses; moving the page to a second buffer level of a cache coupled to the page buffer and to a third buffer level coupled to the second buffer level of the cache, and moving the next page from the next page address to the page buffer; a first command including the page address for initiating a consecutive page read operation including loading and one or more for moving data from the third buffer level of the cache to the input/output interface; responding, including in-stream commands for
receiving at least one in-stream command in said one or more in-stream commands, said at least one in-stream command being transmitted from said third buffer level of said cache to said input/output interface; receiving, including a non-sequential page address, for moving the data of the preceding page in the stream of pages ;
using the non-sequential page address as the next page address in the continuous page read operation;
A method, including 14. The method of Claim 13 , wherein said memory device comprises a NAND flash memory. 14. The method of claim 13, wherein said input/output interface is a serial peripheral interface port. 14. The method of claim 13, wherein the input/output interface includes serial input lines configured to carry both addresses and data.

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