JP7164297B2 - transmitter, receiver and chip - Google Patents

Description

The present invention relates to transmitters, receivers and chips.

Program materials produced outside the broadcasting station, such as sports broadcasting and news broadcasting, are wirelessly transmitted from the production site to the broadcasting station. As a standard corresponding to various frequencies used for such transmission, an FPU (Field Pick-up Unit: program material transmission device) system has been proposed (see Non-Patent Documents 1 to 4).

FIG. 11 shows the configuration of the FPU transmission apparatus described in Non-Patent Documents 1 to 4, and FIG. 1 shows the configuration of an FPU-based transmitter extended to Multi-Output.

Portable Microwave Band Digital Wireless Transmission System for Television Broadcast Program Material Transmission, Standard (ARIB STD-B11 Version 2.2), Association of Radio Industries and Businesses Portable OFDM Digital Wireless Transmission System for Television Broadcast Program Material Transmission, Standard (ARIB STD-B33 Version 1.2), Association of Radio Industries and Businesses Portable millimeter-wave band digital wireless transmission system for television broadcast program material transmission, standard (ARIB STD-B43 version 1.0), Association of Radio Industries and Businesses 1.2GHz/2.3GHz Band Portable OFDM Digital Wireless Transmission System for Television Broadcast Program Material Transmission, Standard (ARIB STD-B57 Version 2.0), Association of Radio Industries and Businesses

In August 2016, 4K/8K test broadcasting was started toward the realization of next-generation broadcasting services. While 4K/8K broadcasting makes it possible to enjoy higher-definition images and more realistic sounds than conventional high-definition broadcasting, the amount of data to be transmitted increases dramatically.

However, in the configuration of the conventional FPU system transmission device, there is a problem that the higher the rate of the input TS packets, the higher the operating clock of the circuit.

In particular, in a conventional FPU transmission apparatus, a convolutional encoder is generally used as an error-correction inner code encoder (in that case, a Viterbi decoder is often used on the decoding side), It is required to drive the convolutional encoder on a bit-by-bit basis, and the data rate output from the convolutional encoder is also high. For example, if the TS packet rate is 200 Mbps, the data rate output from the convolutional encoder is 400 Mbps at the coding rate of 1/2.

At the data rate required for transmission of 4K/8K broadcasting, it is assumed that the required rate of TS packets will reach several hundred Mbps. There is a need to cope with higher data rates.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-described problems, and provides a transmitting device, a receiving device, and a chip that are capable of coping with an increase in the data rate of TS packets in an FPU system. With the goal.

A first feature of the present invention is a transmission device configured to transmit an OFDM signal, comprising: a system allocation unit; and generating the OFDM signal from bit data output by the system allocation unit. and the system distribution unit determines, according to a predetermined rule, the method of outputting the bit data input from a plurality of systems to the OFDM modulation unit. The gist is that it is composed of

A second feature of the present invention is a receiver configured to receive an OFDM signal from the transmitter according to the first feature, wherein the OFDM signal is demodulated to output bit data. and a system distribution unit configured to distribute the bit data output by the OFDM demodulation unit to a plurality of systems according to a predetermined rule. .

A gist of a third aspect of the present invention is a chip configured by a processor that executes a program for causing a computer to function as the transmission device according to the first aspect.

A fourth feature of the present invention is a chip configured by a processor that executes a program for causing a computer to function as the receiving device according to the second feature.

According to the present invention, it is possible to provide a transmitting device, a receiving device, and a chip that are capable of coping with an increase in the data rate of TS packets in an FPU system.

FIG. 1 is an example of a configuration diagram of a transmission device 1 according to the first embodiment. FIG. 2 is a diagram showing an example of the convolutional encoder 130 forming the error correction inner code encoder 13a/13b of the transmission device 1 according to the first embodiment. FIG. 3 is a diagram for explaining an example of puncturing processing performed by the error correction inner code encoding units 13a/13b of the transmission device 1 according to the first embodiment. FIG. 4 is a diagram for explaining an example of puncturing processing performed by the error correction inner code encoding units 13a/13b of the transmission device 1 according to the first embodiment. FIG. 5 is a diagram for explaining an example of the operation of the system distribution unit 16 of the transmission device 1 according to the first embodiment. FIG. 6 is a diagram for explaining an example of the operation of the system distribution unit 16 of the transmission device 1 according to the first embodiment. FIG. 7 is an example of a configuration diagram of the receiving device 3 according to the first embodiment. FIG. 8 is a diagram for explaining an example of the operation of the system distribution unit 32 of the receiving device 3 according to the first embodiment. FIG. 9 is a diagram for explaining an example of the operation of the system distribution unit 16 of the transmission device 1 according to the second embodiment. FIG. 10 is a diagram for explaining an example of the operation of the system distribution unit 32 of the receiving device 3 according to the second embodiment. FIG. 11 is a diagram for explaining the conventional technology. FIG. 12 is a diagram for explaining the conventional technology.

(First embodiment)
A broadcasting system according to a first embodiment of the present invention will be described below with reference to FIGS. 1 to 8. FIG. The broadcasting system according to the present embodiment is configured to support the above-described next-generation digital terrestrial broadcasting, and more specifically, supports the FPU system. The receiving device 3 shown in FIG. 7 is provided.

In the transmitting apparatus 1 according to this embodiment, MISO using one transmitting antenna is applied. In addition, as shown in FIG. 1, the transmission device 1 according to the present embodiment has two transmission systems, system 1 and system 2. In FIG.

As shown in FIG. 1, the transmission device 1 according to this embodiment includes a data frame synchronization unit 11, an energy spreading unit 12a/12b, an error correction outer code encoding unit 13a/13b, and an outer interleaving unit 14a/14b. , an error correction inner code encoder 15a/15b, a system distribution unit 16, and an OFDM modulation unit 17a/17b.

Here, the energy spreading unit 12a, the error correction outer code encoding unit 13a, the outer interleaving unit 14a, the error correction inner code encoding unit 15a, and the OFDM modulation unit 17a correspond to system 1, the energy spreading unit 12b, the error correction The outer code encoder 13b, the outer interleaver 14b, the error correction inner code encoder 15b, and the OFDM modulator 17b correspond to system 2. Also, the data frame synchronization unit 11 and system distribution unit 16 are configured to process both systems 1/2.

The data frame synchronization unit 11 is configured to multiplex input TS packets of 204 bytes to generate a data frame, and perform synchronization processing for each data frame.

Specifically, the data frame synchronization unit 11 is configured to select eight TS packets from the input TS packets and generate data frames.

The data frame synchronization unit 11 is configured to output each generated data frame to one of the energy spreading units 12a/12b (that is, system 1/2).

For example, the data frame synchronizer 14 may be configured to alternately output each of the generated data frames to the energy spreaders 12a/12b (ie, systems 1/2).

The energy diffusion units 12a/12b are configured to apply energy diffusion processing to the data frames of the systems 1/2 output by the data frame synchronization unit 14, respectively.

The error correction outer code encoders 13a/13b are configured to perform error correction encoding processing using outer codes on the data frames of the systems 1/2 output by the energy spreaders 12a/12b, respectively. ing.

The outer interleave units 14a/14b are configured to perform outer interleave processing on the data frames of system 1/2 output from the error correction outer code encoders 13a/13b, respectively.

The error correction inner code encoding units 15a/15b are configured to perform error correction encoding processing using the inner code on the data frames of system 1/2 output by the outer interleaving units 14a/14b. ing.

For example, the error-correction inner code encoders 15a/15b are each configured by the convolutional encoder 130 shown in FIG. As shown in FIG. 2, 1-bit input data Din results in 2-bit output data X/Y. 1/2).

Therefore, as shown in FIG. 1, two convolutional encoders 130 (that is, error correction inner code encoders 1 5 a/1 5 b) are arranged in parallel in system 1/2, and input data is By distributing and processing at /2, the data rate output from the convolutional encoder 130 can be suppressed to the same level as in the case of the configuration of the existing FPU transmission apparatus.

For example, as shown in FIG. 1, when two convolutional encoders 130 (that is, error correction inner code encoders 1 5 a/1 5 b) are arranged in parallel in system 1/2, an input TS packet If the rate is 200 Mbps, the input data rate to each of the two convolutional encoders 130 (ie, error correction inner code encoders 1 5 a/1 5 b) is spread over 100 Mbps. As a result, the output data rate from each of the error correction inner code encoders 1 5 a/1 5 b is 200 Mbps (in the case of an encoding rate of 1/2).

In addition, the error correction inner code encoder 1 5 a/1 5 b, in order to increase the transmission capacity, as shown in FIGS. It is configured to apply puncturing processing for reducing bit data to output data X/Y.

The error correction inner code encoder 1 5 a/1 5 b may be configured to perform puncturing processing based on the table shown in FIG.

In this case, the error-correcting inner code encoder 1 5 a/1 5 b converts the bit data constituting the output data X, for example, as shown in FIG. X1 to X5 may be output as they are as output #1, and bit data Y1 to Y5 constituting output data Y may be output as they are as output #2.

Further, if the coding rate is 2/3, the error correction inner code coding unit 1 5 a/1 5 b, as shown in FIG. After serializing the bit data Y1 to Y5 that make up the output data Y and the bit data obtained by deleting X2/X4 from ~X5, parallelize again and output as output #1 and output #2. good.

Further, if the coding rate is 3/4, the error correction inner code coding unit 1 5 a/1 5 b, as shown in FIG. After serializing the bit data obtained by removing X2/X5 from X5 and the bit data obtained by removing Y3 from the bit data Y1 to Y5 constituting the output data Y, it is parallelized again and output as output #1 and output #2. It may be configured as

Further, if the coding rate is 5/6, the error correction inner code encoder 1 5 a/1 5 b will, for example, convert the bit data X1 constituting the output data X into bit data X1 as shown in FIG. After serializing the bit data obtained by removing X2/X4 from ~X5 and the bit data obtained by removing Y3/Y5 from the bit data Y1 to Y5 constituting the output data Y, they are parallelized again to output #1 and output #2. It may be configured to output

According to this configuration, when the output data rates of the two convolutional encoders 130 are equal in each of the error correction inner code encoding units 1 5 a/1 5 b, two systems 1/ 2, bit data can be exchanged, and an interleaving effect can be obtained between the two systems.

As shown in FIG. 5, the system allocation unit 16 uses a predetermined rule to convert the bit data input from the error correction inner code encoders 15a/15b (that is, the plurality of systems 1/2) into the OFDM modulators 17a/17a/17b. 17b, that is, it is configured to distribute the bit data to a plurality of OFDM modulation units 17a/17b (that is, a plurality of systems 1/2).

Specifically, as shown in FIG. 6, for example, the system allocation unit 16, according to a predetermined rule, bit data #1/#3/# constituting the output #1 from the error correction inner code encoding unit 15a. 5/#7 are input to a parallel-serial converter (P/S) #1, and bit data #2/#4/#6/#8 constituting output #2 from the error correction inner code encoder 15a are input. Bit data #9/#11/#13/#15, which are input to a parallel-serial converter (P/S) #2 and form an output #1 from the error correction inner code encoder 15b, are sent to the parallel-serial converter. Bit data #10/#12/#14/#16 input to (P/S) #1 and forming output #2 from the error correction inner code encoder 15b are converted to a parallel-serial converter (P/S). It may be configured to enter #2.

After that, the bit data #1/#3/#5/#7/#9/#11/#13/#15 serialized by the parallel-serial converter (P/S) #1 are sent to the OFDM modulation section 17a. The bit data #2/#4/#6/#8/#10/#12/#14/#16 output and serialized by the parallel-to-serial converter (P/S) #2 are processed by the OFDM modulation section 17b. may be configured to be output to

The OFDM modulation units 17a and 17b are FPU modulation units, and perform modulation processing on the data frames (bit data) input from the system allocation unit 16. That is, the system allocation unit 16 performs It is configured to generate an OFDM signal from the output bit data.

In the receiving device 3 according to this embodiment, MIMO using a plurality of (specifically, two) receiving antennas is applied. Further, the receiving device 3 according to this embodiment has two receiving systems, system 1 and system 2 .

As shown in FIG. 7, the receiver 3 according to the present embodiment includes OFDM demodulators 31a/31b, system allocation units 32, error correction inner code decoders 33a/33b, and outer deinterleavers 34a/34b. , an error correction outer code decoding unit 35a/35b, an energy despreading unit 36a/36b, and a TS packet extraction unit 37.

Here, the OFDM demodulation unit 31a, the error correction inner code decoding unit 33a, the outer deinterleaving unit 34a, the error correction outer code decoding unit 35a, and the energy despreading unit 36a correspond to system 1, and the OFDM demodulation unit 31b and the error correction unit 36a correspond to system 1. The inner code decoder 33b, the outer deinterleaver 34b, the error correction outer code decoder 35b, and the energy despreader 36b correspond to system 2. Also, the system allocation unit 32 and the TS packet extraction unit 37 are configured to process both systems 1/2.

The OFDM demodulators 31a and 31b are FPU-based demodulators that perform demodulation processing on the OFDM signal transmitted by the transmitter 1, demodulate the OFDM signal, and output bit data. is configured as

As shown in FIG. 8, the system allocation unit 32 divides the bit data output from the OFDM demodulation units 31a/31b into a plurality of systems 1/2 (specifically, the error correction inner code decoding unit 33a) according to a predetermined rule. /33b). Such a predetermined rule corresponds to the predetermined rule used in the system distribution unit 16 of the transmission device 1 described above.

The error correction inner code decoding units 33a/33b are configured to perform error correction decoding processing using the inner code on the system 1/2 bit data (data frame) output by the system allocation unit 32. It is

The outer deinterleaving units 34a/34b are configured to perform outer deinterleaving processing on the bit data (data frames) of system 1/2 output by the error correction inner code decoding units 33a/33b. .

The error correction outer code decoding units 35a/35b perform error correction decoding processing using the outer code on the bit data (data frame) of the system 1/2 output by the outer deinterleaving units 34a/34b. is configured to

The energy despreading units 36a/36b are configured to perform energy despreading processing on the bit data (data frames) of system 1/2 output by the error correction outer code decoding units 35a/35b, respectively. .

The TS packet extractor 37 is configured to extract TS packets from the data frames output by the energy despreaders 36a/36b.

According to the broadcasting system according to the present embodiment, it is possible to cope with an increase in the data rate of TS packets in an FPU system.

Further, according to the broadcasting system according to the present embodiment, the processing system of the conventional FPU system can be reused, and an effect of reducing the development cost can be expected.

Furthermore, according to the broadcasting system according to the present embodiment, when performing MIMO transmission, it is possible to obtain the effect of improving transmission characteristics due to the interleaving effect between systems.

(Second embodiment)
The broadcasting system according to the second embodiment of the present invention will be described below with reference to FIGS. 9 and 10, focusing on the differences from the broadcasting system according to the first embodiment.

In the transmitting device 1 according to this embodiment, SIMO (Single-Input Multi-Output) using one transmitting antenna is applied. Therefore, the transmitter 1 according to this embodiment has one OFDM modulator 17 instead of the OFDM modulators 17a/17b in the transmitter 1 according to the first embodiment.

In addition, in the transmission device 1 according to the present embodiment, the system distribution unit 16 follows a predetermined rule, as shown in FIG. /#3/#5/#7, bit data #2/#4/#6/#8 forming output #2 from the error-correction inner code encoder 15a, and data from the error-correction inner code encoder 15b Bit data #9/#11/#13/#15 forming output #1 and bit data #10/#12/#14/# forming output #2 from the error correction inner code encoder 15b 16 is subjected to parallel-to-serial conversion and output to the OFDM modulation section 17 . Such a predetermined rule corresponds to the predetermined rule used in the system distribution unit 16 of the transmission device 1 described above.

In the receiving device 3 according to this embodiment, SIMO using one receiving antenna is applied. Therefore, the receiver 3 according to this embodiment has one OFDM demodulator 31 instead of the OFDM demodulators 31a/31b in the receiver 3 according to the first embodiment.

Further, as shown in FIG. 10, the system distribution unit 32 of the receiving device 3 according to the present embodiment performs serial-parallel conversion on the bit data output from the OFDM demodulation unit 31 according to a predetermined rule, It is configured to output to an error correction inner code decoding unit 33a and an error correction inner code decoding unit 33b.

(Other embodiments)
As noted above, the present invention has been described through the above-described embodiments, but the statements and drawings forming part of the disclosure in such embodiments should not be understood to limit the present invention. From such disclosure, various alternative embodiments, implementations and operational techniques will become apparent to those skilled in the art.

In the above-described embodiment, a case in which two systems are provided is described as an example, but the present invention is not limited to such a case, and two or more systems are provided. It is also applicable to cases.

Moreover, although not particularly mentioned in the above-described embodiment, a program may be provided that causes a computer to execute each process performed by the above-described transmitting device 1 and receiving device 3 . Also, such a program may be recorded on a computer-readable medium. Such programs can be installed on a computer using a computer readable medium. Here, the computer-readable medium on which the program is recorded may be a non-transitory recording medium. The non-transitory recording medium is not particularly limited, but may be, for example, a recording medium such as a CD-ROM or a DVD-ROM.

Alternatively, a chip configured by a memory storing a program for realizing at least part of the functions in the transmitting device 1 and the receiving device 3 described above and a processor executing the program stored in the memory may be provided. .

Alternatively, at least some of the functions in the above-described transmitting device 1 and receiving device 3 are FPGAs (Field-Programmable Gate Arrays), which are a type of PLDs (Programmable Logic Devices) whose configurations can be set by purchasers and designers after manufacturing. It may be configured to be realized by an integrated circuit such as.

REFERENCE SIGNS LIST 1 transmitter 11 data frame synchronizers 12a, 12b energy spreaders 13a, 13b error correction outer code encoder 130 convolutional encoders 14a, 14b outer interleavers 15a, 15b error correction inner code OFDM modulation unit 3 transmission devices 31a, 31b OFDM demodulation unit 32 system allocation units 33a, 33b error correction inner code decoding units 34a, 34b outer deinterleaving unit 35a, 35b... Error correction outer code decoding units 36a, 36b... Energy despreading unit 37... TS packet extraction unit

Claims (5)

A transmitting device configured to transmit an OFDM signal, comprising:
a first error correction inner code encoding unit corresponding to system 1;
a second error correction inner code encoding unit corresponding to system 2;
a system distribution unit;
a first OFDM modulation unit corresponding to the system 1;
and a second OFDM modulation unit corresponding to the system 2,
The first error-correcting inner code encoding unit and the second error-correcting inner code encoding unit respectively perform convolutional encoding processing on the input bit data, and the bit data constituting the output 1 and the output 2 is configured to output bit data,
The system distribution unit has a first parallel-serial converter corresponding to the system 1 and a second parallel-serial converter corresponding to the system 2,
The system distribution unit inputs bit data constituting the output 1 from the first error correction inner code encoding unit to the first parallel-serial converter, and outputs the bit data from the first error correction inner code encoding unit bit data constituting the output 2 of is input to the second parallel-serial converter, and bit data constituting the output 1 from the second error correction inner code encoding unit is input to the first parallel-serial converter input, and configured to input the bit data constituting the output 2 from the second error correction inner code encoding unit to the second parallel-serial converter,
The system distribution unit outputs the bit data serialized by the first parallel-serial converter to the first OFDM modulation unit, and the bit data serialized by the first parallel-serial converter is subjected to the second OFDM modulation. is configured to output to the
The first OFDM modulation unit is configured to generate an OFDM signal corresponding to the system 1 from the bit data output by the system distribution unit,
The transmission device, wherein the second OFDM modulation section is configured to generate an OFDM signal corresponding to the system 2 from the bit data output by the system allocation section. At least one of the first error-correction inner code encoder and the second error-correction inner code encoder is configured to puncture the bit data that has undergone the convolutional encoding process. 2. The transmitter according to claim 1, characterized by: A receiver configured to receive an OFDM signal transmitted from the transmitter of claim 1, comprising:
a first OFDM demodulator configured to demodulate an OFDM signal corresponding to system 1 and output bit data;
a second OFDM demodulator configured to demodulate an OFDM signal corresponding to system 2 and output bit data;
a system distribution unit;
a first error correction inner code decoding unit corresponding to the system 1;
a second error correction inner code decoding unit corresponding to the system 2;
The system distribution unit has a first parallel-serial converter corresponding to the system 1 and a second parallel-serial converter corresponding to the system 2,
The system distribution unit inputs the bit data from the first OFDM demodulation unit to the first parallel-serial converter, and inputs the bit data from the second OFDM demodulation unit to the second parallel-serial converter. is configured as
The system allocation unit inputs the bit data constituting the output 1 parallelized by the first parallel-serial converter to the first error correction inner code decoding unit, and parallelizes by the first parallel-serial converter. The bit data forming the output 2 thus obtained is input to the second error correction internal code decoding unit, and the bit data forming the output 1 parallelized by the second parallel-to-serial converter is input to the first error correction internal code decoding unit. It is characterized in that the bit data constituting the output 2 input to the code decoding unit and parallelized by the second parallel-to-serial converter is input to the second error correction inner code decoding unit. receiver. A chip configured by a processor that executes a program for causing a computer to function as the transmitting device according to claim 1 or 2. A chip configured by a processor that executes a program for causing a computer to function as the receiving device according to claim 3.

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