JP7158199B2 - semiconductor equipment - Google Patents

Description

The present invention relates to semiconductor devices.

2. Description of the Related Art In recent years, various mounting methods have been proposed to reduce the size and cost of a semiconductor device containing a semiconductor chip and a module on which the semiconductor device is mounted.

For example, Patent Literature 1 discloses a technique for stacking two semiconductor chips without intervening spacers and reducing the thickness of the semiconductor device by using both wire bonding connection and flip chip connection.

In addition, Patent Document 2 discloses a mounting method that eliminates the need for wire bonding technology by forming metal bumps on a semiconductor chip and flip-chip connecting the semiconductor chip to leads, thereby reducing costs. there is

When high reliability is required for a semiconductor device, such as for automotive applications, multiple semiconductor chips with the same structure and the same function are incorporated, and even if one semiconductor chip fails, the other semiconductor chips continue to operate. Therefore, a semiconductor device with improved functional safety may be adopted. Also in such semiconductor devices, along with the generalization of high functional safety, miniaturization and cost reduction are beginning to be demanded, and the above-described technologies are attracting attention.

Even in a semiconductor device with enhanced functional safety that incorporates a plurality of semiconductor chips with sensor elements mounted thereon, even if one semiconductor chip fails, other semiconductor chips need to continue the sensor function with equivalent performance. In order to maintain the same sensor function even if the semiconductor chip that functions is changed, it is necessary to position sensor elements on a plurality of semiconductor chips close to each other with high accuracy in a semiconductor device.

JP 2005-175260 Special table 2004-511081

However, in the semiconductor device disclosed in Patent Document 1, it is necessary to stack and install the semiconductor chips with the surfaces of the two semiconductor chips directed in the same direction with respect to the interposer substrate. Therefore, in the direction perpendicular to the surface of the semiconductor chip, the thickness of the semiconductor chip prevents the sensor elements on each semiconductor chip from approaching each other. In addition, since the planar positional accuracy of semiconductor chip placement is restricted by the mounting accuracy of the die bonding apparatus, the sensor elements on the surfaces of the two semiconductor chips are coaxially (axis in the height direction perpendicular to the surface) high. Accuracy is difficult to match.

In addition, Patent Document 2 does not disclose a method for realizing a semiconductor device that incorporates a plurality of semiconductor chips, and it is difficult to improve functional safety.

The present invention has been made in view of such circumstances, and provides a semiconductor device that is compact and excellent in functional safety, in which sensor elements formed on two semiconductor chips can be arranged close to each other with high accuracy. intended to provide

In order to solve the above problems, the present invention provides the following semiconductor device.

That is, a lead having an upper surface and a lower surface, and a tapered portion having a taper in a direction from one end to the other end in a cross-sectional view is provided at the other end, and a first electrode having a surface formed thereon. a semiconductor chip, a second semiconductor chip having a second electrode formed on a surface thereof, and a sealing body covering the first semiconductor chip and the second semiconductor chip, wherein the first electrode is electrically connected to the upper surface of the tapered portion of the lead, and the second electrode is electrically connected to the lower surface of the tapered portion of the lead; and do.

According to the present invention, the first semiconductor chip is connected to the metal plating on the upper surface of the lead, and the second semiconductor chip having the same structure and the same function as the first semiconductor chip is connected to the metal plating on the lower surface of the lead. , the sensor elements formed on the two semiconductor chips can be arranged close to each other with high accuracy, and a compact semiconductor device with excellent functional safety can be realized.

1 is a see-through perspective view showing a semiconductor device according to a first embodiment of the present invention; FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the invention; FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the invention; FIG. 1 is a cross-sectional view showing an inner lead according to a first embodiment of the invention; FIG. It is a top view which shows the semiconductor device of the 2nd Embodiment of this invention. It is a top view which shows the semiconductor device of the 3rd Embodiment of this invention. It is a top view which shows the semiconductor device of the 4th Embodiment of this invention. It is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention. FIG. 11 is a cross-sectional view showing an inner lead according to a fourth embodiment of the invention; 1 is a see-through perspective view showing a semiconductor device employing a large number of inner leads; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the drawings used in the following description may be partially omitted or enlarged in order to make the features of the present invention easier to understand, and may differ from actual dimensional ratios.

(First embodiment)
A semiconductor device according to the first embodiment will be described below.

FIG. 1 is a see-through perspective view of a semiconductor device 100 according to a first embodiment of the present invention, showing a part of the structure in see-through. The semiconductor device 100 includes two semiconductor chips 110 and 120 formed with metal bumps electrically connected to electrodes on the surface, inner leads 131a and 131b and outer leads 132a and 132b connected to the metal bumps. and an epoxy resin 140 that is a sealing body that seals the leads and the semiconductor chips 110 and 120 inside. Since the semiconductor device 100 includes two semiconductor chips having the same structure and the same function, even if the semiconductor chip 110 stops functioning due to a failure or the like, the semiconductor chip 120 can continue to operate. However, the same here means that the same design and the same manufacturing method are adopted, and differences in structure and function due to manufacturing variations are not taken into consideration. With such a configuration, the semiconductor device 100 achieves high functional safety required for automotive components, industrial equipment components, and the like.

FIG. 2 is a plan view of the semiconductor device 100 of FIG. 1 seen through from the semiconductor chip 110 side. The semiconductor chip 120 (not shown) is arranged at substantially the same position as the semiconductor chip 110 in the epoxy resin 140 on the back side of the paper, with reduced positional variation with the semiconductor chip 110 in plan view.

The semiconductor chips 110 and 120 have a front surface on which a semiconductor integrated circuit including a sensor element is formed and a back surface on the opposite side. In FIG. 2, the semiconductor chip 120 (not shown) faces the front side of the paper surface, and the semiconductor chip 110 faces the back side of the paper surface and sandwiches the inner leads 131a and 131b while overlapping each other in plan view. are arranged with their surfaces facing each other. In this way, since the sensor elements are arranged close to each other, the detection value deviation is suppressed when the detection function of the semiconductor chip 110 is stopped and the function is taken over by the semiconductor chip 120 . Each sensor element formed on the surfaces of the semiconductor chips 110 and ₁₂₀ is formed at the center position of the semiconductor chip indicated by position x1 in FIG. line up in the same position. However, when the surfaces of the semiconductor chips 110 and 120 are arranged facing each other, the positions of the respective sensor elements need only be substantially the same in a plan view, and they do not necessarily have to be arranged at the center of the semiconductor chips.

The leads include six outer leads 132a, 132b serving as external terminals and six inner leads 131a, 131b in epoxy resin 140 connected thereto, and connect the semiconductor chips 110, 120 without a die pad. Supporting. Each lead has a top surface on the front side of the page and a bottom surface on the back side of the page, with the top surface facing the surface of the semiconductor chip 110 on the front side of the page and the bottom surface facing the surface of the semiconductor chip 120 on the back side of the page. arranged on the same plane. The plurality of leads are roughly divided into a plurality of first leads (131a, 131b) connected to the semiconductor chip 110 and a plurality of second leads (132a, 132b) connected to the semiconductor chip 120. FIG.

In FIG. 2 , the top surfaces of inner leads 131 a of three first leads at the upper left, lower left, and center right of the page are connected to metal bumps on semiconductor chip 110 . In addition, the lower surfaces of the three second leads of the inner leads 131b in the upper right, lower right, and center left of the drawing are connected to metal bumps on the semiconductor chip 120 . All signals of the semiconductor chips 110 and 120 connected to the upper surface of the inner lead 131a and the lower surface of the inner lead 131b are taken out by the outer leads 132a and 132b. The plurality of first leads and second leads both include inner leads 131a or 131b on the right and left sides of the drawing, respectively, and support the respective semiconductor chips on both sides. Although not limited to such a configuration, in order to stably support the semiconductor chip, the first lead and the second lead support both one end and the other end of the semiconductor chip, respectively, and have a symmetrical arrangement. It is desirable that

One end of the inner leads 131a and 131b is connected to the outer leads 132a and 132b, respectively, and the other end is connected to electrodes such as pads on the semiconductor chips 110 and 120 via the metal plating 150 formed on the tapered portion 133. It is connected to an electrically connected metal bump. One ends of the inner leads 131a and 131b are spaced apart from each other with the outer leads 132a and 132b in consideration of mountability. I am letting Therefore, some of the inner leads 131a and 131b are partially bent in plan view, and extend from one bent end to the other end at the center position of the semiconductor device 100 in plan view. It is formed such that _a certain position x1 is provided. At this time, the center of the semiconductor device ₁₀₀ coincides with the position x1, which is the center of the semiconductor chips 110 and 120 . With such a configuration, when a semiconductor chip is placed on a plurality of inner leads 131a and 131b, the stress applied to each inner lead in the torsional direction is suppressed and the load is dispersed. This reduces deformation of 131b and tilt defects of the semiconductor chip associated therewith. Therefore, the semiconductor device 100 of the first embodiment makes it possible to reduce mounting defects related to mounting of the semiconductor chip without a die pad for supporting the semiconductor chip.

FIG. 3 is a cross-sectional view of the semiconductor device 100 cut along line A-A' in FIG. A semiconductor chip 110 facing downward in the paper surface has metal bumps 111 on the surface on the right side of the paper surface. It is connected. The metal bumps 111 are electrically connected to electrodes 112 such as pads formed on the surface of the semiconductor chip 110 via the rewiring layer 113 and are insulated from the periphery by the insulating layer 114 . Similarly, the semiconductor chip 120 whose surface faces the upper side of the paper has metal bumps 121 on the surface on the left side of the paper. are flip-chip connected. The metal bumps 121 are electrically connected to electrodes 122 such as pads formed on the surface of the semiconductor chip 120 via a rewiring layer 123 and are insulated from the periphery by an insulating layer 124 . The metal plating formed on the inner leads 131a and 131b is formed on both the upper and lower surfaces of the tapered portion 133 so that the metal bumps 111 and 121 can be arranged on either the left or right side.

FIG. 4 is an enlarged cross-sectional view showing the other end of the inner lead 131a connected to the semiconductor chips 110 and 120 toward the left side of the drawing. The other end of the inner lead 131a has a tapered portion in a cross-sectional view. That is, the tapered portion 133 is provided so that the thickness of the upper surface and the lower surface of the inner lead 131a decreases toward the inside of the inner lead 131a from one end to the other end of the inner lead 131a. Tapered portion 133 is provided in a region including positions facing metal bumps 111 and 121 formed on the surface of semiconductor chips 110 and 120 . Since the thickness of the inner lead 131a is reduced by the tapered portion 133, the sensor elements formed on the surfaces of the semiconductor chips 110 and 120 connected to the upper surface and the lower surface are arranged close to each other, and the detection value deviation between the sensor elements is reduced. suppressed. On the other hand, since the mechanical strength of the inner lead 131a itself is maintained by the thickness of one end, deformation and breakage due to stress during mounting are suppressed.

The metal plating 150 is formed in a region including the tapered portion 133 on the other end side of the inner lead 131a. Metal plating 150 is provided on all upper and lower surfaces in all tapered portions 133 for fusion bonding with metal bumps formed on the surface of the semiconductor chip. The formation position of the metal plating 150 is not limited to this configuration, and may be provided only at the position facing the metal bumps.

Epoxy resin 140 in FIG. 3 is a sealing body that seals semiconductor chips 110 and 120 and inner leads 131a and 131b, and protects them from foreign matter and the like from the outside. When the semiconductor chip and the inner leads are electrically connected by wire bonding, the thickness of the epoxy resin is required to completely cover the wire loops so as not to expose them. In that case, in the configuration of FIG. 3, it is necessary to provide a thick epoxy resin on both sides of the semiconductor chips 110 and 120 to cover the wire loops. In addition, areas for wire bonding connection are required on the semiconductor chip side and the inner lead side in a plan view, and an epoxy resin area for covering them is also required. Since the first embodiment employs flip-chip connection, it is not necessary to ensure the area and thickness of these components, and miniaturization can be promoted.

In the flip-chip connection, even if the mounting position accuracy between the semiconductor chips 110 and 120 and the inner leads 131a and 131b is low, the metal bumps and the metal plating are stably connected by the surface tension of the metal plating when heated and melted. A position correction is made in a self-aligned manner. Furthermore, in the first embodiment, based on the shape of the tapered portion 133, when the mounting position of the semiconductor chip shifts to the right, it tilts upward to the right, and when the mounting position shifts to the left, it tilts upward to the left. . Therefore, during flip-chip bonding, the positions are corrected in a self-aligning manner so that the upper and lower surfaces of the inner leads 131a and 131b and the two semiconductor chips are parallel to each other. Therefore, compared with mounting by die bonding, positional deviation in plan view is reduced. Further, the planar positional deviation of the sensor elements formed on the semiconductor chips 110 and 120 is also reduced compared to mounting by die bonding.

With the above configuration, the semiconductor device 100 of the first embodiment can position the sensor elements formed on the two semiconductor chips close to each other with high accuracy, thereby achieving excellent functional safety. can be realized. Further, the semiconductor device 100 can be miniaturized because the semiconductor chip is flip-chip connected to the leads, and epoxy resin encapsulation of the thickness and area required for wire bonding connection is not required. .

(Second embodiment)
The semiconductor device according to the second embodiment will be described below, focusing on the characteristic parts of the semiconductor device according to the first embodiment.

FIG. 5 is a plan view of a semiconductor device 200 according to the second embodiment, in which two semiconductor chips 210 and 220 and a plurality of leads are arranged, seen through from the semiconductor chip 210 side. The semiconductor chip 220 (not shown) is arranged in the epoxy resin 240 on the far side of the paper surface of the semiconductor chip 210 at substantially the same position as the semiconductor chip 210 in plan view with reduced positional variation. The semiconductor chips 210 and 220 have a surface on which a sensor element and a semiconductor integrated circuit formed at the center of the semiconductor device ₂₀₀ and the center of the semiconductor chips 210 and 220, indicated by position x2, and a surface on which the semiconductor integrated circuit is formed. It has a side back. In FIG. 5, a semiconductor chip 220 whose surface faces the front side of the paper surface and a semiconductor chip 210 whose surface faces the back side of the paper surface are arranged to face each other.

The leads are composed of a first lead and a second lead, each composed of outer leads 232a and 232b and inner leads 231a and 231b in the epoxy resin 240 connected thereto. The inner leads 231a and 231b face the front surface of the semiconductor chip 210 on the front side of the page, and face the bottom surface of the semiconductor chip 220 on the back side of the page. In FIG. 5 , the top surfaces of the inner leads 231 a of the first leads at the upper left, lower left, and center right of the page are connected to metal bumps on the semiconductor chip 210 . In addition, the lower surfaces of the inner leads 231b of the second leads in the upper right, lower right, and center left of the drawing are connected to the metal bumps on the semiconductor chip 220 . These configurations are similar to those of the first embodiment.

One end of the inner leads 231a and 231b is connected to the outer leads 232a and 232b, and the other end is connected to the metal bumps on the semiconductor chips 210 and 220 via the metal plating 250 formed on the tapered portion 233. ing. The tapered portion 233 formed in the inner leads 231a and 231b is formed so that the position x2, which is the central position of the semiconductor device ₂₀₀ , is provided on the extension in the direction from one end to the other end of the inner leads 231a and 231b. It is Furthermore, in the second embodiment, the tips of the inner leads 231a and 231b on the other end side are located from the position x2 based on the circular outer peripheral line ₂₆₀ centered on the position x2, which is the central position of the semiconductor device ₂₀₀ . They are arranged in a circle so that they are equidistant. By adopting such a configuration, the degree of distribution of the load of the semiconductor chips 210 and 220 to the plurality of inner leads 231a and 231b is further enhanced, and the mounting process during mounting such as the twisting of the inner leads 231a and 231b due to uneven load is prevented. Reduces defects. For this reason, the metal bumps formed on the semiconductor chips 210 and 220 are also arranged in a circular shape along the shape of the circular peripheral line 260 . Other configurations are the same as those of the first embodiment.

With the configuration described above, the semiconductor device 200 according to the second embodiment can place the sensor elements formed on the two semiconductor chips close to each other with high accuracy, thereby achieving excellent functional safety. can be realized. Furthermore, the semiconductor device 200 can be miniaturized because the semiconductor chip is flip-chip connected to the leads, which eliminates the need for epoxy resin encapsulation of the thickness and area necessary for wire bonding connection. . Also, by arranging the ends of the inner leads 231a and 231b on the other end side and the metal bumps on the semiconductor chip at the same distance from the center of the semiconductor device 200, mounting defects are reduced and quality is improved.

(Third embodiment)
The semiconductor device according to the third embodiment will be described below, focusing on the characteristic parts of the semiconductor device according to the second embodiment.

FIG. 6 is a plan view of a semiconductor device 300 according to the third embodiment, in which two semiconductor chips 310 and 320 and a plurality of leads are arranged, seen through from the semiconductor chip 310 side. The semiconductor chip 320 (not shown) is placed in the epoxy resin 340 on the back side of the semiconductor chip 310 in the plane of the drawing, at substantially the same position as the semiconductor chip 310 in plan view with reduced positional variation. The semiconductor chips 310 and 320 have a surface on which a sensor element and a semiconductor integrated circuit formed at the center of the semiconductor device 300 and the center of the semiconductor chips 310 and ₃₂₀ , indicated by position x3, and the surface on which the semiconductor integrated circuit is formed. It has a side back. In FIG. 6, a semiconductor chip 320 whose surface faces the front side of the paper surface and a semiconductor chip 310 whose surface faces the back side of the paper surface are arranged to face each other.

The leads are composed of a first lead and a second lead, which are respectively composed of outer leads 332a and 332b and inner leads 331a and 331b in epoxy resin 340 connected thereto. The inner leads 331a and 331b face the front surface of the semiconductor chip 310 on the front side of the page, and face the bottom surface of the semiconductor chip 320 on the back side of the page. In FIG. 6 , the top surfaces of the inner leads 331 a of the first leads at the upper left, lower left, and center right of the paper surface are connected to metal bumps on the semiconductor chip 310 . In addition, the lower surfaces of the inner leads 331b of the second leads in the upper right, lower right, and center left of the drawing are connected to metal bumps on the semiconductor chip 320 . These configurations are similar to those of the second embodiment.

The inner leads 331 a and 331 b have one end connected to the outer leads 332 a and 332 b and the other end connected to the metal bumps on the semiconductor chips 310 and 320 via the metal plating 350 formed on the tapered portion 333 . ing. The tapered portion 333 formed in the inner leads 331a and 331b is formed so that the position _x3 , which is the central position of the semiconductor device 300, is provided on the extension in the direction from one end to the other end of the inner leads 331a and 331b. It is In addition, the tips of the inner leads 331a and 331b on the other end side are formed in a circular shape so as to be equidistant from the position _x3 , which is the central position of the semiconductor device 300, based on the circular outer peripheral line ₃₆₀ centered on the position x3. is the same as in the second embodiment. Furthermore, in the third embodiment, the inner leads 331a and 331b have a circular portion 370 formed in a circular shape around the point of contact with the metal bump at the tip of the other end side. By adopting such a configuration, it is possible to reduce the local unevenness of the load at the portion where the metal bump and the tapered portion 333 are connected, thereby reducing mounting defects during the process such as twisting of this portion. Other configurations are the same as those of the second embodiment.

The semiconductor device 300 of the third embodiment is configured as described above, whereby the sensor elements formed on the two semiconductor chips are arranged close to each other with high accuracy, thereby improving functional safety and wire bonding. It is possible to promote miniaturization for connection. In addition, the tips of the inner leads 331a and 331b on the other end side and the metal bumps on the semiconductor chip are arranged equidistant from the center of the semiconductor device 300, and the tips of the inner leads 331a and 331b on the other end side are circular. This reduces mounting defects and improves quality.

(Fourth embodiment)
The semiconductor device according to the fourth embodiment will be described below, focusing on the characteristic parts of the semiconductor device according to the third embodiment.

FIG. 7 is a plan view of a semiconductor device 400 according to the fourth embodiment, in which two semiconductor chips 410 and 420 and a plurality of leads are arranged, seen through from the semiconductor chip 410 side. The semiconductor chip 420 (not shown) is arranged in the epoxy resin 440 on the far side of the paper surface of the semiconductor chip 410 at substantially the same position as the semiconductor chip 410 in plan view with reduced positional variation. The semiconductor chips 410 and 420 have a surface on which a sensor element and a semiconductor integrated circuit formed at the center of the semiconductor device 400 and the center of the semiconductor chips 410 and ₄₂₀ , indicated by position x4, and a surface on which the semiconductor integrated circuit is formed. It has a side back. In FIG. 7, a semiconductor chip 420 whose surface faces the front side of the paper and a semiconductor chip 410 whose surface faces the back side of the paper are arranged so that their surfaces face each other.

The leads are composed of a first lead and a second lead, which are respectively composed of outer leads 432a and 432b and inner leads 431a and 431b in epoxy resin 440 connected thereto. The inner leads 431a and 431b face the front surface of the semiconductor chip 410 on the front side of the page, and face the bottom surface of the semiconductor chip 420 on the back side of the page. In FIG. 7, the top surfaces of the inner leads 431a of the first leads at the upper left, lower left, and center right of the paper surface are connected to the metal bumps on the semiconductor chip 410. In FIG. In addition, the lower surfaces of the inner leads 431b of the second leads in the upper right, lower right, and center left of the drawing are connected to the metal bumps on the semiconductor chip 420. FIG. These configurations are similar to those of the third embodiment.

One end of the inner leads 431 a and 431 b is connected to the outer leads 432 a and 432 b , and the other end is connected to the metal bumps on the semiconductor chips 410 and 420 via the metal plating 450 formed on the tapered portion 433 . ing. The tapered portion 433 formed in the inner leads 431a and 431b is formed so that the position x4, which is the central position of the semiconductor device ₄₀₀ , is provided on the extension in the direction from one end to the other end of the inner leads 431a and 431b. It is In addition, the tips of the inner leads 431a and 431b on the other end side are formed in a circular shape so as to be equidistant from the position x4, which is the central position of the semiconductor device ₄₀₀ , based on the circular outer peripheral line ₄₆₀ centered on the position x4. are placed in In addition, the inner leads 431a and 431b have a circular portion 470 formed in a circular shape around the point of contact with the metal bump at the tip of the other end side. These configurations are similar to those of the third embodiment. Furthermore, in the fourth embodiment, a semiconductor chip connection portion 480 is provided at the contact point with the metal bump at the center of the circular portion of the tip of the other end of the inner leads 431a and 431b.

FIG. 8 is a cross-sectional view of the semiconductor device 400 cut along line B-B' in FIG. A semiconductor chip 410 facing downward in the paper has metal bumps 411 on the right side of the paper, and a semiconductor chip connection portion 480 formed with metal plating (not shown) of inner leads 431a on the right side and a flip chip. It is connected. The metal bumps 411 are electrically connected to electrodes 412 such as pads formed on the surface of the semiconductor chip 410 via a rewiring layer 413 and are insulated from the periphery by an insulating layer 414 . Similarly, the semiconductor chip 420 whose surface faces the upper side of the paper surface has metal bumps 421 on the surface on the left side of the paper surface, and a semiconductor chip connection portion 480 formed with metal plating (not shown) of the inner lead 431b on the left side. and flip-chip connected. The metal bumps 421 are electrically connected to electrodes 422 such as pads formed on the surface of the semiconductor chip 420 via a rewiring layer 423 and are insulated from the periphery by an insulating layer 424 . The metal plating and semiconductor chip connection portion 480 formed on the inner leads 431a and 431b are formed on both the upper and lower surfaces of the inner leads 431a and 431b so that the metal bumps 411 and 421 can be arranged on either the left or the right side. It is Furthermore, the semiconductor chip connection portion 480 has recesses extending toward the inside of the inner leads 431a and 431b (the vertical direction of the paper surface), and the metal bumps 411 and 421 on the semiconductor chips 410 and 420 are in contact with the recesses. It is connected.

FIG. 9 is an enlarged cross-sectional view showing the other end of the inner lead 431a connected to the semiconductor chips 410 and 420 toward the left side of the paper. The other end of the inner lead 431a has a tapered portion in a cross-sectional view. That is, the tapered portion 433 is provided so that the thickness of the upper surface and the lower surface of the inner lead 431a decreases toward the inside of the inner lead 431a from one end to the other end of the inner lead 431a. Since the thickness of the inner lead 431a is reduced by the tapered portion 433, the sensor elements formed on the surfaces of the semiconductor chips 410 and 420 connected to the upper surface and the lower surface are arranged close to each other, and the detection value deviation between the sensor elements is reduced. suppressed. On the other hand, since the mechanical strength of the inner lead 431a itself is maintained by the thickness of one end, deformation and breakage due to stress during mounting are suppressed. Such a configuration is similar to that of the first embodiment.

The semiconductor chip connection portion 480 of the fourth embodiment is provided at a position facing the metal bumps 411 and 421 formed on the surfaces of the semiconductor chips 410 and 420 in the tapered portion 433 . The semiconductor chip connection portion 480 has spherical recesses facing inwards of the inner leads 431 a and 431 b , corresponding to the surfaces of the spherical protrusions of the metal bumps 411 and 421 . A metal plating 450 is formed in the concave portion of the semiconductor chip connection portion 480 for fusion bonding with the metal bumps 411 and 421 . A semiconductor chip connection portion 480 having a recess and a metal plating 450 are provided in advance on the upper and lower surfaces of the tapered portion 433 of all the inner leads 431a and 431b.

In the fourth embodiment, since the semiconductor chip connecting portion 480 is provided with the concave portion, the connection area between the metal bumps 411 and 421 and the semiconductor chip connecting portion 480 is increased, the connection strength is increased, and the resistance value of the connection portion is increased. A reduction can be realized, and the reliability of the connection is improved. In addition, the concave portion of the semiconductor chip connection portion 480 serves as a guide for alignment of the metal bumps 411 and 421, thereby reducing the positional deviation of the two semiconductor chips in plan view. Furthermore, since the surfaces of the two semiconductor chips 410 and 420 are brought closer to each other by the depth of the concave portion of the semiconductor chip connection portion 480, the detection deviation of the respective sensor elements formed on the semiconductor chip surfaces is suppressed.

The semiconductor device 400 of the fourth embodiment is configured as described above, whereby the sensor elements formed on the two semiconductor chips are arranged close to each other with high precision, thereby improving functional safety and wire bonding. It is possible to promote miniaturization for connection. The ends of the inner leads 431a and 431b on the other end side and the metal bumps on the semiconductor chip are arranged at equal distances from the center of the semiconductor device 400, and the ends of the inner leads 431a and 431b on the other end side are circular. This reduces mounting defects and improves quality. Furthermore, the semiconductor device 400 is provided with a semiconductor chip connecting portion 480 having a concave portion at the tip of the other end of the inner leads 431a and 431b. improvement has been achieved. The semiconductor chip connection portion having such a concave portion is not limited to this configuration, and may be provided in the tapered portion of the first embodiment or the second embodiment.

It goes without saying that the present invention is not limited to the above embodiments, and that various modifications and combinations are possible without departing from the scope of the present invention.

For example, the present invention can be applied to a semiconductor device having terminals on three or more sides of a semiconductor chip. FIG. 10 is a see-through perspective view of a semiconductor device 500 in which terminals are provided along four sides of semiconductor chips 510 and 520. FIG. Although it depends on the chip size and the number of terminals, here, the inner leads 531a and 531b are arranged in four directions corresponding to the four sides of the semiconductor chips 510 and 520, and the respective inner leads 531a and 531b are connected to the outer leads 532a and 532b. They are connected and exposed to the outside of the epoxy resin 540 . The semiconductor device 500 having such a configuration can be individually combined with the arrangement of the inner leads adopted in the second embodiment described above and the semiconductor chip connecting portion described in the fourth embodiment, if necessary. .

Also, the first lead is electrically connected to the first semiconductor chip, and the second lead different from the first lead is electrically connected to the second semiconductor chip. The first lead and the second lead may be the same as long as the lead and the second lead can be shared. Since the first semiconductor chip is always connected to the upper surface of the lead and the second semiconductor chip is always connected to the lower surface of the lead, the two semiconductor chips can be electrically connected to the same lead. not be hindered.

Moreover, the sensor element for detecting the surrounding situation mounted on the semiconductor chip may have a structure such as a MEMS device. For example, a MEMS device having capacitive electrodes, piezoresistive elements, etc. on a semiconductor chip may have a beam structure or a diaphragm structure, and the sensor element may be configured to detect the amount of deformation thereof.

Also, the connection between the other end of the inner lead and the semiconductor chip is flip-chip connection using metal bumps, but anisotropic conductive connection using paste containing conductive particles may also be used. In other words, the connection material is not limited to metal bumps as long as it is a conductive material that can ensure electrical connection between the other end of the inner lead and the electrode on the semiconductor chip.

Furthermore, although the gull-wing outer leads are used as the external terminals in this embodiment, the same effect can be obtained even with a non-lead type semiconductor device.

110, 120, 210, 220, 310, 320, 410, 420, 510, 520 semiconductor chips 111, 121, 411, 421 metal bumps 112, 122, 412, 422 electrodes 113, 123, 413, 423 rewiring layer 114, 124, 414, 424 insulating layers 131a, 131b, 231a, 231b, 331a, 331b, 431a, 431b, 531a, 531b inner leads 132a, 132b, 232a, 232b, 332a, 332b, 432a, 432b, 532a, 532b outer leads 133 , 233, 333, 433 Tapered portions 140, 240, 340, 440, 540 Epoxy resin 150, 250, 350, 450 Metal plating 260, 360, 460 Circular peripheral lines 370, 470 Circular portion 480 Semiconductor chip connecting portion

Claims (10)

a lead having an upper surface and a lower surface, and a tapered portion having a taper in a direction from one end to the other end in cross-sectional view provided at the other end;
a first semiconductor chip having a first electrode formed on its surface;
a second semiconductor chip having a second electrode formed on its surface;
a sealing body covering the first semiconductor chip and the second semiconductor chip;
The semiconductor device, wherein the first electrode is electrically connected to the upper surface of the tapered portion of the lead, and the second electrode is electrically connected to the lower surface of the tapered portion of the lead. 3. The first semiconductor chip and the second semiconductor chip overlap in plan view, and the surface of the first semiconductor chip and the surface of the second semiconductor chip face each other. 2. The semiconductor device according to 1. The first semiconductor chip has a first sensor element, the second semiconductor chip has a second sensor element, and the first semiconductor chip and the second semiconductor chip have the same function. 3. The semiconductor device according to claim 2, wherein said first sensor element and said second sensor element are provided at the same position in plan view. 4. The semiconductor device according to claim 3, wherein the center position of said first semiconductor chip, the center position of said second semiconductor chip, and the center position of said semiconductor device are the same in plan view. 5. The semiconductor device according to claim 4, wherein a central position of said semiconductor device is provided on an extension of said tapered portion in a direction from said one end to said other end. 6. The semiconductor device according to claim 5, wherein said other end of said lead is arranged on the outer periphery of a circle centered on the center position of said semiconductor device in plan view. 7. The semiconductor device according to claim 1, wherein said tapered portion has a circular portion in plan view. 8. The semiconductor according to any one of claims 1 to 7, wherein recesses directed inward are provided at positions of said tapered portion facing said first semiconductor chip and said second semiconductor chip. Device. metal plating is formed on the upper and lower surfaces of the tapered portion;
the first semiconductor chip has a first metal bump electrically connected to the first electrode;
9. The semiconductor device according to claim 1, wherein said second semiconductor chip has second metal bumps electrically connected to said second electrodes. the leads comprise a first lead and a second lead;
the first electrode is electrically connected to an upper surface of the tapered portion of the first lead;
10. The semiconductor device according to claim 1, wherein said second electrode is electrically connected to a lower surface of said tapered portion of said second lead.

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