JP7144609B2 - Semiconductor equipment and automotive electronic control equipment - Google Patents

Description

The present invention relates to the structure of a semiconductor device constructed using a multi-layer wiring technology, and more particularly to a technology effectively applied to a semiconductor device that requires small variation in pairing properties of elements and high reliability.

A current mirror circuit, which is often used in analog integrated circuits, converts an input current to a desired magnification (mirror ratio) according to the sizes of MOS transistors on the input side and the output side, and outputs the result. In order to operate a semiconductor integrated circuit device using a current mirror circuit with high accuracy, it is required to reduce variations in the pairing properties of the transistors forming the current mirror circuit and to suppress changes over time in the pairing properties.

In a semiconductor integrated circuit device, metal wirings for connecting elements such as transistors, diodes, resistors, and capacitors are usually formed on these elements via an interlayer insulating film (interlayer oxide film). A metal wiring (wiring pattern) is formed by repeating formation of a metal film and an insulating film and pattern formation by lithography.

In general, when forming multi-layered metal wiring, upper wiring layers far from transistors are used for long-distance connections within the chip and power main lines. Alternatively, wide wiring is often used. Further, in recent years, in a semiconductor device equipped with a power transistor for controlling a large current, a wider and thicker copper redistribution may be used in the upper layer of the passivation film of the semiconductor device.

Incidentally, since a metal film and an insulating film formed on a semiconductor substrate have different coefficients of linear expansion from that of the semiconductor substrate, thermal strain occurs in the semiconductor element due to temperature changes due to environmental temperature around the semiconductor element and self-heating. Thermal strain of wiring patterns arranged around elements such as transistors and resistors causes variations and fluctuations in the electrical characteristics of these elements.

For example, Japanese Patent Application Laid-Open No. 2002-300000 discloses a technique for reducing aging of an element caused by a wiring pattern. Japanese Patent Application Laid-Open No. 2002-200001 discloses a technique for reducing the influence of dummy wirings on MOS transistors by defining the layout of dummy wirings in the upper layer of MOS transistors forming a pair.

Patent Document 1 describes "a semiconductor device having a dummy wiring for mechanical chemical polishing averaging arranged in an upper layer of a transistor, wherein the dummy wiring does not correspond to any of the pairing transistors when viewed two-dimensionally. or a semiconductor device arranged such that portions overlapping the first transistor and the second transistor are the same between the first transistor and the second transistor.” there is

Japanese Patent Application Laid-Open No. 2003-100899

As described above, wide wiring may be used in upper wiring layers far from transistors. The width of these wirings is wider than each transistor size of transistors forming a pair, and may be narrower than the entire array of pair transistors. When such wide wiring is placed around paired transistors, it is necessary to make the wide wiring bypass the transistor arrangement in order to make the wiring pattern seen from each transistor the same, which increases the chip size. I had a problem to do.

In particular, current mirror circuits used in analog-to-digital converters and the like have a large number of transistors, which greatly affects the chip size.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a highly reliable semiconductor device including a current mirror circuit capable of reducing variations in the mirror ratio of the current mirror circuit and suppressing changes in element pairing over time. .

In order to solve the above problems, the present invention provides a first semiconductor element group in which a plurality of semiconductor elements are connected in parallel, and a semiconductor element group arranged in the same layer as the first semiconductor element group, in which the plurality of semiconductor elements are arranged in parallel. a second semiconductor element group connected to the second semiconductor element group, and arranged in a layer above the first semiconductor element group and the second semiconductor element group, the semiconductor element group of the first semiconductor element group and the second semiconductor element group a plurality of wirings having a width wider than that of each semiconductor element, wherein the first semiconductor element group and the second semiconductor element group are paired to form a circuit having a predetermined pair accuracy; A combination of distances in the plane direction from each semiconductor element of the first semiconductor element group to the wiring closest in the plane direction, and distances of the positions closest to the semiconductor elements in the second semiconductor element group in the plane direction. The plurality of wirings are arranged so that the combinations of distances in the plane direction to the wirings are equal.

According to the present invention, in a semiconductor device including a current mirror circuit, it is possible to realize a highly reliable semiconductor device capable of reducing variations in the mirror ratio of the current mirror circuit and suppressing temporal changes in pairing of elements.

Problems, configurations, and effects other than those described above will be clarified by the following description of the embodiments.

1 is a plan view of a semiconductor device according to Example 1 of the present invention; FIG. 1 is a circuit diagram of a semiconductor device according to Example 1 of the present invention; FIG. It is a figure which shows the simulation model of the thermal strain of wiring. FIG. 3B is a diagram showing a simulation result of thermal strain by the model of FIG. 3A; 2 is a partially enlarged view of the semiconductor device shown in FIG. 1; FIG. 5 is a cross-sectional view taken along the line A-A' in FIG. 4; FIG. FIG. 11 is a plan view of a conventional semiconductor device; It is a circuit diagram of a conventional semiconductor device. 2 is a plan view of a semiconductor device according to Example 2 of the present invention; FIG. FIG. 9 is a cross-sectional view taken along the line B-B' of FIG. 8; 9 is a partially enlarged view of the semiconductor device shown in FIG. 8; FIG. FIG. 11 is a sectional view taken along line C-C' of FIG. 10; It is a top view of the semiconductor device based on Example 3 of this invention. 13 is a cross-sectional view taken along the line D-D' of FIG. 12; FIG. 13 is a partially enlarged view of the semiconductor device shown in FIG. 12; FIG. 15 is a cross-sectional view taken along line EE' of FIG. 14; FIG. It is a top view of the semiconductor device based on Example 4 of this invention. It is a circuit diagram of a semiconductor device according to Example 4 of the present invention. 17 is a partially enlarged view of the semiconductor device shown in FIG. 16; FIG. It is a top view of the semiconductor device based on Example 5 of this invention. It is a top view of the semiconductor device based on Example 6 of this invention. It is a circuit diagram of a semiconductor device according to Example 6 of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in each drawing, the same configurations are denoted by the same reference numerals, and detailed descriptions of overlapping portions are omitted.

A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 7. FIG. 6 and 7 are a plan view and a circuit diagram of a conventional semiconductor device shown as a comparative example to facilitate understanding of the present invention.

FIG. 1 is an example showing a planar positional relationship between the MOS transistors M01 to M74 forming the current mirror circuit and the wide wiring 20 in the semiconductor device of this embodiment. As shown in FIG. 1, the plurality of MOS transistors M01 to M74 are arranged in the X direction, and the plurality of wide wirings 20 are arranged to extend in the Y direction perpendicular to the MOS transistors M01 to M74. Also, the width W2 of one wide wiring 20 is approximately four times the width W1 of one MOS transistor.

FIG. 2 shows a circuit diagram of the semiconductor device shown in FIG. The mirror circuit of FIG. 2 has a mirror terminal 100 and four MOS transistors M01 to M04 connected in parallel. Also, the mirror destination is configured by connecting four MOS transistors M11 to M14, M21 to M24, etc. in parallel to each of the mirror terminals 101 to 107, respectively. However, the arrangement order of the MOS transistors in FIG. 1 may be different from that in FIG.

In FIG. 1, the MOS transistors are distributed and arranged in parallel like M01 to M71, M02 to M72, M03 to M73, and M04 to M74 from the left.

Also, M01 to M31 are arranged in the order of M01, M11, M21 and M31 from the left, and M02 to M32 are arranged in the order of M12, M22, M32 and M02 from the left one by one. M03 to M43 and M04 to M44 are similarly arranged in different order. Similarly, M41 to M71, M42 to M72, M43 to M73, and M44 to M74 are arranged in a different order one by one.

3A and 3B, the influence of the wiring pattern stress on the MOS transistor will be described. FIG. 3A shows thermal stress in which a silicon oxide film 401, which is an interlayer oxide film, a polyimide film 500, and a copper wiring 200 are arranged on an SOI substrate consisting of a silicon substrate (semiconductor substrate) 300, a silicon oxide film 400, and a silicon (Si) layer 301. FIG. FIG. 4 is a cross-sectional view of a simulation model; FIG. 3B is a simulation result of the amount of strain at the interface 302 between the silicon layer 301 and the silicon oxide film 401 in FIG. 3A.

As shown in FIG. 3B, the thermal strain of the silicon interface 302 is affected by the upper layer wiring (copper wiring 200) and varies depending on the planar distance from the wiring end. Also, the mobility of electrons and holes in silicon depends on the amount of strain in silicon. As described above, since the electrical characteristics of a semiconductor element change depending on the positional relationship with the wiring pattern, it is necessary to consider the arrangement, shape, etc. of the upper layer wiring pattern of each element in semiconductor elements that require pairing.

Next, the detailed positional relationship between the MOS transistor and the wide wiring 20, which are the components of this embodiment, will be described. FIG. 4 is a plan view showing an enlarged region of eight MOS transistors M01 to M71 from the left in FIG. 5 is a cross-sectional view taken along line A-A' in FIG. In FIGS. 4 and 5, the wiring layers 10 in the upper layers close to the MOS transistors M01 to M71 are laid out so that the patterns of the upper wiring layers 10 are the same when viewed from each MOS transistor. The strain given to the transistor is the same for each MOS transistor.

Let D2, D1, E1 and E2 be the distances in the planar direction from the MOS transistors M01, M11, M21 and M31 to the wiring end of the wide wiring 20, respectively. The same applies to the distances in the planar direction to the wiring ends of M41 to M71 and the wide wiring 20. FIG. Since M01 to M71 further differ in the presence or absence of the wide wiring 20 in the upper layer and in the distance in the plane direction from the wiring end, the influence of the thermal strain due to the wide wiring 20 is different, and the pairability of the MOS transistors deteriorates.

However, in the circuit of FIG. 2, when MOS transistors and wide wiring 20 are arranged as shown in FIG. Combinations of distances in the planar direction are, for example, as follows.

<<mirror terminal 100>> (mirror source)
Transistors M01 to M04: Distances D2, E2, E1, D1 to wide wiring 20
<<mirror terminal 101>> (mirror tip)
Transistors M11 to M14: Distances D1, D2, E2, E1 to wide wiring 20
<<mirror terminal 102>> (mirror tip)
Transistors M21 to M24: Distances E1, D1, D2, E2 to wide wiring 20
<<mirror terminal 103>> (mirror tip)
Transistors M31 to M34: Distances E2, E1, D1, D2 to wide wiring 20
The same is true for the mirror terminals 104 to 107, and since all of them are combinations of (D1, D2, E1, E2), the electrical characteristics of the MOS for each mirror terminal in FIG. 2 are the same. Therefore, as a current mirror circuit, it is possible to ensure the pairing of the mirror source and each mirror destination.

In this embodiment, a first semiconductor element group (group of mirror terminals 100) in which a plurality of semiconductor elements (MOS transistors M01 to M04) are connected in parallel and a plurality of semiconductor elements (MOS transistors M11 to M14) are connected in parallel. A circuit that requires pairability and at least a connected second semiconductor element group (group of mirror terminals 101); and a plurality of wirings having a width wider than the width of the semiconductor element group (100) from each semiconductor element (M01 to M04) constituting the first semiconductor element group (100) to the wide wiring 20 closest in the planar direction. and the plane from each semiconductor element (M11 to M14) constituting the second semiconductor element group (101) to the wide wiring 20 closest in the plane direction A plurality of wide wirings 20 are arranged so that the combination of the distances (D1, D2, E2, E1) in the direction is the same, so that the first semiconductor element group (group of mirror terminals 100 ) from the wide wiring 20 and the second semiconductor element group (group of the mirror terminals 101) from the wide wiring 20 can be substantially equalized.

Since the degree of deterioration due to stress can be made equal, it is possible to maintain pairing between the first semiconductor element group (group of mirror terminals 100) and the second semiconductor element group (group of mirror terminals 101), and aging deterioration (change over time) can be achieved. ) can be suppressed.

In this embodiment, a current mirror circuit is used as an example of a circuit that requires pairability, but the present invention is not limited to this, and can be widely applied to other circuits that require pairability (pair accuracy). It is possible to

Moreover, although the configuration in which the number of MOS transistors (semiconductor elements) forming each semiconductor element group is four has been exemplified, the present invention is not limited to this. Similarly, the number of semiconductor element groups forming a circuit that requires pairing is not limited to seven.

On the other hand, in the conventional semiconductor device shown in FIGS. 6 and 7, the MOS transistors forming the current mirror circuit are arranged without being dispersed, and in this case, the influence of the wide wiring 20 is different for the MOS transistors M0 to M7. Therefore, the pairability of the MOS transistors is deteriorated, and the mirror ratio of the current mirror circuit is also different for each mirror destination.

As described above, the semiconductor device of this embodiment includes a first semiconductor element group (group of mirror terminals 100) in which a plurality of semiconductor elements (MOS transistors M01 to M04) are connected in parallel, and a first semiconductor element group (group of mirror terminals 100). A second semiconductor element group (group of mirror terminals 101) arranged in the same layer as the element group (group of mirror terminals 100) and in which a plurality of semiconductor elements (MOS transistors M11 to M14) are connected in parallel; are arranged above the semiconductor element group (group of mirror terminals 100) and the second semiconductor element group (group of mirror terminals 101), and are arranged above the first semiconductor element group (group of mirror terminals 101) and the second semiconductor element group (group of mirror terminals 101). A plurality of wide wirings 20 having a width W2 wider than the width W1 of each semiconductor element of the element group (group of mirror terminals 101) are provided, and the first semiconductor element group (group of mirror terminals 100) and the second semiconductor The element groups (group of mirror terminals 101) are paired to form a circuit having a predetermined pair accuracy. A combination of the distances in the plane direction to the wide wiring 20 closest in the plane direction and the distances from the semiconductor devices (MOS transistors M11 to M14) of the second semiconductor device group (group of mirror terminals 101) to the distance closest in the plane direction. A plurality of wide wires 20 are arranged so that the combination of distances in the plane direction to the wide wires 20 located close to each other is equal.

The above circuit is a current mirror circuit, the first semiconductor element group (group of mirror terminals 100) is a mirror source of the current mirror circuit, and the second semiconductor element group (group of mirror terminals 101) is a current mirror circuit. The circuit is mirrored to.

As a result, in a semiconductor device including a current mirror circuit, it is possible to realize a highly reliable semiconductor device capable of reducing variations in the mirror ratio of the current mirror circuit and suppressing temporal changes in pairing of elements.

Moreover, by mounting the semiconductor device of the present embodiment in a vehicle electronic control device, it is possible to improve the reliability of the vehicle electronic control device.

A semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 8 to 11. FIG. FIG. 8 shows a planar positional relationship among the MOS transistors M01 to M74 constituting the current mirror circuit in the semiconductor device of this embodiment, the wide wiring 20, and the wide wiring 30 of a wiring layer different from the wide wiring 20. For example. In FIG. 8, the MOS transistors M01 to M74 and wide wiring 20 are the same as in FIG. Also, the current mirror circuit of this embodiment is the same as that shown in FIG. FIG. 9 shows the B-B' section of FIG.

The detailed arrangement of the MOS transistors and the wide wirings 20 and 30 of this embodiment will be described below. 10 is a plan view showing an enlarged region of eight MOS transistors M01 to M71 from the left in FIG. 8, and FIG. 11 is a sectional view taken along line C-C' in FIG. 10 and 11, the distances D1, D2, E1 and E2 between the MOS transistors M01 to M71 and the wide wiring 20 in the plane direction are the same as in FIGS. 4 and 5 of the first embodiment.

As shown in FIGS. 10 and 11, the distances in the planar direction between the wide wiring 30 and the MOS transistors M01, M11, M21 and M31 are respectively G1, F1, F2 and F3. The same applies to M41, M51, M61 and M71.

By arranging, as shown in FIG. 8, MOS transistors and wide wiring 20 in the upper layer and wide wiring 30 in a wiring layer different from the wide wiring 20, each terminal mirror in the circuit diagram of FIG. In each set of MOS transistors connected to 101 to 107, the distances in the plane direction from the MOS transistors to the wide wiring 30 are, for example, as follows, all of which are combinations of F1, F2, F3 and G1.

<<mirror terminal 100>> (mirror source)
Transistors M01 to M04: Distances G1, F3, F2, F1 to wide wiring 30
<<mirror terminal 101>> (mirror tip)
Transistors M11 to M14: Distances F1, G1, F3, F2 to wide wiring 30
<<mirror terminal 102>> (mirror tip)
Transistors M21 to M24: Distances F2, F1, G1, F3 to wide wiring 30
<<mirror terminal 103>> (mirror tip)
Transistors M31 to M34: Distances F3, F2, F1, G1 to wide wiring 30
As described above, the combination of distances in the plane direction from the MOS transistor to the wide wiring 20 and the wide wiring 30 is the same between each terminal of the mirror source (100) and the mirror destination (101 to 107) of the current mirror circuit. Since the effect of the stress of the wide wiring can be made equal between the terminals of the mirror source and the mirror destination, it is possible to reduce the initial variation of the mirror ratio of the current mirror circuit and suppress aging deterioration (change over time).

As described above, in the semiconductor device of this embodiment, the plurality of wirings are arranged in the plurality of wide wirings 20 arranged in the first wiring layer and in the second wiring layer different from the first wiring layer. and a plurality of wide wirings 30 that are closest in the plane direction to the semiconductor elements (MOS transistors M01, M11, M21, M31) of the first semiconductor element group (group of mirror terminals 100). The combination of the distances in the plane direction to the wide wiring 20 arranged in the first wiring layer and the semiconductor elements (MOS transistors M41, M51, M61, M71) of the second semiconductor element group (group of mirror terminals 101) ) to the wide wiring 20 arranged on the first wiring layer closest in the plane direction, the plurality of wide wirings 20 on the first wiring layer are arranged such that combinations of respective distances in the plane direction are equal, From each semiconductor element (MOS transistors M01, M11, M21, M31) of the first semiconductor element group (group of mirror terminals 100) to the wide wiring 30 arranged in the second wiring layer closest in the plane direction. A combination of distances in the plane direction and a second wiring layer closest in the plane direction to each semiconductor element (MOS transistors M41, M51, M61, M71) of the second semiconductor element group (group of mirror terminals 101). A plurality of wide wirings 30 on the second wiring layer are arranged so that the combinations of distances in the plane direction to the wide wirings 30 arranged on the second wiring layer are equal.

A semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 12 to 15. FIG. FIG. 12 shows the planar positional relationship among the MOS transistors M01 to M74 forming the current mirror circuit in the semiconductor device of this embodiment, the wide wiring 20, and the wide wiring 31 of a wiring layer different from the wide wiring 20. For example. In FIG. 12, the MOS transistors M01 to M74 and wide wiring 20 are the same as in FIG. Also, the current mirror circuit of this embodiment is the same as that shown in FIG. FIG. 13 shows a cross-sectional view taken along line D-D' of FIG.

In this embodiment, as shown in FIG. 13, the wide wiring 31 is arranged on the MOS transistor side (lower layer side) than the wide wiring 20 .

The detailed arrangement of the MOS transistors and the wide wirings 20 and 31 of this embodiment will be described below. 14 is a plan view showing an enlarged region of eight MOS transistors M01 to M71 from the left in FIG. 12, and FIG. 15 is a cross-sectional view taken along EE' in FIG. 14 and 15, the distances D1, D2, E1 and E2 between the MOS transistors M01 to M71 and the wide wiring 20 in the plane direction are the same as in FIGS. 4 and 5 of the first embodiment.

In addition, the distances in the plane direction between the region where the wide wiring 20 and the wide wiring 31 overlap each other and the MOS transistors M01, M11, M21 and M31 are H3, H2, H1 and J1, respectively. 12 and 13, the MOS transistors constituting the current mirror circuit and the wide wiring 20 and wide wiring 31 in the upper layer are arranged as shown in FIGS. , the distance in the plane direction from the MOS transistor to the overlapping region of the wide wiring 20 and the wide wiring 31 is, for example, as follows, all of which are combinations of H1, H2, H3 and J1.

<<mirror terminal 100>> (mirror source)
Transistors M01 to M04: Distances H3, J1, H1, H2 to wide wiring 31
<<mirror terminal 101>> (mirror tip)
Transistors M11 to M14: Distances H2, H3, J1, H1 to wide wiring 31
<<mirror terminal 102>> (mirror tip)
Transistors M21 to M24: Distances H1, H2, H3, J1 to wide wiring 31
<<mirror terminal 103>> (mirror tip)
Transistors M31 to M34: distances J1, H1, H2, H3 to wide wiring 31
As described above, the combination of the distances in the plane direction from the MOS transistor to the wide wiring 20 and the wide wiring 31 and the combination of the distances in the plane direction from the MOS transistor to the overlap of the wide wiring 20 and the wide wiring 31 are used for the current mirror circuit. By setting the same for each combination of MOS transistors at the terminals of the mirror source and each mirror destination, the influence of the stress of the wide wiring can be equalized between the mirror source and the mirror destination, and the initial dispersion of the mirror ratio of the current mirror circuit. reduction and deterioration over time (change over time) can be suppressed.

As described above, in the semiconductor device of this embodiment, the plurality of wirings are arranged in the plurality of wide wirings 20 arranged in the first wiring layer and in the second wiring layer different from the first wiring layer. The wide wiring 20 arranged in the first wiring layer and the wide wiring 31 arranged in the second wiring layer are arranged so as to overlap each other. wide wiring 20 and the second wiring layer arranged in the first wiring layer nearest to each semiconductor element (MOS transistors M01, M11, M21, M31) of the semiconductor element group (group of mirror terminal 100) in the plane direction. , and each semiconductor element (MOS transistors M41, M51, M61, M71 ) to the position where the wide wiring 20 arranged on the first wiring layer and the wide wiring 31 arranged on the second wiring layer, which are closest in the plane direction, are superimposed on each other. , a wide wiring 20 arranged in the first wiring layer and a wide wiring 31 arranged in the second wiring layer are arranged.

A semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. 16 to 18. FIG. FIG. 16 is an example showing the planar positional relationship between the MOS transistors M01 to M84 and the wide wiring 21 that constitute the current mirror circuit in the semiconductor device of this embodiment. 17 shows a circuit diagram of the current mirror circuit of FIG. In FIG. 16, as in FIG. 1, a plurality of MOS transistors M01 to M84 are arranged in the X direction, and a plurality of wide wirings 21 are arranged to extend in the Y direction perpendicular to the MOS transistors M01 to M84. there is However, in this embodiment, the width W3 of one wide wiring 21 is approximately five times the width W1 of one MOS transistor.

The MOS transistors M01 to M04 connected to the mirror terminal 120 of the mirror source in FIG. 17 are all arranged in the center of the wiring 21 in FIG. On the other hand, the mirror-destination MOS transistors M11 to M84 are arranged in a different order one by one, as in the first embodiment (FIG. 1). In the arrangement of FIG. 17, the combination of distances in the plane direction from each mirror tip to the nearest mirror base is the same between the mirror terminals of the mirror tips. Therefore, variations depending on the distance from the mirror source can be reduced.

FIG. 18 is a plan view showing an enlarged region of nine transistors M11 to M81 from the left in FIG. Let D4, D3, E3 and E4 be the distances in the planar direction from the MOS transistors M11, M21, M31 and M41 to the wiring end of the wide wiring 21, respectively. The same applies to M51 to M81.

By arranging the MOS transistors and the wide wires 21 as shown in FIG. , D4, E3, E4. As a result, the influence of the wide wiring on each mirror destination becomes equal, so that the mirror ratio variation between the mirror destinations is reduced.

However, the effect of wiring stress on the mirror source is different from that on the mirror destination. Therefore, in the case of this embodiment, the MOS transistor sizes of the mirror source and the mirror destination are adjusted so as to obtain the required mirror ratio, and the mirror ratio is corrected by calibration after the semiconductor integrated circuit device is manufactured.

Also, long-term fluctuations in the mirror ratio must be corrected if there are fluctuations. However, since the influence of the distortion due to the wide wiring between the mirror ends is the same, it is not necessary to correct the mirror ratio for each mirror end, and the correction can be simplified.

As described above, in the semiconductor device of this embodiment, the circuit is a current mirror circuit, and a third semiconductor element group (mirror terminal 120) in which a plurality of semiconductor elements (MOS transistors M01 to M04) are connected in parallel. ), the first semiconductor element group (group of mirror terminals 121) and the second semiconductor element group (group of mirror terminals 122) are mirror destinations of the current mirror circuit, and the third semiconductor element group The element group (group of mirror terminals 120) is the mirror source of the current mirror circuit.

In addition, it has a plurality of semiconductor element groups (groups of mirror terminals 121 to 128) serving as mirror destinations, and the distance in the planar direction from each semiconductor element in the plurality of semiconductor element groups (groups of mirror terminals 121 to 128) is the largest. Each combination of distances in the plane direction to the wide wiring 21 at the near position is equal to the combination of distances in the plane direction in the first semiconductor element group (group of mirror terminals 121).

A semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIG. FIG. 19 is an example showing a planar positional relationship between the MOS transistors M01 to M74 constituting the current mirror circuit in the semiconductor device of this embodiment, the wide wiring 20, and the dummy wiring 22 in the same wiring layer as the wide wiring 20. . The current mirror circuit of this embodiment is the same as that shown in FIG.

In this embodiment, only two wide wires 20 are arranged for the arrangement of the MOS transistors M01 to M74 forming the current mirror circuit. A dummy wiring 22 having the same width as the wide wiring 20 in the same wiring layer is arranged at a part of the position where the wide wiring 20 is arranged in FIG. For the same reason as in the first embodiment, the dummy wiring 22 has the effect of equalizing the effect of the stress that the MOS transistor receives from the wide wiring 20 between the terminals at the mirror destination and at the mirror origin.

As shown in the stress simulation result of FIG. 3B, the stress applied to silicon is different between the wiring ends and the wiring center, so the dummy wiring 22 of FIG. 19 needs to be extended in the Y direction from the MOS transistor array.

A semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIGS. 20 and 21. FIG. FIG. 20 is an example showing the planar positional relationship between the MOS transistors M01 to M64 and the wide wiring 20 that constitute the current mirror circuit in the semiconductor device of this embodiment. As in the first embodiment (FIG. 1), the MOS transistors M01 to M64 are arranged in the X direction, and the wide wiring 20 is arranged extending in the Y direction perpendicular to the MOS transistors M01 to M64. Also, the width W2 of one wide wiring 20 is approximately four times the width W1 of one MOS transistor. 21 shows a circuit diagram of the current mirror circuit of FIG.

In FIG. 20, in order to adjust the positions of the MOS transistors M01 to M64 and the wide wiring 20, dummy transistors DM1 to DM4, which are dummy semiconductor elements, are arranged in the MOS transistor array. As a result, as in the first embodiment (FIG. 1), in the group of MOS transistors corresponding to the mirror terminals 130 to 136 in FIG. , the influence of the stress of the wide wiring 20 can be equalized between the mirror source and the mirror destination, and the initial variation of the mirror ratio of the current mirror circuit can be reduced and aged deterioration (change over time) can be suppressed.

The first to sixth embodiments described above are examples of arrangement of MOS transistor sets and upper wirings connected in parallel to the mirror terminals of the current mirror circuit. A semiconductor element such as a resistance element and an upper layer wiring may be arranged.

Moreover, the present invention is not limited to the above-described embodiments, and includes various modifications.
For example, the above-described embodiments have been described in detail in order to explain the present invention in an easy-to-understand manner, and are not necessarily limited to those having all the described configurations. In addition, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Moreover, it is possible to add, delete, or replace a part of the configuration of each embodiment with another configuration.

M0 to M7: MOS transistors M01 to M84: MOS transistors DM1 to DM4: dummy transistors 10: (metal) wiring layer 20, 21: wide (metal) wiring 22: dummy wiring 30 (in the same wiring layer as the metal wiring 20), 31: wide (metal) wiring (of wiring layer different from metal wiring 20) W1 to W3: transistor size or width of metal wiring 100 to 107: mirror terminals (of current mirror circuit) 110 to 117: (of current mirror circuit) Mirror terminals 120 to 128: Mirror terminals (of the current mirror circuit) 130 to 136: Mirror terminals (of the current mirror circuit) D1 to D4: Distance (in the plane direction from the MOS transistor to the wide metal wiring) E1 to E5: (MOS Distances (in the plane direction from the transistor to the wide metal wiring) F1 to F3: Distance (in the plane direction from the MOS transistor to the wide metal wiring) G1: Distance (in the plane direction from the MOS transistor to the wide metal wiring) H1 to H3: Distance (in the plane direction from the MOS transistor to the overlap of the wide metal wiring) J1: Distance (in the plane direction from the MOS transistor to the overlap of the wide metal wiring) 200: Copper wiring 300: Silicon substrate (semiconductor substrate)
301: Silicon (Si) layer 302: Interface (between silicon layer 301 and silicon oxide film 401) 400: Silicon oxide film 401: Silicon oxide film (interlayer oxide film)
500: Polyimide film

Claims (9)

a first semiconductor element group in which a plurality of semiconductor elements are connected in parallel;
a second semiconductor element group arranged in the same layer as the first semiconductor element group and having a plurality of semiconductor elements connected in parallel;
a plurality of semiconductor element groups arranged in a higher layer than the first semiconductor element group and the second semiconductor element group and having a width wider than that of each semiconductor element of the first semiconductor element group and the second semiconductor element group; with wiring and
the first semiconductor element group and the second semiconductor element group are paired to form a circuit having a predetermined pair accuracy;
A combination of distances in the planar direction from each semiconductor element of the first semiconductor element group to the wiring closest in the planar direction, and a position closest to the semiconductor element in the second semiconductor element group in the planar direction. 2. A semiconductor device in which the plurality of wirings are arranged so that the combinations of distances in the plane direction to the wirings of are equal. The semiconductor device according to claim 1,
The plurality of wirings includes a plurality of wirings arranged in a first wiring layer and a plurality of wirings arranged in a second wiring layer different from the first wiring layer,
a combination of distances in the planar direction from each semiconductor element of the first semiconductor element group to a wire arranged in the first wiring layer at a position closest in the planar direction;
The first wiring layer is formed so that the combinations of distances in the planar direction from each semiconductor element of the second semiconductor element group to the wiring arranged in the first wiring layer closest in the planar direction are equal. are placed, and
a combination of distances in the planar direction from each semiconductor element of the first semiconductor element group to a wiring arranged in the second wiring layer closest in the planar direction;
The second wiring layer is formed so that the combinations of distances in the plane direction from each semiconductor element of the second semiconductor element group to the wiring arranged in the second wiring layer closest in the plane direction are equal. A semiconductor device in which a plurality of wirings are arranged. The semiconductor device according to claim 1,
The plurality of wirings includes a plurality of wirings arranged in a first wiring layer and a plurality of wirings arranged in a second wiring layer different from the first wiring layer,
The wiring arranged in the first wiring layer and the wiring arranged in the second wiring layer are arranged so as to overlap,
each in the plane direction from each semiconductor element of the first semiconductor element group to a position where the wiring arranged in the first wiring layer closest in the plane direction and the wiring arranged in the second wiring layer overlap each other; A combination of distances and
each in the plane direction from each semiconductor element of the second semiconductor element group to a position where the wiring arranged in the first wiring layer closest in the plane direction and the wiring arranged in the second wiring layer overlap each other; A semiconductor device, wherein the wirings arranged in the first wiring layer and the wirings arranged in the second wiring layer are arranged such that the combinations of distances are equal. The semiconductor device according to any one of claims 1 to 3,
the circuit is a current mirror circuit,
the first semiconductor element group is a mirror source of the current mirror circuit;
A semiconductor device in which the second semiconductor element group is a mirror destination of the current mirror circuit. The semiconductor device according to any one of claims 1 to 3,
the circuit is a current mirror circuit,
further comprising a third semiconductor element group in which a plurality of semiconductor elements are connected in parallel;
the first semiconductor element group and the second semiconductor element group are mirror destinations of the current mirror circuit;
A semiconductor device in which the third semiconductor element group is a mirror source of the current mirror circuit. 6. The semiconductor device according to claim 4 or 5,
It has multiple semiconductor element groups that serve as mirror destinations,
Each combination of the distances in the plane direction from each semiconductor element in the plurality of semiconductor element groups to the wiring at the position closest in the plane direction is equal to the combination of the distances in the plane direction in the first semiconductor element group. semiconductor device. The semiconductor device according to any one of claims 1 to 3,
A semiconductor device including a dummy wiring in the plurality of wirings. The semiconductor device according to any one of claims 1 to 3,
A semiconductor device including a dummy semiconductor element in the arrangement of the plurality of semiconductor elements. An in-vehicle electronic control device comprising the semiconductor device according to claim 1 .

Images