JP7111533B2 - Zero point detector - Google Patents

Description

The present invention relates to a zero-point detection device that uses a voltage whose magnitude and direction periodically change as an input voltage and detects the rise and fall times of this input voltage from a reference voltage as zero points, and particularly relates to an ultrasonic flow rate. The present invention relates to a zero point detection device suitable for use in a meter.

An ultrasonic flow meter uses two piezoelectric elements to measure the flow rate of a fluid. For example, as shown in FIG. 13, a transmission circuit (TX) 103 is used to propagate sound waves from a piezoelectric element 101 to a channel 107, and the other piezoelectric element 102 receives the sound waves. After the received signal is amplified and filtered by the receiving circuit (RX) 104, the comparator 105 detects the zero point (point crossing the reference potential (zero crossing point)), and the transmission start time and the zero point detection time are determined. A time-to-digital conversion circuit (TDC) 106 is used to measure the propagation time. In the example shown in FIG. 13, the flow of sound waves is in the same direction as the direction of the fluid, so the time is measured at the combined speed of the flow velocity and the sound velocity.

Similarly, as shown in FIG. 14, sound waves are propagated from the piezoelectric element 102 and received by the piezoelectric element 101 . Since the sound wave flows in the opposite direction to the direction of the fluid, the time is measured by the speed of sound minus the flow speed. The flow velocity can be obtained from the difference between forward and reverse time measurements (more precisely, the difference of the reciprocal) and the propagation distance, and the flow rate of the fluid can be obtained from the pipe diameter. 13 and 14, the side on which the piezoelectric element 101 is installed is defined as the DOWN side, and the side on which the piezoelectric element 102 is installed is defined as the UP side.

FIG. 15 shows transmission/reception waveforms of the ultrasonic flowmeter. The transmission waveform is a burst wave, and pulses are transmitted several times. A sound wave is transmitted from the piezoelectric element 101 (DOWN side), and after a propagation time (Tdelay), the other piezoelectric element 102 (UP side) receives a signal. Tdelay is determined by propagation distance, sound velocity, and fluid velocity. The speed of sound varies depending on temperature, gas species, and the like. After a certain period of time (Talt), a sound wave is transmitted from the other piezoelectric element 102 (UP side) and received by the opposite piezoelectric element 101 (DOWN side). This operation is repeated at intervals (Tint).

Japanese Patent No. 2859751

As described above, in the ultrasonic flowmeter, the zero point is detected by the comparator when measuring the propagation time. This comparator corresponds to the zero point detection device referred to in the present invention. The comparator must pulse out exactly at the zero point of the incoming waveform. The input waveform is a signal whose voltage magnitude and direction change periodically around the reference potential, and the zero points of both rising and falling edges of this signal are detected.

A comparator must have hysteresis to avoid malfunction due to noise, and a simple comparator cannot detect both the rising and falling zero points. Also, in propagation time measurement, in order to avoid erroneous detection due to noise, a mechanism is required to start zero point detection when the signal exceeds a certain threshold (zero point detection start voltage). Furthermore, from the viewpoint of signal processing in the subsequent stage, it is necessary to determine whether the detected zero point is the rising zero point or the trailing zero point, and output the determination results together.

Note that Patent Document 1 discloses a comparator that outputs both rising and falling zero points with the same polarity. In the comparator disclosed in Patent Document 1, by using an edge detector, it is possible to determine whether the zero point is the rising zero point or the falling zero point.

However, when the comparator shown in Patent Document 1 is used as a comparator (zero point detection device) in an ultrasonic flowmeter, the zero point detection start voltage cannot be set, so the comparator (zero point detection It is necessary to separately provide a comparator for determining the start of zero point detection in the device).

Ultrasonic flowmeters require a high-speed comparator (zero-point detector) in order to accurately measure time, and tend to consume a large amount of power. In such an ultrasonic flowmeter, if a plurality of comparators are provided in a comparator (zero point detection device), power consumption will further increase. The power consumption of ultrasonic flowmeters is severely restricted, and for example, a 10-year warranty is required for battery-powered flowmeters, and an increase in power consumption is undesirable.

SUMMARY OF THE INVENTION The present invention has been made to solve such problems, and its purpose is to perform zero point detection start determination and zero point detection with a single comparator, and to detect both rising and falling zero points. To provide a zero point detection device capable of outputting points with the same polarity and consuming less power.

In order to achieve such an object, the present invention uses a voltage whose magnitude and direction periodically change as an input voltage (VI), and defines the rising and falling times of this input voltage from a reference voltage (VREF). In a zero point detection device (100) for detecting as a zero point, a reference voltage (VREF), a first threshold voltage (VTHP) set on the positive side with respect to the reference voltage, and a voltage on the negative side with respect to the reference voltage. A reference voltage/threshold voltage generating circuit (1) configured to generate a predetermined second threshold voltage (VTHM), an input voltage (VI), a reference voltage (VREF), a first threshold voltage ( VTHP) and a second threshold voltage (VTHM) are input, and the point at which the input voltage falls below the reference voltage after exceeding the first threshold voltage is detected as the falling zero point. a zero point detection unit (2) configured to detect the point of time when the reference voltage is exceeded after falling below the voltage as the rising zero point, and the first threshold voltage (VTHP) is the falling zero point; The second threshold voltage (VTHM) also serves as the zero point detection start voltage (VTHSP) when starting detection from the rising zero point (VTHSM) when starting detection from the rising zero point. It is characterized by

In the present invention, the point at which the input voltage falls below the reference voltage after exceeding the first threshold voltage is detected as the falling zero point, and the point at which the input voltage exceeds the reference voltage after falling below the second threshold voltage. is detected as the rising zero point. In this case, the first threshold voltage creates a dead zone between the detection of the rising zero point and the detection of the next falling zero point, and the second threshold voltage detects the falling zero point. A dead zone is created until the next rising zero point is detected after detection, and this dead zone serves as hysteresis for avoiding malfunction due to noise. The first threshold voltage also serves as a zero point detection start voltage when detection is started from the zero point of falling edge, and the second threshold voltage is the zero point detection voltage when detection is started from zero point of rising edge. Also serves as the starting voltage.

As a result, in the present invention, it is possible to perform zero point detection start determination and zero point detection with one comparator, and to output both rising and falling zero points with the same polarity. In the present invention, when starting the detection of the zero point, the detection may be started from the falling zero point or from the rising zero point. For example, a reset signal or a set signal is used to select and set whether to start detection from the zero point of falling edge or from the zero point of rising edge.

In the above description, as an example, constituent elements on the drawings corresponding to constituent elements of the invention are indicated by parenthesized reference numerals.

As described above, according to the present invention, the time when the input voltage falls below the reference voltage after exceeding the first threshold voltage is detected as the falling zero point, and the input voltage falls below the second threshold voltage. After that, the time when the reference voltage is exceeded is detected as the rising zero point, and the first threshold voltage is also used as the zero point detection start voltage when starting the detection from the falling zero point. Since the threshold voltage is also used as the zero point detection start voltage when detection is started from the rising zero point, one comparator performs zero point detection start determination and zero point detection, and detects both rising and falling edges. It becomes possible to output the zero point with the same polarity, and power consumption can be reduced.

FIG. 1 is a circuit diagram showing essential parts of a zero point detection device according to an embodiment of the present invention. FIG. 2 is a diagram showing input and output waveforms of this zero point detector. FIG. 3 is a diagram showing a control state (first control mode) of the operation of the switch section by the switch control section at point t0 in FIG. FIG. 4 is a diagram showing a control state (second control mode) of the operation of the switch section by the switch control section at point t1 in FIG. FIG. 5 is a diagram showing a control state (third control mode) of the operation of the switch section by the switch control section at point t2 in FIG. FIG. 6 is a diagram showing a control state (fourth control mode) of the operation of the switch section by the switch control section at point t3 in FIG. FIG. 7 is a diagram showing a control state (first control mode) of the operation of the switch section by the switch control section at point t4 in FIG. FIG. 8 is a diagram corresponding to FIG. 2(a) when detection is started from the rising zero point. FIG. 9 is a circuit diagram showing essential parts of a zero-point detection device having an offset cancellation function. FIG. 10 is a diagram showing an excerpt from the peripheral circuits around the comparator in FIG. FIG. 11 shows a state when the clock CLK_CMP is set to "L" level in FIG. FIG. 12 shows a state when the clock CLK_CMP is set to "H" level in FIG. FIG. 13 is a diagram for explaining time measurement (time measurement from the DOWN side to the UP side) of the ultrasonic flowmeter. FIG. 14 is a diagram for explaining time measurement (time measurement from the UP side to the DOWN side) of the ultrasonic flowmeter. FIG. 15 is a diagram showing transmission and reception waveforms of an ultrasonic flowmeter.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing essential parts of a zero point detection device 100 (100A) according to an embodiment of the present invention. This zero point detection device 100A is used as the comparator 105 in the ultrasonic flowmeter shown in FIG.

A zero-point detection device 100A of the present embodiment includes a reference voltage/threshold voltage generation circuit 1 and a zero-point detection section 2. The zero-point detection section 2 includes a switch section 3 and a comparator (amplifier for comparator) 4. and a switch control unit 5 .

In this zero point detection device 100A, a reference voltage/threshold voltage generation circuit 1 includes a reference voltage VREF, a first threshold voltage (+side threshold voltage) VTHP set on the positive side with respect to the reference voltage VREF, and a reference voltage VREF. generating a second threshold voltage (negative threshold voltage) VTHM determined on the negative side with respect to the voltage VREF, outputting the reference voltage VREF from the terminal 1a, outputting the positive threshold voltage VTHP from the terminal 1b, The minus side threshold voltage VTHM is output from the terminal 1c.

The switch section 3 includes switches SW1 to SW6, and one ends of the switches SW1 and SW2 are connected to the input terminal PI1. A received waveform of a sound wave received by the piezoelectric element 102 shown in FIG. 13 is inputted to the input terminal PI1. That is, a voltage whose magnitude and direction change periodically is input as input voltage VI.

In the switch section 3, one end of the switch SW3 is connected to the terminal 1b to which the + side threshold voltage VTHP of the reference voltage/threshold voltage generation circuit 1 is input, and one ends of the switches SW4 and SW5 are connected to the reference voltage of the reference voltage/threshold voltage generation circuit 1. One end of the switch SW6 is connected to a terminal 1a to which VREF is output, and a terminal 1c to which the minus side threshold voltage VTHM of the reference voltage/threshold voltage generating circuit 1 is input. The other ends of the switches SW1, SW5 and SW6 are connected to the non-inverting input end of the comparator 4, and the other ends of the switches SW2, SW3 and SW4 are connected to the inverting input end of the comparator 4. FIG.

The switch control unit 5 includes an inverter circuit 6, NOR circuits 7_1 to 7_4, and a D flip-flop circuit 8. The input terminal of the inverter circuit 6 is connected to the output terminal of the comparator 4 , and the output terminal of the inverter circuit 6 is connected to the clock input terminal of the D flip-flop circuit 8 . The Q output terminal of the D flip-flop circuit 8 is connected to the output terminal PO2, the Q-bar output terminal of the D flip-flop circuit 8 is connected to the D input terminal of the D flip-flop circuit 8, and the reset terminal of the D flip-flop circuit 8 is connected to It is connected to the input terminal PI2. An output terminal PO1 is connected to a connection line between the output terminal of the inverter circuit 6 and the clock input terminal of the D flip-flop circuit 8. FIG.

In the switch control section 5, the Q output of the D flip-flop circuit 8 is output from the output terminal PO2 as the voltage VQ. Also, the voltage generated at the output terminal of the inverter circuit 6 is output from the output terminal PO1 as the voltage VO. As will be described later, the voltage VO output from the output terminal PO1 is a signal indicating the zero point (zero point detection signal), and the voltage VQ output from the output terminal PO2 is the falling zero point. It is a signal indicating whether it is the rising zero point. Further, a reset signal RN is input to the D flip-flop circuit 8 from the input terminal PI2 as a signal for selecting/setting to start the detection from the falling zero point.

In the switch control unit 5, the NOR circuit 7_1 receives the output voltage VOX of the comparator 4 and the Q output (voltage VQ) of the D flip-flop circuit 8, and outputs the logic voltage VOPX. The NOR circuit 7_2 receives the output voltage VO of the inverter circuit 6 and the Q output (voltage VQ) of the D flip-flop circuit 8, and outputs a logic voltage VOP. The NOR circuit 7_3 receives the output voltage VO of the inverter circuit 6 and the Q-bar output (voltage VQN) of the D flip-flop circuit 8, and outputs a logic voltage VOM. The NOR circuit 7_4 receives the output voltage VOX of the comparator 4 and the Q-bar output (voltage VQN) of the D flip-flop circuit 8, and outputs a logic voltage VOMX.

In the switch section 3, the switch SW1 is turned on when the Q-bar output (voltage VQN) of the D flip-flop circuit 8 becomes "H" level, and turned off when it becomes "L" level. The switch SW2 is turned on when the Q output (voltage VQ) of the D flip-flop circuit 8 is at "H" level, and is turned off when it is at "L" level. The switch SW3 is turned on when the logic voltage VOPX from the NOR circuit 7_1 becomes "H" level, and is turned off when it becomes "L" level. The switch SW4 is turned on when the logic voltage VOP from the NOR circuit 7_2 becomes "H" level, and is turned off when it becomes "L" level. The switch SW5 is turned on when the logic voltage VOM from the NOR circuit 7_3 becomes "H" level, and is turned off when it becomes "L" level. The switch SW6 is turned on when the logic voltage VOMX from the NOR circuit 7_4 becomes "H" level, and is turned off when it becomes "L" level.

FIG. 2 shows input and output waveforms of this zero point detection device 100A. 2(a) shows the input voltage VI inputted to the input terminal PI1, FIG. 2(b) shows the reset signal RN inputted to the input terminal PI2, and FIG. 2(c) shows the reset signal RN outputted from the output terminal PO2. FIG. 2D shows the voltage VQ (the Q output of the D flip-flop circuit 8) which is output from the output terminal PO1 (the output voltage of the inverter circuit 6).

In this zero point detection device 100A, first, a reset signal RN is given to the D flip-flop circuit 8. As shown in FIG. That is, the reset signal RN to the D flip-flop circuit 8 is set to "H" level (FIG. 2: point t0). As a result, the D flip-flop circuit 8 is reset, the Q output (voltage VQ) of the D flip-flop circuit 8 is at "L" level, and the Q bar output (voltage VQN) is at "H" level. Also, the logic voltage VOPX output from the NOR circuit 7_1 becomes the "H" level (see FIG. 3). In this example, it is assumed that before reset signal RN is applied to D flip-flop circuit 8, voltage VQ is at "L" level and voltage VO is at "H" level.

As a result, the switches SW1 and SW3 in the switch section 3 are turned on, the input voltage VI is input to the non-inverting input terminal of the comparator 4, and the positive side threshold voltage VTHP is set to the inverting input terminal of the comparator 4. will be made. The control state of the operation of the switch section 3 by the switch control section 5 that turns on the switches SW1 and SW3 is called a first control mode M1.

In this first control mode M1, the positive side threshold voltage VTHP is set to the inverting input terminal of the comparator 4 . As a result, as will be described later, detection is started from the zero point of the trailing edge. In this embodiment, when starting the detection of the zero point, the reset signal RN is used to reset the D flip-flop circuit 8, and the detection is started from the falling zero point. .

In this first control mode M1, the output voltage VOX of the comparator 4 maintains the "L" level until the input voltage VI exceeds the + side threshold voltage VTHP (FIG. 2: points t0 to t1). When the input voltage VI exceeds the + side threshold voltage VTHP (FIG. 2: point t1), the output voltage VOX of the comparator 4 becomes "H" level, and the output voltage VO of the inverter circuit 6 becomes "L" level (FIG. 4). reference). Therefore, the logic voltage VOPX output from the NOR circuit 7_1 becomes "L" level, and the logic voltage VOP output from the NOR circuit 7_2 becomes "H" level.

As a result, in the switch section 3, the switch SW3 is turned off, the switch SW4 is turned on, and the voltage set to the inverting input terminal of the comparator 4 is switched from the + side threshold voltage VTHP to the reference voltage VREF. Since the voltage VQN is maintained at the "H" level, the switch SW1 remains on, and the non-inverting input terminal of the comparator 4 continues to receive the input voltage VI. The control state of the operation of the switch section 3 by the switch control section 5 that turns on the switches SW1 and SW4 is called a second control mode M2.

In this second control mode M2, until the input voltage VI falls below the reference voltage VREF (FIG. 2: points t1 to t2), the output voltage VOX of the comparator 4 is maintained at the "H" level, and the output voltage VO of the inverter circuit 6 is maintained. keeps "L" level. When the input voltage VI falls below the reference voltage VREF (FIG. 2: point t2), the output voltage VOX of the comparator 4 becomes "L" level, and the output voltage VO of the inverter circuit 6 becomes "H" level (see FIG. 5). .

When the output voltage VO of the inverter circuit 6 becomes "H" level, the Q output (voltage VQ) of the D flip-flop circuit 8 becomes "H" level, the Q bar output (voltage VQN) becomes "L" level, and the NOR circuit 7_2. The logic voltage VOP output by the NOR circuit 7_4 is at the "L" level, and the logic voltage VOMX output by the NOR circuit 7_4 is at the "H" level.

As a result, in the switch section 3, the switches SW1 and SW4 are turned off and the switches SW2 and SW6 are turned on. The - side threshold voltage VTHM is set at the end. The control state of the operation of the switch section 3 by the switch control section 5 that turns on the switches SW2 and SW6 is called a third control mode M3.

In the third control mode M3, the output voltage VOX of the comparator 4 is at the "L" level until the input voltage VI falls below the negative side threshold voltage VTHM (points t2 to t3 in FIG. 2), and the output voltage of the inverter circuit 6 VO keeps "H" level. When the input voltage VI falls below the negative side threshold voltage VTHM (Fig. 2: point t3), the output voltage VOX of the comparator 4 becomes "H" level, and the output voltage VO of the inverter circuit 6 becomes "L" level (Fig. 6). reference). Therefore, the logic voltage VOMX output from the NOR circuit 7_4 becomes "L" level, and the logic voltage VOM output from the NOR circuit 7_3 becomes "H" level.

As a result, in the switch section 3, the switch SW6 is turned off, the switch SW5 is turned on, and the voltage set to the non-inverting input terminal of the comparator 4 is switched from the - side threshold voltage VTHM to the reference voltage VREF. Since the voltage VQ is maintained at the "H" level, the switch SW2 remains on, and the input voltage VI continues to be input to the inverting input terminal of the comparator 4. FIG. The control state of the operation of the switch section 3 by the switch control section 5 that turns on the switches SW2 and SW5 is called a fourth control mode M4.

In the fourth control mode M4, until the input voltage VI exceeds the reference voltage VREF (Fig. 2: points t3 to t4), the output voltage VOX of the comparator 4 is maintained at the "H" level, and the output voltage VO of the inverter circuit 6 is maintained. keeps "L" level. When the input voltage VI exceeds the reference voltage VREF (FIG. 2: point t4), the output voltage VOX of the comparator 4 becomes "L" level, and the output voltage VO of the inverter circuit 6 becomes "H" level (see FIG. 7). .

When the output voltage VO of the inverter circuit 6 becomes "H" level, the Q output (voltage VQ) of the D flip-flop circuit 8 becomes "L" level, the Q bar output (voltage VQN) becomes "H" level, and the NOR circuit 7_1. The logic voltage VOPX output by the NOR circuit 7_3 is at the "H" level, and the logic voltage VOM output by the NOR circuit 7_3 is at the "L" level.

As a result, in the switch section 3, the switches SW2 and SW5 are turned off, and the switches SW1 and SW3 are turned on. A + side threshold voltage VTHP is set at the end. That is, the control state of the operation of the switch section 3 by the switch control section 5 returns to the first control mode M1. Similarly, the switch control unit 5 repeats the control of the operation of the switch unit 3 in the order of the first control mode M1, the second control mode M2, the third control mode M3, and the fourth control mode M4. .

In this manner, in the zero-point detection device 100A of the present embodiment, the voltage VO becomes the "H" level each time the waveform of the input voltage VI crosses the reference voltage VREF, and the rising and falling edges thereof change with the same polarity. A voltage VO is obtained from the output terminal PO1 as a zero point detection signal. Further, the voltage VQ changes to "H" level when the zero point of the falling edge is detected, changes to the "L" level when the zero point of the rising edge is detected, and the level changes when the zero point is detected. The voltage VQ is obtained from the output terminal PO2 as a signal indicating whether the detected zero point is the trailing zero point or the rising zero point.

In this zero point detection device 100A, the falling zero point ZPD is detected when the input voltage VI exceeds the + side threshold voltage VTHP and then falls below the reference voltage VREF, and when the input voltage VI falls below the - side threshold voltage VTHM. After that, the time when it exceeds the reference voltage VREF is detected as the rising zero point ZPU. In this case, the + side threshold voltage VTHP forms a dead zone α after the rising zero point ZPU is detected until the next falling zero point ZPD is detected, and the - side threshold voltage VTHM is the falling zero point ZPD. After the zero point ZPD is detected, a dead zone β is created until the next rising zero point ZPU is detected. In the zero point detection device 100A, the + side threshold voltage VTHP also serves as the zero point detection start voltage VTHSP when detection is started from the falling zero point ZPD. This makes it possible to reduce the influence of noise and perform accurate time measurement.

In this way, according to the zero point detection device 100A of the present embodiment, one comparator (amplifier for comparator) 4 performs zero point detection start determination and zero point detection, and detects both rising and falling zero points. Points can be output with the same polarity, and power consumption can be reduced.

In the above-described embodiment, the reset signal RN is used to reset the D flip-flop circuit 8, and selection/setting is made to start detection from the falling zero point. A set signal (not shown) to the circuit 8 may be used to set the D flip-flop circuit 8, and selection/setting may be made to start detection from the rising zero point.

In this case, as shown in FIG. 8, control of the operation of the switch section 3 is repeated in the order of the third control mode M3, the fourth control mode M4, the first control mode M1, and the second control mode M2. make it In this case, the minus side threshold voltage VTHM also serves as the zero point detection start voltage VTHSM when detection is started from the rising zero point.

Further, like the zero point detection device 100 (100B) shown in FIG. You may make it cancel.

In this zero point detection device 100B, switches SWA1, SWA2, SWA3 and switches SWB1, SWB2 are provided, a signal obtained by inverting a clock (offset cancel function clock) CLK_CMP is set as SEL, and a signal obtained by further inverting this SEL is set as SELB. , switches SWA1, SWA2 and SWA3 are turned on when SEL is at the "H" level, and switches SWB1 and SWB2 are turned on when SELB is at the "H" level to store the offset voltage in the capacitor C, I am trying to get an offset cancellation function.

FIG. 10 shows an excerpt from a peripheral circuit centered on the comparator (amplifier) 4 . When the clock CLK_CMP is set to "L" level (see FIG. 11), the switches SWA1, SWA2 and SWA3 are turned on. At this time, the comparator 4 becomes a voltage follower circuit and is given as Vo=A·(V _R +V _os -Vo). Vo is the output of the comparator 4 (amplifier output), V _R is the voltage of the terminal 1a, _Vos is the offset voltage generated at the non-inverting input terminal of the comparator 4, and A is the amplification factor of the comparator (amplifier) 4.

In this case, due to the conservation of charge in the capacitor C, C·(V _R −(A/(A+1))·(V _R +V _os ))=C·(V _A −V _IN ). _VA is the voltage at the non-inverting input terminal of the comparator 4 of the capacitor C, and _VIN is the voltage at the terminal PI1.

When the clock CLK_CMP is set to "H" level (see FIG. 12), the switches SWB1 and SWB2 are turned on. In this case, V _A =V _IN +(1/(1+A)).V _R -(A/(1+A)).V _os ≈V _IN -V _os . As a result, the non-inverting input terminal of the comparator 4 receives the voltage V _IN with the offset voltage V _os canceled.

In the above-described embodiment, the zero-point detection device according to the present invention has been described as an example of using it in an ultrasonic flowmeter, but it can be used in general applications for time measurement of sound waves, light, and the like. In addition, the present invention is not limited to time measurement, and can be used for various kinds of signal processing using a voltage whose magnitude and direction change periodically as an input voltage.

[Expansion of Embodiment]
Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the technical idea of the present invention.

DESCRIPTION OF SYMBOLS 1... Reference voltage/threshold voltage generation circuit 2... Zero point detection part 3... Switch part 4... Comparator 5... Switch control part 6... Inverter circuit 7_1 to 7_4... NOR circuit 8... D flip-flop circuit , M1... first control mode, M2... second control mode, M3... third control mode, M4... fourth control mode, VREF... reference voltage, VTHP... first threshold voltage (+ side threshold voltage ), VTHM... second threshold voltage (negative side threshold voltage), VTHSP, VTHSM... zero point detection start voltage, ZPD... falling zero point, ZPU... rising zero point, α, β... dead zone, C... capacitor , 100 (100A, 100B) . . . zero point detectors.

Claims (3)

A zero-point detection device that receives a voltage whose magnitude and direction periodically change as an input voltage and detects the rising and falling times of the input voltage from a reference voltage as zero points,
configured to generate the reference voltage, a first threshold voltage determined on the positive side with respect to the reference voltage, and a second threshold voltage determined on the negative side with respect to the reference voltage a reference voltage/threshold voltage generating circuit;
The input voltage, the reference voltage, the first threshold voltage, and the second threshold voltage are used as inputs, and the fall occurs at the time when the input voltage exceeds the first threshold voltage and then falls below the reference voltage. A zero point detection unit configured to detect as a zero point and detect a time point when the input voltage exceeds the reference voltage after falling below the second threshold voltage as a rising zero point,
The first threshold voltage is
Also serves as a zero point detection start voltage when detection is started from the zero point of the falling edge,
The second threshold voltage is
Also serves as a zero point detection start voltage when starting detection from the zero point of the rise ,
The zero point detection unit is
a switch unit that receives the input voltage, the reference voltage, the first threshold voltage, and the second threshold voltage;
a switch control unit that controls the operation of the switch unit;
A sole comparator provided between the switch unit and the switch control unit,
The switch control unit
a first control mode for controlling the operation of the switch unit so that the input voltage is applied to the non-inverting input terminal of the comparator and the first threshold voltage is applied to the inverting input terminal of the comparator;
A state in which the input voltage is applied to the non-inverting input terminal of the comparator when the output of the comparator becomes "H" level after the operation of the switch section is controlled by the first control mode. a second control mode for controlling the operation of the switch section so as to apply the reference voltage to the inverting input terminal of the comparator;
a third control mode for controlling the operation of the switch unit so that the input voltage is applied to the inverting input terminal of the comparator and the second threshold voltage is applied to the non-inverting input terminal of the comparator;
When the output of the comparator becomes "H" level after the operation of the switch section is controlled by the third control mode, the input voltage is applied to the inverting input terminal of the comparator. and a fourth control mode for controlling the operation of the switch unit so as to apply the reference voltage to the non-inverting input terminal of the comparator,
After controlling the operation of the switch section in the second control mode, when the output of the comparator becomes "L" level, detecting that point as the falling zero point,
After the operation of the switch section is controlled by the fourth control mode, when the output of the comparator becomes "L" level, that point is detected as the zero point of the rise.
A zero point detection device characterized by: In the zero point detection device according to claim 1 ,
A zero point detection device, wherein a capacitor for canceling an offset voltage generated at the non-inverting input terminal of the comparator is connected to a voltage input line to the non-inverting input terminal of the comparator. In the zero point detection device according to claim 1 or claim 2 ,
The zero point detection unit is
A zero-point detection device comprising a selection/setting unit for starting detection from the zero point of the trailing edge or from the zero point of the rising edge.

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