JP7092968B2 - Semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device including a group III nitride semiconductor. In particular, the present invention relates to a semiconductor device having a p-type p-type region formed by ion implantation and heat treatment.

Group III nitride semiconductors such as GaN have a high dielectric breakdown electric field and can achieve both high withstand voltage and low on-resistance, so they are attracting attention as materials for power devices and are being actively researched and developed. ing.

Patent Document 1 describes a pn diode made of a group III nitride semiconductor, and a low-loss element can be realized by setting the average density of carrier trap levels of the n-layer and p-layer to a predetermined value or less. Is described. The reason why such an effect is obtained is that by reducing the average density of carrier trap levels, non-luminescence recombination is relatively suppressed, luminescence recombination increases, and light due to luminescence recombination is absorbed by the p-layer. It is considered that this is because the hole concentration is increased.

Japanese Unexamined Patent Publication No. 2013-33913

When ion implantation and heat treatment are performed to form the p-layer, there is a problem that the leakage current increases. This is thought to be related to the carrier trap level. However, in Patent Document 1, it is not clear which of the plurality of carrier trap levels contributes to the leakage current. Further, Patent Document 1 does not describe how to control the average density of carrier trap levels.

Therefore, an object of the present invention is to realize a semiconductor device made of a group III nitride semiconductor in which a leakage current is suppressed and a method for manufacturing the same.

The first aspect of the present invention is an n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ , and p provided by ion implantation and heat treatment in a part of the n-layer. It has a p-type region, which is a region made of type GaN, and a Schottky electrode provided on the n-layer and on the p-type region and in Schottky contact with the n-layer.
The area without the p-shaped area in the plan view is defined as the A area.
From the lower end of the conduction band of GaN, the electron trap level of energy of 0.10 eV or more and less than 0.20 eV is set to TE1.
TE3, the electron trap level of energy of 0.30 eV or more and less than 0.45 eV from the lower end of the conduction band of GaN.
Let TE4 be the electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN.
The average density of each electron trap level in the A region is the average density of each electron trap level in the n layer in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the Schottky electrode to the n layer side. As an average density
The average density of each electron trap level in the A region is
The ratio of the average density of the electron trap levels of TE1 to the average density of the electron trap levels of TE4 is larger than the ratio of the average density of the electron trap levels of TE3 to the average density of the electron trap levels of TE4, and The ratio of the average density of the electron trap level of TE1 to the average density of the electron trap level of TE4 is set to be 1 or less.
It is a semiconductor device characterized by this.

A second aspect of the present invention is an n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ , and p provided by ion implantation and heat treatment in a part of the n-layer. It has a p-type region, which is a region made of type GaN, and a Schottky electrode provided on the n-layer and on the p-type region and in Schottky contact with the n-layer.
The area with the p-shaped area in the plan view is defined as the B area.
From the lower end of the conduction band of GaN, the electron trap level of energy of 0.10 eV or more and less than 0.20 eV is set to TE1.
TE2, the electron trap level of energy of 0.20 eV or more and less than 0.30 eV from the lower end of the conduction band of GaN.
TE4, the electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN.
Let TE9 be the electron trap level of energy of 1.10 eV or more and less than 1.40 eV from the lower end of the conduction band of GaN.
The average density of each electron trap level in the B region is the average density of each electron trap level in the n layer in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the p-type region to the n layer side. As an average density
The average density of each electron trap level in region B is
The ratio of the average density of the electron trap levels of TE2 to the average density of the electron trap levels of TE4 is larger than the ratio of the average density of the electron trap levels of TE9 to the average density of the electron trap levels of TE4. The ratio of the average density of the electron trap levels of TE9 to the average density of the electron trap levels is set to be larger than the ratio of the average density of the electron trap levels of TE1 to the average density of the electron trap levels of TE4. ing,
It is a semiconductor device characterized by this.

In the first and second aspects of the present invention, it is preferable that the settings are as follows in order to further suppress the leakage current.

It is preferable that the ratio of the average density of the electron trap level of TE1 in the region A to the average density of the electron trap level of TE1 in the region B is 0.01 or less.

It is preferable that the ratio of the average density of the electron trap level of TE2 in the region A to the average density of the electron trap level of TE2 in the region B is 0.01 or less.

It is preferable that the ratio of the average density of the electron trap level of TE4 in the region A to the average density of the electron trap level of TE4 in the region B is 0.4 to 2.5.

Let TE7 be the electron trap level of energy of 0.90 eV or more and less than 1.00 eV from the lower end of the conduction band of GaN, and the average density of the electron trap level of TE7 in the A region with respect to the average density of the electron trap level of TE7 in the B region. It is preferable that the ratio of is set to 0.2 or less.

It is preferable that the ratio of the average density of the electron trap level of TE9 in the region A to the average density of the electron trap level of TE9 in the region B is 0.04 or less.

Further, the third aspect of the present invention is an n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ and a p-layer made of p-type GaN provided on the n layer. And a p-type region which is a region made of p-type GaN provided by ion implantation and heat treatment in a part of the n-layer.
The area without the p-shaped area in the plan view is defined as the A area.
The electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN is set to TE4.
The average density of each electron trap level in the A region is the average of each electron trap level in the n layer in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the p layer to the n layer side. As a density
The average density of the electron trap levels of TE4 in the n-layer in the A region is set to be 1/500 or less of the donor concentration of the n-layer.
It is a semiconductor device characterized by this.

Further, a fourth aspect of the present invention is an n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ and a p-layer made of p-type GaN provided on the n layer. And a p-type region which is a region made of p-type GaN provided by ion implantation and heat treatment in a part of the n-layer.
The area with the p-shaped area in the plan view is defined as the B area.
From the lower end of the conduction band of GaN, the electron trap level of energy of 0.10 eV or more and less than 0.20 eV is set to TE1.
TE2, the electron trap level of energy of 0.20 eV or more and less than 0.30 eV from the lower end of the conduction band of GaN.
TE4, the electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN.
Let TE9 be the electron trap level of energy of 1.10 eV or more and less than 1.40 eV from the lower end of the conduction band of GaN.
The average density of each electron trap level in the B region is the average density of each electron trap level in the n layer in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the p-type region to the n layer side. As an average density
The average density of each electron trap level in the n layers in the B region is
The ratio of the average density of the electron trap levels of TE2 to the average density of the electron trap levels of TE4 is larger than the ratio of the average density of the electron trap levels of TE9 to the average density of the electron trap levels of TE4. The ratio of the average density of the electron trap levels of TE9 to the average density of the electron trap levels is set to be larger than the ratio of the average density of the electron trap levels of TE1 to the average density of the electron trap levels of TE4. ing,
It is a semiconductor device characterized by this.

In the third and fourth aspects of the present invention, it is preferable that the settings are as follows in order to further suppress the leakage current.

It is preferable that the ratio of the average density of the electron trap level of TE1 in the region A to the average density of the electron trap level of TE1 in the region B is 0.03 or less.

It is preferable that the ratio of the average density of the electron trap level of TE2 in the region A to the average density of the electron trap level of TE2 in the region B is 0.02 or less.

It is preferable that the ratio of the average density of the electron trap level of TE4 in the region A to the average density of the electron trap level of TE4 in the region B is set to 0.3 to 2.0.

The hole trap level of 0.80 eV or more and less than 0.90 eV from the upper end of the valence band of GaN is set to TH3.
The average density of hole trap levels in the A region is the average of the hole trap levels in the p layer in the region at a depth of 0.02 to 0.05 μm from the interface between the n layer and the p layer to the p layer side. Density
The average density of hole trap levels in the B region is 0.02 to 0.05 μm from the interface between the n layer and the p-type region to the p-type region. As the average density of the place,
The ratio of the average density of the hole trap levels of TH3 in the p-layer in the A region to the average density of the hole trap levels of TH3 in the p-type region in the B region is 0.7 to 1.4. It is preferable that it is set to be.

According to the present invention, it is possible to realize a semiconductor device made of a group III nitride semiconductor in which a leakage current is suppressed.

The figure which showed the structure of the semiconductor device of Example 1. FIG. The figure which showed the manufacturing process of the semiconductor device of Example 1. FIG. The figure which showed the modification of the manufacturing method of the semiconductor device of Example 1. FIG. The figure which showed the structure of the semiconductor device of Example 2. FIG. The figure which showed the manufacturing process of the semiconductor device of Example 2. FIG. The figure which showed the structure of the modification 1 of the semiconductor device of Example 2. The figure which showed the manufacturing process of the modification 1 of the semiconductor device of Example 2. The figure which showed the structure of the modification 2 of the semiconductor device of Example 2. The figure which showed the structure of the element for A area evaluation of the semiconductor device of Example 1. FIG. The figure which showed the structure of the element for A area evaluation of the semiconductor device of Example 2. FIG. The figure which showed the structure of the element for B region evaluation of the semiconductor apparatus of Example 1 and Example 2. FIG. The graph which showed the IV characteristic of the element for A region evaluation of the semiconductor device of Example 1. FIG. The graph which showed the DLTS measurement result of the element for A area evaluation of the semiconductor apparatus of Example 1. FIG. The figure which summarized each characteristic for each type of electron trap level about the element for A region evaluation of the semiconductor device of Example 1. FIG. The figure which summarized the ratio of the average density of each electron trap level to the average density of the electron trap level of TE4. The graph which showed the IV characteristic of the element for A region evaluation of the semiconductor device of Example 2. FIG. The graph which showed the DLTS measurement result of the element for A area evaluation of the semiconductor apparatus of Example 2. FIG. The figure which summarized each characteristic for each type of carrier trap level about the element for A area evaluation of the semiconductor device of Example 2. FIG. The graph which showed the IV characteristic of the element for B region evaluation. The graph which showed the DLTS measurement result of the element for B area evaluation. The figure which summarized the energy, the capture cross section, and the average density of the carrier trap level for each type of carrier trap level for the element for B region evaluation. The figure which summarized the ratio of the average density of each carrier trap level to the average density of the carrier trap level of TE4. For each carrier trap level, the figure which summarized the ratio of the average density of the carrier trap level in the A region evaluation element of the semiconductor device of Example 1 to the average density of the carrier trap level in the B region evaluation element. For each carrier trap level, the figure which summarized the ratio of the average density of the carrier trap level in the A region evaluation element of the semiconductor device of Example 2 to the average density of the carrier trap level in the B region evaluation element.

Hereinafter, specific examples of the present invention will be described with reference to the drawings, but the present invention is not limited to the examples.

FIG. 1 is a diagram showing the configuration of the semiconductor device of the first embodiment. As shown in FIG. 1, the semiconductor device of the first embodiment is a Schottky barrier diode, and is composed of a substrate 10, an n-layer 11, a diffusion p region 12, a cathode electrode 13, and an anode electrode 14. There is.

The substrate 10 is made of n-GaN having a Si concentration of 1.0 × 10 ¹⁸ / cm ³ . The thickness of the substrate 10 is 320 μm.

The n-layer 11 is located on the substrate 10 and is composed of n-GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ and a Si concentration of 1 × 10 ¹⁵ to 2.5 × 10 ¹⁶ / cm ³ . Become. The thickness of the n-layer 11 is 5 to 20 μm.

The diffusion p region 12 is a region formed by diffusing Mg by ion implantation and heat treatment as described later, and is composed of p-GaN. The Mg concentration is 2 × 10 ¹⁸ / cm ³ . The diffusion p region 12 is annular in a plan view and has a width of 10 μm. Further, the diffusion p region 12 is formed in a region from the surface of the n layer 11 to a depth of 1 μm. As will be described later, the diffusion p region 12 is provided to improve the withstand voltage of the semiconductor device of the first embodiment. In order to improve the withstand voltage, the Mg concentration is 0.5 × 10 ¹⁷ to 2 × 10 ¹⁹ / cm ³ , the width of the ring of the diffusion p region 12 in a plan view is 1 to 20 μm, and the diffusion p region 12 is formed. The depth may be 0.1 to 5 μm.

The cathode electrode 13 is provided in contact with the entire back surface of the substrate 10. The cathode electrode 13 is made of Ti / Al and makes ohmic contact with the back surface of the substrate 10. Here, "/" means laminated, and A / B means a structure in which A and B are laminated in this order. Hereinafter, the same applies to the description of the material.

The anode electrode 14 is provided on the n layer 11 and on the diffusion p region 12. The anode electrode 14 is made of Ni and is in Schottky contact with the n layer 11. The anode electrode 14 is a circle in a plan view, and its outer periphery is in contact with the diffusion p region 12. In this way, the withstand voltage of the semiconductor device of the first embodiment is improved by bringing the diffusion p region 12 into contact with the end of the anode electrode 14 where the electric field is concentrated when the reverse bias is applied.

(About the average density of carrier trap levels)
Next, the average densities of the carrier trap levels (electron trap level and hole trap level) of the n layer 11 and the diffusion p region 12 will be described. The average density of each carrier trap level can be controlled by the temperature and time in the heat treatment for forming the diffusion p region 12 as described later.

First, with Ec as the lower end of the conduction band of GaN, Ev as the upper end of the valence band, and Et as the electron trap level, each electron trap level and hole trap level are called as follows. do.
TE1: Electronic trap level with Ec-Et of 0.10 eV or more and less than 0.20 eV TE2: Electron trap level with Ec-Et of 0.20 eV or more and less than 0.30 eV TE3: Ec-Et is 0.30 eV or more and 0. Electronic trap level with less than 45 eV TE4: Electronic trap level with Ec-Et of 0.45 eV or more and less than 0.60 eV TE5: Electronic trap level with Ec-Et of 0.60 eV or more and less than 0.75 eV TE6: Ec-Et Electron trap level with 0.75 eV or more and less than 0.85 eV TE7: Electron trap level with Ec-Et of 0.90 eV or more and less than 1.00 eV TE8: Electron trap with Ec-Et of 1.00 eV or more and less than 1.10 eV Level TE9: Electron trap level with Ec-Et of 1.10 eV or more and less than 1.40 eV

TH3: Hole trap level with Et-Ev greater than or equal to 0.80 eV and less than 0.90 eV

Of these carrier trap levels, TE2, TE4, TE9, and TH3 are levels that are generated regardless of heat treatment, and are generated when the n-layer 11 is crystal-grown by the MOCVD method. Therefore, it is considered that the average densities of these carrier trap levels are uniformly distributed in the depth direction of the n-layer 11 at the stage of crystal growth. On the other hand, the other carrier trap levels (TE1, TE3, TE5 to TE8) are levels generated by heat treatment. Therefore, it is considered that the average density of these carrier trap levels is higher on the surface side of the n layer 11, and the density decreases as the depth becomes deeper.

In the semiconductor device of the first embodiment, the average density of each carrier trap level of the n layer 11 and the diffusion p region 12 is set as follows. Of the average density of carrier trap levels, the electron trap is 0.8 to 1 on the n-layer 11 side from the interface between the n-layer 11 and the anode electrode 14 or the interface between the n-layer 11 and the diffusion p-region 12. The average density of the region with a depth of 0.6 μm, and for hole traps, the depth is 0.02 to 0.05 μm from the pn interface (the interface between the n layer 11 and the diffused p region 12) to the diffused p region 12 side. The average density of the region. Hereinafter, the same applies to the average density of the carrier trap levels of Example 1.

When the semiconductor device of the first embodiment is viewed from above perpendicular to the main surface of the substrate 10 (that is, in a plan view), the region where the diffusion p region 12 does not exist is defined as the region A, and the region where the diffusion p region 12 exists is defined as the region B.

For the A region, the ratio of the average density n1A of the electron trap level of TE1 to the average density n4A of the electron trap level of TE4 (n1A / n4A) is the electron trap of TE3 with respect to the average density n4A of the electron trap level of TE4. The ratio of the average density n1A of the electron trap level of TE1 to the average density n4A of the electron trap level of TE4 is 1 or less, which is larger than the ratio of the average density n3A of the level (n3A / n4A). It is set to be. That is, it is set to satisfy (n3A / n4A) <(n1A / n4A) ≦ 1.

In the B region, the ratio of the average density n2B of the electron trap level of TE2 to the average density n4B of the electron trap level of TE4 (n2B / n4B) is that of TE9 with respect to the average density n4B of the electron trap level of TE4. The ratio of the average density n9B of the electron trap level of TE9 to the average density n4B of the electron trap level of TE4, which is larger than the ratio of the average density n9B of the electron trap level (n9B / n4B), is TE4. It is set to be larger than the ratio (n1B / n4B) of the average density n1B of the electron trap level of TE1 to the average density n4B of the electron trap level of. That is, it is set to satisfy (n1B / n4B) <(n9B / n4B) <(n2B / n4B).

By setting the average density of the electron trap levels as described above in at least one of the A region and the B region, the leakage current of the semiconductor device of the first embodiment can be suppressed. Of course, it is more preferable that the average density of the electron trap levels is set as described above in both the A region and the B region.

Further, in order to reduce the leakage current, it is desirable that the lower the average density of each electron trap level is, and it is particularly desirable to sufficiently reduce the average density of the electron trap levels generated by the heat treatment. For example, the following range is desirable.

Of the average densities of each electron trap level in the A region, those generated by heat treatment are preferably in the following range. It is desirable that the average density n1A of the electron trap level of TE1 is 4 × 10 ¹¹ / cm ³ or less. It is desirable that the average density n3A of the electron trap level of TE3 is 6 × 10 ¹⁰ / cm ³ or less. It is desirable that the average density n6A of the electron trap level of TE6 is 2 × 10 ¹³ / cm ³ or less. It is desirable that the average density n7A of the electron trap level of TE7 is 4 × 10 ¹² / cm ³ or less.

Of the average densities of each electron trap level in the A region, those generated regardless of heat treatment are preferably in the following range. It is desirable that the average density n2A of the electron trap level of TE2 is 1/1000 or less of the donor concentration of the n layer 11. It is desirable that the average density n4A of the electron trap level of TE4 is 1/100 or less of the donor concentration of the n layer 11. It is desirable that the average density n9A of the electron trap level of TE9 is 1/500 or less of the donor concentration of the n layer 11.

Further, in the region A, the ratio of the average density of the electron trap levels is preferably in the following range. The ratio of the average densities n1A, n2A, n3A of the electron trap levels of TE1, TE2, and TE3 to the average density n4A of the electron trap levels of TE4 (n1A / n4A, n2A / n4A, n3A / n4A) is 0.01. It is desirable to set it to ~ 0.5. The ratio of the average densities n6A and n7A of the electron trap levels of TE6 and TE7 to the average density n4A of the electron trap levels of TE4 (n6A / n4A, n7A / n4A) is preferably 1.1 to 10.

Further, it is desirable that the average density of each electron trap level and the hole trap level in the B region is in the following range. It is desirable that the average density n4B of the electron trap level of TE4 is 1/100 or less of the donor concentration of the n layer 11. It is desirable that the average density n1B of the electron trap level of TE1 is 3 × 10 ¹⁴ / cm ³ or less. It is desirable that the average density n2B of the electron trap level of TE2 is 3 × 10 ¹⁵ / cm ³ or less. It is desirable that the average density n5B of the electron trap level of TE5 is 1 × 10 ¹³ / cm ³ or less. It is desirable that the average density n7B of the electron trap level of TE7 is 4 × 10 ¹³ / cm ³ or less. The average density n9B of the electron trap level of TE9 is preferably 8 × 10 ¹⁴ / cm ³ or less. It is desirable that the average density nH3B of the hole trap level of TH3 is 1 × 10 ¹³ / cm ³ or less.

Further, in order to reduce the leakage current, it is desirable that the ratio of the average density of each carrier trap level in the A region to the average density of each carrier trap level in the B region is in the following range. The ratio (n1A / n1B) of the average density n1A of the electron trap level of TE1 in the region A to the average density n1B of the electron trap level of TE1 in the region B is preferably 0.01 or less. The ratio (n2A / n2B) of the average density n2A of the electron trap level of TE2 in the region A to the average density n2B of the electron trap level of TE2 in the region B is preferably 0.01 or less. The ratio (n4A / n4B) of the average density n4A of the electron trap level of TE4 in the region A to the average density n4B of the electron trap level of TE4 in the region B is preferably 0.4 to 2.5. The ratio (n7A / n7B) of the average density n7A of the electron trap level of TE7 in the region A to the average density n7B of the electron trap level of TE7 in the region B is preferably 0.2 or less. The ratio (n9A / n9B) of the average density n9A of the electron trap level of TE9 in the region A to the average density n9B of the electron trap level of TE9 in the region B is preferably 0.04 or less.

Next, the method of manufacturing the semiconductor device of the first embodiment will be described with reference to FIG.

First, the n layer 11 made of n-GaN and the p layer 15 made of p-GaN are sequentially laminated on the substrate 10 made of n-GaN by the MOCVD method (see FIG. 2A). The thickness of the n-layer 11 is 5 to 20 μm, and the donor concentration is 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ . The thickness of the p layer 15 is 0.5 to 2 μm, and the Mg concentration is 5 × 10 ¹⁷ to 2 × 10 ¹⁹ / cm ³ .

Next, Mg is ion-implanted into a predetermined region on the surface of the p layer 15 to form an ion-implanted region 16 (see FIG. 2B). A photoresist or the like can be used as a mask formed in a region where ions are not implanted. The element of the ion to be injected may be arbitrary and may be a p-type dopant other than Mg or an n-type dopant such as Si.

Next, a protective film made of SiN is formed on the surfaces of the p layer 15 and the ion implantation region 16 and heat-treated. The atmosphere of the heat treatment may be an inert gas atmosphere, for example, a nitrogen atmosphere. By the heat treatment, Mg contained in the p layer 15 is diffused in the region on the surface of the n layer 11 immediately below the ion implantation region 16. As a result, the diffusion p region 12 is formed in the region from the surface of the n layer 11 to a predetermined depth. Then, the protective film is removed with hydrofluoric acid (see FIG. 2 (c)). The average density of the carrier trap levels of the n layer 11 and the diffusion p region 12 can be controlled by the temperature and time of the heat treatment for forming the diffusion p region 12. Specifically, the lower the heat treatment temperature, the lower the average density of the carrier trap levels, and the longer the heat treatment time, the lower the average density of the carrier trap levels. If the heat treatment temperature is too low or the heat treatment time is too short, it becomes difficult to form the diffusion p region 12 in a predetermined region. Therefore, the heat treatment temperature is controlled in the range of 1000 to 1100 ° C. and the heat treatment time is controlled in the range of 5 to 40 minutes. It is desirable to do. More preferably, the heat treatment temperature is 1020 to 1040 ° C. and the heat treatment time is 12 to 20 minutes.

Next, the p-layer 15 and the ion-implanted region 16 are dry-etched to expose the surface of the n-layer 11 and the diffused p-region 12. Further, the outer periphery of the n-layer 11 is dry-etched to a predetermined depth to form an element separation region (see FIG. 2D).

Next, the cathode electrode 13 is formed on the back surface of the substrate 10, the anode electrode 14 is formed on the n layer 11 and the diffusion p region 12 by vapor deposition, respectively. The anode electrode 14 has a pattern such that its end is on the diffusion p region 12. From the above, the semiconductor device of Example 1 shown in FIG. 1 is manufactured.

In Example 1, Mg is diffused into another region directly under the ion implantation region to form the diffusion p region 12, but Mg ions are directly implanted into the n layer 11 and heat-treated to obtain Mg. The ion-implanted region may be used as it is as the p-type region 17 without being diffused (see FIG. 3). In this case, by setting the heat treatment temperature and time within a predetermined range, a p-type region can be produced without diffusing Mg. However, when the diffusion p region 12 is formed as in the first embodiment, the surface of the n layer 11 is less roughened, and the diffusion p region 12 can be accurately formed in a predetermined region.

As described above, in the semiconductor device of the first embodiment, regarding the average density of each carrier trap level of the n layer 11 and the diffusion p region 12, the region in which the diffusion p region 12 does not exist in the plan view is the region A, and the region in which the diffusion p region 12 exists is the region B. Since the regions A and B are set as follows, the leakage current can be reduced.
For the A region, the ratio of the average density n1A of the electron trap level of TE1 to the average density n4A of the electron trap level of TE4 (n1A / n4A) is the electron trap of TE3 with respect to the average density n4A of the electron trap level of TE4. The ratio of the average density n1A of the electron trap level of TE1 to the average density n4A of the electron trap level of TE4 is 1 or less, which is larger than the ratio of the average density n3A of the level (n3A / n4A). It is set to be.
For the B region, the ratio of the average density n2B of the electron trap level of TE2 to the average density n4B of the electron trap level of TE4 (n2B / n4B) is the electron trap of TE9 with respect to the average density n4B of the electron trap level of TE4. The ratio of the average density n9B of the electron trap level of TE9 to the average density n4B of the electron trap level of TE4, which is larger than the ratio of the average density n9B of the level (n9B / n4B), is the electron of TE4. It is set to be larger than the ratio (n1B / n4B) of the average density n1B of the electron trap level of TE1 to the average density n4B of the trap level.

FIG. 4 is a diagram showing the configuration of the semiconductor device of the second embodiment. As shown in FIG. 4, the semiconductor device of the second embodiment is a trench type FET, and has a substrate 20, an n layer 21, a p layer 22, a diffusion p region 23, an ion implantation region 24, and a regrowth n. It is composed of a layer 25, a gate insulating film 26, a drain electrode 27, a source electrode 28, and a gate electrode 29.

The substrate 20 is made of n-GaN having a Si concentration of 1.0 × 10 ¹⁸ / cm ³ . The thickness of the substrate 10 is 320 μm.

The n-layer 21 is located on the substrate 20 and is composed of n-GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ and a Si concentration of 1 × 10 ¹⁵ to 2.5 × 10 ¹⁶ / cm ³ . Become. The thickness of the n-layer 11 is 10 μm.

The p layer 22 is made of p-GaN having a Mg concentration of 5 × 10 ¹⁷ to 2 × 10 ¹⁹ / cm ³ . The thickness of the p layer 22 is 1 μm.

The regrowth n-layer 25 is located on the p-layer 22 and the ion-implanted region 24, and is composed of n-GaN having a Si concentration of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ . The thickness of the regrowth n layer 25 is 0.2 μm.

In a predetermined region on the surface of the regrowth n-layer 25, a trench 30 having a depth reaching the n-layer 21 from the surface is provided. The n layer 21 is exposed on the bottom surface of the trench 30, and the n layer 21, the p layer 22, and the regrowth n layer 25 are exposed on the side surface.

The diffusion p region 23 is a region provided near the surface of the n layer 21 and near the trench 30. The diffusion p region 23 is a region formed by diffusing Mg by ion implantation and heat treatment as described later, and is composed of p-GaN. The Mg concentration is 5 × 10 ¹⁷ to 2 × 10 ¹⁹ / cm ³ . The diffusion p region 23 is an annular pattern that surrounds the trench 30 in a plan view, and its width is 2 μm. Further, the diffusion p region 23 is formed in a region from the surface of the n layer 21 to a depth of 1 μm, and is formed deeper than the surface of the n layer 21 to the bottom surface of the trench 30. By providing such a diffusion p region 23 in the vicinity of the corner portion of the trench 30, the electric field concentrated on the corner portion of the trench 30 is relaxed, and the pressure resistance is improved.

The ion implantation region 24 is a region provided near the surface of the p layer 22 and near the trench 30, and is a p-type region. As will be described later, the ion implantation region 24 is a region in which Mg ions for forming the diffusion p region 23 are implanted on the surface of the p layer 22, and is located above the diffusion p region 23. The ion implantation region 24 has substantially the same pattern as the diffusion p region 23 in a plan view, and is a pattern that surrounds the trench 30. The region may be a region in which a p-type dopant other than Mg is ion-implanted.

The gate insulating film 26 is formed in a film shape along the bottom surface, the side surface, and the top surface (the region of the surface of the regrowth n layer 25 in the vicinity of the trench 30) of the trench 30. The gate insulating film 26 is made of SiO ₂ .

The drain electrode 27 is provided in contact with the entire back surface of the substrate 20. The drain electrode 27 is made of Ti / Al.

The source electrode 28 is provided on the regrowth n layer 25. Further, in a part of the region of the regrowth n layer 25, a groove 31 is formed which penetrates the regrowth n layer 25 and exposes the p layer 22. The groove 31 is filled with the source electrode 28, and the source electrode 28 and the p layer 22 are connected via the groove 31. The source electrode 28 is made of Ti / Al.

The gate electrode 29 is provided in a film shape along the bottom surface, the side surface, and the top surface (the region of the surface of the regrowth n layer 25 in the vicinity of the trench 30) via the gate insulating film 26. The gate electrode 29 is made of Al.

The semiconductor device of the second embodiment is a trench-type MISFET in which the region of the p-layer 22 near the trench 30 operates as a channel.

(About the average density of carrier trap levels)
Next, the average density of the carrier trap levels of the n layer 21, the p layer 22, and the diffused p region 23 will be described. The carrier trap levels TE1-9 and TH3 have the same definitions as in Example 1. That is, of the average density of the carrier trap levels, the electron trap is 0.8 from the pn interface (the interface between the n layer 21 and the p layer 22 or the interface between the n layer 21 and the diffusion p region 23) to the n layer 21 side. For the average density and hole trap in the region with a depth of ~ 1.6 μm, 0. The average density is defined as the region having a depth of 02 to 0.05 μm.

In the semiconductor device of the second embodiment, the average density of each carrier trap level of the n layer 21, the p layer 22, and the diffusion p region 23 is set as follows. When the semiconductor device of the second embodiment is viewed from above (that is, in a plan view), the region where the diffusion p region 23 does not exist is defined as the region A, and the region where the diffusion p region 23 exists is defined as the region B. In the A region, the average density n4A of the electron trap level of TE4 is set to be 1/500 or less of the donor concentration of the n layer 21.

Further, the B region is set in the same manner as in the first embodiment. That is, the ratio of the average density n2B of the electron trap level of TE2 to the average density n4B of the electron trap level of TE4 (n2B / n4B) is the electron trap level of TE9 with respect to the average density n4B of the electron trap level of TE4. The ratio of the average density n9B of the electron trap level of TE9 to the average density n4B of the electron trap level of TE4 is larger than the ratio of the average density n9B (n9B / n4B) (n9B / n4B). It is set to be larger than the ratio (n1B / n4B) of the average density n1B of the electron trap level of TE1 to the average density n4B of. That is, it is set to satisfy (n1B / n4B) <(n9B / n4B) <(n2B / n4B).

By setting the average density of the carrier trap levels as described above in at least one of the A region and the B region, the leakage current of the semiconductor device of the second embodiment can be suppressed. Of course, it is more preferable that the average density of the electron trap levels is set as described above in both the A region and the B region.

In Example 2, as in Example 1, the lower the average density of each carrier trap level is, the more desirable it is to reduce the leakage current. For example, the following range is desirable.

The average density of each carrier trap level in the A region is preferably in the following range. It is desirable that the average density n1A of the electron trap level of TE1 is 5 × 10 ¹² / cm ³ or less. It is desirable that the average density n2A of the electron trap level of TE2 is 8 × 10 ¹² / cm ³ or less. It is desirable that the average density n4A of the electron trap level of TE4 is 4 × 10 ¹² / cm ³ or less. It is desirable that the average density n9A of the electron trap level of TE9 is 2 × 10 ¹² / cm ³ or less. It is desirable that the average density nH3A of the hole trap level of TH3 is 7 × 10 ¹² / cm ³ or less.

Further, in the region A, the ratio of the average density of the electron trap levels is preferably in the following range. The ratio of the average densities of the electron trap levels of TE1 and TE2 n1A and n2A (n1A / n4A, n2A / n4A) to the average density n4A of the electron trap levels of TE4 is preferably 2.5 or less.

Further, it is desirable that the average density of each carrier trap level in the B region is in the following range. It is desirable that the average density n4B of the electron trap level of TE4 is 1/100 or less of the donor concentration of the n layer 11. It is desirable that the average density n1B of the electron trap level of TE1 is 3 × 10 ¹⁴ / cm ³ or less. It is desirable that the average density n2B of the electron trap level of TE2 is 3 × 10 ¹⁵ / cm ³ or less. It is desirable that the average density n5B of the electron trap level of TE5 is 1 × 10 ¹³ / cm ³ or less. It is desirable that the average density n7B of the electron trap level of TE7 is 4 × 10 ¹³ / cm ³ or less. The average density n9B of the electron trap level of TE9 is preferably 8 × 10 ¹⁴ / cm ³ or less. It is desirable that the average density nH3B of the hole trap level of TH3 is 1 × 10 ¹³ / cm ³ or less.

Further, in order to reduce the leakage current, it is desirable that the ratio of the average density of each carrier trap level in the A region to the average density of each carrier trap level in the B region is in the following range. The ratio (n1A / n1B) of the average density n1A of the electron trap level of TE1 in the region A to the average density n1B of the electron trap level of TE1 in the region B is preferably 0.03 or less. The ratio (n2A / n2B) of the average density n2A of the electron trap level of TE2 in the region A to the average density n2B of the electron trap level of TE2 in the region B is preferably 0.02 or less. The ratio (n4A / n4B) of the average density n4A of the electron trap level of TE4 in the region A to the average density n4B of the electron trap level of TE4 in the region B is preferably 0.3 to 2.0. The ratio (n9A / n9B) of the average density n9A of the electron trap level of TE9 in the region A to the average density n9B of the electron trap level of TE9 in the region B is preferably 0.02 or less. The ratio of the average density nH3A of the hole trap level of TH3 in the region A to the average density nH3B of the hole trap level of TH3 in the region B is preferably 0.7 to 1.4. ..

Next, the method of manufacturing the semiconductor device of the second embodiment will be described with reference to FIG.

First, the n layer 21 made of n-GaN and the p layer 22 made of p-GaN are laminated in order on the substrate 20 made of n-GaN by the MOCVD method (see FIG. 5A). Then, a heat treatment is performed to activate Mg in the p layer 22 and form it into a p-type.

Next, Mg is ion-implanted into a predetermined region on the surface of the p layer 22 to form an ion-implanted region 24 (see FIG. 5B). A photoresist or the like can be used as a mask formed in a region where ions are not implanted.

Next, a protective film made of SiN is formed on the surfaces of the p layer 22 and the ion implantation region 24, and heat treatment is performed. The atmosphere of the heat treatment may be an inert gas atmosphere, for example, a nitrogen atmosphere. By the heat treatment, Mg contained in the p layer 22 is diffused in the region on the surface side of the n layer 21 immediately below the ion implantation region 24. As a result, the diffusion p region 23 is formed in the region directly below the ion implantation region 24 from the surface of the n layer 21 to a predetermined depth. Then, the protective film is removed with hydrofluoric acid (see FIG. 5 (c)). The average density of the carrier trap levels of the n layer 21 and the diffusion p region 23 can be controlled by the temperature and time of the heat treatment for forming the diffusion p region 23. Specifically, the lower the heat treatment temperature, the lower the average density of the carrier trap levels, and the longer the heat treatment time, the lower the average density of the carrier trap levels. If the heat treatment temperature is too low or the heat treatment time is too short, it becomes difficult to form the diffusion p region 23 in a predetermined region. Therefore, the heat treatment temperature is controlled in the range of 1000 to 1100 ° C. and the heat treatment time is controlled in the range of 5 to 40 minutes. It is desirable to do. More preferably, the heat treatment temperature is 1020 to 1040 ° C. and the heat treatment time is 12 to 20 minutes.

Next, a re-growth n-layer 25 made of n-GaN is formed on the p-layer 22 by the MOCVD method (see FIG. 5D).

Next, a part of the regrowth n-layer 25 is dry-etched until the n-layer 21 is exposed to form a trench 30. Further, a part of the regrowth n layer 25 is dry-etched until the p-layer 22 is exposed to form a groove 31 for bringing the source electrode 28 into contact with the p-layer 22. Further, the outer peripheral region of the regrowth n layer 25 is dry-etched to a predetermined depth to form an element separation region (see FIG. 5 (e)).

Next, the gate insulating film 26 is formed on the bottom surface, the side surface, and the top surface of the trench 30 by the ALD method. Next, the source electrode 28 is formed on the regrowth n layer 25 by thin film deposition, and is brought into contact with the p layer 22 via the groove 31. Next, the gate electrode 29 is formed on the bottom surface, the side surface, and the top surface of the trench 30 via the gate insulating film 26 by thin film deposition. Next, the drain electrode 27 is formed on the back surface of the substrate 20 by thin film deposition. As described above, the semiconductor device of Example 1 shown in FIG. 4 is manufactured.

(Modification 1 of Example 2)
In Example 2, Mg is diffused into a region different from the ion-implanted region 24 into which ions are implanted to form a diffusion p region 23. However, the n-layer 21 is directly ion-implanted and heat-treated to obtain Mg. The ion-implanted region may be used as it is as the p-type region 33 by activating without diffusing. In that case, the ion implantation region 24 in the semiconductor device of the second embodiment is not provided, and the p-layer 22 is replaced with the regrowth p-layer 32 (see FIG. 6). The manufacturing method in this case will be described below.

First, the n layer 21 made of n-GaN is laminated on the substrate 20 made of n-GaN by the MOCVD method (see FIG. 7A).

Next, Mg is ion-implanted into a predetermined region on the surface of the n-layer 21 to form an ion-implanted region. Then, a protective film made of SiN is formed on the surfaces of the n-layer 21 and the ion-implanted region, and heat treatment is performed. The atmosphere of the heat treatment may be an inert gas atmosphere, for example, a nitrogen atmosphere. The heat treatment activates the Mg in the ion-implanted region without diffusing it, thereby making the ion-implanted region the p-type region 33 (see FIG. 7 (b)).

Next, a re-growth p-layer 32 made of p-GaN and a re-growth n-layer 25 made of n-GaN are formed on the n-layer 21 and the p-type region 33 by the MOCVD method (see FIG. 7 (c)). ). Hereinafter, the semiconductor device shown in FIG. 6 can be manufactured by the same process as in Example 2.

(Modification 2 of Example 2)
In Example 2, Mg is ion-implanted to form the ion-implanted region 24, but an n-type dopant such as Si may be ion-implanted to form the ion-implanted region 34. The diffusion p region 23 can be formed in the same region as in the case of ion implantation of Mg. Since the ion implantation region 34 is n-type, the regrowth n-layer 25 in Example 2 can be omitted (see FIG. 8).

(Experimental example)
Next, various experimental examples relating to Examples 1 and 2 will be described.

An element for evaluating the A region of the semiconductor device of Example 1 (see FIG. 9), an element for evaluating the A region of the semiconductor device of Example 2 (see FIG. 10), and B of the semiconductor devices of Examples 1 and 2. An element for evaluating a region (see FIG. 11) was manufactured as follows, and the type of carrier trap level and the average density of carrier trap levels were evaluated.

(Evaluation of Area A of the Semiconductor Device of Example 1)
The A region evaluation element of Example 1 was manufactured as follows. First, an n-layer 101 having a thickness of 10 μm and a donor concentration of 2.5 × 10 ¹⁵ / cm ³ was prepared on a substrate 100 made of n-GaN having a Si concentration of 1.0 × 10 ¹⁸ / cm ³ . Then, a protective film made of SiN was formed on the n-layer 101, and a heat-treated element and a non-heat-treated element were produced. The heat treatment produced a device at 1050 ° C. for 4 minutes and a device at 1150 ° C. for 4 minutes. After that, the protective film is removed from hydrofluoric acid, and the outer periphery of the device is dry-etched to form an element separation region. The cathode electrode 103 was formed.

A reverse voltage was applied in the range of 0 to 200 V at a temperature of 25 ° C. to the A region evaluation element manufactured as described above, and IV measurement was performed. FIG. 12 shows the graph. Further, DLTS measurement was performed at a temperature of 77 to 500 K, a bias voltage of -5 V, and a pulse voltage of 0 V. FIG. 13 is a graph showing the result.

As shown in FIG. 12, it was found that a leak current was generated by the heat treatment, and it was found that the leak current increased as the heat treatment temperature increased. It was found that the heat treatment at 1050 ° C. or lower is sufficient for reducing the leakage current.

Further, by DLTS measurement, the electron trap levels TE1 to TE9 in the region having a depth of 0.8 to 1.6 μm could be identified from the interface between the n layer 101 and the anode electrode 104 to the n layer 101 side. FIG. 14 is a table summarizing the energy, capture cross-sectional area, average density of electron trap levels, and ratio of TE4 to the average density of electron trap levels for each type of electron trap level. As shown in FIG. 14, among the electron trap levels, TE2, TE4, and TE9 were found to be carrier trap levels generated regardless of the heat treatment. It was also found that the average density of all electron trap levels was increased by heat treatment. Therefore, the increase in current leakage due to heat treatment is considered to be due to the increase in the average density of the electron trap levels. Although TE5 and TE8 could not be detected, it is considered that this was because the density was below the detection limit.

At the heat treatment temperature of 1150 ° C., the leakage current is significantly increased as compared with the heat treatment temperature of 1050 ° C. Therefore, the state of the average density of each electron trap level at 1050 ° C is the average density of each electron trap level at 1150 ° C. It is considered that the leak current can be reduced more than the state of. Further, it is considered that the smaller the trap level is, the larger the contribution to the leakage current is, and it is not conceivable that the heat treatment is not performed for the formation of the diffusion p region 12. Therefore, it is considered better to define a state in which the leakage current can be reduced by the average density of the electron trap levels of TE1 and TE3, which are generated by the heat treatment and have a small trap level. Further, it is considered that the evaluation of the average density of the electron trap levels of TE1 and TE3 should be based on the average density of the electron trap levels generated regardless of the heat treatment.

Therefore, FIG. 15 summarizes the ratio of the average density of each electron trap level to the average density of the electron trap levels of TE4. Looking at FIG. 15, among the electron trap levels generated by the heat treatment, TE1 and TE3 have a large variation with respect to TE4. Further, the average density of the electron trap level of TE1 is larger than the average density of the electron trap level of TE3 at any of the heat treatment temperatures of 1050 ° C and 1150 ° C. Further, the ratio of the average density of the electron trap level of TE1 to the average density of the electron trap level of TE4 is larger than 1 at 1150 ° C., but is 1 or less at 1050 ° C.

For this reason, in the region A of the semiconductor device of Example 1, the ratio of the average density of the electron trap levels of TE1 to the average density of the electron trap levels of TE4 is relative to the average density of the electron trap levels of TE4. Leakage current is reduced by setting the ratio of the average density of the electron trap levels of TE1 to 1 or less, which is larger than the ratio of the average density of the electron trap levels of TE3 and to the average density of the electron trap levels of TE4. The average density of the possible electron trap levels (the state of the average density of each electron trap level at the heat treatment temperature of 1050 ° C.) was specified.

(Evaluation of Area A of the Semiconductor Device of Example 2)
The A region evaluation element of Example 2 was manufactured as follows. First, on a substrate 100 made of n-GaN having a Si concentration of 1.0 × 10 ¹⁸ / cm ³ , by the MOCVD method, an n layer 101 having a thickness of 10 μm and a donor concentration of 5 × 10 ¹⁵ / cm ³ and a thickness of 1 μm. The p-layer 102 made of p-GaN having a Mg concentration of 2 × 10 ¹⁸ / cm ³ was laminated in order. Then, a protective film made of SiN was formed on the p layer 102, and an element subjected to heat treatment and an element not subjected to heat treatment were manufactured. The heat treatment conditions were 1050 ° C. for 4 minutes, 1150 ° C. for 4 minutes, and 1250 ° C. for 30 seconds, respectively. Then, the protective film was removed from hydrofluoric acid, and the outer periphery of the device was dry-etched to form a device separation region. Next, an ohmic contact anode electrode 105 made of Pd was formed on the surface of the p layer 102, and a cathode electrode 103 made of Al / Ti was formed on the back surface of the substrate 100.

A reverse voltage was applied in the range of 0 to 300 V at a temperature of 25 ° C. to the A region evaluation element manufactured as described above, and IV measurement was performed. FIG. 16 shows the graph. Further, DLTS measurement was performed at a temperature of 77 to 600 K, a bias voltage of -10 V, and a pulse voltage of 0 V. However, the temperature was set to 77 to 700 K only when the heat treatment temperature was 1250 ° C. for 30 seconds. FIG. 17 is a graph showing the result.

As shown in FIG. 16, it was found that the leak current was generated by the heat treatment at 1250 ° C. or higher, and it was found that the leak current increased as the heat treatment temperature was higher. It was found that the heat treatment at 1150 ° C. or lower is sufficient for reducing the leakage current.

Further, by DLTS measurement, the carrier trap level (electron trap level) in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer 101 and the p layer 102 to the n layer 101 side and the n layer 101. The carrier trap level (hole trap level) in the region having a depth of 0.02 to 0.05 μm could be identified from the interface between the tool and the p layer 102 to the p layer 102 side. The electron trap levels of TE10 and TE11, which have higher energies than TE9, and the hole trap levels of TH2, which have lower energies than TH3, could also be identified. FIG. 18 is a table summarizing each characteristic for each type of carrier trap level. It was also found that the heat treatment changed the type of carrier trap level and increased the average density of the carrier trap level. Therefore, the increase in current leakage due to heat treatment is considered to be due to the increase in the types of carrier trap levels and the increase in the average density of carrier trap levels.

At the heat treatment temperature of 1250 ° C., the leakage current is significantly increased as compared with the heat treatment temperature of 1150 ° C. Therefore, the average density of each carrier trap level at 1050 ° C and 1150 ° C is the state of each carrier trap level at 1250 ° C. It is considered that the leak current can be reduced more than the state of the average density of. Looking at FIG. 17, TE4 appears at any heat treatment temperature and appears in both the heat treatment at 1150 ° C and the heat treatment at 1250 ° C. On the other hand, other carrier trap levels appear and disappear depending on the presence or absence of heat treatment and the heat treatment temperature. Therefore, it is considered better to define a state in which the leakage current can be reduced by the average density of the carrier trap levels of TE4.

Since the electron trap level of TE4 is generated regardless of the heat treatment, it is considered that the average density of the electron trap level of TE4 also depends on the donor concentration of the n layer 102. For this reason, in the A region of the semiconductor device of Example 2, the leakage current can be reduced by setting the average density of the electron trap level of TE4 to 1/500 or less of the donor concentration of the n layer 101. The average density of trap levels (state of average density of each carrier trap level at a heat treatment temperature of 1150 ° C.) was specified.

(Evaluation of B region of the semiconductor device of Examples 1 and 2)
The B region evaluation element was manufactured as follows. First, on a substrate 100 made of n-GaN having a Si concentration of 1.0 × 10 ¹⁸ / cm ³ , by the MOCVD method, an n layer 101 having a thickness of 10 μm and a donor concentration of 5 × 10 ¹⁵ / cm ³ and a thickness of 1 μm. The p-layer 102 made of p-GaN having a Mg concentration of 2 × 10 ¹⁸ / cm ³ was laminated in order. Next, Mg was ion-implanted on the entire surface of the p-layer 102 to form an ion-implanted region 106. Next, a protective film made of SiN was formed on the ion-implanted region 106 and heat-treated. The heat treatment conditions were 1050 ° C. for 4 minutes, 1050 ° C. for 20 minutes, and 1050 ° C. for 40 minutes, respectively. By this heat treatment, Mg was diffused into the n-layer 101, and a diffused p-region 107 was formed in a region from the surface of the n-layer 101 to a predetermined depth. Next, the protective film was removed with hydrofluoric acid, and the outer periphery of the device was dry-etched to form a device separation region. Next, an ohmic contact anode electrode 105 made of Pd was formed on the surface of the ion implantation region 106, and a cathode electrode 103 made of Al / Ti was formed on the back surface of the substrate 100.

Although the structure of this B region evaluation element is different from that of the B region of the semiconductor device of the first embodiment, the carrier trap level in the depletion layer region at the pn interface between the n layer and the diffusion p region is detected. The same is true in terms of points. Therefore, not only the B region of the semiconductor device of the second embodiment but also the B region of the semiconductor device of the first embodiment can be evaluated by the B region evaluation element.

A reverse voltage was applied in the range of 0 to 300 V at a temperature of 25 ° C. to the B region evaluation element manufactured as described above, and IV measurement was performed. FIG. 19 shows the graph. Further, DLTS measurement was performed at a temperature of 77 to 600 K, a bias voltage of -10 V, and a pulse voltage of 0 V. FIG. 20 is a graph showing the result.

As shown in FIG. 19, it was found that the current leakage can be reduced as the heat treatment time becomes longer, and it is found that the leakage current can be sufficiently reduced by the heat treatment for 20 minutes or more. It is considered that this is because the longer the heat treatment time, the more the damage to the crystal due to the ion implantation is recovered.

Further, by DLTS measurement, the carrier trap level (electron trap level) in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer 21 and the diffusion p region 23 to the n layer 21 side, and the n layer. A carrier trap level (hole trap level) in a region having a depth of 0.02 to 0.05 μm could be identified from the interface between 21 and the diffusion p region 23 on the diffusion p region 23 side. A hole trap level with a lower energy than TH2 could also be identified. FIG. 21 is a table summarizing each characteristic for each type of carrier trap level. It was also found that the type of carrier trap level changed depending on the heat treatment time, and the longer the heat treatment time, the lower the average density of the carrier trap level. Therefore, the decrease in current leakage due to the longer heat treatment time is considered to be due to the decrease in the types of carrier trap levels and the decrease in the average density of carrier trap levels.

In the heat treatment of 4 minutes, the leakage current increased significantly compared to the heat treatment of 20 minutes and 40 minutes. Therefore, the average density of each carrier trap level in the heat treatment of 20 minutes and 40 minutes was changed to that of the heat treatment in 4 minutes. It is considered that the leakage current can be reduced more than the state of the average density of each carrier trap level. Looking at FIG. 20, the peaks of TE1, TE2, and TE9 appear at any of the heat treatment times. In particular, it is considered that the smaller the trap level is, the larger the contribution to the leak current is, and the average density of the electron trap levels of TE1 and TE2 is considered to have a large contribution to the leak current. Therefore, it is considered better to define a state in which the leakage current can be reduced by the average density of the electron trap levels of TE1, TE2, and TE9. Further, it is considered that the evaluation of the average density of these electron trap levels should be based on the average density of the electron trap levels generated regardless of the heat treatment.

Therefore, FIG. 22 summarizes the ratio of the average density of each electron trap level to the average density of the electron trap levels of TE4. As shown in FIG. 22, in the case of the heat treatment for 4 minutes, the average density ratio of the electron trap level of TE1 was the largest, followed by TE9 and TE2 in that order. On the other hand, in the case of heat treatment for 20 minutes, the average density ratio of the electron trap level of TE2 was the largest, followed by TE9 and TE1.

For this reason, in the B region of the semiconductor device of Examples 1 and 2, the ratio of the average density of the electron trap levels of TE2 to the average density of the electron trap levels of TE4 is the average of the electron trap levels of TE4. The ratio of the average density of the electron trap levels of TE9 to the average density of the electron trap levels of TE4 is greater than the ratio of the average density of the electron trap levels of TE9 to the density, to the average density of the electron trap levels of TE4. By setting it to be larger than the ratio of the average density of the electron trap levels of TE1, the average density of the electron trap levels that can reduce the leakage current (the state of the average density of each carrier trap level at the heat treatment temperature of 20 minutes) can be determined. Prescribed.

FIG. 23 summarizes the ratio of the average density of the electron trap levels in the A region evaluation element of the semiconductor device of Example 1 to the average density of the electron trap levels in the B region evaluation element for each electron trap level. It is a table. From FIG. 23, it is considered that the leakage current can be reduced by defining each density ratio as follows. The density ratio for the electron trap level of TE1 is 0.01 or less. The density ratio for the electron trap level of TE2 is 0.01 or less. The density ratio for the electron trap level of TE4 is 0.4 to 2.5. The density ratio for the electron trap level of TE7 is 0.2 or less. The density ratio for the electron trap level of TE9 is 0.04 or less.

FIG. 24 summarizes the ratio of the average density of the electron trap levels in the A region evaluation element of the semiconductor device of Example 2 to the average density of the electron trap levels in the B region evaluation element for each electron trap level. It is a table. From FIG. 24, it is considered that the leakage current can be reduced by defining each density ratio as follows. The density ratio for the electron trap level of TE1 is 0.01 to 0.03. The density ratio for the electron trap level of TE2 is 0.0001 to 0.005. The density ratio for the electron trap level of TE4 is 0.3 to 2.0. The density ratio for the electron trap level of TE9 is 0.002 to 0.02. Further, from the same comparison, it is considered that the leakage current can be reduced if the density ratio for the hole trap level of TH3 is 0.7 to 1.4.

Further, from the above experimental results, it was found that the heat treatment temperature should be controlled in the range of 1000 to 1100 ° C. and the heat treatment time should be controlled in the range of 5 to 40 minutes as the heat treatment for diffusing Mg to form the diffusion p region. ..

(Other various modifications)
Although the Schottky barrier diode was used in the first embodiment, any structure can be used as long as the diffusion p region 12 is provided in a part of the n layer 11 and the Schottky electrode is provided on the n layer 11. It can be applied to semiconductor devices with structures. Further, although the second embodiment is a trench type MISFET, any structure can be used as long as the n-layer 21 and the p-layer 22 are stacked in this order and the diffusion p-region 23 is provided in a part of the n-layer 21. It can be applied to semiconductor devices with structures. For example, the present invention can be applied to a pn diode, a pin diode, an IGBT, an HFET, and the like. Further, although Examples 1 and 2 both have a vertical structure that conducts conduction in the vertical direction (direction perpendicular to the main surface of the substrate), the present invention is a semiconductor having a horizontal structure that conducts conduction in the direction horizontal to the main surface of the substrate. It can also be applied to devices.

The semiconductor device of the present invention can be used as a power device or the like.

10, 20: Substrate 11, 21: n layer 12, 23: Diffusion p region 13: Cathode electrode 14: Anode electrode 22: p layer 24: Ion implantation region 25: Re-growth n layer 26: Gate insulating film 27: Drain electrode 28: Source electrode 29: Gate electrode 30: Trench

Claims (22)

An n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ and a region made of p-type GaN provided in a part of the n-layer by ion implantation and heat treatment. It has a p-type region and a Schottky electrode provided on the n-layer and on the p-type region and in Schottky contact with the n-layer.
The region without the p-shaped region in a plan view is defined as the A region.
The region with the p-shaped region in a plan view is defined as the B region.
From the lower end of the conduction band of GaN, the electron trap level of energy of 0.10 eV or more and less than 0.20 eV is set to TE1.
TE3, the electron trap level of energy of 0.30 eV or more and less than 0.45 eV from the lower end of the conduction band of GaN.
Let TE4 be the electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN.
The average density of each electron trap level in the A region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the shotkey electrode to the n layer side. The average density of the electron trap level is used.
The average density of each electron trap level in the B region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the p-type region to the n layer side. As the average density of electron trap levels,
The average density of each electron trap level in the A region is
The ratio of the average density of the electron trap levels of TE1 to the average density of the electron trap levels of TE4 is larger than the ratio of the average density of the electron trap levels of TE3 to the average density of the electron trap levels of TE4, and The ratio of the average density of the electron trap level of TE1 to the average density of the electron trap level of TE4 is set to be 1 or less .
The ratio of the average density of the electron trap level of TE1 in the region A to the average density of the electron trap level of TE1 in the region B is set to be 0.01 or less.
A semiconductor device characterized by this. An n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ and a region made of p-type GaN provided in a part of the n-layer by ion implantation and heat treatment. It has a p-type region and a Schottky electrode provided on the n-layer and on the p-type region and in Schottky contact with the n-layer.
The region without the p-shaped region in a plan view is defined as the A region.
The region with the p-shaped region in a plan view is defined as the B region.
From the lower end of the conduction band of GaN, the electron trap level of energy of 0.10 eV or more and less than 0.20 eV is set to TE1.
TE2, the electron trap level of energy of 0.20 eV or more and less than 0.30 eV from the lower end of the conduction band of GaN.
TE3, the electron trap level of energy of 0.30 eV or more and less than 0.45 eV from the lower end of the conduction band of GaN.
Let TE4 be the electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN.
The average density of each electron trap level in the A region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the shotkey electrode to the n layer side. The average density of the electron trap level is used.
The average density of each electron trap level in the B region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the p-type region to the n layer side. As the average density of electron trap levels,
The average density of each electron trap level in the A region is
The ratio of the average density of the electron trap levels of TE1 to the average density of the electron trap levels of TE4 is larger than the ratio of the average density of the electron trap levels of TE3 to the average density of the electron trap levels of TE4, and The ratio of the average density of the electron trap level of TE1 to the average density of the electron trap level of TE4 is set to be 1 or less .
The ratio of the average density of the electron trap level of TE2 in the region A to the average density of the electron trap level of TE2 in the region B is set to be 0.01 or less.
A semiconductor device characterized by this. An n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ and a region made of p-type GaN provided in a part of the n-layer by ion implantation and heat treatment. It has a p-type region and a Schottky electrode provided on the n-layer and on the p-type region and in Schottky contact with the n-layer.
The region without the p-shaped region in a plan view is defined as the A region.
The region with the p-shaped region in a plan view is defined as the B region.
From the lower end of the conduction band of GaN, the electron trap level of energy of 0.10 eV or more and less than 0.20 eV is set to TE1.
TE3, the electron trap level of energy of 0.30 eV or more and less than 0.45 eV from the lower end of the conduction band of GaN.
Let TE4 be the electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN.
The average density of each electron trap level in the A region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the shotkey electrode to the n layer side. The average density of the electron trap level is used.
The average density of each electron trap level in the B region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the p-type region to the n layer side. As the average density of electron trap levels,
The average density of each electron trap level in the A region is
The ratio of the average density of the electron trap levels of TE1 to the average density of the electron trap levels of TE4 is larger than the ratio of the average density of the electron trap levels of TE3 to the average density of the electron trap levels of TE4, and The ratio of the average density of the electron trap level of TE1 to the average density of the electron trap level of TE4 is set to be 1 or less .
The ratio of the average density of the electron trap level of TE4 in the region A to the average density of the electron trap level of TE4 in the region B is set to be 0.4 to 2.5.
A semiconductor device characterized by this. An n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ and a region made of p-type GaN provided in a part of the n-layer by ion implantation and heat treatment. It has a p-type region and a Schottky electrode provided on the n-layer and on the p-type region and in Schottky contact with the n-layer.
The region without the p-shaped region in a plan view is defined as the A region.
The region with the p-shaped region in a plan view is defined as the B region.
From the lower end of the conduction band of GaN, the electron trap level of energy of 0.10 eV or more and less than 0.20 eV is set to TE1.
TE3, the electron trap level of energy of 0.30 eV or more and less than 0.45 eV from the lower end of the conduction band of GaN.
TE4 , the electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN.
Let TE7 be the electron trap level of energy of 0.90 eV or more and less than 1.00 eV from the lower end of the conduction band of GaN.
The average density of each electron trap level in the A region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the shotkey electrode to the n layer side. The average density of the electron trap level is used.
The average density of each electron trap level in the B region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the p-type region to the n layer side. As the average density of electron trap levels,
The average density of each electron trap level in the A region is
The ratio of the average density of the electron trap levels of TE1 to the average density of the electron trap levels of TE4 is larger than the ratio of the average density of the electron trap levels of TE3 to the average density of the electron trap levels of TE4, and The ratio of the average density of the electron trap level of TE1 to the average density of the electron trap level of TE4 is set to be 1 or less .
The ratio of the average density of the electron trap level of TE7 in the region A to the average density of the electron trap level of TE7 in the region B is set to be 0.2 or less.
A semiconductor device characterized by this. An n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ and a region made of p-type GaN provided in a part of the n-layer by ion implantation and heat treatment. It has a p-type region and a Schottky electrode provided on the n-layer and on the p-type region and in Schottky contact with the n-layer.
The region without the p-shaped region in a plan view is defined as the A region.
The region with the p-shaped region in a plan view is defined as the B region.
From the lower end of the conduction band of GaN, the electron trap level of energy of 0.10 eV or more and less than 0.20 eV is set to TE1.
TE3, the electron trap level of energy of 0.30 eV or more and less than 0.45 eV from the lower end of the conduction band of GaN.
TE4 , the electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN.
The electron trap level of energy of 1.10 eV or more and less than 1.40 eV from the lower end of the conduction band of GaN is set to TE9.
The average density of each electron trap level in the A region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the shotkey electrode to the n layer side. The average density of the electron trap level is used.
The average density of each electron trap level in the B region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the p-type region to the n layer side. As the average density of electron trap levels,
The average density of each electron trap level in the A region is
The ratio of the average density of the electron trap levels of TE1 to the average density of the electron trap levels of TE4 is larger than the ratio of the average density of the electron trap levels of TE3 to the average density of the electron trap levels of TE4, and The ratio of the average density of the electron trap level of TE1 to the average density of the electron trap level of TE4 is set to be 1 or less .
The ratio of the average density of the electron trap level of TE9 in the region A to the average density of the electron trap level of TE9 in the region B is set to be 0.04 or less.
A semiconductor device characterized by this. An n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ and a region made of p-type GaN provided in a part of the n-layer by ion implantation and heat treatment. It has a p-type region and a Schottky electrode provided on the n-layer and on the p-type region and in Schottky contact with the n-layer.
The region with the p-shaped region in a plan view is defined as the B region.
From the lower end of the conduction band of GaN, the electron trap level of energy of 0.10 eV or more and less than 0.20 eV is set to TE1.
TE2, the electron trap level of energy of 0.20 eV or more and less than 0.30 eV from the lower end of the conduction band of GaN.
TE4, the electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN.
Let TE9 be the electron trap level of energy of 1.10 eV or more and less than 1.40 eV from the lower end of the conduction band of GaN.
The average density of each electron trap level in the B region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the p-type region to the n layer side. As the average density of electron trap levels,
The average density of each electron trap level in the B region is
The ratio of the average density of the electron trap levels of TE2 to the average density of the electron trap levels of TE4 is larger than the ratio of the average density of the electron trap levels of TE9 to the average density of the electron trap levels of TE4. The ratio of the average density of the electron trap levels of TE9 to the average density of the electron trap levels is set to be larger than the ratio of the average density of the electron trap levels of TE1 to the average density of the electron trap levels of TE4. ing,
A semiconductor device characterized by this. The region without the p-shaped region in a plan view is defined as the A region.
The average density of each electron trap level in the A region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the shotkey electrode to the n layer side. As the average density of electron trap levels,
The ratio of the average density of the electron trap level of TE1 in the region A to the average density of the electron trap level of TE1 in the region B is set to be 0.01 or less.
The semiconductor device according to claim 6 . The region without the p-shaped region in a plan view is defined as the A region.
The average density of each electron trap level in the A region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the shotkey electrode to the n layer side. As the average density of electron trap levels,
The ratio of the average density of the electron trap level of TE2 in the region A to the average density of the electron trap level of TE2 in the region B is set to be 0.01 or less.
The semiconductor device according to claim 6 . The region without the p-shaped region in a plan view is defined as the A region.
The average density of each electron trap level in the A region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the shotkey electrode to the n layer side. As the average density of electron trap levels,
The ratio of the average density of the electron trap level of TE4 in the region A to the average density of the electron trap level of TE4 in the region B is set to be 0.4 to 2.5.
The semiconductor device according to claim 6 . The electron trap level of energy of 0.90 eV or more and less than 1.00 eV from the lower end of the conduction band of GaN is set to TE7.
The region without the p-shaped region in a plan view is defined as the A region.
The average density of each electron trap level in the A region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the shotkey electrode to the n layer side. As the average density of electron trap levels,
The ratio of the average density of the electron trap level of TE7 in the region A to the average density of the electron trap level of TE7 in the region B is set to be 0.2 or less.
The semiconductor device according to claim 6 . The region without the p-shaped region in a plan view is defined as the A region.
The average density of each electron trap level in the A region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the shotkey electrode to the n layer side. As the average density of electron trap levels,
The ratio of the average density of the electron trap level of TE9 in the region A to the average density of the electron trap level of TE9 in the region B is set to be 0.04 or less.
The semiconductor device according to claim 6 . An n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ , a p-layer made of p-type GaN provided on the n-layer, and a partial region of the n-layer. Has a p-type region, which is a region made of p-type GaN provided by ion implantation and heat treatment.
The region without the p-shaped region in a plan view is defined as the A region.
The region with the p-shaped region in a plan view is defined as the B region.
From the lower end of the conduction band of GaN, the electron trap level of energy of 0.10 eV or more and less than 0.20 eV is set to TE1.
The electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN is set to TE4.
The average density of each electron trap level in the A region is 0.8 to 1.6 μm from the interface between the n layer and the p layer to the n layer side, and the average density of each electron in the n layer is 0.8 to 1.6 μm. The average density of trap levels
The average density of each electron trap level in the B region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the p-type region to the n layer side. As the average density of electron trap levels,
The average density of the electron trap levels of TE4 in the n-layer in the A region is set to be 1/500 or less of the donor concentration of the n-layer .
The ratio of the average density of the electron trap level of TE1 in the region A to the average density of the electron trap level of TE1 in the region B is set to be 0.03 or less.
A semiconductor device characterized by this. An n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ , a p-layer made of p-type GaN provided on the n-layer, and a partial region of the n-layer. Has a p-type region, which is a region made of p-type GaN provided by ion implantation and heat treatment.
The region without the p-shaped region in a plan view is defined as the A region.
The region with the p-shaped region in a plan view is defined as the B region.
TE2, the electron trap level of energy of 0.20 eV or more and less than 0.30 eV from the lower end of the conduction band of GaN.
The electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN is set to TE4.
The average density of each electron trap level in the A region is 0.8 to 1.6 μm from the interface between the n layer and the p layer to the n layer side, and the average density of each electron in the n layer is 0.8 to 1.6 μm. The average density of trap levels
The average density of each electron trap level in the B region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the p-type region to the n layer side. As the average density of electron trap levels,
The average density of the electron trap levels of TE4 in the n-layer in the A region is set to be 1/500 or less of the donor concentration of the n-layer .
The ratio of the average density of the electron trap levels of TE2 in the region A to the average density of the electron trap levels of TE2 in the region B is set to be 0.02 or less.
A semiconductor device characterized by this. An n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ , a p-layer made of p-type GaN provided on the n-layer, and a partial region of the n-layer. Has a p-type region, which is a region made of p-type GaN provided by ion implantation and heat treatment.
The region without the p-shaped region in a plan view is defined as the A region.
The region with the p-shaped region in a plan view is defined as the B region.
The electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN is set to TE4.
The average density of each electron trap level in the A region is 0.8 to 1.6 μm from the interface between the n layer and the p layer to the n layer side, and the average density of each electron in the n layer is 0.8 to 1.6 μm. The average density of trap levels
The average density of each electron trap level in the B region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the p-type region to the n layer side. As the average density of electron trap levels,
The average density of the electron trap levels of TE4 in the n-layer in the A region is set to be 1/500 or less of the donor concentration of the n-layer .
The ratio of the average density of the electron trap level of TE4 in the region A to the average density of the electron trap level of TE4 in the region B is set to be 0.3 to 2.0.
A semiconductor device characterized by this. An n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ , a p-layer made of p-type GaN provided on the n-layer, and a partial region of the n-layer. Has a p-type region, which is a region made of p-type GaN provided by ion implantation and heat treatment.
The region without the p-shaped region in a plan view is defined as the A region.
The region with the p-shaped region in a plan view is defined as the B region.
TE4 , the electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN.
Let TE9 be the electron trap level of energy of 1.10 eV or more and less than 1.40 eV from the lower end of the conduction band of GaN.
The average density of each electron trap level in the A region is 0.8 to 1.6 μm from the interface between the n layer and the p layer to the n layer side, and the average density of each electron in the n layer is 0.8 to 1.6 μm. The average density of trap levels
The average density of each electron trap level in the B region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the p-type region to the n layer side. As the average density of electron trap levels,
The average density of the electron trap levels of TE4 in the n-layer in the A region is set to be 1/500 or less of the donor concentration of the n-layer .
The ratio of the average density of the electron trap level of TE9 in the region A to the average density of the electron trap level of TE9 in the region B is set to be 0.02 or less.
A semiconductor device characterized by this. An n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ , a p-layer made of p-type GaN provided on the n-layer, and a partial region of the n-layer. Has a p-type region, which is a region made of p-type GaN provided by ion implantation and heat treatment.
The region without the p-shaped region in a plan view is defined as the A region.
The region with the p-shaped region in a plan view is defined as the B region.
TE4 , the electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN.
The hole trap level of energy of 0.80 eV or more and less than 0.90 eV from the upper end of the valence band of GaN is set to TH3.
The average density of each electron trap level in the A region is 0.8 to 1.6 μm from the interface between the n layer and the p layer to the n layer side, and the average density of each electron in the n layer is 0.8 to 1.6 μm. The average density of trap levels
The average density of hole trap levels in the B region is in the p-type region in a region having a depth of 0.02 to 0.05 μm from the interface between the n layer and the p-type region to the p-type region side. As the average density of hole trap levels in
The average density of the electron trap levels of TE4 in the n-layer in the A region is set to be 1/500 or less of the donor concentration of the n-layer .
The ratio of the average density of the hole trap levels of TH3 in the p-type region to the average density of the hole trap levels of TH3 in the p-type region in the B region is 0.7 to 1. .4, which is set to be
A semiconductor device characterized by this. An n-layer made of n-type GaN having a donor concentration of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ , a p-layer made of p-type GaN provided on the n-layer, and a partial region of the n-layer. Has a p-type region, which is a region made of p-type GaN provided by ion implantation and heat treatment.
The region with the p-shaped region in a plan view is defined as the B region.
From the lower end of the conduction band of GaN, the electron trap level of energy of 0.10 eV or more and less than 0.20 eV is set to TE1.
TE2, the electron trap level of energy of 0.20 eV or more and less than 0.30 eV from the lower end of the conduction band of GaN.
TE4, the electron trap level of energy of 0.45 eV or more and less than 0.60 eV from the lower end of the conduction band of GaN.
Let TE9 be the electron trap level of energy of 1.10 eV or more and less than 1.40 eV from the lower end of the conduction band of GaN.
The average density of each electron trap level in the B region is each of the n layers in the region having a depth of 0.8 to 1.6 μm from the interface between the n layer and the p-type region to the n layer side. As the average density of electron trap levels,
The average density of each electron trap level in the n-layer in the B region is
The ratio of the average density of the electron trap levels of TE2 to the average density of the electron trap levels of TE4 is larger than the ratio of the average density of the electron trap levels of TE9 to the average density of the electron trap levels of TE4. The ratio of the average density of the electron trap levels of TE9 to the average density of the electron trap levels is set to be larger than the ratio of the average density of the electron trap levels of TE1 to the average density of the electron trap levels of TE4. ing,
A semiconductor device characterized by this. The region without the p-shaped region in a plan view is defined as the A region.
The average density of each electron trap level in the A region is 0.8 to 1.6 μm from the interface between the n layer and the p layer to the n layer side, and the average density of each electron in the n layer is 0.8 to 1.6 μm. As the average density of trap levels,
The ratio of the average density of the electron trap level of TE1 in the region A to the average density of the electron trap level of TE1 in the region B is set to be 0.03 or less.
The semiconductor device according to claim 17 . The region without the p-shaped region in a plan view is defined as the A region.
The average density of each electron trap level in the A region is 0.8 to 1.6 μm from the interface between the n layer and the p layer to the n layer side, and the average density of each electron in the n layer is 0.8 to 1.6 μm. As the average density of trap levels,
The ratio of the average density of the electron trap levels of TE2 in the region A to the average density of the electron trap levels of TE2 in the region B is set to be 0.02 or less.
The semiconductor device according to claim 17 . The region without the p-shaped region in a plan view is defined as the A region.
The average density of each electron trap level in the A region is 0.8 to 1.6 μm from the interface between the n layer and the p layer to the n layer side, and the average density of each electron in the n layer is 0.8 to 1.6 μm. As the average density of trap levels,
The ratio of the average density of the electron trap level of TE4 in the region A to the average density of the electron trap level of TE4 in the region B is set to be 0.3 to 2.0.
The semiconductor device according to claim 17 . The region without the p-shaped region in a plan view is defined as the A region.
The average density of each electron trap level in the A region is 0.8 to 1.6 μm from the interface between the n layer and the p layer to the n layer side, and the average density of each electron in the n layer is 0.8 to 1.6 μm. As the average density of trap levels,
The ratio of the average density of the electron trap level of TE9 in the region A to the average density of the electron trap level of TE9 in the region B is set to be 0.02 or less.
The semiconductor device according to claim 17 . The hole trap level of 0.80 eV or more and less than 0.90 eV from the upper end of the valence band of GaN is set to TH3.
The region without the p-shaped region in a plan view is defined as the A region.
The average density of hole trap levels in the A region is the holes in the p layer in the region having a depth of 0.02 to 0.05 μm from the interface between the n layer and the p layer to the p layer side. The average density of trap levels
The average density of hole trap levels in the B region is in the p-type region in a region having a depth of 0.02 to 0.05 μm from the interface between the n layer and the p-type region to the p-type region side. As the average density of hole trap levels in
The ratio of the average density of the hole trap levels of TH3 in the p-type region to the average density of the hole trap levels of TH3 in the p-type region in the B region is 0.7 to 1. .4, which is set to be
The semiconductor device according to claim 17 .

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