JP7068640B2 - Manufacturing method of lead frame and semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a lead frame and a semiconductor device.

In recent years, there has been a demand for miniaturization and thinning of semiconductor devices mounted on a substrate. In order to meet such demands, a so-called QFN is conventionally configured by using a lead frame, sealing a semiconductor element mounted on the mounting surface with a sealing resin, and exposing a part of the lead on the back surface side. Various (Quad Flat Non-lead) type semiconductor devices have been proposed.

Conventionally, in the process of producing a QFN package, the lead frame is cut after the resin is sealed, and the lead frame is separated for each package. When cutting the lead frame in this way, the lead frame is first cut by about half the thickness by the first sewing, and then the second time using a blade thinner than the blade used for the first sewing. There is known a method of sewing the lead frames to separate the lead frames from each other (see, for example, Patent Document 1).

US Pat. No. 7,183,630

However, when the lead frame is cut by two sewing steps as described above, when the lead frame is cut by about half the thickness in the first sewing, the alignment mark for positioning the lead frame disappears. 2 There is a problem that it becomes difficult to position the lead frame during the second sewing.

The present invention has been made in consideration of such a point, and when the lead frame is cut by about half the thickness in the first sewing, the alignment mark remains, and this alignment mark is used in the second sewing. It is an object of the present invention to provide a lead frame and a semiconductor device capable of providing a lead frame and a semiconductor device.

The present invention includes an outer peripheral region, a package region arranged in the outer peripheral region, a step cut region extending from the periphery of the package region to the outer peripheral region, and an alignment mark provided in the outer peripheral region in the lead frame. The alignment mark is a lead frame arranged so as not to overlap the step cut region.

In the present invention, the alignment mark is a lead frame provided on both sides of the step cut region in the width direction.

In the present invention, the alignment mark is a lead frame including a non-penetrating region recessed halfway in the thickness direction of the outer peripheral region.

The present invention relates to an outer peripheral region, a package region arranged in the outer peripheral region, a step cut region extending from the periphery of the package region to the outer peripheral region, and an alignment mark provided in the outer peripheral region in the lead frame. The alignment mark is a lead frame including a penetration region penetrating the outer peripheral region in the thickness direction.

In the present invention, the alignment mark is a lead frame including a non-penetrating region recessed halfway in the thickness direction of the outer peripheral region.

In the present invention, in the method for manufacturing a semiconductor device, the lead frame is prepared, the lead frame is sealed with a sealing resin, the lead frame is positioned based on the alignment mark, and the step cut is performed. A step of cutting a part of the lead frame in the thickness direction along the region, and a step of positioning the lead frame based on the alignment mark and cutting the lead frame and the sealing resin for each package region. It is a manufacturing method of a semiconductor device provided with.

According to the present invention, when the lead frame is cut by about half the thickness in the first sewing, the alignment mark remains, and this alignment mark can be used in the second sewing.

FIG. 1 is a plan view showing a part of a lead frame according to an embodiment of the present invention. FIG. 2 is a bottom view showing a part of a lead frame according to an embodiment of the present invention. FIG. 3 is a cross-sectional view showing a lead frame according to an embodiment of the present invention (cross-sectional view taken along the line III-III of FIG. 1). FIG. 4 is a plan view showing a semiconductor device according to an embodiment of the present invention. FIG. 5 is a cross-sectional view (VV line cross-sectional view of FIG. 4) showing a semiconductor device according to an embodiment of the present invention. 6 (a)-(e) are cross-sectional views showing a method of manufacturing a lead frame according to an embodiment of the present invention. 7 (a)-(d) are cross-sectional views showing a method (first half) of manufacturing a semiconductor device according to an embodiment of the present invention. 8 (a)-(c) are cross-sectional views showing a method (second half) of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 9 is a bottom view showing a part of a lead frame according to a modification (modification 1) of the present invention. FIG. 10 is a bottom view showing a part of a lead frame according to a modification (modification 2) of the present invention. FIG. 11 is a bottom view showing a part of a lead frame according to a modification of the present invention (modification 3).

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 8. In each of the following figures, the same parts are designated by the same reference numerals, and some detailed description may be omitted.

Configuration of Lead Frame First, the outline of the lead frame according to the present embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 is a plan view showing a part of a lead frame according to the present embodiment, FIG. 2 is a bottom view showing a part of the lead frame according to the present embodiment, and FIG. 3 is a bottom view showing a part of the lead frame according to the present embodiment. It is sectional drawing which shows the lead frame by.

The lead frame 10 shown in FIGS. 1 to 3 is used when manufacturing the semiconductor device 20 (FIGS. 4 and 5). Such a lead frame 10 includes an outer peripheral region 18 having a rectangular outer shape, and a plurality of package regions 10a arranged in multiple rows and stages (in a matrix) within the outer peripheral region 18. In addition, in FIG. 1 and FIG. 2, only a part including a corner portion of the lead frame 10 is shown.

The outer peripheral region 18 is formed in a rectangular annular shape in a plan view so as to surround the periphery of the plurality of package regions 10a. The width W1 of the outer peripheral region 18 may be 10 mm or more and 50 mm or less. The outer peripheral region 18 has the same thickness as the metal substrate before processing (metal substrate 31 described later) without being thinned (half-etched) except for the alignment mark 40 described later.

An outer peripheral thin portion 18a is formed between the outer peripheral region 18 and the plurality of package regions 10a. The outer peripheral thin portion 18a is formed in a rectangular annular shape in a plan view so as to surround the plurality of package regions 10a arranged on the outermost side. The outer peripheral thin-walled portion 18a is a portion formed to be thin-walled by half-etching from the back surface side.

Here, half-etching means etching the material to be etched halfway in the thickness direction thereof. The thickness of the material to be etched after half-etching is, for example, 30% or more and 70% or less, preferably 40% or more and 60% or less of the thickness of the material to be etched before half-etching. In each figure, the half-etched region is shaded.

In the present specification, "inside" and "inside" refer to the side facing the center of the die pad 11 in each package area 10a, and "outside" and "outside" refer to the center of the die pad 11 in each package area 10a. The side away from (connecting bar 13 side). Further, the "front surface" is the surface on the side on which the semiconductor element 21 is mounted, and the "back surface" is the surface on the opposite side of the "front surface" and is connected to an external mounting board (not shown). Refers to the surface.

As shown in FIGS. 1 to 3, each package region 10a is provided with a planar rectangular die pad 11 on which the semiconductor element 21 (described later) is mounted, and around the die pad 11, and the semiconductor element 21 and an external circuit (not shown). ) Is provided with a plurality of elongated lead portions 12. The package region 10a is a region corresponding to the semiconductor device 20 (described later), respectively. The package area 10a is an area surrounded by a cutting area 46 extending vertically and horizontally in FIGS. 1 and 2. In the present embodiment, the lead frame 10 includes a plurality of package areas 10a, but the present invention is not limited to this, and only one package area 10a may be formed in one lead frame 10.

The plurality of package areas 10a are connected to each other via a connecting bar (support member) 13. The connecting bar 13 supports the die pad 11 and the lead portion 12, and extends along the X direction and the Y direction, respectively. Here, the X direction and the Y direction are two directions parallel to each side of the die pad 11 in the plane of the lead frame 10, and the X direction and the Y direction are orthogonal to each other. Further, the Z direction is a direction perpendicular to both the X direction and the Y direction. The length L1 of one side of the package region 10a may be 2 mm or more and 9 mm or less.

The die pad 11 has a substantially square shape in a plane, and a semiconductor element 21 described later is mounted on the surface thereof. The planar shape of the die pad 11 is not limited to a square, but may be a polygon such as a rectangle. Further, a suspension lead 14 is connected to each of the four corners of the die pad 11, and the die pad 11 is connected and supported to the connecting bar 13 or the outer peripheral region 18 via the four suspension leads 14. Each hanging lead 14 is formed thinly from the back surface side by half etching over the entire area. However, the present invention is not limited to this, and only a part of the hanging lead 14 may be thinned from the back surface side.

Each connecting bar 13 has an elongated rod shape, and its width W2 (length in the direction perpendicular to the longitudinal direction of the connecting bar 13) may be 100 μm or more and 250 μm or less. A plurality of lead portions 12 are connected to each connecting bar 13 at intervals along the longitudinal direction. The connecting bar 13 is thinned from the back surface side by half etching over the entire area.

The die pad 11 has a die pad thick portion 11a located at the center and a die pad thin portion 11b formed over the entire periphery of the die pad thick portion 11a. Of these, the die pad thick portion 11a is not half-etched and has the same thickness as the metal substrate before processing (the metal substrate 31 described later). Specifically, the thickness of the die pad thick portion 11a can be 80 μm or more and 200 μm or less, although it depends on the configuration of the semiconductor device 20. On the other hand, the die pad thin-walled portion 11b is formed to be thin-walled from the back surface side by half etching. By providing the die pad thin portion 11b in this way, it is possible to prevent the die pad 11 from coming off from the sealing resin 23 (described later).

Each lead portion 12 is connected to the semiconductor element 21 via a bonding wire 22 as described later, and is arranged between the lead portion 12 and the die pad 11 via a space. Each lead portion 12 extends from the connecting bar 13. In this case, the shapes of the plurality of lead portions 12 are all the same as each other, but the shape is not limited to this, and the shapes of the plurality of lead portions 12 may be different from each other.

As described above, the plurality of lead portions 12 are arranged around the die pad 11 at intervals along the longitudinal direction of the connecting bar 13. The adjacent lead portions 12 have a shape that is electrically insulated from each other after the semiconductor device 20 (described later) is manufactured. Further, the lead portion 12 has a shape that is electrically insulated from the die pad 11 after the semiconductor device 20 is manufactured. External terminals 17 electrically connected to external mounting boards (not shown) are formed on the back surface of the lead portion 12, respectively. Each external terminal 17 is exposed to the outside from the semiconductor device 20 after the semiconductor device 20 (described later) is manufactured.

In this case, the external terminals 17 are arranged in a row along each side of the die pad 11 in a plan view. However, not limited to this, the external terminals 17 may be arranged in a staggered manner in a plan view so as to be alternately located inside and outside between the adjacent lead portions 12.

Each lead portion 12 has a thin-walled portion 12a formed on its inner end (end on the die pad 11 side), which is thinned from the back surface side by half etching. Further, an internal terminal 15 is formed on the surface of each lead portion 12. The internal terminal 15 is a region electrically connected to the semiconductor element 21 via the bonding wire 22 as described later. Therefore, a plated portion for improving the adhesion to the bonding wire 22 may be provided on the internal terminal 15.

The base end portion of each lead portion 12 is connected to the connecting bar 13. Each lead portion 12 extends perpendicular to the longitudinal direction of the connecting bar 13 to which the lead portion 12 is connected. However, the present invention is not limited to this, and a part or all of each lead portion 12 may be inclined and extended with respect to the connecting bar 13.

By the way, the lead frame 10 according to the present embodiment is cut by two-step sewing as described later. That is, first, by the first sewing, the lead frame 10 is partially cut (step cut) along the connecting bar 13 by about half the thickness. Then, a second sewing is performed using a cutting blade 38 (described later) thinner than the step cutting blade 37 (described later) used for step cutting, and the lead frames 10 are separated from each other.

Therefore, the lead frame 10 is provided with a step cut region 45 that is step cut along the length direction of the connecting bar 13 and a cutting region 46 that is separated by dicing. Then, in a plan view, the entire area of the connecting bar 13 is located inside the corresponding cutting area 46, and the entire area of the cutting area 46 is located inside the corresponding step cut area 45. Further, the widthwise center lines CL of the step cut region 45, the cut region 46, and the connecting bar 13 coincide with each other.

The step cut region 45 is a region that is step cut (half cut) by approximately half in the thickness direction (Z direction) of the lead frame 10 by the first sewing after resin sealing, and is a pair of regions parallel to each other in a plan view. It is partitioned by outer edges S1 and S1. The step cut regions 45 are arranged in a grid pattern along the outer periphery of the package region 10a, and extend along the X direction or the Y direction, respectively. The step cut region 45 extends from the package region 10a to the outer peripheral region 18, and crosses the outer peripheral region 18 in the width direction. The width W3 of the step cut region 45 corresponds to the width of the step cut blade 37 (described later) for performing the step cut, and is wider than the width W2 of the connecting bar 13. Specifically, the width W3 of the step cut region 45 may be 30 μm or more and 80 μm or less.

The cutting region 46 is a region that is cut in the entire thickness direction (Z direction) of the lead frame 10 by the second sewing, and is partitioned by a pair of outer edges C1 and C1 that are parallel to each other in a plan view. The cut regions 46 are arranged in a grid pattern along the outer periphery of the package region 10a, and extend along the X direction or the Y direction, respectively. Further, the cutting region 46 extends from the package region 10a to the outer peripheral region 18, and also crosses the outer peripheral region 18 in the width direction. The outer edge of the package area 10a coincides with the outer edges C1 and C1 of the cutting area 46. The width W4 of the cutting region 46 corresponds to the width of the cutting blade 38 (described later) for performing the second sewing, is wider than the width W2 of the connecting bar 13, and is narrower than the width W3 of the step cutting region 45 (described later). W2 <W4 <W3). Specifically, the width W4 of the cutting region 46 may be 10 μm or more and 40 μm or less.

In the present embodiment, the outer peripheral region 18 is provided with a plurality of alignment marks 40. The alignment mark 40 is for positioning the blades 37 and 38 during sewing. Specifically, the alignment mark 40 is used for positioning to perform both a step cut along the step cut region 45 (first sewing) and a cutting separation along the cutting region 46 (second sewing). .. Therefore, each alignment mark 40 is arranged at a position corresponding to each step cut region 45 and cut region 46. In this case, the plurality of alignment marks 40 are provided along the four sides of the outer peripheral region 18, and correspond to the step cut region 45 and the cut region 46 extending in the X direction or the Y direction, respectively.

Each alignment mark 40 has a substantially rectangular shape in a plan view. The length L2 of the side of each alignment mark 40 parallel to the width direction of the outer peripheral region 18 may be 100 μm or more and 1500 μm or less. The length L3 of the side of each alignment mark 40 parallel to the longitudinal direction of the outer peripheral region 18 may be 50 μm or more and 300 μm or less. Further, each alignment mark 40 is composed of a non-penetrating region recessed halfway in the thickness direction (Z direction) of the outer peripheral region 18. That is, each alignment mark 40 is formed thinly from the back surface side by half etching, and the depth thereof is 30% or more and 70% or less, preferably 40% or more and 60% or less of the thickness of the outer peripheral region 18. Not limited to this, each alignment mark 40 may be composed of a penetration region penetrating in the thickness direction (Z direction) of the lead frame 10.

In the present embodiment, each alignment mark 40 is arranged so as to be offset from the step cut region 45 in the width direction so as not to overlap the step cut region 45. As a result, even after the lead frame 10 is step-cut, each alignment mark 40 remains on the lead frame 10. That is, in FIG. 2, each alignment mark 40 remains on the outer peripheral region 18 even after the step cut region 45 is partially removed in the thickness direction by the step cut. Therefore, the alignment mark 40 can be used to position the cutting blade 38 for the second sewing.

In this case, one alignment mark 40 is provided on each side of each step cut region 45 in the width direction (two in total). The distance P1 between each alignment mark 40 and the corresponding step cut region 45 is set to a constant value, and specifically, it may be 50 μm or more and 300 μm or less. That is, the center positions of the pair of alignment marks 40 are aligned on the widthwise center line CL of the step cut region 45 and the cut region 46 corresponding to them. Not limited to this, only one alignment mark 40 may correspond to each step cut region 45.

The lead frame 10 described above is composed of a metal such as copper, a copper alloy, and a 42 alloy (Ni 42% Fe alloy) as a whole. The thickness of the lead frame 10 can be 80 μm or more and 200 μm or less, although it depends on the configuration of the semiconductor device 20 to be manufactured.

In the present embodiment, the lead portion 12 is arranged along all four sides of the die pad 11, but is not limited to this, and is arranged, for example, along only two opposing sides of the die pad 11. You may be.

Configuration of Semiconductor Device Next, the semiconductor device according to the present embodiment will be described with reference to FIGS. 4 and 5. 4 and 5 are diagrams showing a semiconductor device (QFN type) according to the present embodiment.

As shown in FIGS. 4 and 5, the semiconductor device (semiconductor package) 20 includes a die pad 11, a plurality of lead portions 12 arranged around the die pad 11, and a semiconductor element 21 mounted on the die pad 11. A plurality of bonding wires (connecting members) 22 for electrically connecting the lead portion 12 and the semiconductor element 21 are provided. Further, the die pad 11, the lead portion 12, the semiconductor element 21, and the bonding wire 22 are resin-sealed with the sealing resin 23.

The die pad 11 and the lead portion 12 are manufactured from the lead frame 10 described above. The portion of the lead portion 12 located on the peripheral edge of the sealing resin 23 is thinned from the back surface side by step cutting to form a stepped step cutting portion 45a. The step cut portion 45a is not filled with the sealing resin 23. The step cut portion 45a may be covered with solder plating. Further, burrs may be generated on the side surface 45b of the step cut portion 45a at the time of step cutting, and the burrs may protrude toward the back surface side. The depth D1 of the step cut portion 45a may be deeper than the depth D2 of the half-etched portion (die pad thin-walled portion 11b or the like). In addition, since the configurations of the die pad 11 and the lead portion 12 are the same as those shown in FIGS. 1 to 3 described above except for the region not included in the semiconductor device 20, detailed description thereof will be omitted here.

As the semiconductor element 21, various semiconductor elements generally used in the past can be used, and the semiconductor element 21 is not particularly limited, and for example, an integrated circuit, a large-scale integrated circuit, a transistor, a thyristor, a diode, or the like can be used. The semiconductor element 21 has a plurality of electrodes 21a to which the bonding wires 22 are attached. Further, the semiconductor element 21 is fixed to the surface of the die pad 11 with an adhesive 24 such as a die bonding paste.

Each bonding wire 22 is made of a highly conductive material such as gold or copper. One end of each bonding wire 22 is connected to the electrode 21a of the semiconductor element 21, and the other end is connected to the internal terminal 15 of each lead portion 12. The internal terminal 15 may be provided with a plated portion that improves the adhesion to the bonding wire 22.

As the sealing resin 23, a thermosetting resin such as a silicone resin or an epoxy resin, or a thermoplastic resin such as a PPS resin can be used. The thickness of the entire sealing resin 23 can be about 300 μm or more and 1200 μm or less. Further, one side of the sealing resin 23 (one side of the semiconductor device 20) can be, for example, 6 mm or more and 16 mm or less. In FIG. 4, the display of the portion of the sealing resin 23 located on the surface side of the die pad 11 and the lead portion 12 is omitted.

Method for Manufacturing Lead Frame Next, a method for manufacturing the lead frame 10 shown in FIGS. 1 to 3 will be described with reference to FIGS. 6 (a) and 6 (e). 6 (a)-(e) are cross-sectional views (corresponding to FIG. 3) showing a method of manufacturing the lead frame 10.

First, as shown in FIG. 6A, a flat plate-shaped metal substrate 31 is prepared. As the metal substrate 31, a substrate made of a metal such as copper, a copper alloy, or a 42 alloy (Ni 42% Fe alloy) can be used. It is preferable to use a metal substrate 31 that has been degreased and cleaned on both sides thereof.

Next, the photosensitive resists 32a and 33a are applied to the entire front and back of the metal substrate 31, respectively, and dried (FIG. 6 (b)). As the photosensitive resists 32a and 33a, conventionally known ones can be used.

Subsequently, the metal substrate 31 is exposed to the metal substrate 31 via a photomask and developed to form etching resist layers 32 and 33 having desired openings 32b and 33b (FIG. 6 (c)).

Next, the metal substrate 31 is etched with a corrosion solution using the etching resist layers 32 and 33 as corrosion resistant films (FIG. 6 (d)). As a result, the outer shapes of the die pad 11 and the lead portion 12 are formed. At this time, the alignment mark 40 is formed on the outer peripheral region 18 by half-etching from the back surface side thereof. The corrosion liquid can be appropriately selected depending on the material of the metal substrate 31 to be used. For example, when copper is used as the metal substrate 31, a ferric chloride aqueous solution is usually used and both sides of the metal substrate 31 are used. Can be spray etched from.

Then, by peeling off and removing the etching resist layers 32 and 33, the lead frame 10 shown in FIGS. 1 to 3 can be obtained. (FIG. 6 (e)).

Manufacturing Method of Semiconductor Device Next, a manufacturing method of the semiconductor device 20 shown in FIGS. 4 and 5 will be described with reference to FIGS. 7 (a)-(d) and 8 (a)-(c).

First, the lead frame 10 is manufactured, for example, by the method shown in FIGS. 6A-(e) (FIG. 7A).

Next, the semiconductor element 21 is mounted on the die pad 11 of the lead frame 10. In this case, the semiconductor element 21 is placed and fixed on the die pad 11 by using an adhesive 24 such as a die bonding paste (diaattachment step) (FIG. 7 (b)).

Next, each electrode 21a of the semiconductor element 21 and the internal terminal 15 of each lead portion 12 are electrically connected to each other by a bonding wire (connecting member) 22 (wire bonding step) (FIG. 7 (c)). ..

Next, the sealing resin 23 is formed by injection molding or transfer molding of a thermosetting resin or a thermoplastic resin with respect to the lead frame 10 (resin sealing step) (FIG. 7 (d)). In this way, the lead frame 10 (die pad 11 and lead portion 12), the semiconductor element 21, and the bonding wire 22 are sealed. At this time, the sealing resin 23 is also filled in the alignment mark 40 of the outer peripheral region 18.

Subsequently, the lead frame 10 is positioned based on the alignment mark 40, and a part of the lead frame 10 in the thickness direction is cut along the step cut region 45 (step cut step: first sewing) (FIG. 8 (FIG. 8). a)).

During this period, first, an image pickup device (not shown) detects alignment marks 40 located on both sides of the step cut region 45 in the width direction, and obtains a center line passing through the center of the pair of alignment marks 40. Next, a step-cutting blade 37 made of, for example, a diamond grindstone is prepared, and the step-cutting blade 37 is moved along the center line. At this time, the step cut region 45 is cut while rotating the step cut blade 37. As a result, the connecting bar 13, the outer peripheral region 18, and the sealing resin 23 in the step cut region 45 are partially cut off. By this step cut, the connecting bar 13 and the outer peripheral region 18 of the step cut region 45 are cut off halfway in the thickness direction, and the step cut portion 45a is formed. This step cut operation is repeated a plurality of times along the X direction and the Y direction, and the step cut portion 45a is formed in a planar grid pattern.

After this step cut step, a solder plating layer (not shown) may be formed on the step cut portion 45a by performing electrolytic plating.

Next, the lead frame 10 is repositioned based on the alignment mark 40, and the lead frame 10 and the sealing resin 23 are cut for each package region 10a (cutting step: second sewing) (FIG. 8 (b)).

At this time, an image pickup device (not shown) detects alignment marks 40 located on both sides of the cutting region 46 in the width direction, and obtains a center line passing through the center of the pair of alignment marks 40. Next, a cutting blade 38 made of, for example, a diamond grindstone is prepared. The cutting blade 38 has a narrower width than the step cutting blade 37 described above. Next, the cutting region 46 is cut by moving the cutting blade 38 along the center line while rotating the blade 38. As a result, the connecting bar 13, the outer peripheral region 18, and the sealing resin 23 in the cutting region 46 are cut (diced) over the entire thickness direction (Z direction). This cutting operation is repeated a plurality of times along the X direction and the Y direction, and cutting lines are formed in a planar grid pattern.

In this way, the lead frame 10 is separated for each semiconductor device 20, and the semiconductor device 20 shown in FIGS. 4 and 5 is obtained (FIG. 7 (c)).

As described above, according to the present embodiment, the outer peripheral region 18 is provided with an alignment mark 40 for positioning the lead frame 10 in both the step cutting step and the cutting step. The alignment mark 40 is arranged so as not to overlap the step cut region 45. As a result, the alignment mark 40 does not disappear even after the step cut region 45 is step cut and partially cut in the thickness direction. Therefore, the lead frame 10 can be positioned using the alignment mark 40 in the cutting process.

Further, according to the present embodiment, since the alignment mark 40 does not overlap the step cut region 45, burrs and the like do not occur in the alignment mark 40 due to the step cutting operation. As a result, the shape of the alignment mark 40 does not change, and the alignment mark 40 can be accurately identified in the cutting process.

Further, according to the present embodiment, the alignment marks 40 are provided on both sides of the step cut region 45 in the width direction. By positioning the center of the pair of alignment marks 40 with, for example, the center line of the step cut region 45, the step cut region 45 can be accurately positioned and the step cut operation can be performed with high position accuracy.

Further, according to the present embodiment, the alignment mark 40 includes a non-penetrating region recessed halfway in the thickness direction of the outer peripheral region 18. Since the alignment mark 40 can be formed at the same time by half etching when the lead frame 10 is formed by etching, it is not necessary to separately provide a step of forming the alignment mark 40.

Modification Example Next, a modification of the lead frame according to the present embodiment will be described with reference to FIGS. 9 to 11. The modified examples shown in FIGS. 9 and 10 have different configurations of the alignment marks, and the other configurations are substantially the same as those of the embodiments shown in FIGS. 1 to 8. Further, in the modified example shown in FIG. 11, the configurations of the die pad and the lead portion are mainly different. In FIGS. 9 to 11, the same parts as those in FIGS. 1 to 8 are designated by the same reference numerals, and detailed description thereof will be omitted.

(Modification 1)
In the lead frame 10A shown in FIG. 9, the alignment mark 40 has a penetrating region 41 that penetrates the outer peripheral region 18 in the thickness direction (Z direction) and a non-penetrating region 42 that is recessed halfway in the thickness direction of the outer peripheral region 18. ing.

The penetration region 41 is located on the outer side of the outer peripheral region 18 from the non-penetration region 42 (the side far from the package region 10a), and is arranged away from the non-penetration region 42. In this case, the penetrating region 41 has a rectangular shape in a plan view, and each side thereof is parallel to the X direction or the Y direction. The length L4 of the side of the penetration region 41 parallel to the longitudinal direction of the outer peripheral region 18 is wider than the width of the step cut region 45, and may be specifically 200 μm or more and 600 μm or less. The length L5 of the side of the penetration region 41 parallel to the width direction of the outer peripheral region 18 may be 50 μm or more and 600 μm or less.

The non-penetrating region 42 has a rectangular shape in a plan view, and each side thereof is parallel to the X direction or the Y direction. The non-penetrating region 42 is formed thinly from the back surface side by half etching, and the depth thereof is 30% or more and 70% or less, preferably 40% or more and 60% or less of the thickness of the outer peripheral region 18. The length L6 of the side of the non-penetrating region 42 parallel to the width direction of the outer peripheral region 18 may be the same as the length L4 of the side of the penetrating region 41 parallel to the longitudinal direction of the outer peripheral region 18. The length L7 of the side of the non-penetrating region 42 parallel to the width direction of the outer peripheral region 18 may be 100 μm or more and 1500 μm or less.

The center positions of the penetrating region 41 and the non-penetrating region 42 coincide with the widthwise center line CL of the step cut region 45 and the cutting region 46 corresponding to them. Therefore, the step cut region 45 can be cut or the cut region 46 can be cut along the center lines of the penetrating region 41 and the non-penetrating region 42.

When manufacturing a semiconductor device using the lead frame 10A shown in FIG. 9, first, a non-penetrating region 42 of the alignment mark 40 is detected by an image pickup device (not shown), and a center line passing through the center of the non-penetrating region 42 is obtained. .. Next, by moving the step cutting blade 37 (see FIG. 7A) along the center line, the connecting bar 13, the outer peripheral region 18, and the sealing resin 23 in the step cutting region 45 are partially formed in the thickness direction. Excision.

After that, a penetrating region 41 of the alignment mark 40 is detected by an image pickup device (not shown), and a center line passing through the central portion of the penetrating region 41 is obtained. Next, the cutting region 46 is cut by moving the cutting blade 38 (see FIG. 7B) along the center line.

As described above, according to the present modification, the alignment mark 40 includes the penetration region 41 penetrating the outer peripheral region 18 in the thickness direction. As a result, even after the step cut region 45 is step cut and partially cut in the thickness direction, the penetration region 41 of the alignment mark 40 does not disappear. Therefore, the lead frame 10A can be positioned using the penetration region 41 in the cutting step.

(Modification 2)
In the lead frame 10B shown in FIG. 10, the alignment mark 40 has a penetrating region 43 that penetrates the outer peripheral region 18 in the thickness direction (Z direction) and a non-penetrating region 44 that is recessed halfway in the thickness direction of the outer peripheral region 18. ing. In this case, the penetrating region 43 and the non-penetrating region 44 are integrally formed.

The penetration region 43 has a rectangular shape in a plan view, and each side thereof is parallel to the X direction or the Y direction. The length L8 of the side of the penetration region 43 parallel to the longitudinal direction of the outer peripheral region 18 is narrower than the width of the cutting region 46, and may be specifically 80 μm or more and 300 μm or less. The length L9 of the side of the penetration region 43 parallel to the width direction of the outer peripheral region 18 may be 100 μm or more and 1500 μm or less.

The non-penetrating region 44 is arranged so as to surround the entire circumference of the penetrating region 43 in a plan view. That is, in a plan view, the penetrating region 43 is located inside the non-penetrating region 44. The non-penetrating region 44 has an annular rectangular shape, and each side of the rectangle is parallel to the X direction or the Y direction. The non-penetrating region 44 is formed thinly from the back surface side by half etching, and the depth thereof is 30% or more and 70% or less, preferably 40% or more and 60% or less of the thickness of the outer peripheral region 18. The length L10 of the side of the non-penetrating region 44 parallel to the width direction of the outer peripheral region 18 may be the same as the width of the step cut region 45. The length L11 of the side of the non-penetrating region 44 parallel to the width direction of the outer peripheral region 18 may be 200 μm or more and 600 μm or less.

The center positions of the penetrating region 43 and the non-penetrating region 44 coincide with the widthwise center line CL of the step cut region 45 and the cutting region 46 corresponding to them. Therefore, the step cut region 45 can be cut or the cut region 46 can be cut along the center lines of the penetrating region 43 and the non-penetrating region 44.

When manufacturing a semiconductor device using the lead frame 10B shown in FIG. 10, first, a non-penetrating region 44 of the alignment mark 40 is detected by an image pickup device (not shown), and a center line passing through the center of the non-penetrating region 44 is obtained. .. Next, by moving the step cutting blade 37 (see FIG. 7A) along the center line, the connecting bar 13, the outer peripheral region 18, and the sealing resin 23 in the step cutting region 45 are partially formed in the thickness direction. Excision.

After that, the penetrating region 43 of the alignment mark 40 is detected by an image pickup device (not shown), and the center line passing through the central portion of the penetrating region 43 is obtained. Next, the cutting region 46 is cut by moving the cutting blade 38 (see FIG. 7B) along the center line.

According to this modification, the alignment mark 40 includes a penetration region 43 that penetrates the outer peripheral region 18 in the thickness direction. As a result, even after the step cut region 45 is step cut and partially cut in the thickness direction, the penetration region 43 of the alignment mark 40 does not disappear. Therefore, the lead frame 10B can be positioned using the penetration region 43 in the cutting step.

Further, according to this modification, since the sealing resin 23 enters the penetrating region 43 and the non-penetrating region 44 of the alignment mark 40, the sealing resin 23 in the alignment mark 40 serves as an anchor and seals. The stop resin 23 and the lead frame 10B can be firmly adhered to each other.

(Modification 3)
The lead frame 10C shown in FIG. 11 includes a plurality of package areas 10a, and each package area 10a includes a planar rectangular die pad 61 and a plurality of planar rectangular lead portions 62 provided around the die pad 61. I have. In this case, four lead portions 62 are arranged around each die pad 61. Further, each die pad 61 is held in the connecting bar 13 or the outer peripheral region 18 by four suspension leads 64. In this case, the suspension lead 64 extends in parallel in the X direction or the Y direction, and is thinned by half etching from the back surface side.

The lead portions 62 are connected to connecting bars 13 extending in the X direction, respectively. On the other hand, the lead portion 62 is not connected to the connecting bar 13 extending in the Y direction. Further, the step cut region 45 and the cut region 46 are formed around the connecting bar 13 extending in the Y direction. On the other hand, the step cut region 45 is not formed around the connecting bar 13 extending in the X direction, and only the cut region 46 is formed.

One alignment mark 40 (two in total) is provided on each side of the step cut region 45 extending in the Y direction in the width direction. The configuration of the alignment mark 40 is substantially the same as the configuration of the alignment mark 40 shown in FIGS. 1 to 3. On the other hand, one plane rectangular alignment mark 40A is provided on each of the cutting regions 46 extending in the X direction. The alignment mark 40A is composed of a non-penetrating region 42 that is recessed halfway in the thickness direction of the outer peripheral region 18. Further, the length of the alignment mark 40A in the Y direction is substantially the same as the width of the corresponding cutting region 46.

In FIG. 11, a region near the corner of the package region 10a where the cutting region 46 extending in the X direction and the cutting region 46 extending in the Y direction overlap (for example, the portion indicated by the arrow A in FIG. 11) is formed three times. This is the part to be sewn. In this modification, the portion A to be sewn three times is made to penetrate in the thickness direction. This makes it possible to suppress burrs caused by the ductility of the material (for example, copper) of the lead frame 10C during sewing.

Further, according to the present modification, the connecting bar 13 extending in the Y direction is saw-inked twice, and the connecting bar 13 extending in the X direction is sewn only once. As a result, the distortion generated in the lead frame 10C due to sewing can be minimized, and the positional deviation generated at the time of the second cutting due to this distortion can be reduced.

Further, according to this modification, both the connecting bar 13 extending in the X direction (sewing once) and the connecting bar 13 extending in the Y direction (sewing twice) are thinned from the back surface side. Therefore, since the cutting amount of the metal in the portion sewn once and the portion sewn twice is substantially the same, the cutting condition in the X direction and the sewing condition in the Y direction can be substantially the same.

It is also possible to appropriately combine a plurality of components disclosed in the above embodiments and modifications as necessary. Alternatively, some components may be deleted from all the components shown in the above embodiments and modifications.

10 Lead frame 10a Package area 11 Die pad 12 Lead part 13 Connecting bar 14 Suspended lead 15 Internal terminal 17 External terminal 18 Outer peripheral area 20 Semiconductor device 21 Semiconductor element 22 Bonding wire 23 Encapsulation resin 40 Alignment mark 45 Step cut area 46 Cutting area

Claims (5)

In the lead frame
Outer peripheral area and
The package area arranged in the outer peripheral area and the package area
A step cut area extending from the periphery of the package area to the outer peripheral area,
With an alignment mark provided in the outer peripheral region,
The alignment mark is arranged so as not to overlap the step cut region.
No other alignment mark is arranged in the step cut region of the outer peripheral region.
The alignment marks are lead frames provided on both sides of the step cut region in the width direction . The lead frame according to claim 1 , wherein the alignment mark includes a non-penetrating region recessed halfway in the thickness direction of the outer peripheral region. In the lead frame
Outer peripheral area and
The package area arranged in the outer peripheral area and the package area
A step cut area extending from the periphery of the package area to the outer peripheral area,
With an alignment mark provided in the outer peripheral region,
The alignment mark includes a penetrating region that penetrates the outer peripheral region in the thickness direction and a non-penetrating region that is recessed halfway in the thickness direction of the outer peripheral region.
A lead frame in which the center positions of the penetrating region and the non-penetrating region coincide with the widthwise center line of the penetrating region and the step cut region corresponding to the non-penetrating region. The lead frame according to claim 3 , wherein the non-penetrating region is arranged so as to surround the entire periphery of the penetrating region in a plan view. In the manufacturing method of semiconductor devices
The step of preparing the lead frame according to any one of claims 1 to 4 , and the step of preparing the lead frame.
The step of sealing the lead frame with a sealing resin and
A step of positioning the lead frame based on the alignment mark and cutting a part of the lead frame in the thickness direction along the step cut region.
A method for manufacturing a semiconductor device, comprising a step of positioning the lead frame based on the alignment mark and cutting the lead frame and the sealing resin for each package region.

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