JP7043791B2 - Inverter abnormality judgment device - Google Patents

Description

The present invention relates to an abnormality determination device for an inverter, and more particularly to an abnormality determination device for an inverter having a plurality of legs including a switching element for an upper arm and a switching element for a lower arm.

Conventionally, as an abnormality determination device for this type of inverter, a device including a drive circuit (driver) and a determination device (CPU) has been proposed (see, for example, Patent Document 1). The drive circuit drives each switching element of the upper and lower arms of the inverter. The judgment device controls the drive circuit so that the switching elements of the upper and lower arms of the inverter are turned on by sequentially shifting the timing, and the terminal voltage of the specific phase of the motor driven by the inverter when each switching element is turned on. Is calculated, and it is determined whether or not a short-circuit failure has occurred in each switching element using the terminal voltage of the specific phase.

JP-A-2015-89294

However, in the above-mentioned inverter abnormality determination device, since each switching element is turned on at different timings in sequence, an abnormality may occur in other switching elements by turning on each switching element. For example, if the normal lower arm switching element is turned on when an excessive current flows in the upper arm switching element and the normal lower arm switching element is turned on, the upper and lower arms are short-circuited and the normal lower arm switching element is abnormal. May occur.

The inverter abnormality determination device of the present invention mainly determines whether or not an abnormality has occurred in the other switching element by executing the first process for driving the switching element in order to determine the abnormality in the specific switching element. The purpose.

The abnormality determination device for the inverter of the present invention has adopted the following means in order to achieve the above-mentioned main object.

The inverter abnormality determination device of the present invention is
An inverter abnormality determination device having a plurality of legs including an upper arm switching element and a lower arm switching element.
When the corresponding switching element is driven by using the input drive signal provided for each switching element and a predetermined abnormality of the corresponding switching element is detected, the abnormality signal is transmitted to a single signal line. Multiple drive circuits that output only for one hour,
A determination device that outputs the drive signal to the plurality of drive circuits and determines the type of abnormality of the switching element based on the abnormality signal output to the signal line.
Equipped with
The determination device is
For each leg, the first process of outputting the drive signal to one of the two switching elements of the upper and lower arms and the drive signal to the other switching element of the switching elements of the upper and lower arms. The second process to output is executed in order, and
When the abnormal signal is output to the signal line for the first time during the period in which the first process and the second process are executed, it is determined that the predetermined abnormality has occurred in one of the switching elements. When the abnormality signal is output to the signal line for a longer time than the first time, it is determined that the other switching element has an abnormality due to the execution of the first process.
The gist is that.

In the abnormality determination device of the inverter of the present invention, the first process of outputting a drive signal to one of the two switching elements of the upper and lower arms and the other of the switching elements of the upper and lower arms for each leg. In the period in which the second process of outputting the drive signal to the switching element of the above is executed in order, and the first process and the second process are executed, when the abnormal signal is output to the signal line for only the first time, one of them. It is determined that a predetermined abnormality has occurred in the switching element of the above, and when the abnormality signal is output to the signal line for longer than the first time, it is said that the other switching element has an abnormality due to the execution of the first process. judge. This makes it possible to determine whether or not an abnormality has occurred in the other switching element due to the execution of the first process.

It is a schematic block diagram of the electric vehicle 1 equipped with the abnormality determination device of the inverter of this embodiment. FIG. 3 is a schematic configuration diagram showing a configuration related to abnormality determination of the inverter in the vehicle of FIG. 1. It is a flowchart which shows an example of the abnormality determination processing routine executed by the microcomputer 11 (CPU) of the ECU 10. Explanatory drawing which shows an example of time change of the switching control signal of the upper and lower arm from the microcomputer 11, the gate signals UU, UL from ASIC12, and the abnormal signal when an abnormality occurs in the U phase upper arm Tr1 of an inverter 40. Is.

Next, an embodiment for carrying out the present invention will be described with reference to examples.

FIG. 1 is a schematic configuration diagram of an electric vehicle 1 equipped with an abnormality determination device for the inverter of this embodiment. The electric vehicle 1 includes a motor MG, a power storage device (battery) 2, a power control device (hereinafter referred to as “PCU”) 4, and an electronic control device (hereinafter referred to as “ECU”) 10 that controls the power control device 4. And include.

The motor MG is configured as a three-phase synchronous motor, is connected to the left and right drive wheels DW via a differential gear or the like, and exchanges electric power with the power storage device 2 via the PCU 4. The motor MG is driven by the electric power from the power storage device 2 to output the traveling torque to the drive wheel DW, and also outputs the regenerative braking torque to the drive wheel DW when braking the electric vehicle 1. Further, the motor MG is provided with a rotation angle sensor (resolver) 6 for detecting the rotation angle θ (rotation position) of the rotor. In the present embodiment, the power storage device 2 is a lithium ion secondary battery, a nickel hydrogen secondary battery, or a capacitor. As shown in the figure, the system main relay 3 has a positive electrode side relay connected to the positive electrode side power line PL and a negative electrode side relay connected to the negative electrode side power line NL.

The PCU 4 is connected to the power storage device 2 via the system main relay 3. The PCU 4 includes an inverter 40 which is an electronic circuit for driving a motor MG, a voltage conversion module (boost converter) 45 capable of stepping up the power from the power storage device 2 and stepping down the power from the motor MG, and a smoothing capacitor 46. And 47, a PCU case 4C and the like for accommodating them. It is controlled by the ECU 10. The inverter 40 is connected to six transistors (for example, insulated gate bipolar transistors (IGBTs)) Tr1, Tr2, Tr3, Tr4, Tr5 and Tr6 as switching elements in parallel in the opposite directions to the transistors Tr1 to Tr6. The two diodes D1, D2, D3, D4, D5 and D6 are included.

The six transistors Tr1 to Tr6 are paired with each other so as to be on the source side and the sink side with respect to the positive electrode side power line PL and the negative electrode side power line NL. Further, each of the three-phase coils (U-phase, V-phase, W-phase) of the motor MG is electrically connected to each of the connection points between the two paired transistors. The transistor Tr1 is an upper arm of a leg corresponding to the U phase of the motor MG (hereinafter referred to as “U phase leg”), and the transistor Tr2 is a lower arm of the U phase leg. Further, the transistor Tr3 is an upper arm of a leg corresponding to the V phase of the motor MG (hereinafter referred to as “V phase leg”), and the transistor Tr4 is a lower arm of the V phase leg. Further, the transistor Tr5 is an upper arm of a leg corresponding to the W phase of the motor MG (hereinafter referred to as “W phase leg”), and the transistor Tr6 is a lower arm of the W phase leg. Hereinafter, the transistor Tr1 is referred to as "U-phase upper arm Tr1" or "upper arm Tr1", the transistor Tr2 is referred to as "U-phase lower arm Tr2" or "lower arm Tr2", and the transistor Tr3 is referred to as "V-phase upper arm". The transistor Tr4 is referred to as "Tr3" or "upper arm Tr3", the transistor Tr4 is referred to as "V-phase lower arm Tr4" or "lower arm Tr4", and the transistor Tr5 is referred to as "W-phase upper arm Tr5" or "upper arm Tr5". Tr6 is referred to as "W phase lower arm Tr6" or "lower arm Tr6".

As shown in FIG. 2, the inverter 40 has a drive circuit 4u corresponding to the U-phase upper arm Tr1, a drive circuit 4ul corresponding to the U-phase lower arm Tr2, and a drive circuit 4vu and V-phase lower corresponding to the V-phase upper arm Tr3. It has a drive circuit 4vl corresponding to the arm Tr4, a drive circuit 4woo corresponding to the W phase upper arm Tr5, and a drive circuit 4wl corresponding to the W phase lower arm Tr6. Each drive circuit 4uu to 4wl includes a drive IC 41, a photocoupler 42 connected to the drive IC 41, and a photocoupler 44 connected to the drive IC via a MOS transistor 43. As shown, the optocouplers 44 of the drive circuits 4uu-4wl are incorporated in series with each other with respect to a single fail signal line FSL, one end of which is grounded and the other end of which is connected to the ECU 10. The fail signal line FSL is connected to a power supply (DC5V) via a pull-up resistor.

The drive IC 41 of each drive circuit 4uu to 4wl inputs a gate signal UU, UL, VU, VL, WU or WL from the ECU 10 via the photocoupler 42, and controls the corresponding transistors Tr1 to Tr6 on / off. Further, the drive IC 41 detects an abnormality related to the corresponding transistors Tr1 to Tr6, that is, an element abnormality such as a short circuit, an overcurrent, and a heating, and a circuit abnormality such as a voltage drop or an erroneous drive in the drive circuits 4uu to 4wl. Further, when the drive IC 41 of each drive circuit 4uu to 4wl detects an abnormality related to the corresponding transistors Tr1 to Tr6, the MOS transistor 43 is turned off for a predetermined output time, so that the fail signal line FSL is used for the output time. Output an abnormal signal. That is, when the MOS transistor 43 is turned off, no current flows through the diode of the corresponding photocoupler 44, so that the transistor of the photocoupler 44 connected to the fail signal line FSL is turned off. As a result, the voltage (5V) from the power supply is pulled up for the time when the MOS transistor 43 is turned off, that is, the output time, so that the logic of the fail signal line FSL is inverted and the drive circuit 4uu to 4wl side as the abnormality detection circuit side. An abnormal signal (Hi level signal) is output to the ECU 10 via the fail signal line FSL. Further, the drive IC 41 of each drive circuit 4u to 4 wl turns on the MOS transistor 43 for a predetermined output stop time after outputting an abnormal signal, and sets the fail signal line FSL to Lo level. Then, when the output stop time elapses, the MOS transistor 43 is controlled to be turned on / off, and a Hi-level pulse as a failure signal is output to the fail signal line FSL a predetermined number of times.

At least one of the above output time and output stop time is determined to be different between the upper arm Tr1, Tr3, Tr5 and the lower arm Tr2, Tr4, Tr6 in each of the U-phase leg, the V-phase leg, and the W-phase leg. Has been done. In this embodiment, when an abnormality occurs in at least one of the upper arms Tr1, Tr3, and Tr5, the output time of the abnormal signal is set to "T1f", the output stop time is set to "T1nf", and the lower arms Tr2, Tr4, and Tr6 are set. When the output time of the abnormal signal is "T2f" and the output stop time is "T2nf" when an abnormality related to at least one of It is defined to satisfy T1f <T2f and T1f + T1nf-T2f ≠ T2nf, and is the same for the U-phase leg, the V-phase leg, and the W-phase leg, respectively. Further, the number of times the pulse is output as a failure signal is set so as to be different between the U-phase leg, the V-phase leg, and the W-phase leg. In this embodiment, for example, the number of pulse outputs in the U-phase leg is 1, the number of pulse outputs in the V-phase leg is 3, and the number of pulse outputs in the W-phase leg is 5.

The voltage conversion module 45 includes, for example, two transistors which are insulated gate bipolar transistors (IGBTs), two diodes connected in parallel to each transistor in the opposite direction, and a reactor (both are not shown). .. Further, the smoothing capacitor 46 is installed between the system main relay 3 and the voltage conversion module 45, and smoothes the voltage on the power storage device 2 side of the voltage conversion module 45, that is, the voltage before boosting. Further, the smoothing capacitor 47 is installed between the voltage conversion module 45 and the inverter 40, and smoothes the boosted voltage VH boosted by the voltage conversion module 45.

The ECU 10 includes a microcomputer 11 (hereinafter referred to as “microcomputer”) 11 having an input / output interface including a CPU, ROM, RAM, timer input port 110, first and second general-purpose output ports 111, 112 (hereinafter referred to as “microcomputer”), ASIC 12 and the like (hereinafter referred to as “microcomputer”), which are not shown. include. The microcomputer 11 of the ECU 10 includes a rotation angle θ of the motor MG detected by the rotation angle sensor 6, a pre-boost voltage VL and a post-boost voltage VH detected by a voltage sensor (not shown), and a motor MG detected by a current sensor (not shown). Enter the value of the current (phase current) flowing through each phase. Based on these input signals, the microcomputer 11 generates a switching control signal (PWM signal) to the inverter 40 and the voltage conversion module 45 and outputs the switching control signal (PWM signal) to the ASIC 12 as a gate signal.

Further, the microcomputer 11 is connected to the fail signal line FSL, and when a signal is input from the fail signal line FSL, it is usually set to the Lo level within the time xx before the output time T1f or T2f falls. The first general-purpose output port 111 is switched to the Hi level, whereby a shutdown command is continuously given to the ASIC 12 until a predetermined time Tpref elapses from the input of the pulse as a failure signal at least regardless of the logic of the fail signal line FSL. Further, after identifying the failure phase and the failure location, the microcomputer 11 gives a shutdown release command to the ASIC 12 by switching the second general-purpose output port 112 to the Lo level. The timer input port 110 of the microcomputer 11 corresponds to the fail Hi duration TH, which is the input duration of the abnormal signal (Hi level signal) corresponding to the output times T1f, T2f, and the output stop times T1nf, T2nf of the abnormal signal. The fail Lo duration TL, which is the duration of the Lo level, is counted, and the number of times a pulse (rising edge) is input as a failure signal is counted.

The ASIC 12 includes an OR gate connected to the fail signal line FSL and the first general-purpose output port 111 of the microcomputer 11, and an AND gate connected to the OR gate and the second general-purpose output port 112 of the microcomputer 11, respectively. It has a plurality of (6) AND gates and a plurality of (6) MOS transistors corresponding to any of 4 wls. The ASIC 12 does not input an abnormal signal (Hi level signal) from the fail signal line FSL, and while the input from the first general-purpose output port 111 of the microcomputer 11 is at Lo level, the ASIC 12 gates the switching control signal from the microcomputer 11. Output as UU to WL. Further, the ASIC 12 inputs an abnormal signal and a failure signal from the fail signal line FSL, and turns off all the MOS transistors while the input from the first general-purpose output port 111 of the microcomputer 11 is at the Hi level, thereby turning off the inverter 40. Shut down. Further, when the ASIC 12 stops inputting the abnormality signal and the failure signal from the fail signal line FSL and the input from the second general-purpose output port 112 of the microcomputer 11 reaches the Lo level, the MOS corresponding to the switching control signal from the microcomputer 11. The transistor is turned on to cancel the shutdown of the inverter 40.

In the microcomputer 11 (CPU) of the ECU 10, which of the transistors Tr1 to Tr6 has an abnormality in the U-phase leg, the V-phase leg, or the W-phase leg based on the abnormality signal and the failure signal from the fail signal line FSL. To judge. The details of the abnormality determination will be described later. Then, the ECU 10 executes a fail-safe process according to the abnormality determination result. For example, if the two-phase leg of the U-phase leg, V-phase leg, and W-phase leg does not contain anomalously related transistors, the ECU 10 switches the second general-purpose output port 112 to Lo level. The electric vehicle 1 is retracted and traveled by switching and controlling the transistors of the two-phase legs. In this case, when the transistor related to the abnormality is off-failed, the electric vehicle 1 can be continuously driven by controlling the switching of the transistor of the two-phase leg. In addition, when the transistor related to the abnormality is on-failed, by turning on the upper arm or the lower arm of the above-mentioned two-phase leg, a so-called three-phase on state is formed and the current flowing through the motor MG is reduced. It is possible to suppress demagnetization of the motor MG.

Next, the operation of the electric vehicle 1 thus configured, particularly the operation when determining the abnormality of the inverter 40 will be described. FIG. 3 is a flowchart showing an example of an abnormality determination processing routine executed by the microcomputer 11 (CPU) of the ECU 10. This routine is executed by the microcomputer 11 of the ECU 10 when an abnormal signal is input from the fail signal line FSL.

When this routine is executed, the microcomputer 11 waits for a predetermined time Tref, which is sufficiently longer than the output time T2f of the abnormal signal output to the fail signal line FSL, to elapse after the execution of this routine is started. It is executed (step S100), and it is determined whether or not the abnormal signal output to the fail signal line FSL is normal (step S110). When the abnormal signal is normal, the Hi level continues for the fail Hi duration TH, which is the input duration of the abnormal signal (Hi level signal) corresponding to the output times T1f and T2f (T1f <T2f), and the abnormal signal is output. The Lo level continues for the fail Lo duration TL, which is the duration of the Lo level corresponding to the stop times T1nf and T2nf, and then the pulse (rising edge) as a failure signal is input a predetermined number of times. The predetermined time Tref is set to a predetermined time as the time at which the output of the pulse as a failure signal ends after the execution of this routine is started when the abnormal signal is normal. In step S100, when the output of the abnormal signal is stopped before the output time T1f elapses after the execution of this routine is started, some abnormality has occurred in the drive IC 41 of the drive circuits 4uu to 4wl, and the abnormal signal is normal. Judge that it is not. When it is determined that the abnormal signal is not normal, this routine is terminated.

When the abnormal signal is normal in step S100, the output from the first general-purpose output port 111 is set to the Lo level, and the output from the second general-purpose output port 112 is set to the Hi level, and the ASIC 12 is allowed to be driven (step S120). Since step S120 is a process after waiting for Tref to elapse for a predetermined time of the abnormal signal, the abnormal signal (Hi level signal) is not input from the fail signal line FSL.

Subsequently, a switching control signal for turning on the U-phase upper arm Tr1 of the inverter 40 once is generated and output to the ASIC 12 (step S130). The ASIC 12 to which the switching control signal to the U-phase upper arm Tr1 is input outputs the switching control signal from the microcomputer 11 as the gate signal UU. As a result, the U-phase upper arm Tr1 of the inverter 40 is switched and controlled.

Next, it is determined whether or not an abnormal signal from the fail signal line FSL has been input (step S140). When the abnormal signal from the fail signal line FSL is not input, it is determined that the U-phase upper arm Tr1 is normal, and the process proceeds to step S190.

When an abnormal signal from the fail signal line FSL is input in step S140, a switching control signal for turning on the U-phase lower arm Tr2 of the inverter 40 once is generated in the ASIC 12 before the fail Hi duration TH elapses. Output (step S150). The ASIC 12 to which the switching control signal to the U-phase upper arm Tr2 is input outputs the switching control signal from the microcomputer 11 as the gate signal UL. As a result, the U-phase lower arm Tr2 of the inverter 40 is switched and controlled.

Subsequently, it is determined whether or not the fail Hi duration TH of the abnormal signal exceeds the output time T1f (step S160). FIG. 4 shows an example of time changes of the switching control signals of the upper and lower arms from the microcomputer 11, the gate signals UU and Ul from the ASIC 12, and the abnormal signals when the U-phase upper arm Tr1 of the inverter 40 has an abnormality. It is explanatory drawing which shows. In the figure, as a comparative example, an example of a time change of an abnormal signal when no abnormality has occurred in the U-phase upper arm Tr1 of the inverter 40 is shown. As for the abnormality signal, when an abnormality has occurred in the U-phase upper arm Tr1 of the inverter 40, the Hi level continues for the fail Hi duration TH (output time T1f) as shown in the figure, and then the fail Lo duration TL ( The Lo level continues for the output stop time T1nf), and a pulse (rising edge) as a failure signal is input once. If the U-phase upper arm Tr1 is turned on once and the U-phase upper arm Tr2 is turned on before the fail Hi duration TH has elapsed, an abnormal signal is not output when the U-phase lower arm Tr2 is normal, so the fail Hi The duration TH is the output time T1f. For example, when the U-phase upper arm Tr1 is overcurrent and the U-phase upper arm Tr1 is short-circuited to output an abnormal signal, when the U-phase lower arm Tr2 is turned on, the U-phase upper and lower arms Tr1 and Tr2 are short-circuited. , A new abnormality may occur in the U-phase lower arm Tr2. When an abnormality occurs in the U-phase lower arm Tr2 in this way, an abnormal signal having a fail Hi duration TH and an output time T2f is output, so that the abnormal signal continues to be at the Hi level. Therefore, step S160 is a process of determining whether or not a new abnormality has occurred in the U-phase lower arm Tr2 by outputting a switching control signal in order to determine the abnormality of the U-phase upper arm Tr1 of the inverter 40 in step S130. It has become.

When the fail Hi duration TH of the abnormal signal does not exceed the output time T1f in step S160, that is, when the fail Hi duration TH is equal to the output time T1f, an abnormality has occurred in the U-phase upper arm Tr1 of the inverter 40 (when the fail Hi duration TH is equal to the output time T1f). When it is determined that no new abnormality has occurred in the U-phase lower arm Tr2) and the fail Hi duration TH of the abnormal signal is longer than the output time T1f in step S160, the U-phase upper arm Tr1 of the inverter 40 is set in step S130. It is determined whether an abnormality has occurred in the U-phase lower arm Tr2 by outputting a switching control signal to determine an abnormality, or an abnormality has occurred in the U-phase lower arm Tr2 by turning on the U-phase upper arm Tr1 of the inverter 40. (Step S180), the process proceeds to step S190.

In the processes of steps S190 to S240, the U-phase upper arm Tr1 is the U-phase lower arm Tr2 and the U-phase lower arm Tr1 is the U-phase upper arm Tr1 in the processes of steps S130 to S180. In the process of step S190, a switching control signal for turning on the U-phase lower arm Tr2 of the inverter 40 once is generated and output to the ASIC 12 (step S190). The ASIC 12 to which the switching control signal to the U-phase lower arm Tr2 is input outputs the switching control signal from the microcomputer 11 as the gate signal UL. As a result, the U-phase lower arm Tr2 of the inverter 40 is switched and controlled.

Next, it is determined whether or not an abnormal signal from the fail signal line FSL has been input (step S200). When the abnormal signal from the fail signal line FSL is not input, it is determined that the U-phase lower arm Tr2 is normal, and the processing (not shown) after step S250 is executed.

When an abnormal signal from the fail signal line FSL is input in step S200, a switching control signal for turning on the U-phase upper arm Tr1 of the inverter 40 once is generated in the ASIC 12 before the fail Hi duration TH elapses. Output (step S210). The ASIC 12 to which the switching control signal to the U-phase upper arm Tr1 is input outputs the switching control signal from the microcomputer 11 as the gate signal UU. As a result, the U-phase lower arm Tr2 of the inverter 40 is switched and controlled.

Subsequently, it is determined whether or not the fail Hi duration TH of the abnormal signal exceeds the output time T2f (step S220). In step S220, as in the process of step S160 described above, a switching control signal is output in step S190 to determine an abnormality in the U-phase lower arm Tr2 of the inverter 40, so that a new abnormality is found in the U-phase upper arm Tr1. It is a process of determining whether or not it has occurred.

When the fail Hi duration TH of the abnormal signal does not exceed the output time T2f in step S220, that is, when the fail Hi duration TH is equal to the output time T2f, an abnormality has occurred in the U-phase lower arm Tr2 of the inverter 40 (when the fail Hi duration TH is equal to the output time T2f). It is determined that no new abnormality has occurred in the U-phase upper arm Tr1) (step S230), and when the fail Hi duration TH of the abnormal signal is longer than the output time T2f in step S220, the U phase of the inverter 40 is determined in step S190. By outputting a switching control signal to determine the abnormality of the lower arm Tr2, it is determined that a new abnormality has occurred in the U-phase upper arm Tr1 (step S240). From such a process, it is possible to determine whether or not a new abnormality has occurred in the U-phase upper arm Tr1 by outputting a switching control signal in order to determine an abnormality in the U-phase lower arm Tr2 of the inverter 40 in step S190. ..

When it is determined in this way whether or not an abnormality has occurred in the U-phase upper and lower arms Tr1 and Tr2 of the inverter 40, subsequently, in the subsequent processing (not shown) of step S250, the V-phase and W-phase of the inverter 40 are described in step S130. This routine is terminated by applying the same processing as in S240. By such processing, for each phase of the inverter 40, it is possible to determine whether or not an abnormality has occurred in the other switching element due to the processing of outputting the switching control signal to one of the two switching elements of the upper and lower arms. can.

In the electric vehicle 1 equipped with the abnormality determination device of the inverter 40 of the above-described embodiment, the first process of outputting a switching control signal to one of the two switching elements of the upper and lower arms for each leg (1st process). Steps S130, S190, etc.) and the second process (steps S150, S210) that outputs a control signal to the other switching element of the switching elements of the upper and lower arms are executed in order, and the fail signal line FSL is executed during that period. When the abnormal signal is output only for the fail Hi duration TH, it is determined that a predetermined abnormality has occurred in one of the switching elements, and the abnormal signal is output to the fail signal line FSL longer than the fail Hi duration TH. If so, it is determined that an abnormality has occurred in the other switching element due to the execution of the first process. This makes it possible to determine whether or not an abnormality has occurred in the other switching element due to the execution of the first process.

The correspondence between the main elements of the embodiment and the main elements of the invention described in the column of means for solving the problem will be described. In the embodiment, the drive IC 41 of the drive circuits 4u to 4 wl corresponds to the "plurality of drive circuits", and the ECU 10 corresponds to the "determination device".

As for the correspondence between the main elements of the examples and the main elements of the invention described in the column of means for solving the problem, the invention described in the column of means for solving the problems of the examples is carried out. Since it is an example for specifically explaining the form for solving the problem, the elements of the invention described in the column of means for solving the problem are not limited. That is, the interpretation of the invention described in the column of means for solving the problem should be performed based on the description in the column, and the examples are the inventions described in the column of means for solving the problem. It is just a concrete example.

Although the embodiments for carrying out the present invention have been described above with reference to the embodiments, the present invention is not limited to these embodiments and may be in various embodiments within the scope of the gist of the present invention. Of course it can be done.

INDUSTRIAL APPLICABILITY The present invention can be used in the manufacturing industry of an abnormality determination device for an inverter.

1 Electric vehicle, 2 Power storage device, 3 System main relay, 4 Power control device (PCU), 4C PCU case, 4uu, 4vu, 4woo, 4ul, 4vl, 4wl drive circuit, 6 rotation angle sensor, 10 electronic control device (ECU) ), 11 Microcomputer (microcomputer), 12 ASIC, 40 Inverter, 41 Drive IC, 42,44 Photocoupler, 43 MOS transistor, 45 Voltage conversion module, 46,47 Smoothing capacitor, 110 Timer input port, 111 First general-purpose output Port, 112 2nd general-purpose output port, D1, D2, D3, D4, D5, D6 diode, DW drive wheel, FSL fail signal line, MG motor generator, PL positive side power line, NL negative side power line, Tr1, Tr2 , Tr3, Tr4, Tr5, Tr6 Transistor, UU, UL, VU, VL, WU, WL Gate signal.

Claims (1)

An inverter abnormality determination device having a plurality of legs including an upper arm switching element and a lower arm switching element.
When the corresponding switching element is driven by using the input drive signal provided for each switching element and a predetermined abnormality of the corresponding switching element is detected, an abnormality signal is previously transmitted to a single signal line. Multiple drive circuits that output only the specified output time,
A determination device that outputs the drive signal to the plurality of drive circuits and determines the type of abnormality of the switching element based on the abnormality signal output to the signal line.
Equipped with
The determination device is
For each leg, a determination process for determining the type of abnormality of the switching element is executed.
The determination process is
The first process of outputting the drive signal to one of the switching elements of the upper arm switching element and the lower arm switching element is executed.
When the abnormal signal is input by executing the first process, the other switching element of the switching element of the upper arm and the switching element of the lower arm while the input of the abnormal signal continues. The second process of outputting the drive signal is executed.
When the abnormal signal is output to the signal line for the output time, it is determined that the predetermined abnormality has occurred in one of the switching elements, and the abnormal signal is output to the signal line longer than the output time. When it is, it is determined that an abnormality has occurred in the other switching element due to the execution of the first process.
Inverter abnormality judgment device.

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