JP6983570B2 - Manufacturing method of semiconductor laminate, manufacturing method of nitride semiconductor self-supporting substrate, semiconductor laminate and semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor laminate, a method for manufacturing a nitride semiconductor self-standing substrate, a semiconductor laminate, and a semiconductor device.

Group III nitride semiconductors are widely used as materials for constituting semiconductor devices such as light emitting devices and electronic devices. In order to improve the quality (semiconductor characteristics, etc.) of semiconductor devices composed of group III nitride semiconductors, semiconductor laminates or nitride semiconductor self-standing substrates for manufacturing semiconductor devices shall be manufactured so that the crystal quality is good. Is desired.

As a method for manufacturing a nitride semiconductor self-supporting substrate, for example, a step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the substrate and a step of manufacturing a nitride semiconductor self-supporting substrate by slicing the semiconductor layer. , Is known (for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2008-156189

In recent years, it has been desired to manufacture semiconductor laminates, nitride semiconductor self-standing substrates or semiconductor devices having better crystal quality than conventional methods.

An object of the present invention is to provide a technique capable of manufacturing a semiconductor laminate having good crystal quality, a nitride semiconductor self-standing substrate, or a semiconductor device.

According to one aspect of the invention
A process of preparing a substrate that is housed in a substrate container made of an organic resin material and whose surface layer is at least a group III nitride semiconductor.
A step of putting the substrate into a predetermined processing chamber from the substrate accommodating body and etching at least the entire surface of the surface layer of the substrate in a gas phase in the processing chamber over a predetermined thickness or more.
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the substrate by a vapor phase growth method.
Have,
In the etching step,
A method for producing a semiconductor laminate in which adhering impurities adhering to the surface of the substrate due to the substrate container in the step of preparing the substrate are removed together with at least the group III nitride semiconductor constituting the surface layer of the substrate. , And related techniques are provided.

According to the present invention, it is possible to manufacture a semiconductor laminate having good crystal quality, a nitride semiconductor self-standing substrate, or a semiconductor device.

It is a flowchart which shows the manufacturing method of the semiconductor laminate or the manufacturing method of a nitride semiconductor self-supporting substrate which concerns on 1st Embodiment of this invention. (A) is a schematic cross-sectional view showing a substrate, (b) is a schematic cross-sectional view showing a substrate accommodated in a substrate accommodating body in a substrate preparation process, and (c) is a substrate in a substrate preparation process. It is a schematic enlarged sectional view which shows. It is a schematic block diagram of the vapor phase growth apparatus used in the manufacturing method which concerns on 1st Embodiment of this invention. It is a figure which shows the temperature change of the substrate from the etching process to the vapor phase growth process of 1st Embodiment of this invention. (A) is a schematic cross-sectional view showing a substrate in the etching step, and (b) is a schematic cross-sectional view showing the substrate after the etching step. (A) is a schematic cross-sectional view showing a semiconductor laminate in a vapor phase growth step, and (b) is a schematic cross-sectional view showing a nitride semiconductor self-standing substrate produced in a slicing step. It is a flowchart which shows the manufacturing method of the semiconductor laminate or the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. (A) is a schematic cross-sectional view showing a semiconductor laminate according to the second embodiment of the present invention, and (b) is a schematic cross-sectional view showing a semiconductor device according to the second embodiment of the present invention. (A) is a schematic cross-sectional view showing a semiconductor laminate according to a modified example of the second embodiment of the present invention, and (b) is a schematic showing a semiconductor device according to a modified example of the second embodiment of the present invention. It is a cross-sectional view. (A) is an SEM image showing an example of the adhered impurities, and (b) is the result of performing EDX analysis of the adhered impurities of (a). It is a figure which shows the Si concentration of the substrate surface measured by the total reflection fluorescent X-ray analysis with respect to the storage days which the substrate was stored in the substrate containing body. (A) is a photograph showing the appearance of the semiconductor laminate of the example, and (b) is a photograph showing the appearance of the semiconductor laminate of the comparative example. (A) to (c) are diagrams showing pits and morphology abnormal parts on the surface of the semiconductor laminate of the comparative example.

<Findings obtained by the inventor, etc.>
First, the findings obtained by the inventors will be described.

In the case of manufacturing a semiconductor laminate, a nitride semiconductor self-supporting substrate, or a semiconductor device using a substrate contained in a substrate housing made of an organic resin material, the inventors and others have diligently studied the semiconductor laminate. , Nitride semiconductor It has been found that the quality of self-supporting substrates or semiconductor devices may deteriorate.

When the substrate is housed in the substrate container made of an organic resin material for a long period of time, adherent impurities may adhere to the surface of the substrate due to the substrate container. Specifically, the substrate accommodating body is made of, for example, polypropylene (PP) or the like. When the substrate container is manufactured, an additive such as a stabilizer (antioxidant, light stabilizer, etc.) is added to the pellet of the resin composition as a precursor. In addition, a mold release agent is applied to the surface of the mold during mold molding. The mold release agent may be added as an additive in the resin composition. Such additives and the like may remain in the substrate containing body even after the substrate containing body is manufactured (molded). Therefore, when the substrate is housed in the substrate housing for a long time, the additive or the like becomes outgas and is released from the substrate housing, and the adhered impurities adhere to the surface of the substrate.

It is often not disclosed as the manufacturer's know-how what kind of additive or the like was used when manufacturing the substrate container, and the user of the substrate container specifies a detailed type of the additive or the like. I can't. Therefore, even if there is a possibility that the adhered impurities adhere to the substrate, it is not known what kind of material the adhered impurities adhere to the substrate, and the adhered impurities are removed by what method and conditions. I didn't know what to do. Further, since the amount of additives and the like remaining on the substrate container may differ depending on the lot in which the substrate container is manufactured, it is difficult to grasp the amount of adhered impurities adhering to the substrate. Further, since such adhered impurities adhere with a thickness of one to several monolayers, they cannot be found even when the substrate is observed with an optical microscope or the like, and the adhered position and the adhered range in a plan view can be determined. Could not be identified. For the above reasons, it has been difficult to directly remove the adhered impurities adhering to the substrate before manufacturing the semiconductor laminate or the like.

Even when the substrate is washed with a predetermined solvent, adherent impurities may adhere to the surface of the substrate and remain. Even when cleaning is the cause, it is not known what kind of material impurities are attached to the substrate. Therefore, the semiconductor laminate or the like is manufactured in the same manner as in the case of the above-mentioned substrate accommodating body. Previously, it was difficult to directly remove the adherent impurities adhering to the substrate.

When a semiconductor layer is epitaxially grown on a substrate to which such adhered impurities are adhered by a vapor phase growth method, pits and morphology abnormal parts may be generated at positions on the surface of the semiconductor layer where the adhered impurities overlap. There is. The pits and morphology abnormal parts may be caused by an inversion domain (ID: Version Domain) whose polarity is reversed with respect to other regions of the semiconductor layer. When pits or morphology abnormal portions are generated on the surface of the semiconductor layer, the oxygen (O) concentration becomes high in faceted growth zones other than the c-plane, such as pit slopes and slopes of morphology abnormal portions. In the portion where the O concentration is high, the carrier concentration is relatively higher than in the other portions, and the resistance is locally lowered. If a portion having a low resistance locally is generated in the semiconductor layer in this way, the characteristics of the semiconductor device may vary in the plane.

Further, when the semiconductor layer is epitaxially grown on the substrate on which the adhered impurities are adhered by the vapor phase growth method, there is a possibility that a non-growth region in which the semiconductor layer is not grown is formed on the adhered impurities. In this case, when the nitride semiconductor self-supporting substrate is produced by slicing the semiconductor layer, a through hole is formed at a position corresponding to the non-growth region of the semiconductor layer in the nitride semiconductor self-supporting substrate. If through holes are formed in the nitride semiconductor self-supporting substrate, various problems may occur in the process of manufacturing a semiconductor device using the nitride semiconductor self-supporting substrate. Specifically, for example, when a semiconductor layer is epitaxially grown on a nitride semiconductor self-supporting substrate, parasitic growth may occur due to through holes, which may contaminate the growth furnace. Further, for example, there is a possibility that the nitride semiconductor self-supporting substrate cannot be conveyed by vacuum suction. Further, for example, when a resist film is formed on a nitride semiconductor self-supporting substrate by a spin coating method or the like, a resist liquid is sucked into the nitride semiconductor self-supporting substrate through a through hole, or a pump for vacuum adsorption is inserted through a hole. There is a possibility that the pump may break down by sucking in the resist liquid through the device.

Further, when a large amount of adhered impurities adhere to the substrate, outgas may be generated from the adhered impurities. Therefore, there is a possibility that a large amount of impurities (impurity elements such as O) may be incorporated into the semiconductor layer or many crystal defects may be formed in the semiconductor layer due to the outgas derived from the adhered impurities. be.

The present invention described below is based on the above-mentioned new problems found by the present inventors.

<First Embodiment of the present invention>
Hereinafter, the first embodiment of the present invention will be described with reference to the drawings.

(1) Method for manufacturing semiconductor laminate or method for manufacturing nitride semiconductor self-supporting substrate With reference to FIGS. 1 to 6, a method for manufacturing a semiconductor laminate or a method for manufacturing a nitride semiconductor self-supporting substrate according to the present embodiment will be described. FIG. 1 is a flowchart showing a method for manufacturing a semiconductor laminate or a method for manufacturing a nitride semiconductor self-standing substrate according to the present embodiment. The step is abbreviated as S. 2A is a schematic cross-sectional view showing a substrate, FIG. 2B is a schematic cross-sectional view showing a substrate accommodated in a substrate accommodating body in a substrate preparation step, and FIG. 2C is a schematic cross-sectional view showing a substrate in a substrate preparation step. It is a schematic enlarged sectional view which shows the substrate of. FIG. 3 is a schematic configuration diagram of a vapor phase growth apparatus used in the manufacturing method according to the present embodiment. FIG. 4 is a diagram showing the temperature change of the substrate from the etching process to the vapor phase growth process of the present embodiment. FIG. 5A is a schematic cross-sectional view showing a substrate in the etching step, and FIG. 5B is a schematic cross-sectional view showing the substrate after the etching step. FIG. 6A is a schematic cross-sectional view showing a semiconductor laminate in the vapor phase growth step, and FIG. 6B is a schematic cross-sectional view showing a nitride semiconductor self-standing substrate produced in the slicing step.

In the following, in the various substrates used in the present embodiment, the upper main surface (first main surface, upper surface) is referred to as "front surface", and the lower main surface (second main surface, lower surface) is referred to as "back surface". ..

In the present embodiment, a case where, for example, a semiconductor laminate 1 made of gallium nitride (GaN) or a nitride semiconductor self-supporting substrate (hereinafter, also simply referred to as a self-supporting substrate) 2 is manufactured as a group III nitride semiconductor will be described.

(S120: Substrate preparation process)
First, a substrate preparation step S120 for preparing a substrate (base substrate, seed crystal substrate) 10 whose surface layer is at least a group III nitride semiconductor is performed.

The substrate 10 shown in FIG. 2A is configured as, for example, a group III nitride semiconductor self-standing substrate or a group III nitride semiconductor template. Here, the substrate 10 is, for example, a GaN free-standing substrate manufactured by the vapor phase growth method.

The substrate 10 has a front surface 10a as a crystal growth surface and a back surface 10b opposite to the front surface 10a. The surface 10a of the substrate 10 is, for example, a (0001) plane (+ C plane, Ga polar plane) or a plane having a predetermined off angle with respect to the (0001) plane. The size of the off angle (off amount) is, for example, within 2 °. The dislocation density (average dislocation density) on the surface 10a of the substrate 10 is, for example, 1 × 10 ³ pieces / cm ² or more and 1 × 10 ⁷ pieces / cm ² or less.

At this time, as shown in FIG. 2B, the substrate 10 is housed in, for example, a substrate container 200 made of an organic resin material. Examples of the resin material constituting the substrate container 200 include polypropylene (PP), polycarbonate (PC), polytetrafluoroethylene (PTFE), perfluoroalkoxy alkane (PFA), and the like. Here, the substrate accommodating body 200 is made of, for example, PP.

In the present embodiment, the substrate accommodating body 200 accommodating the substrate 10 is configured as, for example, a so-called wafer tray. Specifically, the substrate accommodating body 200 has, for example, a tray main body portion 210, a lid portion 220, and a spring portion 230. The tray main body 210 has, for example, a curved concave portion (not shown). The lid portion 220 is screwed (engaged) with the tray main body portion 210 to seal the tray main body portion 210. The spring portion 230 is a curved plate-shaped member.

When accommodating the substrate 10 in the substrate accommodating body 200, first, the substrate 10 is placed in the recess of the tray main body 210 so that the surface 10a of the substrate 10 faces the recess of the tray main body 210. After the substrate 10 is placed on the tray main body 210, the spring portion 230 is interposed between the back surface 10b of the substrate 10 and the lid portion 220, and the lid portion 220 is screwed with the tray main body portion 210. As a result, the substrate 10 can be accommodated in the space between the tray main body 210 and the lid 220. Further, by pressing the substrate 10 against the recess of the tray main body 210 by the spring portion 230, the displacement of the substrate 10 can be suppressed.

The substrate 10 is stored in the substrate accommodating body 200 for a predetermined period until the semiconductor laminate 1 or the self-supporting substrate 2 is manufactured. When a large number of substrates 10 used for manufacturing the semiconductor laminate 1 or the self-supporting substrate 2 are prepared, the accommodation period of the substrate 10 may be long. Here, the substrate 10 is accommodated in the substrate accommodating body 200 for, for example, at least 12 hours or more.

In this way, when the substrate is housed in the organic substrate container 200 for a long period of time, as shown in FIG. 2C, the adhered impurities 20 adhere to the surface 10a of the substrate 10 due to the substrate container 200. Sometimes. Specifically, for example, additives and the like remaining in the substrate container 200 may become outgas and be released from the substrate container 200, and the adhered impurities 20 may adhere to the surface 10a of the substrate 10. For example, when a mold release agent is used in manufacturing the substrate container 200, the adhered impurity 20 contains, for example, at least siloxane. The thickness of the adhered impurities 20 is, for example, one to several monolayers.

As described above, when the accommodating period of the substrate 10 in the substrate accommodating body 200 becomes long, the adhered impurities 20 tend to adhere to the surface 10a of the substrate 10. In particular, when the accommodating period of the substrate 10 in the substrate accommodating body 200 is 12 hours or more as described above, the tendency becomes remarkable.

Further, particularly when the substrate accommodating body 200 is configured as the wafer tray as described above, since the surface 10a of the substrate 10 is close to the recess of the tray main body 210, the adhered impurities 20 as described above are present on the substrate 10. It is easy to adhere to the surface 10a of.

As described above, once the adhered impurities 20 adhere to the surface 10a of the substrate 10, it is difficult to directly remove the adhered impurities 20. This is because, as described above, the detailed type of the additive or the like of the substrate accommodating body 200 that caused the adhered impurity 20 is not disclosed as the manufacturer's know-how and cannot be specified, so that the material of the adhered impurity 20 is used. In many cases, it is unknown, or the method or conditions for removing the adhered impurities 20 are unknown. Therefore, it is difficult to directly remove the adhered impurities 20 adhering to the substrate 10. Further, such adhered impurities 20 may be firmly adhered to the surface 10a of the substrate 10. Therefore, once the adhered impurities 20 are adhered, it is difficult to remove the adhered impurities 20 even if they are washed with a predetermined solvent or the like. In particular, when the adhered impurity 20 contains siloxane, it is known that the adhered impurity 20 tends to remain on the surface 10a of the substrate 10.

Therefore, in the present embodiment, the following etching step S140 is performed before the vapor phase growth step S160.

(S140: Etching process)
In the present embodiment, for example, the vapor phase growth apparatus 400 shown in FIG. 3 is used to perform an etching step S140 for etching the surface 10a of the substrate 10 in the vapor phase.

The vapor phase growth apparatus 400 is configured as, for example, a hydride vapor phase growth apparatus (HVPE apparatus). The vapor phase growth apparatus 400 is made of a heat-resistant material such as quartz, and includes an airtight container 403 having a processing chamber 401 inside. A susceptor 408 for holding the substrate 10 is provided in the processing chamber 401. The susceptor 408 is connected to the rotation shaft 415 of the rotation mechanism 416, and the substrate 10 mounted on the susceptor 408 is configured to be rotatable in the circumferential direction (direction along the upper surface). At one end of the airtight container 403, a gas supply pipe 432a for supplying hydrogen chloride (HCl) gas into the gas generator 433a described later, and a gas for supplying ammonia (NH ₃ ) gas as a film forming gas into the processing chamber 401. A gas supply pipe 432b for supplying an HCl gas as an etching gas into the supply pipe 432b and the processing chamber 401 are connected to each other. The gas supply pipe 432a~432c, in addition to HCl gas and NH ₃ gas, carrier gas or hydrogen as an etching gas _{(H 2)} gas, and an inert gas, nitrogen as a carrier gas or a purge gas _{(N 2} ) It is also configured to be able to supply gas. The gas supply pipes 432a to 432c are provided with a flow rate controller and a valve (neither of which is shown) for each of these gas types, and the flow rate control and supply start / stop of various gases are individually performed for each gas type. It is configured so that it can be done. A gas generator 433a for accommodating a Ga melt as a raw material is provided downstream of the gas supply pipe 432a. The gas generator 433a has a nozzle 449a that supplies gallium chloride (GaCl) gas as a film-forming gas generated by the reaction of HCl gas and Ga melt toward the substrate 10 held on the susceptor 408. It is connected. On the downstream side of the gas supply pipes 432b and 432c, nozzles 449b and 449c that supply the gas supplied from these gas supply pipes toward the substrate 10 held on the susceptor 408 are connected, respectively. The nozzles 449a to 449c are arranged so as to allow gas to flow in a direction parallel to the upper surface of the substrate 10 (direction along the upper surface). On the other hand, at the other end of the airtight container 403, an exhaust pipe 430 for exhausting the inside of the processing chamber 401 is provided. The exhaust pipe 430 is provided with a pump 431 via a pressure regulator (APC) 429. A zone heater 407 that heats the substrate 10 held in the gas generator 433a or the susceptor 408 to a desired temperature is provided on the outer periphery of the airtight container 403, and the temperature in the processing chamber 401 is measured in the airtight container 403. Sensors 409 are provided respectively. Each member included in the vapor phase growth apparatus 400 is connected to a controller 480 configured as a computer, and is configured so that a processing procedure and processing conditions described later are controlled by a program executed on the controller 480. There is.

The etching step S140 can be carried out by using the above-mentioned vapor phase growth apparatus 400, for example, by the following processing procedure.

First, the substrate 10 is taken out from the substrate accommodating body 200. After taking out the substrate 10, the substrate 10 is put into (carried in) into the airtight container 403 (processing chamber 401) and held on the susceptor 408. At this time, the Ga melt as a raw material used in the vapor phase growth step S160 described later is housed in the gas generator 433a. Then, from at least one of the gas supply pipe 432a~432c into the process chamber 401 to supply _{N 2} gas, to implement the heating and evacuation of the processing chamber 401. At this time, the rotation of the susceptor 408 also starts.

As shown in FIG. 4, the temperature of the substrate 10 gradually rises due to the heating in the processing chamber 401. When the temperature of the substrate 10 reaches the predetermined temperature Te and the pressure in the processing chamber 401 reaches the predetermined pressure, the predetermined etching gas is supplied to the upper surface of the substrate 10.

As a result, as shown in FIG. 5A, the entire surface of the surface 10a of the substrate 10 can be etched in the gas phase over a predetermined thickness (depth) or more. At this time, the portion of the substrate 10 to be etched is a portion that is exposed to the outer atmosphere of the substrate 10 and can come into contact with the outer atmosphere (for example, etching gas). Not only the surface 10a of the substrate 10 but also the side surface of the substrate 10 will be etched.

At this time, as shown in FIG. 5A, the adhered impurities 20 adhering to the surface 10a of the substrate 10 in the substrate preparation step S120 are removed together with the GaN constituting the matrix of the substrate 10. That is, the etching gas supplied to the surface 10a of the substrate 10 immediately spreads to the exposed portion of the surface 10a of the substrate 10 and etches the exposed portion. At this time, the adhered impurities 20 adhering to the surface 10a of the substrate 10 do not have to be etched by the etching gas. As the etching of the exposed portion of the surface 10a of the substrate 10 progresses, the etching gas also enters between the surface 10a of the substrate 10 and the adhered impurities 20. When all the portions of the surface 10a of the substrate 10 in contact with the adhered impurities 20 are etched, the adhered impurities 20 are peeled off from the surface 10a of the substrate 10. The peeled adherent impurities 20 are removed (discharged) to the outside of the substrate 10 according to the flow of the etching gas with respect to the surface 10a of the substrate 10. In this way, the adhered impurities 20 adhering to the surface 10a of the substrate 10 can be removed together with the GaN constituting the matrix of the substrate 10.

In the above process of removing the adhered impurities 20 together with the matrix of the substrate 10, it is considered that the adhered impurities 20 are removed together with the GaN by a principle similar to the so-called "lift-off" used for patterning a metal film or the like in the semiconductor process. You may.

At this time, etching is performed for at least 1 hour or more while maintaining the temperature of the substrate 10 at a predetermined temperature. If the etching time is less than 1 hour, the surface 10a of the substrate 10 may not be sufficiently etched. Therefore, the adhered impurities 20 may remain on the non-etched portion on the surface 10a of the substrate 10. On the other hand, by setting the etching time to 1 hour or more, the entire surface of the surface 10a of the substrate 10 can be reliably etched over a predetermined thickness or more. As a result, no matter where the adhered impurities 20 are attached on the surface 10a of the substrate 10, the adhered impurities 20 can be removed together with the matrix of the substrate 10.

At this time, the surface 10a of the substrate 10 is etched at least by 10 nm or more in the depth direction. If the etching depth is less than 10 nm, a portion where the etching gas does not enter is generated between the surface 10a of the substrate 10 and the adhered impurities 20, and the adhered impurities 20 may remain on the surface 10a of the substrate 10. be. On the other hand, by setting the etching depth to 10 nm or more, the etching gas is sufficiently allowed to enter between the surface 10a of the substrate 10 and the adhered impurities 20, and the portion of the surface 10a of the substrate 10 in contact with the adhered impurities 20 is formed. It can be reliably removed. As a result, the adhered impurities 20 can be reliably removed together with the matrix of the substrate 10.

At this time, the surface 10a of the substrate 10 is etched under the condition that the region of the surface 10a of the substrate 10 excluding the crystal defect portion is smooth. The "crystal defect portion" of the substrate 10 here means dislocations, pits, and the like. Further, the "condition in which the region of the surface 10a of the substrate 10 excluding the crystal defect portion is smooth" is the region of the surface 10a of the substrate 10 excluding the crystal defect portion, that is, does not include the etching pit. When compared in a visual field (for example, a 1 μm square visual field), the difference between the surface roughness before the etching step S140 (arithmetic mean roughness Ra) and the surface roughness after the etching step S140 is within 10 nm, preferably within 5 nm. It is a condition that becomes. By keeping the surface 10a of the substrate 10 smooth under such mild etching conditions, the semiconductor layer 40 can be smoothly epitaxially grown on the surface 10a of the substrate 10 in the vapor phase growth step S160 described later.

As shown in FIG. 5B, even when etching is performed under the above conditions, the surface 10a of the substrate 10 has an etch pit 10ep corresponding to dislocations as crystal defects in the substrate 10. Can appear.

Specific etching conditions, for example, etched in an atmosphere containing HCl gas and H ₂ gas as the etching gas. For example, with respect to the surface 10a of the substrate 10 from the gas supply pipe 432c, and supplies the HCl gas and _{H 2} gas as the etching gas. By etching in an atmosphere containing HCl gas, the GaN constituting the substrate 10 can be etched by the following reaction formula (1).
2GaN + 2HCl → 2GaCl + H ₂ + N ₂ ... (1)
At this time, Ga droplets may be generated as a by-product of a reaction other than the reaction formula (1). Here, since the mild etching conditions are applied as described above, the above-mentioned Ga droplets are likely to occur. _{Therefore, by etching in an atmosphere containing H 2} gas in addition to HCl gas, Ga droplet as a by-product can be vaporized and removed as _{galan (GaH 3) which is a hydride of Ga.} ..

Further, for example, in addition to the above-mentioned HCl gas and H ₂ gas as etching gas, etching is performed in an atmosphere containing _{N 2} gas as an inert gas (diluting gas), _{and the partial pressure of N 2} gas is divided into HCl gas and H 2 gas. H ₂ higher than the respective partial pressures of the gas. As a result, the surface 10a of the substrate 10 can be mildly etched, and the region of the surface 10a of the substrate 10 excluding the crystal defect portion can be kept smooth.

At this time, the ratio of the partial pressures of the HCl gas and the H _{2 gas to the partial pressure of the N 2} gas (partial pressure ratio) is, for example, 1% or more and 10% or less. If the partial pressure ratio is less than 1%, the etching rate of the GaN constituting the substrate 10 becomes low, so that the time until the adhered impurities 20 are removed may become excessively long. On the other hand, by setting the partial pressure ratio to 1% or more, the etching rate of the GaN constituting the substrate 10 is secured to a predetermined value or more, and the lengthening of the time until the adhered impurities 20 are removed is suppressed. Can be done. On the other hand, if the voltage division ratio is more than 10%, the GaN constituting the substrate 10 is excessively etched, so that the surface 10a of the substrate 10 may be roughened. On the other hand, by setting the partial pressure ratio to 10% or less, the surface 10a of the substrate 10 can be mildly etched, and the region of the surface 10a of the substrate 10 excluding the crystal defect portion can be kept smooth.

Further, for example, etching is performed in an atmosphere free of _{NH 3 gas.} When etching is performed in an atmosphere containing _{NH 3} gas, Ga-containing gas (GaCl or GaH _{3 ) generated by the reaction of GaN constituting the substrate 10 with each of HCl gas and H 2} gas, and NH ₃ gas Reacts and GaN re-grows on the surface 10a of the substrate 10. Since the regrown GaN is formed in an irregular shape, the surface 10a of the substrate 10 may be roughened. In contrast, by performing the etching in an atmosphere which is a non-containing NH ₃ gas, it is possible to suppress the regrowth of GaN. As a result, the surface 10a of the substrate 10 can be kept smooth.

Further, the temperature (etching temperature) Te of the substrate 10 in the etching step S140 is set to, for example, a critical temperature (hereinafter referred to as an etching critical temperature) at which the GaN constituting the substrate 10 starts to be etched. As a result, the adhered impurities 20 on the surface 10a can be removed while etching the GaN constituting the surface 10a of the substrate 10.

On the other hand, as shown in FIG. 4, the etching temperature Te of the substrate 10 in the etching step S140 is made lower than, for example, the temperature (deposition temperature) Tg of the substrate 10 in the vapor phase growth step S160 described later. As a result, the surface 10a of the substrate 10 can be mildly etched, and the region of the surface 10a of the substrate 10 excluding the crystal defect portion can be kept smooth.

The following are exemplified as more detailed etching conditions in the etching step S140.
Etching temperature Te: 500-900 ° C, preferably 600-800 ° C
Pressure in processing chamber 401: 90-105 kPa, preferably 90-95 kPa
HCl gas partial pressure / N ₂ gas partial pressure: 1-10%, preferably 1-5%
H ₂ gas partial pressure / N ₂ gas partial pressure: 1 to 10%, preferably 3 to 7%
Gas flow velocity: 5 to 15 cm / s
(Note that the gas flow velocity is a value calculated from the amount of gas supplied without considering the volume expansion due to heating.)
Etching time: 1-10h, preferably 2-5h
Etching rate: 0.1 to 10 μm / h, preferably 0.5 to 3 μm / h

By the above etching, as shown in FIG. 5B, the adhered impurities 20 adhering to the surface 10a of the substrate 10 can be removed. The surface 10a of the substrate 10 is etched as shown by the dotted arrow.

After remove adhering impurities 20 from the surface 10a of the substrate 10, the supply of HCl gas and _{H 2} gas as an etching gas into the processing chamber 401 is stopped, thereby terminating the etching step S140.

(S160: vapor phase growth process)
Next, a vapor phase growth step S160 is performed in which a semiconductor layer (vapor phase growth layer) 40 made of a group III nitride semiconductor is epitaxially grown by a vapor phase growth method on the surface 10a of the substrate 10.

In this embodiment, for example, the semiconductor layer 40 is epitaxially grown by the HVPE method using the above-mentioned vapor phase growth apparatus 400.

Further, in the present embodiment, after the completion of the etching step S140 described above, the same vapor is used as it is without opening the processing chamber 401 of the vapor deposition apparatus 400 to the atmosphere and without carrying out the substrate 10 from the processing chamber 401. The following vapor phase growth step S160 is continuously performed in the processing chamber 401 of the phase growth apparatus 400. In that sense, the above-mentioned etching step S140 can be considered as an in-situ etching step (in-situ etching step).

Specifically, the vapor phase growth step S160 can be carried out, for example, by the following processing procedure.

_{In the etching step S140, after stopping the supply of the HCl gas and the H 2} gas as the etching gas into the processing chamber 401, the supply of the N ₂ gas into the processing chamber 401, the exhaust gas in the processing chamber 401, and the susceptor in a state of being continued holding and rotation of the substrate 10 by 408, and supplies the NH ₃ gas to the surface 10a of the substrate 10 of the processing chamber 401 through the gas supply pipe 432b. That is, the atmosphere in the processing chamber 401 is switched to an atmosphere that does not contain etching gas, that is, an atmosphere that contains NH ₃ gas and N _{2 gas.} As a result, it is possible to suppress the decomposition of the GaN constituting the substrate 10 and suppress the roughness of the surface of the substrate 10 when the temperature rises. After _{supplying NH 3} gas into the processing chamber 401, the inside of the processing chamber 401 is further heated.

As shown in FIG. 4, the temperature of the substrate 10 is raised above the etching temperature Te in the etching step S140 by heating in the processing chamber 401. At this time, the temperature of the substrate 10 is monotonically raised from the etching step S140 to the vapor phase growth step S160. That is, between the etching step S140 and the gas phase step S160, the temperature of the substrate 10 is not temporarily lowered, or the temperature of the substrate 10 is not overshooted. This makes it possible to suppress the reattachment of the adhered impurities 20.

When the temperature of the substrate 10 reaches the predetermined temperature Tg and the pressure in the processing chamber 401 reaches the predetermined pressure, the gas is supplied from the gas supply pipe 432a with the _{NH 3 gas supplied to the surface 10a of the substrate 10.} HCl gas is supplied into the generator 433a, and GaCl gas is supplied to the surface 10a of the substrate 10. At this time, H ₂ gas may be supplied into the processing chamber 401.

As a result, as shown in FIG. 6A, the semiconductor layer 40 made of GaN grows epitaxially on the surface 10a of the substrate 10.

At this time, as described above, by mildly etching the surface 10a of the substrate 10 in the etching step S140, the semiconductor layer 40 can be smoothly epitaxially grown on the surface 10a of the substrate 10, and the surface of the semiconductor layer 40 can be grown smoothly. It is possible to suppress the generation of facets other than the crystal plane ((0001) plane) constituting 10a.

Further, at this time, as described above, the etch pit 10ep that appears on the surface 10a of the substrate 10 in the etching step S140 is embedded by the semiconductor layer 40. As a result, even if the etch pit 10ep appears on the surface 10a of the substrate 10, the semiconductor layer 40 can be smoothly epitaxially grown on the surface 10a of the substrate 10.

At this time, the dislocation density on the surface of the semiconductor layer 40 can be equal to or less than the dislocation density on the surface 10a of the substrate 10. Specifically, the dislocation density on the surface of the semiconductor layer 40 can be, for example, 1 × 10 ³ pieces / cm ² or more and 1 × 10 ⁷ pieces / cm ² or less.

At this time, a GaN free-standing substrate is used as the substrate 10, and a semiconductor layer 40 made of GaN having a lattice constant equal to the lattice constant of the substrate 10 is homoepitaxially grown on the substrate 10 to generate a semiconductor in a low stress state. The layer 40 can be formed. Further, by making the coefficient of linear expansion of the substrate 10 equal to the coefficient of linear expansion of the semiconductor layer 40, cracks in the substrate 10 and the semiconductor layer 40 even when the temperature of the substrate 10 is lowered after the semiconductor layer 40 has grown. Can be suppressed. As a result, the semiconductor layer 40 can be formed into a thick film. Specifically, the thickness of the semiconductor layer 40 can be, for example, 45 μm or more and 5 mm or less, preferably 150 μm or more and 2 mm or less.

The following are examples of growth conditions when the vapor phase growth step S160 is carried out.
Growth temperature Tg: 980-1100 ° C, preferably 1050-1100 ° C
Pressure in processing chamber 401: 90-105 kPa, preferably 90-95 kPa
Partial pressure of GaCl gas: 1.5 to 15 kPa
Partial pressure of NH ₃ gas / Partial pressure of GaCl gas: 2-6
Flow rate of N ₂ gas / Flow rate of H ₂ gas: 1 to 20
Gas flow velocity: 5 to 15 cm / s
(Note that the gas flow velocity is a value calculated from the amount of gas supplied without considering the volume expansion due to heating.)

By growing the semiconductor layer 40 under the above growth conditions, the semiconductor laminate 1 having the substrate 10 and the semiconductor layer 40 can be manufactured.

When the growth of the semiconductor layer 40 is completed, _{while supplying NH 3} gas and N ₂ gas into the processing chamber 401, the inside of the processing chamber 401 is exhausted, and the HCl gas is supplied into the gas generator 433a, and the processing chamber is used. _{The supply of H 2} gas into the 401 and the heating by the heater 407 are stopped. When the temperature inside the treatment chamber 401 becomes 500 ° C or lower, _{the supply of NH 3} gas is stopped, and then the atmosphere inside the treatment chamber 401 is _{replaced with N 2} gas to restore the atmospheric pressure, and the inside of the treatment chamber 401 is changed to atmospheric pressure. After the temperature is lowered to a temperature at which it can be carried out, the semiconductor laminate 1 is carried out from the inside of the processing chamber 401.

(S180: Slicing process)
Next, as shown in FIG. 6B, the semiconductor layer 40 of the semiconductor laminate 1 is sliced to produce a plurality of free-standing substrates 2 as GaN free-standing substrates.

After that, at least the surface of the free-standing substrate 2 is polished, and the surface of the free-standing substrate 2 is made an epiready surface. After the polishing of the self-supporting substrate 2 is completed, a predetermined cleaning is performed on the self-supporting substrate 2.

As described above, the self-supporting substrate 2 of the present embodiment is manufactured.

Similar to the substrate 10, the surface of the self-standing substrate 2 manufactured in this manner is a (0001) surface or a surface having a predetermined off angle with respect to the (0001) surface. Further, the dislocation density on the surface of the self-standing substrate 2 is, for example, 1 × 10 ³ pieces / cm ² or more and 1 × 10 ⁷ pieces / cm ² or less, similar to the dislocation density on the surface of the semiconductor layer 40 described above.

The above-mentioned vapor phase growth step S160 may be re-executed using the substrate 10 or the semiconductor laminate 1 left after slicing the self-supporting substrate 2 or the sliced self-supporting substrate 2. As a result, the self-supporting substrate 2 having good crystal quality can be repeatedly manufactured.

(2) Effects obtained by the present embodiment According to the present embodiment, one or more of the following effects can be obtained.

(A) In the etching step S140, the entire surface of the surface 10a of the substrate 10 is etched in the gas phase over a predetermined thickness or more. At this time, in the substrate preparation step S120, the adhered impurities 20 adhering to the surface 10a of the substrate 10 due to the substrate accommodating body 200 are removed together with the GaN constituting the matrix of the substrate 10. As a result, in the vapor phase growth step S160, the generation of pits and morphology abnormal portions on the surface of the semiconductor layer 40 can be suppressed, and the local uptake of O into the semiconductor layer 40 can be suppressed. As a result, the carrier concentration in the semiconductor layer 40 can be made uniform in the plane, and the resistance of the semiconductor layer 40 can be made uniform in the plane.

Further, in the etching step S140, by removing the adhered impurities 20 adhering to the surface 10a of the substrate 10 together with the GaN, it is possible to suppress the formation of a non-growth region in which the semiconductor layer 40 is not grown. By suppressing the formation of the non-growth region in the semiconductor layer 40, it is possible to suppress the formation of through holes in the self-supporting substrate 2 when the semiconductor layer 40 is sliced to produce the self-supporting substrate 2 in the slicing step S180.

Further, even if a large amount of the adhered impurities 20 are adhered to the surface 10a of the substrate 10, the adhered impurities 20 are removed together with the GaN in the etching step S140 to become the adhered impurities 20 in the vapor phase growth step S160. It is also possible to suppress the generation of derived outgas. By epitaxially growing the semiconductor layer 40 while suppressing the generation of outgas derived from the adhered impurities 20, the uptake of impurities into the semiconductor layer 40 is suppressed and the formation of crystal defect portions in the semiconductor layer 40 is suppressed. be able to.

As described above, according to the present embodiment, it is possible to manufacture the semiconductor laminate 1 or the self-standing substrate 2 having good crystal quality.

(B) In the etching step S140, the adhered impurities 20 are removed by etching the matrix of the substrate 10 to which the adhered impurities 20 are attached, instead of directly etching the adhered impurities 20. As a result, even if the material of the adhered impurities 20, the amount of the adhered impurities 20, the position of the adhered impurities 20, the adhesion range of the adhered impurities 20 in a plan view, etc. are unknown, the adhered impurities 20 are arranged in the matrix of the substrate 10. It can be reliably removed together with.

(C) In the etching step S140, the surface 10a of the substrate 10 is etched under the condition that the region of the surface 10a of the substrate 10 excluding the crystal defect portion is smooth. By keeping the surface 10a of the substrate 10 smooth under such mild etching conditions, the semiconductor layer 40 can be smoothly epitaxially grown on the surface 10a of the substrate 10 in the vapor phase growth step S160. Further, at this time, it is possible to suppress the generation of facets other than the crystal planes constituting the surface of the semiconductor layer 40. If facets other than the crystal planes constituting the surface of the semiconductor layer 40 are generated during the growth of the semiconductor layer 40, the uptake of impurities into the semiconductor layer 40 will increase. On the other hand, in the present embodiment, by suppressing the generation of such facets, it is possible to suppress the uptake of impurities into the semiconductor layer 40.

(D) The etching step S140 and the vapor phase growth step S160 are continuously performed in the same processing chamber 401 without opening the processing chamber 401 of the vapor phase growth apparatus 400 to the atmosphere. As a result, it is possible to suppress the formation of an oxide layer on the surface 10a of the substrate 10 between the etching step S140 and the vapor phase growth step S160. That is, the semiconductor layer 40 can be directly grown on the surface 10a of the substrate 10 purified by the etching step S140. By not interposing the oxide layer between the substrate 10 and the semiconductor layer 40 in this way, the semiconductor layer 40 can take over without deteriorating the crystallinity of the substrate 10.

<Second Embodiment of the present invention>
In the above-described embodiment, the case of manufacturing the self-supporting substrate 2 has been described, but the etching step S140 may be applied to the case of manufacturing the semiconductor device 3 as in the second embodiment below. Hereinafter, only the elements different from the above-described embodiment will be described, and the elements substantially the same as the elements described in the above-described embodiment are designated by the same reference numerals and the description thereof will be omitted.

(1) Issues in the present embodiment As a group III nitride semiconductor-based semiconductor device, for example, an electron traveling layer made of GaN and an electron supply layer made of AlGaN are arranged in this order on a semi-insulating GaN free-standing substrate. A high electron mobility transistor (HEMT) configured by laminating is known. When a semiconductor device as a HEMT is manufactured, if a GaN free-standing substrate is housed in a substrate housing made of an organic resin material for a long period of time, the GaN free-standing substrate is caused by the substrate housing as in the above embodiment. Adhering impurities may adhere to the surface. Specifically, for example, Si may pile up at the interface between the GaN free-standing substrate and the electron traveling layer as an adversary impurity. When Si piles up at the interface between the GaN free-standing substrate and the electron traveling layer, a conductive GaN: Si layer is formed by the Si at the interface, and leak paths and parasitic capacitances may be generated. As a result, for example, the withstand voltage of the HEMT may decrease, or the high frequency characteristics of the HEMT may deteriorate.

Therefore, there is known a technique of doping Fe or the like in the vicinity of the interface between the GaN free-standing substrate and the electron traveling layer among the electron traveling layers. When doping Fe, for example, biscyclopentadienyl iron (Cp ₂ Fe) gas is used. In this way, by doping Fe in the vicinity of the interface between the GaN free-standing substrate and the electron traveling layer in the electron traveling layer, Si piled up at the interface is compensated, and the region near the interface has high resistance. Can be transformed.

However, the Cp ₂ Fe gas used when doping Fe can produce the so-called memory effect. _{That is, even if the Cp 2} Fe gas is flowed when growing the region of the electron traveling layer near the interface between the GaN free-standing substrate and the electron traveling layer, the inside of the pipe for supplying the _{Cp 2 Fe gas and thereafter. Cp 2} Fe gas remains in the processing chamber. Therefore, Fe is unintentionally doped even in the region near the interface between the electron traveling layer and the electron supply layer in the electron traveling layer. As a result, the two-dimensional electron gas (2DEG) generated in the region near the interface between the electron traveling layer and the electron supply layer in the electron traveling layer is reduced.

Further, when Fe is doped in the vicinity of the interface between the GaN self-supporting substrate and the electron traveling layer in the electron traveling layer, the interface between the electron traveling layer and the electron supply layer in the electron traveling layer is formed from the Fe-doped region. Fe diffuses into the nearby region. From this point of view, 2DEG is reduced.

Further, when the concentration of piled-up Si in the vicinity of the interface between the GaN free-standing substrate and the electron traveling layer in the electron traveling layer is high, even if Fe is doped in the vicinity of the interface, the piled-up Si is sufficient. It may not be possible to compensate for.

The present embodiment described below is based on the above-mentioned problems.

(2) Manufacturing Method of Semiconductor Laminate or Manufacturing Method of Semiconductor Device With reference to FIGS. 7 and 8, a method of manufacturing a semiconductor laminate or a method of manufacturing a semiconductor device according to the present embodiment will be described. FIG. 7 is a flowchart showing a method for manufacturing a semiconductor laminate or a method for manufacturing a semiconductor device according to the present embodiment. FIG. 8A is a schematic cross-sectional view showing a semiconductor laminate according to the present embodiment, and FIG. 8B is a schematic cross-sectional view showing a semiconductor device according to the present embodiment.

(S120: Substrate preparation process)
First, the substrate 10 is prepared. At this time, the substrate 10 is, for example, a semi-insulating GaN free-standing substrate. The concentration of Fe in the substrate 10 is, for example, 5.0 × 10 ¹⁷ at · cm ^-3 or more and 5.0 × 10 ¹⁸ at · cm ^-3 or less.

Further, at this time, the substrate 10 is accommodated in the substrate accommodating body 200 made of an organic resin material. When the substrate 10 is accommodated in the substrate accommodating body 200, for example, siloxane may be attached as the adhered impurity 20.

(S140: Etching process)
In this embodiment, as the vapor phase growth apparatus, for example, an organic metal vapor deposition (MOVPE) apparatus is used. After the substrate preparation step S120, the substrate 10 is taken out from the substrate accommodating body 200, and the substrate 10 is put into the processing chamber of the MOVPE apparatus. After the substrate 10 is put into the processing chamber of the MOVPE apparatus, the entire surface of the surface 10a of the substrate 10 is etched in the gas phase in the processing chamber over a predetermined thickness or more. At this time, the adhered impurities 20 adhering to the surface 10a of the substrate 10 in the substrate preparation step S120 are removed together with the GaN constituting the matrix of the substrate 10. Further, the etching conditions at this time are the same as the etching conditions of the first embodiment described above.

By removing the adhered impurities 20 together with the matrix of the substrate 10 in this way, it is possible to prevent Si as the adhered impurities 20 from being piled up on the surface of the substrate 10 (the interface between the substrate 10 and the semiconductor layer 40). be able to.

(S160: vapor phase growth process)
Next, the semiconductor layer 40 is epitaxially grown on the surface 10a of the substrate 10 using a MOVPE device. At this time, the etching step S140 and the vapor phase growth step S160 are continuously performed in the same processing chamber without opening the processing chamber of the MOVPE apparatus to the atmosphere.

In the present embodiment, as the semiconductor layer 40, for example, an electron traveling layer (channel layer) 42 and an electron supply layer (barrier layer) 44 are grown.

_{Specifically, first, by supplying trimethylgallium (TMG) gas and NH 3} gas to the substrate 10 heated to a predetermined temperature, an electronic traveling layer 42 made of GaN is formed on the substrate 10. Homo epitaxial growth. At this time, the thickness of the electron traveling layer 42 is set to, for example, 500 nm or more and 2500 nm or less.

When the electron traveling layer 42 is grown, the Cp ₂ Fe gas is not doped.

_{Next, by supplying TMA gas, TMG gas, and NH 3} gas to the substrate 10 heated to a predetermined temperature, the electron supply layer 44 made of AlGaN is epitaxially grown on the electron traveling layer 42. At this time, the thickness of the electron supply layer 44 is set to, for example, 5 nm or more and 50 nm or less.

As a result, as shown in FIG. 8A, the semiconductor laminate 1 of the present embodiment is manufactured.

(S220: Semiconductor device manufacturing process)
Next, a semiconductor device manufacturing step S220 for manufacturing the semiconductor device 3 using the above-mentioned semiconductor laminate 1 is performed. Specifically, a gate electrode 61 made of nickel (Ni) / gold (Au) is formed on the electron supply layer 44. Further, a source electrode 62 made of titanium (Ti) / Al is formed on the electron supply layer 44 at a position separated from the gate electrode 61 by a predetermined distance, and a source electrode 62 made of titanium (Ti) / Al is formed at a position separated from the source electrode 62 by sandwiching the gate electrode 61. The drain electrode 63 made of Ti / Al is formed. After forming each electrode, the semiconductor multilayer structure 1, a predetermined time annealing at a predetermined temperature in a N ₂ atmosphere. After the annealing treatment, a protective film made of silicon nitride (SiN) may be formed so as to cover the electron supply layer 44 and each electrode.

As described above, as shown in FIG. 8B, the semiconductor device 3 configured as the HEMT of the present embodiment is manufactured.

(3) Semiconductor Laminates and Semiconductor Devices In this embodiment, as described above, before forming the semiconductor layer 40 on the substrate 10 in the vapor phase growth step S160, adhesion on the surface 10a of the substrate 10 in the etching step S140. Impurity 20 is removed. As a result, the semiconductor laminate 1 and the semiconductor device 3 have the following features.

Since the adhered impurities 20 are removed from the surface 10a of the substrate 10, for example, the pile-up of Si is suppressed at the interface between the substrate 10 and the semiconductor layer 40. That is, at the interface between the substrate 10 and the semiconductor layer 40, Si is not accumulated at a concentration 10 times or more higher than the Si concentration in the substrate 10 or the Si concentration in the semiconductor layer 40, whichever is higher. In other words, the Si concentration at the interface between the substrate 10 and the semiconductor layer 40 is less than 10 times the higher of the Si concentration in the substrate 10 and the Si concentration in the semiconductor layer 40.

Further, in the semiconductor laminate 1 and the semiconductor device 3, the generation of the morphology abnormality portion on the surface of the semiconductor layer 40 is suppressed. Specifically, the surface density of the morphology abnormal portion in the surface of the semiconductor layer 40 is, for example, 10 cm ^-2 or more 1000 cm ^-2 or less.

Further, in the semiconductor laminate 1 and the semiconductor device 3, the formation of pits on the surface of the semiconductor layer 40 is suppressed. Specifically, the surface density of the pits in the surface of the semiconductor layer 40 is, for example, 10 cm- ² or less, preferably 1 cm- ² or less.

(4) Effects obtained by the present embodiment According to the present embodiment, one or more of the following effects can be obtained.

(A) In the etching step S140, the adherent impurities 20 adhering to the surface 10a of the substrate 10 in the substrate preparation step S120 are removed together with the GaN constituting the matrix of the substrate 10. As a result, it is possible to suppress the pile-up of Si as the adhered impurity 20 at the interface between the substrate 10 and the semiconductor layer 40. By suppressing the pile-up of Si at the interface between the substrate 10 and the semiconductor layer 40, the formation of a conductive GaN: Si layer near the interface is suppressed, and the generation of leak paths and parasitic capacitance is suppressed. can do. As a result, the withstand voltage and high frequency characteristics of the semiconductor device 3 can be improved. As described above, according to the present embodiment, it is possible to manufacture the semiconductor device 3 having good crystal quality and good characteristics.

(B) By removing the adhered impurities 20 from the surface 10a of the substrate 10 in the etching step S140, it is possible to suppress the generation of pits and morphology abnormal portions on the surface of the semiconductor layer 40 in the vapor phase growth step S160. As a result, local electric field concentration in the electron supply layer 44 can be suppressed. As a result, the withstand voltage of the semiconductor device 3 can be improved.

(C) The etching step S140 and the vapor phase growth step S160 are continuously performed in the same processing chamber without opening the processing chamber of the MOVPE apparatus to the atmosphere.

Here, for reference, when Si is adhered to the surface of the GaN free-standing substrate as an adversary impurity, the surface of the GaN free-standing substrate is wet-etched and the adhered impurities before the semiconductor layer is grown on the GaN free-standing substrate. Is conceivable. However, in this method, even if the adhered impurities can be removed from the surface of the GaN free-standing substrate by wet etching, when the GaN free-standing substrate is housed in the substrate housing after wet etching, it immediately adheres to the surface of the GaN free-standing substrate. There is a possibility that impurities will reattach.

On the other hand, in the present embodiment, by continuously performing the etching step S140 and the vapor phase growth step S160 in the same processing chamber, the adhered impurities 20 are reattached to the surface 10a of the substrate 10 after the etching step S140. It can be suppressed. As a result, it is possible to reliably suppress the pile-up of Si as the adhered impurity 20 at the interface between the substrate 10 and the semiconductor layer 40.

(5) Modification Example of This Embodiment In the above-described embodiment, the case where the semiconductor device 3 is configured as a HEMT has been described, but the semiconductor device 3 is not limited to the HEMT, and is, for example, a Schottky barrier diode (SBD). It may be configured. Hereinafter, only the elements different from the above-described embodiment will be described.

(5-1) Method for manufacturing semiconductor laminate or method for manufacturing nitride crystal substrate With reference to FIGS. 7 and 9, a method for manufacturing a semiconductor laminate or a method for manufacturing a semiconductor device according to this modification will be described. FIG. 9A is a schematic cross-sectional view showing a semiconductor laminate according to a modified example of the present embodiment, and FIG. 9B is a schematic cross-sectional view showing a semiconductor device according to a modified example of the present embodiment.

(S120: Substrate preparation process)
First, the substrate 10 is prepared. At this time, the substrate 10 is an n-type GaN free-standing substrate containing n-type impurities such as silicon (Si). Further, the concentration of the n-type impurities in the substrate 10 is set to, for example, 5.0 × 10 ¹⁷ at · cm ^-3 or more and 1.0 × 10 ¹⁹ at · cm ^-3 or less.

Further, at this time, the substrate 10 is accommodated in the substrate accommodating body 200 made of an organic resin material.

(S140: Etching process)
Next, the substrate 10 is put into the processing chamber of the MOVPE apparatus from the substrate accommodating body 200, and the entire surface of the surface 10a of the substrate 10 is etched in the gas phase of the processing chamber over a predetermined thickness or more. At this time, the adhered impurities 20 adhering to the surface 10a of the substrate 10 in the substrate preparation step S120 are removed together with the GaN constituting the matrix of the substrate 10.

(S160: vapor phase growth process)
Next, the semiconductor layer 40 is epitaxially grown on the surface 10a of the substrate 10 using a MOVPE device. In the present embodiment, as the semiconductor layer 40, for example, the base n-type semiconductor layer 46 and the drift layer 48 are grown.

Specifically, first, the base n-type semiconductor layer 46 as the n-type GaN layer is epitaxially grown on the substrate 10. At this time, for example, by doping Si or Ge as an n-type impurity, the concentration of the n-type impurity in the underlying n-type semiconductor layer 46 is substantially equal to that of the substrate 10, for example, 5.0 × 10 ¹⁷ at · cm ^{−. 3} or more and 1.0 × 10 ¹⁹ at · cm ^-3 or less.

Next, the drift layer 48 as the n-type GaN layer is epitaxially grown on the base n-type semiconductor layer 46. At this time, the concentration of n-type impurities in the drift layer 48 is lower than the concentration of n-type impurities in the substrate 10 and the underlying n-type semiconductor layer 46, for example, 1.0 × 10 ¹⁵ at · cm ^-3 or more. 0 × 10 ¹⁶ at · cm ^-3 or less.

As a result, as shown in FIG. 9A, the semiconductor laminate 1 of this modification is manufactured.

(S220: Semiconductor device manufacturing process)
Next, a semiconductor device manufacturing step S220 for manufacturing the semiconductor device 3 using the above-mentioned semiconductor laminate 1 is performed. Specifically, a protective film 50 having a circular opening in a plan view is formed on the semiconductor layer 40. At this time, the protective film 50 is, for example, a silicon oxide (SiO ₂ ) film. After the protective film 50 is formed, the p-type electrode 64 as a field plate electrode is formed so as to be in contact with the semiconductor layer 40 in the opening of the protective film 50 and to cover wider than the opening of the protective film 50 in a plan view. At this time, the p-type electrode 64 is, for example, a palladium (Pd) / nickel (Ni) film. Further, an n-type electrode 65 is formed on the back surface side of the substrate 10. At this time, the n-type electrode 65 is, for example, a titanium (Ti) / (Al) film.

As described above, as shown in FIG. 9B, the semiconductor device 3 configured as the Schottky barrier diode (SBD) of this modification is manufactured.

(5-2) Semiconductor Laminates and Semiconductor Devices The semiconductor laminates 1 and semiconductor devices 3 of the present embodiment also have the following features as in the above-described embodiment. In the semiconductor laminate 1 and the semiconductor device 3, the surface density of the morphology abnormal portion in the surface of the semiconductor layer 40 is, for example, 10 cm ^-2 or more 1000 cm ^-2 or less. The surface density of the pits in the surface of the semiconductor layer 40 is, for example, 10 cm- ² or less, preferably 1 cm- ² or less. At the interface between the substrate 10 and the semiconductor layer 40, Si is not accumulated at a concentration 10 times or more higher than the Si concentration in the substrate 10 or the Si concentration in the semiconductor layer 40, whichever is higher.

(5-3) Effects obtained by the present embodiment (a) By suppressing the growth of pits and morphology abnormal portions in the semiconductor layer 40, desired rectification can be obtained in the semiconductor device 3 configured as an SBD. ..

Here, if pits or morphology abnormal parts are present on the surface of the semiconductor layer, even if the carrier concentration around them is low, the O concentration is high in the portion of the semiconductor layer where the pits or morphology abnormal parts have grown, as described above. It becomes higher and the carrier concentration becomes higher. Since the Schottky barrier width of the semiconductor layer is inversely proportional to the square root of the carrier concentration, the tunnel current tends to flow in the portion of the semiconductor layer where the carrier concentration is high when the reverse bias is applied. That is, this corresponds to the formation of a parallel circuit having an SBD and a resistor. Therefore, there is a possibility that the desired rectifying property cannot be obtained in the semiconductor device configured as the SBD.

On the other hand, by suppressing the growth of pits and morphology abnormal portions in the semiconductor layer 40, it is possible to suppress the formation of portions having a locally high O concentration and a high carrier concentration. As a result, it is possible to suppress the local flow of tunnel current when the reverse bias is applied. As a result, the desired rectifying property can be obtained in the semiconductor device 3 configured as the SBD.

(B) By suppressing the generation of pits and morphology abnormal portions on the surface of the semiconductor layer 40, it is possible to suppress local electric field concentration in the drift layer 48. As a result, the withstand voltage of the semiconductor device 3 can be improved.

<Other embodiments>
The embodiment of the present invention has been specifically described above. However, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist thereof.

In the above embodiment, the case where each of the substrate 10 and the nitride semiconductor self-supporting substrate 2 is a GaN free-standing substrate has been described, but each of the substrate 10 and the nitride semiconductor self-supporting substrate 2 is not limited to the GaN free-standing substrate, for example. Group III nitride semiconductors such as aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium nitride (InN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN), that is, Al _x In _y Ga _{1. It may be a self-standing substrate made of a group III nitride semiconductor represented by the composition formula of −x−y} N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).

Further, the substrate 10 may be a substrate whose surface layer is at least a group III nitride semiconductor, for example, a support substrate made of sapphire or the like and Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, It may be a group III nitride semiconductor template having a semiconductor layer made of a group III nitride semiconductor represented by the composition formula of 0 ≦ y ≦ 1 and 0 ≦ x + y ≦ 1).

In the above-described embodiment, the case where the substrate accommodating body 200 is configured as a wafer tray has been described, but the substrate accommodating body 200 may be configured as a wafer box accommodating a plurality of substrates 10.

In the above-mentioned first embodiment, the doping in the vapor phase growth step S160 has not been described, but in order to impart predetermined conductivity or insulating property to the semiconductor layer 40, the semiconductor layer 40 is subjected to the vapor phase growth step S160. Impurities may be doped.

In the above-described embodiment, the case where the etching step S140 and the vapor phase growth step S160 are continuously performed in the processing chamber 401 of the same vapor phase growth apparatus 400 has been described, but the etching step S140 and the vapor phase growth step S160 have been described. May be performed by different devices. However, it is preferable to continuously perform the etching step S140 and the vapor phase growth step S160 in the processing chamber 401 of the same vapor phase growth apparatus 400 in that the formation of an oxide layer on the exposed portion of the substrate 10 can be suppressed.

In the modification of the second embodiment described above, the case where the semiconductor layer 40 is grown by the MOVPE method has been described, but the semiconductor layer 40 may be grown by the HVPE method. Since the HVPE method has a high growth rate, it is possible to improve the throughput when manufacturing a semiconductor device.

In the modification of the second embodiment described above, in the gas phase growth step S160 after the etching step S140, first, the base n-type semiconductor layer 46 as the n-type GaN layer is grown on the substrate 10, and then the base n-type semiconductor layer 46 is grown. The case where the drift layer 48 as the n-type GaN layer is grown has been described. However, since the adhesion impurities 20 (for example, pile-up Si) on the surface 10a of the substrate 10 are removed by the etching step S140, the etching step S140 In the later gas phase growth step S160, the drift layer 48 as the n-type GaN layer may be directly grown on the substrate 10 without the intervention of the base n-type semiconductor layer 46 as the n-type GaN layer. As a result, the drift layer 48 having good crystal quality can be directly grown on the substrate 10.

In the above-mentioned second embodiment and its modification, the case where HEMT or SBD is manufactured as the semiconductor device 3 has been described. However, as the semiconductor device 3, for example, a junction barrier Schottky diode (JBS), a pn junction diode, and a light emitting diode have been described. , Laser diodes, gate injection transistors (GIT), bipolar transistors and the like may be manufactured.

[Other Modifications of the Second Embodiment]
Here, another modification of the second embodiment will be described. In this modification, for example, a case where a pn junction diode is manufactured as a semiconductor device will be described. In addition, it will be described using the flowchart of FIG.

(S120: Substrate preparation process)
First, a base substrate made of an n-type GaN free-standing substrate is prepared.

Here, for example, in order to obtain a pn junction diode having a high withstand voltage as a semiconductor device, it is necessary to grow a drift layer as an n-type GaN layer having a thickness of several tens of μm on the base substrate. Since the growth rate in the MOVPE method is about several μm / h, it takes a very long time to grow the drift layer by the MOVPE method, and the throughput becomes low. Therefore, in this modification, the drift layer as the n-type GaN layer is grown on the base substrate by the HVPE method having a high growth rate.

As described above, a substrate having a drift layer whose surface layer is an n-type GaN layer is manufactured. After the substrate is produced, the substrate is housed in a substrate container made of an organic resin material.

(S140: Etching process)
Next, the substrate is put into the processing chamber of the MOVPE apparatus from the substrate accommodating body, and the entire surface of the drift layer constituting the surface layer of the substrate is etched in the gas phase of the processing chamber over a predetermined thickness or more. At this time, the adherent impurities adhering to the surface of the substrate (that is, the surface of the drift layer) in the substrate preparation step S120 are removed together with the GaN constituting the matrix of the surface layer (that is, the drift layer) of the substrate.

(S160: vapor phase growth process)
Next, using a MOVPE apparatus, a first p-type semiconductor layer as a p-type GaN layer is epitaxially grown on the drift layer. Examples of the p-type impurity in the first p-type semiconductor layer include magnesium (Mg). The concentration of p-type impurities in the first p-type semiconductor layer is, for example, 1.0 × 10 ¹⁷ at · cm ^-3 or more and 2.0 × 10 ¹⁹ at · cm ^-3 or less.

Next, the second p-type semiconductor layer as the p-type GaN layer is epitaxially grown on the first p-type semiconductor layer. The concentration of p-type impurities in the second p-type semiconductor layer is higher than the concentration of p-type impurities in the first p-type semiconductor layer, for example, 5.0 × 10 ¹⁹ at · cm ^-3 or more 2.0 × 10 ²⁰ at ·. It should be cm ^{-3 or less.}

As a result, the semiconductor laminate of this modification is manufactured.

(S220: Semiconductor device manufacturing process)
Next, a semiconductor device manufacturing step S220 for manufacturing a semiconductor device using the above-mentioned semiconductor laminate is performed. Specifically, a p-type electrode (for example, Pd / Ni) is formed on the second p-type semiconductor layer, and an n-type electrode (for example, Ti / Al) is formed on the back surface side of the base substrate.

As described above, the semiconductor device of this modification is manufactured.

According to this modification, the throughput when manufacturing a pn junction diode as a semiconductor device can be improved by growing a drift layer as an n-type GaN layer on a base substrate by the HVPE method having a high growth rate. can.

Further, according to this modification, in the etching step S140, the adherent impurities adhering to the surface of the drift layer in the substrate preparation step S120 are removed together with the GaN constituting the matrix of the drift layer. As a result, it is possible to suppress the pile-up of Si as an attached impurity at the interface between the drift layer and the first p-type semiconductor layer. By suppressing the pile-up of Si at the interface between the drift layer and the first p-type semiconductor layer, it is possible to suppress the p-type impurities in the first p-type semiconductor layer from being compensated by the pile-up Si. can.

In this modification, the case where the first p-type semiconductor layer as the p-type GaN layer is directly epitaxially grown on the drift layer in the vapor phase growth step S160 after the etching step S140 has been described. In the phase growth step S160, a thin n-type GaN layer may be grown on the drift layer, and then the first p-type semiconductor layer may be grown on the n-type GaN layer.

Hereinafter, various experimental results supporting the effects of the present invention will be described.

(1) Confirmation of adhered impurities (1-1) Preparation of substrate First, as a substrate, a GaN free-standing substrate having a diameter of 2 inches and a thickness of 400 μm was prepared. Next, the substrate was housed in a wafer tray as a board container and stored for a predetermined period of time.

(1-2) Evaluation The surface of the substrate housed in the wafer tray for 240 days was observed with a scanning electron microscope (SEM), and the surface of the substrate was subjected to energy dispersive X-ray spectroscopy (EDX). Composition analysis was performed.

In addition, the composition of each surface of the substrate housed in the wafer tray was analyzed for 0 to 240 days by total internal reflection fluorescent X-ray analysis (TXRF).

(1-3) Results FIG. 10 (a) is an SEM image showing an example of adhered impurities, and (b) is the result of EDX analysis of the adhered impurities of (a).
As shown in FIG. 10A, adhered impurities were attached to the surface of the substrate housed in the wafer tray. When the composition of these adhered impurities was analyzed by EDX, it was confirmed that the adhered impurities contained Si, C and O as shown in FIG. 10 (b). From this result, it is presumed that the adhered impurities include siloxane due to the mold release agent used in manufacturing the wafer tray.

FIG. 11 is a diagram showing the Si concentration on the surface of the substrate measured by total internal reflection fluorescent X-ray analysis with respect to the number of storage days in which the substrate was stored in the substrate housing.
As shown in FIG. 11, it was confirmed that the Si concentration on the surface of the substrate monotonically increased with respect to the number of storage days in the wafer tray. That is, it was confirmed that Si as an attached impurity may be attached more as the storage period is longer.

(2) Confirmation of the effect of the etching process (2-1) Preparation of the substrate First, as the substrate, a plurality of GaN free-standing substrates having a diameter of 2 inches and a thickness of 400 μm were prepared. Next, each of the plurality of substrates was housed in a wafer tray as a board container and stored for 240 days.

(2-2) Production of Semiconductor Laminate A semiconductor laminate of Comparative Example and a semiconductor laminate of Example were produced under the following conditions.

(Comparative example)
Etching process: Not implemented Vapor deposition process:
Method: HVPE method Semiconductor layer material: GaN
Growth temperature: 1050 ° C
Processing chamber pressure: constant NH ₃ gas partial pressure / GaCl gas partial pressure: 3
N ₂ gas flow rate / H ₂ gas flow rate: 5
Semiconductor layer thickness: 200 μm

(Example)
Etching process: Implementation equipment: HVPE equipment same as the vapor phase growth process Etching temperature: 650 ° C
Processing chamber pressure: Constant gas: N ₂ gas, HCl gas, H ₂ gas HCl gas partial pressure / N ₂ gas partial pressure: 3%
H ₂ gas partial pressure / N ₂ gas partial pressure: 5%
Etching time: 3h
Vapor deposition process:
Same as the comparative example

(2-3) Evaluation Regarding the semiconductor laminates of Comparative Examples and Examples, the presence or absence of pits and morphology abnormalities on the surface of the semiconductor layer and the presence or absence of non-growth regions in the semiconductor layer were observed.

(2-4) Results The results will be described with reference to FIGS. 12 and 13. FIG. 12A is a photograph showing the appearance of the semiconductor laminate of the example, and FIG. 12B is a photograph showing the appearance of the semiconductor laminate of the comparative example. 13 (a) to 13 (c) are views showing pits and morphology abnormalities on the surface of the semiconductor laminate of the comparative example.

In the semiconductor laminate of the comparative example, as shown in FIG. 12 (b), a non-growth region (arrow) was generated in the semiconductor layer. In the semiconductor laminate of the comparative example, as shown in FIGS. 13 (a) to 13 (c), pits and morphology abnormal parts were generated on the surface of the semiconductor layer. In the comparative example, since adherent impurities were attached to the surface of the substrate due to the wafer tray, pits and morphology abnormal parts were formed on the surface of the semiconductor layer or non-growth regions were formed in the vapor phase growth step. It is thought that it has been done.

On the other hand, in the semiconductor laminate of the example, as shown in FIG. 12A, no non-growth region was generated in the semiconductor layer. Moreover, the surface of the semiconductor layer was smooth.

In the embodiment, it was confirmed that the formation of the non-growth region of the semiconductor layer can be suppressed in the vapor phase growth step by removing the adhered impurities adhering to the surface of the substrate together with the GaN constituting the matrix of the substrate in the etching step. did. It was also confirmed that the semiconductor layer can be smoothly epitaxially grown in the vapor phase growth step by etching the surface of the substrate under mild conditions in the etching step. As a result, it was confirmed that a semiconductor laminate having good crystal quality can be produced.

<Preferable Aspect of the Present Invention>
Hereinafter, preferred embodiments of the present invention will be described.

(Appendix 1)
A process of preparing a substrate that is housed in a substrate container made of an organic resin material and whose surface layer is at least a group III nitride semiconductor.
A step of putting the substrate into a predetermined processing chamber from the substrate accommodating body and etching at least the entire surface of the surface layer of the substrate in a gas phase in the processing chamber over a predetermined thickness or more.
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the substrate by a vapor phase growth method.
Have,
In the etching step,
A method for producing a semiconductor laminate in which adherent impurities adhering to the surface of the substrate due to the substrate container in the step of preparing the substrate are removed together with at least the group III nitride semiconductor constituting the surface layer of the substrate. ..

(Appendix 2)
In the etching step,
The method for producing a semiconductor laminate according to Appendix 1, wherein the surface of the surface layer is etched under the condition that the region excluding the crystal defect portion of the surface layer is smooth.

(Appendix 3)
In the etching step,
The method for producing a semiconductor laminate according to Appendix 1 or 2, wherein the etching is performed in an atmosphere containing hydrogen chloride gas and hydrogen gas.

(Appendix 4)
In the etching step,
The etching was performed in an atmosphere containing the hydrogen chloride gas, the hydrogen gas and the inert gas.
The method for producing a semiconductor laminate according to Appendix 3, wherein the partial pressure of the inert gas is made higher than the partial pressures of the hydrogen chloride gas and the hydrogen gas.

(Appendix 5)
In the etching step,
The method for producing a semiconductor laminate according to Appendix 4, wherein the ratio of the partial pressures of the hydrogen chloride gas and the hydrogen gas to the partial pressure of the inert gas is 1% or more and 10% or less.

(Appendix 6)
In the etching step,
The method for producing a semiconductor laminate according to any one of Supplementary note 1 to 5, wherein the etching is performed in an atmosphere free of ammonia gas.

(Appendix 7)
The method for manufacturing a semiconductor laminate according to any one of Supplementary note 1 to 6, wherein the temperature of the substrate in the etching step is lower than the temperature of the substrate in the step of epitaxially growing the semiconductor layer.

(Appendix 8)
The method for manufacturing a semiconductor laminate according to Appendix 7, wherein the temperature of the substrate is monotonically raised from the etching step to the epitaxial growth of the semiconductor layer.

(Appendix 9)
The method for manufacturing a semiconductor laminate according to any one of Supplementary note 1 to 8, wherein the etching step and the step of epitaxially growing the semiconductor layer are continuously performed in the same processing chamber.

(Appendix 10)
In the etching process,
The method for producing a semiconductor laminate according to any one of Supplementary note 1 to 9, wherein the etching is performed for at least 1 hour or more while the temperature of the substrate is maintained at a predetermined temperature.

(Appendix 11)
In the etching process,
The method for manufacturing a semiconductor laminate according to any one of Supplementary note 1 to 10, wherein the entire surface layer of the substrate is etched at least by 10 nm or more in the depth direction.

(Appendix 12)
In the etching process,
Etch pits corresponding to dislocations in the surface layer appear on the surface of the surface layer of the substrate.
In the step of epitaxially growing the semiconductor layer,
The method for manufacturing a semiconductor laminate according to any one of Supplementary note 1 to 11, wherein the etch pits appearing on the surface of the surface layer are embedded by the semiconductor layer.

(Appendix 13)
In the process of preparing the substrate,
The method for producing a semiconductor laminate according to any one of Supplementary note 1 to 12, wherein the substrate is accommodated in the substrate housing for at least 12 hours.

(Appendix 14)
In the process of preparing the substrate,
The method for producing a semiconductor laminate according to any one of Supplementary note 1 to 13, wherein the substrate is housed in the substrate housing made of polypropylene.

(Appendix 15)
The method for producing a semiconductor laminate according to any one of Supplementary note 1 to 14, wherein the adhered impurity contains at least siloxane.

(Appendix 16)
The method for manufacturing a semiconductor laminate according to any one of Supplementary note 1 to 15, wherein the group III nitride semiconductor constituting at least the surface layer of the substrate is gallium nitride.

(Appendix 17)
The method for manufacturing a semiconductor laminate according to Appendix 16, wherein the surface of the surface layer of the substrate is a + C surface or a surface having an off angle within 2 ° with respect to the + C surface.

(Appendix 18)
A process of preparing a substrate that is housed in a substrate container made of an organic resin material and whose surface layer is at least a group III nitride semiconductor.
A step of putting the substrate into a predetermined processing chamber from the substrate accommodating body and etching at least the entire surface of the surface layer of the substrate in a gas phase in the processing chamber over a predetermined thickness or more.
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the substrate by a vapor phase growth method.
Have,
In the etching step,
A method for manufacturing a semiconductor device that removes adherent impurities adhering to the surface of the substrate due to the substrate container in the step of preparing the substrate together with at least the group III nitride semiconductor constituting the surface layer of the substrate.

(Appendix 19)
A process of preparing a substrate that is housed in a substrate container made of an organic resin material and whose surface layer is at least a group III nitride semiconductor.
A step of putting the substrate into a predetermined processing chamber from the substrate accommodating body and etching at least the entire surface of the surface layer of the substrate in a gas phase in the processing chamber over a predetermined thickness or more.
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the substrate by a vapor phase growth method.
The process of slicing the semiconductor layer to produce a nitride semiconductor self-supporting substrate,
Have,
In the etching step,
A nitride semiconductor self-standing substrate that removes adherent impurities adhering to the surface of the substrate due to the substrate container in the step of preparing the substrate together with at least the group III nitride semiconductor constituting the surface layer of the substrate. Production method.

(Appendix 20)
A substrate whose surface layer is at least a group III nitride semiconductor,
A semiconductor layer provided on the substrate and made of a group III nitride semiconductor,
Have,
A semiconductor laminate in which silicon is not accumulated at the interface between the substrate and the semiconductor layer at a concentration 10 times or more higher than the silicon concentration in the substrate or the silicon concentration in the semiconductor layer.

(Appendix 21)
A substrate whose surface layer is at least a group III nitride semiconductor,
A semiconductor layer provided on the substrate and made of a group III nitride semiconductor,
Have,
A semiconductor device in which silicon is not accumulated at the interface between the substrate and the semiconductor layer at a concentration 10 times or more higher than the silicon concentration in the substrate or the silicon concentration in the semiconductor layer.

1 Semiconductor laminate 2 Nitride semiconductor self-supporting substrate 10 Substrate (substrate)
20 Adhering impurities 40 Semiconductor layer

Claims (17)

A process of preparing a substrate that is housed in a substrate container made of an organic resin material and whose surface layer is at least a group III nitride semiconductor.
A step of putting the substrate into a predetermined processing chamber from the substrate accommodating body and etching at least the entire surface of the surface layer of the substrate in a gas phase in the processing chamber over a predetermined thickness or more.
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the substrate by a vapor phase growth method.
Have,
In the etching step,
While lowering the temperature of the substrate in the etching step to be lower than the temperature of the substrate in the step of epitaxially growing the semiconductor layer,
Adhering impurities attached on the front surface of the substrate as resulting from the substrate container in the step of preparing the substrate, it is removed together with the group III nitride semiconductor constituting at least the surface layer of the substrate,
From the etching step to the epitaxial growth step of the semiconductor layer, the temperature of the substrate is monotonically increased without temporarily lowering the temperature of the substrate and without overshooting the temperature of the substrate. /> A method for manufacturing a semiconductor laminate. In the etching step,
The method for producing a semiconductor laminate according to claim 1, wherein the surface of the surface layer is etched under the condition that the region of the surface excluding the crystal defect portion is smooth. In the etching step,
The method for producing a semiconductor laminate according to claim 1 or 2, wherein the etching is performed in an atmosphere containing hydrogen chloride gas and hydrogen gas. In the etching step,
The etching was performed in an atmosphere containing the hydrogen chloride gas, the hydrogen gas and the inert gas.
The ratio of the partial pressures of the hydrogen chloride gas and the hydrogen gas to the partial pressure of the inert gas shall be 1% or more and 10% or less.
The method for manufacturing a semiconductor laminate according to claim 3. In the etching step,
The etching is performed in an atmosphere free of ammonia gas.
The method for manufacturing a semiconductor laminate according to any one of claims 1 to 4. The method for producing a semiconductor laminate according to any one of claims 1 to 5, wherein the etching step and the step of epitaxially growing the semiconductor layer are continuously performed in the same processing chamber. In the etching process,
The method for producing a semiconductor laminate according to any one of claims 1 to 6, wherein the etching is performed for at least 1 hour or more while the temperature of the substrate is maintained at a predetermined temperature. In the etching process,
The method for manufacturing a semiconductor laminate according to any one of claims 1 to 7, wherein the entire surface layer of the substrate is etched at least by 10 nm or more in the depth direction. In the etching process,
Etch pits corresponding to dislocations in the surface layer appear on the surface of the surface layer of the substrate.
In the step of epitaxially growing the semiconductor layer,
The method for manufacturing a semiconductor laminate according to any one of claims 1 to 8, wherein the etch pits appearing on the surface of the surface layer are embedded by the semiconductor layer. In the process of preparing the substrate,
The method for producing a semiconductor laminate according to any one of claims 1 to 9, wherein the substrate is accommodated in the substrate housing for at least 12 hours. In the process of preparing the substrate,
The method for producing a semiconductor laminate according to any one of claims 1 to 10, wherein the substrate is housed in the substrate housing made of polypropylene. The method for producing a semiconductor laminate according to any one of claims 1 to 11, wherein the adhered impurity contains at least siloxane. The method for producing a semiconductor laminate according to any one of claims 1 to 12, wherein the group III nitride semiconductor constituting at least the surface layer of the substrate is gallium nitride. The method for manufacturing a semiconductor laminate according to claim 13, wherein the surface of the surface layer of the substrate is a + C surface or a surface having an off angle within 2 ° with respect to the + C surface. A process of preparing a substrate that is housed in a substrate container made of an organic resin material and whose surface layer is at least a group III nitride semiconductor.
A step of putting the substrate into a predetermined processing chamber from the substrate accommodating body and etching at least the entire surface of the surface layer of the substrate in a gas phase in the processing chamber over a predetermined thickness or more.
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the substrate by a vapor phase growth method.
The process of slicing the semiconductor layer to produce a nitride semiconductor self-supporting substrate,
Have,
In the etching step,
While lowering the temperature of the substrate in the etching step to be lower than the temperature of the substrate in the step of epitaxially growing the semiconductor layer,
Adhering impurities attached on the front surface of the substrate as resulting from the substrate container in the step of preparing the substrate, it is removed together with the group III nitride semiconductor constituting at least the surface layer of the substrate,
From the etching step to the epitaxial growth step of the semiconductor layer, the temperature of the substrate is monotonically increased without temporarily lowering the temperature of the substrate and without overshooting the temperature of the substrate. /> A method for manufacturing a nitride semiconductor self-supporting substrate. A substrate whose surface layer is at least a group III nitride semiconductor,
A semiconductor layer provided on the substrate and made of a group III nitride semiconductor,
Have,
At the interface between the substrate and the semiconductor layer, silicon is not accumulated at a concentration 10 times or more higher than the silicon concentration in the substrate or the silicon concentration in the semiconductor layer, whichever is higher.
A semiconductor laminate having ^{a pit surface density of 10 cm-2} or less in the surface of the semiconductor layer, where the oxygen concentration is relatively higher than that of other parts. A substrate whose surface layer is at least a group III nitride semiconductor,
A semiconductor layer provided on the substrate and made of a group III nitride semiconductor,
Have,
At the interface between the substrate and the semiconductor layer, silicon is not accumulated at a concentration 10 times or more higher than the silicon concentration in the substrate or the silicon concentration in the semiconductor layer, whichever is higher.
^{A semiconductor device having a pit surface density of 10 cm-2} or less in the surface of the semiconductor layer, where the oxygen concentration is relatively higher than that of other parts .

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