JP6981261B2 - Surge voltage detection circuit - Google Patents

Description

The present invention relates to a surge voltage detection circuit that detects a surge voltage generated when a switch is switched to an off state.

As a circuit of this type, as seen in Patent Document 1, a circuit including a series connection body of a pair of resistors is known. The series connection body of the resistor is connected in parallel to a switch such as an IGBT. The surge voltage detection circuit divides the voltage between the terminals of the switch by a pair of resistors, and detects the divided voltage value as the surge voltage. Here, the responsiveness of the voltage dividing value by the resistor is low with respect to the transient change in the voltage between the terminals of the switch when the switch is switched to the off state. Since the surge voltage generation period is extremely short, if the response to transient changes is low, the surge voltage detection accuracy may decrease.

Therefore, the surge voltage detection circuit described in Patent Document 1 further includes a series connection body of a pair of capacitors in order to improve the responsiveness. The series connection of capacitors is connected in parallel to the switch. This is intended to improve the detection accuracy of the surge voltage.

Japanese Unexamined Patent Publication No. 2004-236371

It is not the voltage divider value due to the resistor but the voltage divider value due to the capacitor that instantly follows the transient change in the voltage between the terminals of the switch. However, when the voltage between the terminals of the switch is in a steady state, the detection accuracy of the surge voltage based on the voltage dividing value by the capacitor is lower than the detection accuracy of the surge voltage based on the voltage dividing value by the resistor. This is because, for example, the tolerance of capacitance due to the individual difference of the capacitors mass-produced in the manufacturing process is larger than the tolerance of the resistance value due to the individual difference of the resistor.

Therefore, in the circuit described in Patent Document 1, the response to a transient change in the voltage between the terminals of the switch can be improved by adding a capacitor, but the detection accuracy of the surge voltage depends on the resistor. It will be lower than the one based on the voltage division value.

An object of the present invention is to provide a surge voltage detection circuit capable of improving the accuracy of surge voltage detection.

The present invention is a surge voltage detection circuit that detects the surge voltage generated when the switch is switched to the off state, and is connected between the high potential side terminal and the low potential side terminal of the switch, and the voltage between the terminals of the switch. Multiple capacitors that divide the voltage, multiple resistors that divide the voltage between the terminals of the switch that is turned off or the voltage that correlates with the voltage between the terminals, and the peak value of the voltage division value by the plurality of capacitors. A peak holding unit for holding the voltage and a correction unit for correcting the voltage held by the peak holding unit based on the voltage division values of the plurality of resistors.

Considering the transient change in the voltage between the terminals of the switch when it is switched to the off state, the present invention includes a plurality of capacitors and a peak holding portion. The peak holding portion holds the peak value of the voltage between the terminals of the switch divided by the plurality of capacitors.

Here, when the voltage between the terminals of the switch is in a steady state, the detection accuracy of the surge voltage based on the voltage divider value by the resistor is higher than the detection accuracy of the surge voltage based on the voltage divider value by the capacitor. .. In view of this point, the present invention includes a plurality of resistors that divide the voltage between the terminals of the switch that is turned off or the voltage that correlates with the voltage between the terminals. The value obtained by dividing the voltage between the terminals of the switch in the off state by multiple resistors grasps the detection error between the surge voltage based on the voltage divider value by the capacitor and the surge voltage based on the voltage divider value by the resistor. It can be used as a reference value for this. Therefore, in the present invention, the peak holding unit is used based on the value obtained by dividing the voltage between the terminals of the switch turned off or the voltage correlated with the voltage between the terminals by a plurality of resistors by the correction unit. The held voltage is corrected. This makes it possible to improve the detection accuracy of the surge voltage.

The overall block diagram of the control system of the rotary electric machine which concerns on 1st Embodiment. The figure which shows the drive circuit of a switch. A time chart showing changes in the gate voltage of the switch. The figure for demonstrating the correction method of a surge voltage. The figure which shows the structure which variably sets the gate resistance value based on the detected value of the surge voltage which concerns on the modification 1 of 1st Embodiment. The figure which shows the drive circuit of the switch which concerns on 2nd Embodiment. A time chart showing changes in the drive state of the first and second discharge switches. A time chart showing changes in the drive state of the first and second discharge switches according to the first modification of the second embodiment. A time chart showing changes in the drive state of the first and second discharge switches according to the second modification of the second embodiment. A time chart showing changes in the drive state of the first and second discharge switches according to the third modification of the second embodiment. The figure which shows the drive circuit of the switch which concerns on 3rd Embodiment. A time chart showing changes in the gate voltage of the switch. The figure which shows the drive circuit of the switch which concerns on 4th Embodiment.

<First Embodiment>
Hereinafter, a first embodiment embodying the surge voltage detection circuit according to the present invention will be described with reference to the drawings. The surge voltage detection circuit according to this embodiment constitutes a control system for a rotary electric machine.

As shown in FIG. 1, the control system includes a battery 10 as a DC power source, an inverter 20 as a power converter, a rotary electric machine 30, and a control device 40. The rotary electric machine 30 is connected to the battery 10 via the inverter 20. A smoothing capacitor 11 is provided between the battery 10 and the inverter 20. Further, as the rotary electric machine 30, for example, a permanent magnet field type synchronous machine may be used.

The inverter 20 includes upper and lower arm switch SWs for three phases. The first end of the winding 31 of the rotary electric machine 30 is connected to the connection points of the upper and lower arm switches SW of each phase. The second end of the winding 31 of each phase is connected at the neutral point. In the present embodiment, a voltage-controlled semiconductor switching element is used as the switch SW of the inverter 20, and specifically, a Si or SiC N-channel MOSFET is used. The drain of the switch SW corresponds to the high potential side terminal, and the source of the switch SW corresponds to the low potential side terminal. The body diode FD is built in the switch SW. An external freewheel diode may be connected to the switch SW in antiparallel.

The inverter 20 includes a power supply voltage detecting unit 12 that detects the voltage between terminals of the smoothing capacitor 11 as the power supply voltage of the inverter 20. The power supply voltage detection unit 12 includes a series connection body of the first main resistor 12a and the second main resistor 12b. The power supply voltage detection unit 12 divides the voltage between the terminals of the smoothing capacitor 11 by the main resistors 12a and 12b, and detects the divided voltage value as the power supply voltage VDC. The detected power supply voltage VDC is input to the drive circuit Dr of the control device 40 or the inverter 20.

The control device 40 alternately turns on the upper arm switch SW and the lower arm switch SW in each phase in order to control the control amount of the rotary electric machine 30 to the command value. The control amount is, for example, torque. The control device 40 outputs an on command indicating an on state or an off command indicating an off state to the drive circuit Dr as a drive signal G of the switch SW. In this embodiment, for convenience, the on command is represented by a signal of logic H, and the off command is represented by a signal of logic L.

The drive circuit Dr is individually provided corresponding to each switch SW. The drive circuit Dr acquires the drive signal G from the control device 40, and drives the switch SW based on the acquired drive signal G.

Subsequently, the drive circuit Dr of the switch SW will be described with reference to FIG. FIG. 2 shows an equivalent gate capacity 13 and a feedback capacity 14 related to the input capacity of the switch SW.

The drive circuit Dr includes a drive control unit 50, a first switch 51, and a second switch 52. In this embodiment, a PNP type transistor is used as the first switch 51, and an NPN type transistor is used as the second switch 52.

A constant voltage power supply (not shown) is connected to the emitter of the first switch 51. The gate of the switch SW is connected to the collector of the first switch 51 and the collector of the second switch 52. The source of the switch SW is connected to the emitter of the second switch 52.

When the drive control unit 50 determines that the acquired drive signal G is an ON command, the drive control unit 50 charges the gate of the switch SW by a charging process in which the first switch 51 is turned on and the second switch 52 is turned off. Supply current. As a result, the gate voltage of the switch SW becomes equal to or higher than the threshold voltage Vth, and the switch SW is turned on. On the other hand, when the drive control unit 50 determines that the acquired drive signal G is an off command, the gate of the switch SW is subjected to a discharge process in which the first switch 51 is turned off and the second switch 52 is turned on. Discharges the discharge current from. As a result, the gate voltage of the switch SW becomes less than the threshold voltage Vth, and the switch SW is turned off.

The drive circuit Dr includes a surge voltage detection circuit 60. The surge voltage detection circuit 60 includes a lower capacitor 61, an upper capacitor 62, a peak hold circuit 63 as a peak holding unit, a correction unit 64, and a correction value calculation unit 70. The upper capacitor 61 and the lower capacitor 62 are connected in series, and the series connection body thereof is connected in parallel to the switch SW.

Note that FIG. 2 shows an example in which the surge voltage detection circuit 60 includes one capacitor as the lower capacitor 61, but the present invention is not limited to this. For example, the surge voltage detection circuit 60 may include a series connection of a plurality of capacitors as the lower capacitor 61. Similarly, the surge voltage detection circuit 60 may include a series connection of a plurality of capacitors as the upper capacitor 62.

The peak hold circuit 63 includes a first amplifier 63a, a second amplifier 63b, a diode 63c, a capacitor 63d, and a discharge switch 63e. In the present embodiment, the discharge switch 63e is an N-channel MOSFET.

The connection points of the lower capacitor 61 and the upper capacitor 62 are connected to the non-inverting input terminal of the first amplifier 63a. The anode of the diode 63c is connected to the output terminal of the first amplifier 63a, and the non-inverting input terminal of the second amplifier 63b, the first end of the capacitor 63d, and the drain of the discharge switch 63e are connected to the cathode. Has been done. The output terminal of the second amplifier 63b is connected to the inverting input terminal of each of the first amplifier 63a and the second amplifier 63b. The source of the switch SW is connected to the second end of the capacitor 63d and the source of the discharge switch 63e.

The discharge switch 63e is driven by the discharge instruction signal CLR output from the drive control unit 50. In the present embodiment, when the logic of the discharge instruction signal CLR is H, the discharge switch 63e is turned on, and when the logic of the discharge instruction signal CLR is L, the discharge switch 63e is in the off state. It is said that. The peak hold circuit 63 holds the peak value of the first voltage division value VA after the timing when the discharge switch 63e is switched to the ON state. The first voltage dividing value VA is a value obtained by dividing the voltage between the terminals of the switch SW by the capacitors 61 and 62, respectively. The peak value of the first partial pressure value VA is the output signal of the second amplifier 63b. Hereinafter, the output signal of the second amplifier 63b will be referred to as a pre-correction peak voltage Vpr. The pre-correction peak voltage Vpr is expressed by the following equation (eq1).

上式（ｅｑ１）において、Ｃ１は下側コンデンサ６１の静電容量を示し、Ｃ２は上側コンデンサ６２の静電容量を示し、Ｖｓｕｒｇｅはサージ電圧を示し、Ｖｏｆｆｓはピークホールド回路６３のオフセット電圧を示す。なお、放電用スイッチ６３ｅがオフ状態に切り替えられると、コンデンサ６３ｄの電荷が放電され、補正前ピーク電圧Ｖｐｒはリセットされる。

In the above equation (eq1), C1 indicates the capacitance of the lower capacitor 61, C2 indicates the capacitance of the upper capacitor 62, Vsurge indicates the surge voltage, and Voffs indicates the offset voltage of the peak hold circuit 63. .. When the discharge switch 63e is switched to the off state, the electric charge of the capacitor 63d is discharged, and the pre-correction peak voltage Vpr is reset.

The correction unit 64 calculates the corrected peak voltage Vpc by adding the correction value ΔV calculated by the correction value calculation unit 70 to the pre-correction peak voltage Vpr output from the peak hold circuit 63. In the present embodiment, after the switch SW is switched to the off state, the correction unit 64 sets the corrected peak voltage Vpc based on the surge voltage generated by the switch to the off state to the next off state. Calculate before switching. Specifically, after the switch SW is switched to the off state, the correction unit 64 starts the next discharge process of the corrected peak voltage Vpc based on the surge voltage generated by the switch to the off state. Calculate before This makes it possible to use the most recently calculated corrected peak voltage Vpc during the discharge process.

The correction value calculation unit 70 includes a lower resistor 71a, an upper resistor 71b, a subtractor 72, a divider 73, and an adder 74. The lower resistor 71a and the upper resistor 71b are connected in series, and the series connection is connected in parallel to the switch SW. In the present embodiment, the value obtained by dividing the voltage between the terminals of the switch SW by the resistors 71a and 71b will be referred to as the second voltage dividing value VB.

Note that FIG. 2 shows an example in which the correction value calculation unit 70 includes one resistor as the lower resistor 71a, but the present invention is not limited to this. For example, the correction value calculation unit 70 may include a series connection body of a plurality of resistors as the lower resistor 71a. Similarly, the correction value calculation unit 70 may include a series connection body of a plurality of resistors as the upper resistor 71b.

The resistance value of the lower resistor 71a is R1, and the resistance value of the upper resistor 71b is R2. In this embodiment, the capacitances C1 and C2 of the capacitors 61 and 62 and the resistance values R1 and R2 of the resistors 71a and 71b are set so that "C1 / C2 = R2 / R1".

The subtractor 72 calculates the voltage detection error e (= VB-VA) by subtracting the first voltage dividing value VA from the second voltage dividing value VB.

The divider 73 calculates the conversion coefficient k (= Vpr / VA) by dividing the uncorrected peak voltage Vpr by the first voltage dividing value VA.

The adder 74 calculates the correction value ΔV (= k × e) by multiplying the voltage detection error e calculated by the subtractor 72 and the conversion coefficient k calculated by the divider 73. The calculated correction value ΔV is input to the correction unit 64.

The correction method of the peak voltage Vpr before correction will be further described with reference to FIGS. 3 and 4. FIG. 3A shows the transition of the drive signal G, FIG. 3B shows the transition of the gate voltage Vgs of the switch SW, and FIG. 3C shows the transition of the terminal voltage Vds (drain and source voltage) of the switch SW. ) Is shown. FIG. 3D shows the transition of the uncorrected peak voltage Vpr, the first voltage dividing value VA, and the second voltage dividing value VB, and FIG. 3E shows the transition of the discharge instruction signal CLR.

The discharge instruction signal CLR is temporarily set to H at the timing before the time t1 when the drive signal G is switched to the off command. In the present embodiment, the discharge instruction signal CLR is temporarily set to H at time t1. As a result, the pre-correction peak voltage Vpr corresponding to the previous surge voltage held in the peak hold circuit 63 is reset to 0.

At time t1, the drive signal G is switched to the off command. As a result, the discharge current is discharged from the gate of the switch SW, and the gate voltage Vgs begins to decrease. Further, the voltage Vds between the terminals of the switch SW begins to rise. As the voltage between terminals Vds increases, the first voltage dividing value VA and the second voltage dividing value VB also increase. However, the ascending speed of the second partial pressure value VB is lower than the ascending speed of the first partial pressure value VA. Therefore, although the first voltage dividing value VA instantly follows the terminal voltage Vds when the surge voltage is generated, the second voltage dividing value VB has a terminal voltage Vds as compared with the first voltage dividing value VA. Follow slowly.

After that, at time t2, the terminal voltage Vds reaches the peak value. This peak value is held by the peak hold circuit 63 as a surge voltage.

After the surge voltage is generated, the voltage Vds between the terminals of the switch SW drops to the power supply voltage VDC at time t3. After that, at time t4 when a predetermined time has elapsed from time t1, the correction value ΔV is calculated based on the pre-correction peak voltage Vpr and the first and second divided voltage values VA and VB at time t4. For a predetermined time, after the switch SW is switched to the off state, the first and second voltage dividing values VA and VB are in a steady state, and the first and second voltage divider values VA and VB are substantially constant according to the power supply voltage. It is set to a value time.

As shown in FIGS. 3 (c) and 3 (d) and FIG. 4, the time t2 when the terminal voltage Vds becomes the surge voltage Vsurge with respect to the first voltage dividing value VA at the time t4 when the terminal voltage Vds becomes the power supply voltage VDC. The ratio of the first voltage dividing value VA (corrected peak voltage Vpr) in is the same as the ratio of the voltage to be obtained (corrected peak voltage Vpc) at the time t4 to the second voltage dividing value VB at the time t4. Therefore, the value obtained by multiplying the voltage detection error e (= VB-VA) by the conversion coefficient k as the ratio can be set as the correction value ΔV.

In the present embodiment described in detail above, when the voltage between the terminals of the switch SW is in a steady state, the surge voltage based on the voltage dividing value by the resistor is rather than the detection accuracy of the surge voltage based on the voltage dividing value by the capacitor. It is based on the fact that the detection accuracy of is higher. In the present embodiment, the second voltage dividing value VB obtained by dividing the voltage between the terminals of the switch SW in the off state by the resistors 71a and 71b is the first voltage divided by the capacitors 61 and 62. It can be used as a reference value for grasping the detection error between the surge voltage based on the value VA and the surge voltage based on the second voltage dividing value VB. Therefore, according to the present embodiment in which the corrected peak voltage Vpc is calculated, the surge voltage detection accuracy can be improved.

<Modification 1 of the first embodiment>
An example of how to use the corrected peak voltage Vpc calculated by the above method will be described with reference to FIG.

The drive circuit Dr includes a discharge resistor 54 and an amplifier 53. The discharge resistor 54 is configured so that the resistance value can be variably set. The collector of the second switch 52 is connected to the first end of the discharge resistor 54, and the source of the switch SW is connected to the second end of the discharge resistor 54. The corrected peak voltage Vpc output from the surge voltage detection circuit 60 is input to the non-inverting input terminal of the amplifier 53. The target value Vstgt is input to the inverting input terminal of the amplifier 53. The target value Vstgt is a value for setting the switching speed when the switch SW is switched to the off state to the target speed.

The resistance value of the discharge resistor 54 is set to a value corresponding to the difference between the corrected peak voltage Vpc and the target value Vstgt. After the switch SW is switched to the off state, the resistance value of the discharge resistor 54 in the next discharge process is set based on the corrected peak voltage Vpc based on the surge voltage generated by the switch to the off state. Will be done. As a result, the surge voltage generated when the switch SW is switched to the off state can be feedback-controlled to a desired value. As a result, the switching speed can be increased, and thus the switching loss can be reduced.

<Modification 2 of the first embodiment>
When the drive control unit 50 determines that the corrected peak voltage Vpc calculated by the above method exceeds a predetermined threshold value, for example, the drive control unit 50 may perform a process of notifying the control device 40 to that effect.

<Second Embodiment>
Hereinafter, the second embodiment will be described with reference to the drawings, focusing on the differences from the first embodiment. In the present embodiment, as shown in FIG. 6, the configuration of the peak hold circuit 80 as the peak hold portion is changed. In FIG. 6, some configurations having the same configuration as that shown in FIG. 2 above are designated by the same reference numerals for convenience.

The peak hold circuit 80 includes a lower capacitor 81, an upper capacitor 82, a diode 83, a first discharge switch 84, and a second discharge switch 85. In the present embodiment, the first and second discharge switches 84 and 85 are N-channel MOSFETs.

The drain of the switch SW is connected to the first end of the upper capacitor 82, and the anode of the diode 83 is connected to the second end of the upper capacitor 82. The source of the switch SW is connected to the first end of the lower capacitor 81, and the cathode of the diode 83 is connected to the second end of the lower capacitor 81.

The second end of the lower capacitor 81 is connected to the drain of the first discharge switch 84, and the source of the switch SW is connected to the source of the first discharge switch 84. The second end of the upper capacitor 82 is connected to the drain of the second discharge switch 85, and the source of the switch SW is connected to the source of the second discharge switch 85. The first discharge switch 84 and the second discharge switch 85 are turned on or off by the drive control unit 50.

The potential of the connection point between the diode 83 and the lower capacitor 81 with respect to the potential of the first end (source of the switch SW) of the lower capacitor 81 is output from the peak hold circuit 80 as the uncorrected peak voltage Vpr. The pre-correction peak voltage Vpr is output to the subtractor 72, the divider 73, and the correction unit 64. The uncorrected peak voltage Vpr of this embodiment is expressed by the following equation (eq2). In the following equation (eq2), Vf indicates the amount of voltage drop in the diode 83.

なお、下側コンデンサ８１の静電容量をＣ１とし、上側コンデンサ８２の静電容量をＣ２とする。本実施形態では、「Ｃ１／Ｃ２＝Ｒ２／Ｒ１」となるように、各コンデンサ８１，８２の静電容量Ｃ１，Ｃ２及び各抵抗体７１ａ，７１ｂの抵抗値Ｒ１，Ｒ２が設定されている。

The capacitance of the lower capacitor 81 is C1, and the capacitance of the upper capacitor 82 is C2. In this embodiment, the capacitances C1 and C2 of the capacitors 81 and 82 and the resistance values R1 and R2 of the resistors 71a and 71b are set so that "C1 / C2 = R2 / R1".

When the discharge switches 84 and 85 are turned off and a surge voltage is generated, electric charges are accumulated in the capacitors 81 and 82. Here, the diode 83 holds the charge stored in the lower capacitor 81. Therefore, the peak value of the voltage Vds between the terminals of the switch SW is held by the peak hold circuit 80 as a surge voltage.

However, even if the switch SW is switched on, the charge of each of the capacitors 81 and 82 is retained by the diode 83. Therefore, in order to discharge the electric charge and prepare for the detection of the next surge voltage, it is necessary to turn on the discharge switches 84 and 85 while the switch SW is turned on.

Subsequently, the driving mode of each of the discharge switches 84 and 85 will be described with reference to FIG. 7. 7 (a) shows the transition of the drive signal G, and FIGS. 7 (b) and 7 (c) show the transition of the drive states of the first and second discharge switches 84 and 85.

In the present embodiment, the discharge switches 84 and 85 are turned on in synchronization with the periods t1 to t2 in which the drive signal G is commanded to be turned on. During the period when the drive signal G is set to the ON command and the switch SW is in the ON state, the voltage Vds between the terminals of the switch SW is set to a value close to 0. Therefore, when the first discharge switch 84 is turned on while the switch SW is turned on, both ends of the lower capacitor 81 are short-circuited with the source of the switch SW. As a result, the electric charge accumulated in the lower capacitor 81 is released, and the voltage between the terminals of the lower capacitor 81 drops. If the second discharge switch 85 is turned on while the switch SW is turned on, both ends of the upper capacitor 82 are short-circuited with the source of the switch SW. As a result, the electric charge accumulated in the upper capacitor 82 is released, and the voltage between the terminals of the upper capacitor 82 drops. As a result, the next surge voltage can be detected.

After that, when the discharge switches 84 and 85 are turned off and a surge voltage is generated, the charge accumulated in the lower capacitor 81 is retained by the diode 83. Therefore, the peak value of the voltage Vds between the terminals of the switch SW is held by the peak hold circuit 80 as a surge voltage.

In the present embodiment described above, the pair of capacitors 81 and 82 that divide the voltage between the terminals of the switch SW is also used as a component of the peak hold circuit 80. Therefore, the number of parts of the surge voltage detection circuit 60 can be reduced, and the cost of the surge voltage detection circuit 60 can be reduced.

<Modification 1 of the second embodiment>
In the second embodiment, the first and second discharge switches 84 and 85 are turned on during the entire period in which the drive signal G is turned on. Instead of this, as shown in FIG. 8, the first and second discharge switches 84 and 85 may be turned on during a part of the period when the drive signal G is turned on.

<Modification 2 of the second embodiment>
As shown in FIG. 9, the period during which the first and second discharge switches 84 and 85 are turned on is not limited to the configuration synchronized with the on command period of the drive signal G. In FIG. 9, during the period (t1 to t6) when the drive signal G is set to the ON command, the second discharge switch 85 is in the ON state after the switching timing (t2) of the second discharge switch 85 to the ON state. At the time t3 on the way, the first discharge switch 84 is switched to the on state. After that, at time t4 while the first discharge switch 84 is in the on state, the second discharge switch 85 is switched to the off state. Then, at time t5, the first discharge switch 84 is switched to the off state.

If the timing for switching the second discharge switch 85 to the ON state is later than the timing for switching the first discharge switch 84 to the ON state during the period when the switch SW is in the ON state, the lower capacitor 81 It may not be possible to sufficiently discharge the charge from. This is because the period during which the discharge current from the upper capacitor 82 is supplied to the lower capacitor 81 during discharge becomes longer.

Further, even when the timing of switching the first discharge switch 84 to the off state is before the timing of switching the second discharge switch 85 to the off state, the lower capacitor 81 should sufficiently discharge the electric charge. May not be possible. This is because the discharge current is supplied from the upper capacitor 82 to the lower capacitor 81 after the discharge of the lower capacitor 81 is completed. If the lower capacitor 81 is not sufficiently discharged, the next surge voltage may not be properly detected.

Therefore, in this embodiment, the driving modes of the discharge switches 84 and 85 shown in FIG. 9 are adopted. As a result, the lower capacitor 81 can be sufficiently discharged before the switch SW is switched to the off state next time, and the surge voltage of the next time can be detected appropriately.

The on period of the first discharge switch 84 and the on period of the second discharge switch 85 may be different.

<Modification 3 of the second embodiment>
Instead of the driving mode of the first and second discharge switches 84 and 85 shown in FIG. 9, as shown in FIG. 10, the second discharge switch 85 is changed to the off state after the switching timing (t3). 1 The timing (t4) for switching the discharge switch 84 to the ON state may be set. Even in this case, the lower capacitor 81 can be sufficiently discharged before the switch SW is switched to the off state next time, and the surge voltage of the next time can be detected appropriately.

The on period of the first discharge switch 84 and the on period of the second discharge switch 85 may be different.

<Third Embodiment>
Hereinafter, the third embodiment will be described with reference to the drawings, focusing on the differences from the second embodiment. In this embodiment, as shown in FIG. 11, the peak hold circuit 80 includes a bypass switch 86 and a sample hold circuit 87. In FIG. 11, some of the same configurations as those shown in FIG. 6 are designated by the same reference numerals for convenience.

The second end of the upper capacitor 82 is connected to the first end of the bypass switch 86, and the second end of the lower capacitor 81 is connected to the second end of the bypass switch 86. The bypass switch 86 is turned on or off by the drive control unit 50.

The sample hold circuit 87 is connected to the connection point between the second end of the lower capacitor 81 and the cathode of the diode 83. The sample hold circuit 87 holds the pre-correction peak voltage Vpr of the peak hold circuit 80 at the input timing of the hold signal HOLD output from the drive control unit 50.

Subsequently, the correction method of the pre-correction peak voltage Vpr will be further described with reference to FIG. 12 (e) and 12 (f) show the transition of the drive state of the first and second discharge switches 84 and 85, and FIG. 12 (g) shows the transition of the drive state of the bypass switch 86. It should be noted that FIGS. 12 (a) to 12 (d) correspond to FIGS. 3 (a) to 3 (d) above.

At time t1, the discharge switches 84 and 85 are switched to the off state. Further, the drive signal G is switched to the off command. As a result, the gate voltage Vgs begins to decrease. Further, the voltage Vds between the terminals of the switch SW begins to rise. As the voltage between terminals Vds increases, the first voltage dividing value VA and the second voltage dividing value VB also increase. After that, at time t2, the terminal voltage Vds reaches the peak value. This peak value is held by the peak hold circuit 80 as a surge voltage. After the surge voltage is generated, the voltage Vds between the terminals of the switch SW drops to the power supply voltage VDC at time t3.

After that, the hold signal HOLD is output at the time t4 when the predetermined time has elapsed from the time t1. Therefore, the sample hold circuit 87 holds the first partial pressure value VA at time t2. Then, at time t5, the bypass switch 86 is switched to the ON state. Therefore, the anode and cathode of the diode 83 are short-circuited by the bypass switch 86, and the uncorrected peak voltage Vpr output from the peak hold circuit 80 drops to the value obtained by dividing the power supply voltage VDC by the capacitors 81 and 82. .. The pre-correction peak voltage Vpr is used in the subtractor 72 and the divider 73, and the correction value ΔV is calculated. Then, by the time the switch SW discharge process is performed next time, the pre-correction peak voltage Vpr is corrected by the correction unit 64 with the calculated correction value ΔV.

The bypass switch 86 may be switched to the off state after the bypass switch 86 is turned on and before the switch SW is switched to the off state next time.

According to the present embodiment described above, the same effect as that of the second embodiment can be obtained.

<Fourth Embodiment>
Hereinafter, the fourth embodiment will be described with reference to the drawings, focusing on the differences from the first embodiment. In the present embodiment, as shown in FIG. 13, in the correction value calculation unit 70, the first main resistor 12a and the second main resistor 12b are used instead of the lower resistor 71a and the upper resistor 71b. In the present embodiment, the voltage between the terminals of the smoothing capacitor 11 divided by the main resistors 12a and 12b is referred to as a second voltage dividing value VB. This voltage dividing value VB is a voltage that correlates with the voltage Vds between the terminals of the switch SW that is in the off state, and is used in the subtractor 72.

The resistance value of the first main resistor 12a is R1, and the resistance value of the second main resistor 12b is R2. In this embodiment, the capacitances C1 and C2 of the capacitors 61 and 62 and the resistance values R1 and R2 of the resistors 12a and 12b are set so that "C1 / C2 = R2 / R1".

According to the present embodiment described above, since the power supply voltage detection unit 12 is used as the configuration of the correction value calculation unit 70, the number of parts of the surge voltage detection circuit 60 can be reduced.

<Other embodiments>
In addition, each of the above-mentioned embodiments may be changed and carried out as follows.

In the first embodiment, the correction value calculation unit 70 calculates a conversion coefficient by dividing the second voltage dividing value VB by the first voltage dividing value VA, and multiplies this conversion coefficient by the uncorrected peak voltage Vpr. Therefore, the correction value ΔV may be calculated.

In the first embodiment, the capacitances C1 and C2 of the capacitors 61 and 62 and the resistance values R1 and R2 of the resistors 71a and 71b are set so as not to be "C1 / C2 = R2 / R1". You may. The same applies to the second to fourth embodiments.

The surge voltage detection circuit 60 is not limited to the one externally attached to the drive control unit 50, and may be, for example, one built in the drive control unit 50.

-The switch is not limited to the N-channel MOSFET, and may be another switch such as an IGBT, for example. When an IGBT is used as a switch, the collector corresponds to the high potential side terminal and the emitter corresponds to the low potential side terminal.

-The power converter equipped with the switch SW is not limited to the three-phase one.

The correction value ΔV may be stored in a storage unit such as a non-volatile memory included in the drive circuit Dr. In the storage unit, for example, the correction value ΔV is stored as storage information in relation to the first and second voltage dividing values VA and VB and the pre-correction peak voltage Vpr. The stored information is stored, for example, in the manufacturing process of the drive circuit Dr. The drive control unit 50 calculates the correction value ΔV based on the respective voltage dividing values VA, VB, the pre-correction peak voltage Vpr, and the storage information of the storage unit at the time t4 in FIG. The drive control unit 50 calculates the corrected peak voltage Vpc by adding the calculated correction value ΔV to the pre-correction peak voltage Vpr. According to this configuration, for example, the correction value calculation unit 70 becomes unnecessary, and the number of parts of the drive circuit Dr can be reduced.

61 ... lower capacitor, 62 ... upper capacitor, 71a ... lower resistor, 71b ... upper resistor, 60 ... surge voltage detection circuit, 63 ... peak hold circuit, 64 ... correction unit, SW ... switch.

Claims (9)

In the surge voltage detection circuit (60) that detects the surge voltage generated when the switch (SW) is switched to the off state.
A plurality of capacitors (61,62,81,82) connected between the high-potential side terminal and the low-potential side terminal of the switch and dividing the voltage between the terminals of the switch, and
A plurality of resistors (71a, 71b, 12a, 12b) that divide the voltage between the terminals of the switch that is turned off or the voltage that correlates with the voltage between the terminals, and
A peak holding unit (63, 80) that holds the peak value of the partial pressure value of the plurality of capacitors, and
A surge voltage detection circuit including a correction unit (64) that corrects a voltage held by the peak holding unit based on a voltage dividing value by the plurality of resistors. The plurality of the capacitors (81, 82) are included in the peak holding portion (80).
The plurality of the capacitors are
An upper capacitor (82) whose first end is connected to the high potential side terminal of the switch, and
Includes a lower capacitor (81), the first end of which is connected to the low potential side terminal of the switch.
The peak holding portion is
A diode (83) having an anode connected to the second end of the upper capacitor and a cathode connected to the second end of the lower capacitor.
When turned on, the second end of the lower capacitor and the low potential side terminal of the switch are brought into a conductive state, and when turned off, the second end of the lower capacitor and the said are said. The first discharge switch (84) that cuts off between the low potential side terminal of the switch and
When it is turned on, the second end of the upper capacitor and the low potential side terminal of the switch are made conductive, and when it is turned off, the second end of the upper capacitor and the switch are connected. It has a second discharge switch (85) that cuts off between the low potential side terminal, and the peak value of the potential difference at the connection point between the lower capacitor and the diode with respect to the low potential side terminal of the switch. The surge voltage detection circuit according to claim 1. The surge voltage detection circuit according to claim 2, wherein the first discharge switch and the second discharge switch are turned on during at least a part of the period in which the switch is turned on. During the period in which the switch is in the on state, the timing for switching the second discharge switch to the on state is not later than the timing for switching the first discharge switch to the on state, and The surge voltage detection circuit according to claim 3, wherein the timing of switching the first discharge switch to the off state does not precede the timing of switching the second discharge switch to the off state. The peak holding portion is
A bypass switch (86) that puts the diode between the anode and the cathode in a conductive state by turning it on, and shuts off between the anode and the cathode of the diode by turning it off.
2. The surge voltage detection circuit described. A correction value calculation unit (70) that calculates a correction value for correcting the voltage held by the peak holding unit based on the voltage dividing value by the plurality of resistors and the voltage held by the peak holding unit. )
The surge voltage detection circuit according to any one of claims 1 to 5, wherein the correction unit corrects the voltage held by the peak holding unit based on the calculated correction value. The correction value calculation unit is
A subtractor (72) for calculating the difference between the voltage held by the peak holding portion and the voltage dividing value due to the plurality of resistors.
It has a divider 73 for calculating the ratio between the voltage held by the peak holding unit and the voltage dividing value by the plurality of resistors, and the difference calculated by the subtractor and calculated by the divider. The surge voltage detection circuit according to claim 6, wherein the correction value is calculated based on the ratio. The surge voltage detection circuit according to any one of claims 1 to 7, wherein the plurality of resistors (71a, 71b) divide the voltage between terminals of the switch that is turned off. In the surge voltage detection circuit applied to the inverter (20) including the upper arm switch and the lower arm switch connected in series as the switch.
The plurality of resistors (12a, 12b) divide the power supply voltage of the inverter applied to the series connection of the upper arm switch and the lower arm switch as a voltage correlating with the voltage between the terminals of the switch. The surge voltage detection circuit according to any one of claims 1 to 7.

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