JP6954333B2 - Semiconductor device - Google Patents

Description

In the present invention, an IGBT region in which an insulated gate type electric field effect transistor (hereinafter referred to as an IGBT (Insulated Gate Bipolar Transistor)) is formed and a diode region in which a freewheeling diode (hereinafter referred to as FWD (Free Wheeling Diode)) is formed are provided. Regarding the semiconductor device to have.

Conventionally, for example, as a switching element such as an inverter, a semiconductor device having an RC-IGBT (abbreviation of Reverse-Conducting IGBT) structure having an FWD on one chip together with an IGBT has been used.

In this RC-IGBT, a large reverse current transiently flows during the recovery operation. In particular, at the boundary between the IGBT region and the diode region, as shown in Patent Document 1, from a high-concentration P-type region such as a channel formed on the front surface side of the IGBT region to the back surface side of the diode region. Holes are injected toward the formed N-type cathode layer. Since the injection of holes causes an increase in the maximum reverse current Irr during recovery, it is desirable to suppress the injection amount of holes. Therefore, in the semiconductor device described in Patent Document 1, a second anode layer having a constant P-type impurity concentration is provided in the first anode layer in the diode region. By increasing the concentration of P-type impurities in the second anode layer to some extent, latch-up is suppressed, and by not making it too high, the injection amount of holes is suppressed, enabling high-speed switching and switching loss. I am trying to reduce it.

Japanese Unexamined Patent Publication No. 2015-109341

However, in the configuration of Patent Document 1, since the IGBT region and the diode region are arranged adjacent to each other, it is possible to inject holes from a high-concentration P-type region such as a channel formed on the surface side of the IGBT region. It cannot be sufficiently suppressed. Therefore, the switching loss cannot be sufficiently reduced. In addition, a high carrier density on the cathode side leads to an increase in tail current, which may lead to recovery destruction.

In view of the above points, it is an object of the present invention to provide a semiconductor device capable of further suppressing carrier injection from the IGBT region side to the diode region side during recovery.

In order to achieve the above object, the semiconductor device according to claim 1 has an IGBT region (1a) in which an IGBT is formed and a diode region (1b) in which a diode is formed, and an IGBT region and a diode region. Drift in the first conductive type drift layer (11) having a boundary region (1c) to be formed, the second conductive type base layer (12) formed on the surface layer of the drift layer, and the IGBT region. The second conductive type collector layer (21) formed on the side opposite to the base layer side of the layer, and the first formed on the side opposite to the base layer side of the drift layer in the diode region and the boundary region. conductivity-type cathode layer (22), a second conductivity type discrete layer which is partially disposed Oite cathode layer in the diode area (24), by using a semiconductor substrate (10) including a configured ..

In the IGBT region, the diode region, and the boundary region, a gate insulating film (16) is formed in a plurality of trenches (13) in which one direction is the longitudinal direction and the base layer is formed deeper than the base layer. ) And the gate electrode (17) are arranged to form a trench gate structure. Further, the base layer in the IGBT region is used as the first base layer (12a), and the first conductive type emitter region formed in contact with the trench in at least a part of the first base layer divided into a plurality by the trench. (14) and a first contact region (15a) arranged in a portion of the first base layer different from the emitter region are formed. Further, the base layer in the diode region and the boundary region is used as the second base layer (12b), and is formed on the surface layer portion of the second base layer in the diode region, and the concentration of the second conductive type impurities is higher than that of the second base layer. In the second conductive type second contact region (15b) and the boundary region formed, the second conductive type impurity concentration was higher than that of the second base layer, which was formed on the surface layer of the second base layer. A two conductive type third contact region (15c) is formed. Then, in addition to the emitter region, the upper electrode (19) is electrically connected to the first contact region, the second contact region, and the third contact region, and the lower electrode (23) is electrically connected to the collector layer and the cathode layer. Has been done. In such a configuration, the formation area of the third contact region is smaller than the formation area of the second contact region per unit area of the surface of the semiconductor substrate.

In this way, a boundary region is provided between the IGBT region and the diode region, that is, at a position adjacent to the diode region, where the formation ratio of the high-concentration second conductive type layer is smaller than that of the IGBT region. Therefore, during recovery, carrier injection from the IGBT region to the diode region can be suppressed, and since the formation ratio of the high-concentration second conductive type layer formed in the boundary region is small, the high-concentration second conductive type in the boundary region is formed. The amount of carrier injected from the layer can also be reduced. Therefore, it is possible to obtain a semiconductor device capable of further suppressing carrier injection from the IGBT region side to the diode region side during recovery.

The reference numerals in parentheses of each of the above means indicate an example of the correspondence with the specific means described in the embodiment described later.

It is a top layout view of the semiconductor device which concerns on 1st Embodiment. FIG. 5 is a perspective cross-sectional view of a cross section of a semiconductor substrate cut along the line II-II of FIG. FIG. 2 is a cross-sectional view taken along the line IIIA-IIIA of FIG. FIG. 2 is a cross-sectional view taken along the line IIIB-IIIB of FIG. It is a figure which showed the flow of the hole at the time of the IGBT operation of the semiconductor device which concerns on 1st Embodiment. It is a figure which showed the reverse-direction current characteristic of the semiconductor device which concerns on 1st Embodiment, and the semiconductor device of a conventional structure. It is a perspective sectional view of the semiconductor substrate which comprises the semiconductor device which concerns on 2nd Embodiment. It is a perspective sectional view of the semiconductor substrate which comprises the semiconductor device which concerns on 3rd Embodiment. It is a perspective sectional view of the semiconductor substrate which comprises the semiconductor device which concerns on the modification of 3rd Embodiment. It is a perspective sectional view of the semiconductor substrate which comprises the semiconductor device which concerns on 4th Embodiment. It is a perspective sectional view of the semiconductor substrate which comprises the semiconductor device which concerns on 5th Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, parts that are the same or equal to each other will be described with the same reference numerals.

(First Embodiment)
The semiconductor device according to the first embodiment of the present invention will be described. The semiconductor device according to this embodiment is configured by an RC-IGBT structure in which a vertical IGBT and an FWD for passing a current in the thickness direction of the substrate are provided on one substrate. This semiconductor device is preferably used as a power switching element used in a power supply circuit such as an inverter or a DC / DC converter. Specifically, the semiconductor device according to this embodiment is configured as follows.

As shown in FIG. 1, the semiconductor device includes a cell region 1 and an outer peripheral region 2 surrounding the cell region 1.

In the cell region 1, as shown in FIGS. 1, 2, 3A and 3B, the IGBT region 1a in which the IGBT element is formed and the diode region 1b in which the FWD is formed are alternately formed. Further, the boundary region 1c is formed between the IGBT region 1a and the diode region 1b.

Specifically, the IGBT region 1a, the diode region 1b, and the boundary region 1c are ^{formed on the N-} type semiconductor substrate 10 that functions as the drift layer 11 as shown in FIGS. 2, 3A, and 3B. It is made up of one chip. The IGBT region 1a, the diode region 1b, and the boundary region 1c extend along one direction of one surface 10a of the semiconductor substrate 10, that is, in the vertical direction of the paper surface in FIG. Then, the IGBT region 1a and the diode region 1b are alternately and repeatedly formed in the direction orthogonal to the extension direction, and the boundary region 1c is formed between them.

A P-shaped base layer 12 is formed on the drift layer 11, that is, on the one side 10a side of the semiconductor substrate 10. Then, a plurality of trenches 13 are formed so as to penetrate the base layer 12 and reach the drift layer 11, and the base layer 12 is separated into a plurality of trenches 13 by the trench 13.

In the present embodiment, the plurality of trenches 13 are formed at equal intervals along one of the surface directions of one surface 10a of the semiconductor substrate 10, or, in FIG. 2, the depth direction of the paper surface. Further, one surface 10a of the semiconductor substrate 10 is composed of one surface of the base layer 12 opposite to the drift layer 11.

In the base layer 12, the P-type impurity concentration is changed between the IGBT region 1a, the diode region 1b, and the boundary region 1c. In the IGBT region 1a, the P-type impurity concentration is higher than that of the diode region 1b and the boundary region 1c. There is. Hereinafter, the base layer 12 formed in the IGBT region 1a is referred to as a first base layer 12a, and the base layer 12 formed in the diode region 1b and the boundary region 1c is referred to as a second base layer 12b.

The first base layer 12a functions as a body region as well as a channel region. ^{As shown in FIGS. 2 and 3B, an N +} type emitter region 14 having a depth shallower than that of the first base layer 12a is partially formed on the surface layer portion of the first base layer 12a. There is.

The emitter region 14 is configured to have a higher impurity concentration than the drift layer 11, is terminated in the first base layer 12a, and is formed so as to be in contact with the side surface of the trench 13. In the case of the present embodiment, a plurality of emitter regions 14 are scattered among the trenches 13 at equal intervals along the longitudinal direction of the trench 13. In other words, the emitter region 14 extends so as to intersect the longitudinal directions of the plurality of trenches 13 when viewed from the normal direction with respect to one surface 10a of the semiconductor substrate 10, and more specifically to be orthogonal to each other. .. Then, each emitter region 14 located between the plurality of trenches 13 is in contact with both side surfaces of the adjacent trenches 13.

In the direction perpendicular to the longitudinal direction of the plurality of trenches 13, when the adjacent emitter regions 14 are connected, they are linear, but since they are divided by the trenches 13, each emitter region 14 has a rectangular shape. ing. Each emitter region 14 is arranged inside the trench 13 from both ends in the longitudinal direction.

Further, the first base layer 12a is formed up to one surface 10a side of the semiconductor substrate 10 in a portion where the emitter region 14 is not formed, and this portion is in ohmic contact with the upper electrode 19 described later in the first contact region 15a. It is said that. The width of the first contact region 15a in the longitudinal direction of the trench 13 is equal to, for example, the width of the emitter region 14 in the same direction, and their area ratio is 1: 1.

The first contact region 15a is composed of a part of the first base layer 12a, but may be a region in which the surface density is partially increased. In the case of the present embodiment, the first contact region 15a has the same upper surface layout as the emitter region 14 when viewed from the normal direction with respect to one surface 10a of the semiconductor substrate 10, and the portion not designated as the emitter region 14 is the first. It is defined as one contact area 15a. That is, the first contact region 15a is extended so as to intersect the longitudinal direction of the plurality of trenches 13 and more specifically to be orthogonal to each other, and each first contact located between the plurality of trenches 13 is located between the plurality of trenches 13. The region 15a is in contact with both side surfaces of the adjacent trench 13.

In the direction perpendicular to the longitudinal direction of the plurality of trenches 13, when the adjacent first contact regions 15a are connected, they form a straight line, but since they are divided by the trenches 13, each of the first contact regions 15a is divided. It has a rectangular shape.

The second base layer 12b constitutes an anode layer that functions as a part of the anode in the diode region 1b. Although the emitter region 14 like the IGBT region 1a is not formed in the second base layer 12b in the diode region 1b, the P-type impurity concentration is higher than that in the second base layer 12b, and the upper electrode 19 and ohmic described later are described. A second contact region 15b to be contacted is formed. In the case of the present embodiment, a plurality of second contact regions 15b are scattered along the longitudinal direction of the trench 13. In other words, the second contact region 15b is extended so as to intersect the longitudinal direction of the plurality of trenches 13 when viewed from the normal direction with respect to one surface 10a of the semiconductor substrate 10, and more specifically to be orthogonal to each other. ing. Then, each second contact region 15b located between the plurality of trenches 13 is in contact with both side surfaces of the adjacent trenches 13. The depth of each second contact region 15b is shallower than that of the second base layer 12b. Further, the width of each second contact region 15b, that is, the dimension in the same direction as the longitudinal direction of the trench 13 is arbitrary, but in the case of the present embodiment, it is equal to the first contact region 15a. In this case, the area ratio of the second contact region 15b to the portion of the second base layer 12b where the second contact region 15b is not formed is 1: 1.

Further, since the second base layer 12b of the boundary region 1c is a portion forming the boundary between the IGBT region 1a and the diode region 1b, it does not have to function in particular. However, the formation of the boundary region 1c may reduce the amount of energization per unit area, and as a result, the on-voltage Von may increase and the on-resistance may increase. In order to suppress this, in the present embodiment, the second base layer 12b of the boundary region 1c is made to function as a hole passing layer during the IGBT operation. This will be explained later.

Further, the second base layer 12b in the boundary region 1c also has a third contact region 15c which has a higher P-type impurity concentration than the second base layer 12b and is in ohmic contact with the upper electrode 19 described later. In the case of the present embodiment, a plurality of third contact regions 15c are scattered along the longitudinal direction of the trench 13. In other words, the third contact region 15c is extended so as to intersect the longitudinal direction of the plurality of trenches 13 when viewed from the normal direction with respect to one surface 10a of the semiconductor substrate 10, and more specifically to be orthogonal to each other. ing. Then, each third contact region 15c located between the plurality of trenches 13 is in contact with both side surfaces of the adjacent trenches 13. In the case of the present embodiment, the depth of the third contact region 15c is equal to the depth of the second contact region 15b. Further, the width of each third contact region 15c, that is, the dimension in the same direction as the longitudinal direction of the trench 13, is arbitrary, but is narrower than that of the second contact region 15b. For example, here, the dimensions of the third contact region 15c are set so that the area ratio of the third contact region 15c to the portion of the second base layer 12b where the third contact region 15c is not formed is 1: 2. It has been set.

As described above, the second contact region 15b and the third contact region 15c are formed in the diode region 1b and the boundary region 1c. Then, by changing the formation area of the second contact region 15b and the third contact region 15c, the formation ratio of the high-concentration P-type layer per unit area and the ohmic contact area ratio are changed. Here, since the width of the third contact region 15c is narrower than that of the second contact region 15b, the boundary region 1c has a higher concentration P-type layer formation ratio per unit area than the diode region 1b. And ohmic contact area ratio is reduced. Further, the second base layer 12b of the boundary region 1c has a lower P-type impurity concentration than the first base layer 12a formed in the IGBT region 1a, and the width of the third contact region 15c is also narrowed. Therefore, the boundary region 1c has a smaller ratio of high-concentration P-type layer formation and ohmic contact area ratio per unit area than the IGBT region 1a.

Further, the inside of each trench 13 is composed of a gate insulating film 16 formed so as to cover the inner wall surface of each trench 13 and a gate electrode 17 formed of polysilicon or the like formed on the gate insulating film 16. It is embedded. As a result, a trench gate structure is constructed.

The gate electrode 17 is controlled to a desired gate voltage in the IGBT region 1a, and is connected to an emitter in the diode region 1b. As a result, in the IGBT region 1a, when a high level voltage is applied as the gate voltage for the IGBT operation, a channel is formed on the side surface of the trench 13. Further, in the diode region 1b, since the gate electrode 17 is used as the emitter potential, no channel is formed even during the IGBT operation, and a predetermined FWD operation is performed.

Further, in the present embodiment, the gate electrode 17 in the boundary region 1c has the same potential as the gate electrode 17 in the IGBT region 1a, and is controlled to a desired gate voltage. Therefore, even in the boundary region 1c, a channel is formed on the side surface of the trench 13, and holes easily flow through the channel, and holes attracted to the channel side also flow through the second base layer 12b. Therefore, as described above, in the boundary region 1c, the second base layer 12b functions as a hole passing layer, and it is possible to suppress a decrease in the amount of energization per unit area due to the presence of the boundary region 1c. Therefore, it is possible to suppress an increase in the on-voltage Von and suppress an increase in the on-resistance.

Further, as shown in FIGS. 3A and 3B, an interlayer insulating film 18 composed of BPSG or the like is formed on the base layer 12 on the one side 10a side of the semiconductor substrate 10. A contact hole 18a is formed in the interlayer insulating film 18 to expose a part of the emitter region 14 and the first contact region 15a in the IGBT region 1a. Further, in the interlayer insulating film 18, contact holes 18b and 18c are formed in the diode region 1b and the boundary region 1c to expose the second base layer 12b, the second contact region 15b and the third contact region 15c.

An upper electrode 19 is formed on the interlayer insulating film 18. The upper electrode 19 is electrically connected to the emitter region 14 and the first contact region 15a via the contact hole 18a in the IGBT region 1a. Further, the upper electrode 19 is electrically connected to the second base layer 12b, the second contact region 15b, and the third contact region 15c via the contact holes 18b and 18c in the diode region 1b and the boundary region 1c. That is, the upper electrode 19 functions as an emitter electrode in the IGBT region 1a and functions as an anode electrode in the diode region 1b. Further, the upper electrode 19 does not have to function particularly in the boundary region 1c, but as described above, in the present embodiment, the gate electrode 17 is controlled to the same gate voltage as the IGBT region 1a in the boundary region 1c. Therefore, it functions as a hole extraction electrode.

Further, the upper electrode 19 is in ohmic contact with the second contact region 15b and the third contact region 15c in the diode region 1b and the boundary region 1c, and is in Schottky contact with the second base layer 12b. Therefore, the structure is such that the ohmic contact area ratio is changed stepwise from the boundary region 1c adjacent to the IGBT region 1a to the diode region 1b further away. That is, the layout is such that the IGBT region 1a passes through the boundary region 1c having a small ohmic contact area ratio and then reaches the diode region 1b.

On the other hand, on the side of the drift layer 11 opposite to the base layer 12 side, that is, on the other surface 10b side of the semiconductor substrate 10, a field stop (hereinafter referred to as FS) layer having an N-type impurity concentration higher than that of the drift layer 11 20 is formed. Although the FS layer 20 is not essential, the depletion layer is prevented from spreading to improve the performance of withstand voltage and steady loss, and the injection amount of holes injected from the other surface 10b side of the semiconductor substrate 10 is controlled. Be prepared to do.

Further, in the IGBT region 1a and the boundary region 1c, a P-type collector layer 21 is formed on the opposite side of the drift layer 11 with the FS layer 20 sandwiched between them, and in the diode region 1b, the drift layer 11 sandwiches the FS layer 20. An N-shaped cathode layer 22 is formed on the opposite side. That is, in the present embodiment, the IGBT region 1a, the boundary region 1c, and the diode region 1b are partitioned by whether the layer formed on the other surface 10b side of the semiconductor substrate 10 is the collector layer 21 or the cathode layer 22. ing.

Further, on the other surface 10b of the semiconductor substrate 10, a lower electrode 23 is formed on the surfaces of the collector layer 21 and the cathode layer 22. The lower electrode 23 functions as a collector electrode in the IGBT region 1a and the boundary region 1c, and functions as a cathode electrode in the diode region 1b.

With this configuration, in the IGBT region 1a, an IGBT element having the first base layer 12a as the base, the emitter region 14 as the emitter, and the collector layer 21 as the collector is configured. Further, in the diode region 1b, a PN-junctioned FWD element is configured in which the second base layer 12b and the second contact region 15b are used as anodes, and the drift layer 11 and the cathode layer 22 are used as cathodes.

The operation and effect of the semiconductor device having the IGBT element and the FWD element configured as described above will be described.

In the semiconductor device of the present embodiment, for the IGBT formed in the IGBT region 1a, the applied voltage to the gate electrode 17 is controlled as in the conventional case to perform an on / off operation, that is, a current is passed or cut off between the emitter and the collector. Perform switching operation. Further, with respect to the FWD formed in the diode region 1b, the generation of surge during switching is suppressed by performing the diode operation in association with the switching operation of the IGBT.

When performing such an operation, while the IGBT is on, as shown in FIG. 4, the gate electrode 17 in the boundary region 1c is also controlled to the same gate voltage as the IGBT region 1a, so that the trench in the boundary region 1b Channels are formed on the sides of the thirteenth. Therefore, even in the boundary region 1c, a channel is formed on the side surface of the trench 13, and holes easily flow through the channel, and holes attracted to the channel side also flow through the second base layer 12b. Therefore, in the boundary region 1c, the second base layer 12b functions as a hole passage layer, and the decrease in the amount of energization per unit area due to the presence of the boundary region 1c can be suppressed, so that the increase in the on-voltage Von can be suppressed. It is possible to suppress an increase in on-resistance.

Further, if the formation ratio of the high-concentration P-type layer on the one side 10a side of the semiconductor substrate 10 is large at the position adjacent to the diode region 1b, the high-concentration P-type layer is generated during recovery when the IGBT is switched from off to on. The amount of holes injected from the layer to the cathode increases. This causes an increase in the maximum reverse current Irr during recovery. In addition, the higher carrier density on the cathode side increases the tail current, which may lead to recovery failure.

However, in the semiconductor device of the present embodiment, the boundary region 1c in which the formation ratio of the high-concentration P-type layer is smaller than that in the IGBT region 1a is formed between the IGBT region 1a and the diode region 1b, that is, at a position adjacent to the diode region 1b. It is provided. Therefore, at the time of recovery, hole injection from the IGBT region 1a to the diode region 1b can be suppressed, and since the formation ratio of the high-concentration P-type layer formed in the boundary region 1c is small, the high-concentration P-type in the boundary region 1c The amount of hole injected from the layer can also be reduced. Therefore, an increase in the maximum reverse current Irr during recovery can be suppressed, and an increase in the tail current can be suppressed by lowering the carrier density on the cathode side. As a result, not only the switching loss can be reduced, but also the semiconductor device having high resistance to recovery failure can be obtained.

Specifically, when the maximum reverse current Irr was examined for the semiconductor device having the conventional structure and the structure of the present embodiment, the results shown in FIG. 5 were obtained. Compared with the case of the conventional structure shown by the broken line in the figure, in the case of the structure of the present embodiment shown by the solid line in the figure, the maximum reverse current Irr could be reduced. Then, since the integrated value of the reverse current Ir in this figure, that is, the area of the region where the current value is negative corresponds to the recovery loss Err, the recovery loss Err can be reduced by reducing the maximum reverse current Irr. It is possible to reduce it.

Further, in the present embodiment, the lifetime killer is not generated by irradiation with He beam or electron beam. Since the recovery loss Err can be reduced, it is common to generate a lifetime killer in the past, but it is difficult to separate He beam or electron beam irradiation into an accurate position, and the characteristics of other elements deteriorate. It may be invited. In order to avoid the generation of the lifetime killer by the He-ray or electron beam irradiation, it is conceivable to take measures such as reducing the impurity concentration of the drift layer 11 and the base layer 12. However, if the impurity concentration is reduced, the difference in impurity concentration at the PN junction with the high concentration region where the impurity concentration is increased becomes large, which increases the tail current and causes recovery destruction.

On the other hand, as in the semiconductor device of the present embodiment, by providing the boundary region 1c having the above configuration, hole injection from the IGBT region 1a to the diode region 1b can be suppressed at the time of recovery, so that the drift layer 11 and the base can be suppressed. The impurity concentration of the layer 12 can be reduced. Therefore, it is not necessary to generate a lifetime killer by irradiating with a He ray or an electron beam, and it is possible to suppress deterioration of the characteristics of other elements.

(Second Embodiment)
The second embodiment will be described. In this embodiment, the connection form of the gate electrode 17 in the boundary region 1c is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Only explain.

As shown in FIG. 6, in the present embodiment, the gate electrode 17 in the boundary region 1c is an emitter connection like the gate electrode 17 in the diode region 1b. In this way, when the gate electrode 17 of the boundary region 1c is connected to the emitter, when the IGBT is turned on, a channel is not formed on the side surface of the trench 13 in the boundary region 1c, so that the amount of passage of the hole through the boundary region 1c increases. Decrease. Therefore, the effect of suppressing the increase of the on-voltage Von and the effect of reducing the on-resistance cannot be obtained, but other than that, the same effect as that of the first embodiment can be obtained.

(Third Embodiment)
A third embodiment will be described. In this embodiment, the top layout of each part is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only the parts different from the first embodiment will be described.

As shown in FIG. 7, the emitter region 14 is laid out linearly along the longitudinal direction of the trench 13. Here, the emitter region 14 is arranged only on one side surface of the trench 13, specifically, on the left side surface in the drawing with respect to the trench 13, but a structure may be arranged on both side surfaces. Further, since the emitter region 14 is linear, the first contact region 15a also has a linear layout accordingly.

The same applies to the diode region 1b and the boundary region 1c, and the second contact region 15b and the third contact region 15c are laid out linearly along the longitudinal direction of the trench 13. In the case of the present embodiment, the second contact region 15b and the third contact region 15c are formed on one side surface of the trench 13, specifically, the side surface on the right side in the drawing opposite to the side surface on which the emitter region 14 is formed. Only placed. However, this is also an example, and the second contact region 15b and the third contact region 15c may be arranged on both side surfaces or at a position away from the trench 13. Further, since the second contact region 15b and the third contact region 15c are linear, the portion of the second base layer 12b that is in shot key contact with the upper electrode 19 also has a linear layout. There is.

Further, also in the present embodiment, the formation area of the second contact region 15b and the third contact region 15c, that is, the formation ratio of the high-concentration P-type layer per unit area and the ohmic contact ratio are changed between the diode region 1b and the boundary region 1c. ing.

In the case of the present embodiment, in the diode region 1b, a second contact region 15b is formed in all the second base layers 12b between the plurality of trenches 13. On the other hand, in the boundary region 1c, the third contact region 15c is not formed in all the second base layers 12b between the plurality of trenches 13, but one in each of the plurality of second base layers 12b. Inside, the third contact region 15c is formed at a ratio of one in two.

In this way, in addition to the emitter region 14 and the first contact region 15a, the second contact region 15b and the third contact region 15c can be laid out in a linear shape. Even with such a configuration, the same effect as that of the first embodiment can be obtained.

Here, the first contact region 15a, the second contact region 15b, and the third contact region 15c are all made of linear objects having the same width, but may have different widths. Further, regarding the boundary region 1c, the third contact region 15c is formed in all the second base layers 12b between the plurality of trenches 13, and the third contact region is formed in the diode region 1b rather than the second contact region 15b. The width of 15c may be narrowed.

Further, even within the boundary region 1c, the formation area of the third contact region 15c can be changed stepwise. For example, as shown in FIG. 8, the formation pitch, which is the interval at which the third contact region 15c is formed, is gradually reduced from the IGBT region 1a to the diode region 1b. By doing so, the formation area of the third contact region 15c can be made smaller on the side of the IGBT region 1a than on the side of the diode region 1b.

By changing the formation area of the third contact region 15c stepwise, the trade-off relationship between the forward voltage drop Vf of the FWD and the recovery loss Err can be adjusted. For example, if the pitch of the third contact region 15c is increased, the forward voltage drop Vf is increased, and the recovery loss Err can be reduced. On the contrary, when the pitch of the third contact region 15c is reduced, the forward voltage drop Vf is reduced and the recovery loss Err is increased. Therefore, by setting the pitch of the third contact region 15c according to the desired characteristics, the trade-off relationship between the forward voltage drop Vf and the recovery loss Err can be adjusted to the desired relationship.

(Fourth Embodiment)
A fourth embodiment will be described. This embodiment is different from the first to third embodiments in that the configurations of the diode region 1b and the boundary region 1c on the other side 10b side are changed, and the other aspects are the same as those of the first to third embodiments. Therefore, only the parts different from the first to third embodiments will be described. Although the structure of the first embodiment is described here when the configuration on the other side 10b side is changed, the structure of the second and third embodiments can also be applied.

As shown in FIG. 9, in the present embodiment, in the diode region 1b and the boundary region 1c, a P-type discrete layer 24 partially composed of a P-type impurity layer is formed on the other surface 10b side. The P-type discrete layer 24 extends, for example, along the longitudinal direction of the trench 13, and a plurality of P-type discrete layers 24 are arranged at equal intervals. The concentration of P-type impurities in the P-type discrete layer 24 is arbitrary, but when formed at the same time as the collector layer 21, the concentration is the same as that of the collector layer 21.

In this way, the P-type discrete layer 24 can be formed in the diode region 1b or the boundary region 1c. When such a P-type discrete layer 24 is formed, holes injected from the high-concentration P-type layer on the one side 10a side of the IGBT region 1a can be regarded as invalid carriers when they reach the P-type discrete layer 24. Therefore, it is possible to further reduce the number of holes, and even if the hole injection amount cannot be sufficiently suppressed only by forming the boundary region 1c and the hole injection amount becomes large, the P-type discrete layer 24 can turn a hole into an invalid carrier. Therefore, it is possible to enhance the effect described in the first embodiment.

(Fifth Embodiment)
A fifth embodiment will be described. This embodiment is different from the first to fourth embodiments in that the configurations of the diode region 1b and the boundary region 1c on the one side 10a side are changed, and the other aspects are the same as those of the first to fourth embodiments. , Only the parts different from the first to fourth embodiments will be described. Although the structure of the first embodiment is described here when the configuration on the one side 10a side is changed, the structure of the second to fourth embodiments can also be applied.

As shown in FIG. 10, in the present embodiment, an N-type discrete layer 25 composed of an N-type impurity layer is formed on the one side 10a side of the diode region 1b and the boundary region 1c. The N-type discrete layer 25 is formed at a position different from that of the second contact region 15b and the third contact region 15c in the surface layer portion of the second base layer 12b, for example. In the case of the present embodiment, the N-type discrete layer 25 is formed in the entire surface layer portion of the second base layer 12b where the second contact region 15b and the third contact region 15c are not formed. The concentration of N-type impurities in the N-type discrete layer 25 is arbitrary, but when it is formed at the same time as the emitter region 14, the concentration is the same as that of the emitter region 14.

By forming the N-type discrete layer 25 on the surface layer portion of the second base layer 12b in this way, the upper electrode 19 and the N-type discrete layer 25 can be brought into ohmic contact. That is, in order to reduce the switching loss, it is desired to reduce the concentration of P-type impurities in the second base layer 12b, the second contact region 15b, and the third contact region 15c in the diode region 1b and the boundary region 1c. It can be a shot key contact with 19. Therefore, by forming the N-type discrete layer 25 and making ohmic contact with the upper electrode 19, it is possible to make contact with the upper electrode 19 more reliably.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and can be appropriately modified within the scope of the claims.

For example, the element structures of the IGBTs and FWDs shown in the first to fifth embodiments are merely examples, and other structures may be used. Specifically, regarding the IGBT, the first base layer 12a is made to function not only as a channel region but also as a body region, but only functions as a channel region, and the body region is added to the first base layer 12a. May be formed. In that case, for example, between the trench gate structures, the emitter region 14 is formed so as to be in contact with the trench 13, and the P-shaped body is located on the opposite side of the emitter region 14 from the trench 13, that is, at a position away from the trench 13. It can be a structure in which a region is formed. Then, the surface of the body region constitutes the first contact region 15a in the first base layer 12a.

Further, in the first to fifth embodiments, the P-type impurity concentrations of the diode region 1b and the second base layer 12b of the boundary region 1c are the same, but they may be different concentrations.

Further, the structures of the IGBT region 1a, the diode region 1b and the boundary region 1c described in the first to fifth embodiments can be arbitrarily combined. That is, the structures of the IGBT region 1a, the diode region 1b, and the boundary region 1c can be combined in different embodiments. For example, as in the first and second embodiments, the emitter regions 14 are scattered along the longitudinal direction of the trench 13, and as in the third and fourth embodiments, the second contact regions 15b and the third. A structure in which the contact region 15c is linear may be combined. On the contrary, as in the third and fourth embodiments, the emitter region 14 is formed linearly along the longitudinal direction of the trench 13, and as in the first and second embodiments, the second contact region 15b. And a structure in which the third contact region 15c is scattered along the longitudinal direction of the trench 13 may be combined.

Further, in the fourth embodiment, the P-shaped discrete layer 24 is extended along the longitudinal direction of the trench 13, but it may be formed by another upper surface layout such as a structure in which the P-shaped discrete layers 24 are scattered in a desired pattern. good.

Further, although the IGBT has a structure in which the emitter region 14 is formed in all the first base layers 12a between the adjacent trench gate structures, the IGBT is provided with a thinning structure in which the emitter region 14 is not formed and the channel is not formed. Is also good. Further, a hole barrier layer may be formed in the first base layer 12a in a portion where a channel is not formed as a thinning structure.

Further, in each of the above embodiments, a semiconductor device provided with an n-channel type IGBT in which the first conductive type is an n-type and the second conductive type is a p-type has been described as an example, but the conductive type of each component has been described. It may be a p-channel type IGBT in which is inverted.

1a IGBT region 1b Diode region 1c Boundary region 10 Semiconductor substrate 12 Base layer 13 Trench 14 Emitter region 17 Gate electrode 21 Collector layer 22 Cathode layer

Claims (9)

A semiconductor device having an IGBT and a diode.
It has an IGBT region (1a) in which the IGBT is formed, a diode region (1b) in which the diode is formed, and a boundary region (1c) formed between the IGBT region and the diode region. The 1 conductive type drift layer (11), the 2nd conductive type base layer (12) formed on the surface layer portion of the drift layer, and the IGBT region opposite to the base layer side of the drift layer. The second conductive type collector layer (21) formed on the side and the first conductive type cathode layer formed on the side opposite to the base layer side of the drift layer in the diode region and the boundary region. A semiconductor substrate (10) including (22) and a second conductive discrete layer (24) partially arranged in the cathode layer in the diode region.
Formed in the IGBT region, the diode region, and the boundary region, one direction is the longitudinal direction and the base layer is formed deeper than the base layer, so that the base layer is divided into a plurality of trenches (13). , A trench gate structure in which a gate insulating film (16) and a gate electrode (17) are arranged, and
A first conductive type formed in contact with the trench in at least a part of the first base layer divided into a plurality by the trench, using the base layer in the IGBT region as the first base layer (12a). Emitter region (14) and
A first contact region (15a) arranged in a portion of the first base layer different from the emitter region, and
The base layer in the diode region and the boundary region is used as a second base layer (12b), and is formed on the surface layer portion of the second base layer in the diode region, and is a second conductive impurity rather than the second base layer. In the second conductive type second contact region (15b) having a higher concentration and the boundary region, the concentration of the second conductive type impurities is formed on the surface layer portion of the second base layer and is higher than that of the second base layer. 3rd contact region (15c) of the 2nd conductive type with increased height
In addition to the emitter region, an upper electrode (19) electrically connected to the first contact region, the second contact region, and the third contact region,
It has a lower electrode (23) electrically connected to the collector layer and the cathode layer, and has.
A semiconductor device in which the formation area of the third contact region is smaller than the formation area of the second contact region per unit area of the surface of the semiconductor substrate. The semiconductor device according to claim 1, wherein the gate electrode formed in the boundary region has the same potential as the gate electrode formed in the IGBT region. The semiconductor device according to claim 1, wherein the gate electrode formed in the boundary region has the same potential as the gate electrode formed in the diode region. The first base layer formed in the IGBT region has a higher concentration of second conductive impurities than the second base layer formed in the diode region and the boundary region.
Claims 1 to 3, wherein the first contact region is formed by the surface of the first base layer, and the first base layer functions as a channel region in which a channel is formed and also functions as a body region. The semiconductor device according to any one. One of claims 1 to 4, wherein a plurality of the emitter regions are arranged between the plurality of trenches along the longitudinal direction of the trench and are in contact with the side surfaces of both adjacent trenches. The semiconductor device described in 1. The semiconductor device according to any one of claims 1 to 4, wherein the emitter region extends along the longitudinal direction of the trench among the plurality of trenches. The second contact region and the third contact region extend along the longitudinal direction of the trench among the plurality of trenches.
The second contact region is formed in all of the second base layers arranged between the plurality of trenches.
The semiconductor device according to any one of claims 1 to 6, wherein the third contact region is formed at a ratio of one in a plurality of the second base layers arranged between the plurality of trenches. The formation pitch, which is the interval at which the third contact region is formed, gradually changes from the IGBT region toward the diode region, and the formation is performed from the IGBT region toward the diode region. The semiconductor device according to claim 7, wherein the pitch is gradually reduced. A first conductive discrete layer (25) is formed at a position different from the second contact region and the third contact region in the surface layer portion of the second base layer formed in the diode region and the boundary region. The semiconductor device according to any one of claims 1 to 7, wherein the upper electrode is in ohmic contact with the first conductive type discrete layer.

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