JP6949635B2 - Multiplexer - Google Patents

Description

The present invention relates to a multiplexer, for example, a multiplexer having a plurality of filters.

Mobile phone terminals represented by mobile communication terminals support a plurality of frequency bands. Therefore, a multiplexer such as a quad plexer is used. It is known that two duplexers are mounted on a substrate (for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2014-158099

When four filters are mounted on a substrate to form a quad plexer, four filters are arranged in consideration of miniaturization, matching of the four filters and / or interference between the four filters.

The present invention has been made in view of the above problems, and an object of the present invention is to appropriately arrange four filters.

The present invention is mounted on a substrate, a quadrangular element mounted on the substrate and having a first side, a second side, a third side, and a fourth side when the substrate is viewed in a plan view, and mounted on the substrate. A first filter is provided between the common terminal and the first terminal, which is electrically connected, and has a quadrangular shape having a fifth side adjacent to the first side when the substrate is viewed in a plan view. A sixth filter mounted on the board and electrically connected between the common terminal and the second terminal is provided, and when the board is viewed in a plan view, a sixth side adjacent to the second side is provided. When a second chip having a quadrangular side and a third filter mounted on the substrate and electrically connected between the common terminal and the third terminal are provided and the substrate is viewed in a plan view. A quadrangular third chip having a seventh side adjacent to the third side and a fourth filter mounted on the substrate and electrically connected between the common terminal and the fourth terminal are provided. The fourth chip, which has an eighth side adjacent to the fourth side when the substrate is viewed in a plan view, is provided in the substrate, and the first filter and the element are electrically connected to each other. The first wiring to be provided, the second wiring provided in the substrate to electrically connect the second filter and the element, and the third wiring provided in the substrate to electrically connect the third filter and the element. A third wiring that is provided in the substrate and electrically connects the fourth filter and the element is provided, and one end of the element is electrically connected to the common terminal. The other end of the inductor is electrically connected to the ground, and the first wiring electrically connects one end of the first filter on the common terminal side and one end of the element on the common terminal side. The second wiring electrically connects one end of the second filter on the common terminal side and one end of the element on the common terminal side, and the third wiring is the common of the third filter. One end on the terminal side and one end on the common terminal side of the element are electrically connected, and the fourth wiring is formed on one end on the common terminal side of the fourth filter and one end on the common terminal side of the element. It is a multiplexer that electrically connects the above.

In the above configuration, the fifth side of the first chip is adjacent to the second chip, the sixth side of the second chip is adjacent to the third chip, and the seventh side of the third chip is adjacent to the third chip. The eighth side of the fourth chip may be adjacent to the fourth chip, and may be adjacent to the first chip.

In the above configuration, the first chip has a first pad provided in a region corresponding to a first angle closest to the element when the substrate is viewed in a plan view, and the first filter has the first pad. Electrically connected to the first wiring via the second chip, the second chip has a second pad provided in a region corresponding to a second corner closest to the element when the substrate is viewed in a plan view, and the first pad is provided. The second filter is electrically connected to the second wiring via the second pad, and the third chip is provided in a region corresponding to the third corner closest to the element when the substrate is viewed in a plan view. It has three pads, the third filter is electrically connected to the third wiring through the third pad, and the fourth chip is at the fourth corner closest to the element when the substrate is viewed in a plan view. It has a fourth pad provided in the corresponding region, and the fourth filter can be configured to be electrically connected to the fourth wiring via the fourth pad.

In the above configuration, the first chip has a fifth pad provided in a region corresponding to a fifth corner located diagonally to the first corner when the substrate is viewed in a plan view, and the first filter has a fifth pad. It is electrically connected to the first terminal via the fifth pad, and the second chip is provided in a region corresponding to a sixth corner located diagonally to the second corner when the substrate is viewed in a plan view. The second filter is electrically connected to the second terminal via the sixth pad, and the third chip is diagonal to the third corner when the substrate is viewed in a plan view. It has a seventh pad provided in a region corresponding to a seventh corner located in, the third filter is electrically connected to the third terminal via the seventh pad, and the fourth chip is said. When the substrate is viewed in a plan view, it has an eighth pad provided in a region corresponding to the eighth corner located diagonally to the fourth corner, and the fourth filter is connected to the fourth terminal via the eighth pad. It can be configured to be electrically connected.

In the above configuration, when the substrate is viewed in a plan view, the first side and the third side of the element are opposite sides, the second side and the fourth side of the element are opposite sides, and the first filter. And the third filter is a reception filter and a transmission filter of the first band, respectively, and the second filter and the fourth filter are a reception filter and a transmission filter of a second band different from the first band, respectively. can do.

In the above configuration, the first chip, the second chip, the third chip, and the fourth chip may be configured to be flip-chip mounted on the substrate.

In the above configuration, a lid is provided in contact with the first chip, the second chip, the third chip, and the fourth chip, and a space is formed between the element and the lid. can do.

In the above configuration, the first filter, the second filter, the third filter, and the fourth filter may be configured to be an elastic wave filter.

According to the present invention, the four filters can be arranged appropriately.

FIG. 1 is a circuit diagram of a multiplexer according to the first embodiment. FIG. 2 is a cross-sectional view of the multiplexer according to the first embodiment. FIG. 3 is a plan view of the multiplexer according to the first embodiment. FIG. 4 is a circuit diagram of the filter according to the first embodiment. FIG. 5 is a plan view of the chip according to the first embodiment. 6 (a) and 6 (b) are diagrams showing an example of an elastic wave resonator. FIG. 7 is a plan view of the insulating layer according to the first embodiment. 8 (a) and 8 (b) are plan views of the insulating layer in the first embodiment. 9 (a) is a plan view of the multiplexer according to Comparative Example 1, and FIG. 9 (b) is a top view of the insulating layer. 10 (a) is a plan view of the multiplexer according to Comparative Example 2, and FIG. 10 (b) is a top view of the insulating layer. FIG. 11A is a plan view of the multiplexer according to Comparative Example 3, and FIG. 11B is a top view of the insulating layer.

Hereinafter, examples will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a multiplexer according to the first embodiment. As shown in FIG. 1, a filter 51 (first filter) is electrically connected between the common terminal Ant and the terminal T1 (first terminal). A filter 52 (second filter) is electrically connected between the common terminal Ant and the terminal T2 (second terminal), and a filter 53 (third terminal) is between the common terminal Ant and the terminal T3 (third terminal). 3 filters) are electrically connected. A filter 54 (fourth filter) is electrically connected between the common terminal Ant and the terminal T4 (fourth terminal). A matching circuit 55 is electrically connected between the filters 51 and 54. The matching circuit 55 includes an inductor L. The inductor L is electrically connected between the common terminal and the ground.

The filters 51 to 54 have different pass bands and do not overlap each other. For example, the filters 51 and 53 are a band B1 transmit filter and a receive filter, respectively. The filters 52 and 54 are a transmission filter and a reception filter of band B2, respectively. Bands B1 and B2 are LTE (Long Term Evolution) bands (E-UTRA (Evolved Universal Terrestrial Radio Access) Operating Band). Bands B1 and B2 are, for example, a combination of LET band 1 and band 3, or a combination of band 2 and band 4.

The filter 51 outputs a signal in the transmission band of band B1 among the high frequency signals input to the terminal T1 to the common terminal Ant, and suppresses other signals. The filter 52 outputs a signal in the transmission band of band B2 among the high frequency signals input to the terminal T2 to the common terminal Ant, and suppresses other signals. The filter 53 outputs the signal of the reception band of the band B1 among the high frequency signals input to the common terminal Ant to the terminal T3, and suppresses other signals. The filter 54 outputs the signal of the reception band of the band B2 out of the high frequency signals input to the common terminal Ant to the terminal T4, and suppresses other signals.

The matching circuit 55 sets the impedance in the pass band of the self-filter (for example, the filter 51) as seen from the common terminal Ant to the self-filter (for example, the filter 51) as a standard impedance (for example, 50Ω), and sets the impedance in the pass band from the common terminal Ant to the self-filter (for example, the filter 51). The impedance in the pass band of other filters (for example, filters 52 to 54) is increased.

FIG. 2 is a cross-sectional view of the multiplexer according to the first embodiment. As shown in FIG. 2, the chip 20 is flip-chip mounted on the substrate 10 via the bump 24. The substrate 10 includes a plurality of laminated insulating layers 10a and 10b. The insulating layers 10a and 10b are, for example, a ceramic layer or a resin layer. A pad 12 and an annular electrode 34 are provided on the upper surface of the insulating layer 10b. Wiring 14 is provided on the upper surface of the insulating layer 10a. The terminal 16 is provided on the lower surface of the insulating layer 10b. Through electrodes 13 and 15 that penetrate the insulating layers 10a and 10b are provided. The through silicon via 13 electrically connects the pad 12 and the wiring 14. The through silicon via 15 electrically connects the wiring 14 and the terminal 16. The pad 12, the wiring 14, the terminal 16, the through electrodes 13 and 15, and the annular electrode 34 are metal layers such as, for example, a copper layer, a gold layer, or an aluminum layer.

A filter 50 and a pad 22 are formed on the lower surface of the chip 20. The filter 50 corresponds to the filters 51 to 54 and faces the substrate 10 with the gap 26 interposed therebetween. The pad 22 is a metal layer such as a copper layer, a gold layer or an aluminum layer. The bump 24 is joined to the pads 12 and 22. The bump 24 is a metal bump such as a gold bump, a copper bump or a solder bump, for example. The element 40 is mounted on the pad 12. An electrode 42 is provided on the surface of the element 40. The pad 12 and the electrode 42 are joined by a solder 44.

A sealing portion 30 is provided so as to surround the chip 20. The sealing portion 30 is, for example, a metal sealing portion such as solder or an insulator sealing portion such as resin. The lower surface of the sealing portion 30 is joined to the annular electrode 34. A lid 32 is provided on the tip 20 and the sealing portion 30. The lid 32 is a metal plate such as a Kovar plate or an insulator plate. The upper surface of the chip 20 is in contact with the lid 32. A space is formed between the element 40 and the lid 32. A sealing portion 30 may be provided between the tip 20 and the lid 32. The lid 32 may not be provided. A protective film 36 is provided so as to cover the sealing portion 30 and the lid 32. The protective film 36 is a metal film such as a nickel film or an insulator film.

FIG. 3 is a plan view of the multiplexer according to the first embodiment. FIG. 3 shows the substrate 10, the chips 20a to 20d, and the element 40. The chips 20a to 20d show the filters 51 to 54, the pads 22a to 22h, and the bumps 24 through the lower surface from above. The stretching directions of the sides of the substrate 10 are the X direction and the Y direction, and the stacking direction of the substrate 10 is the Z direction.

As shown in FIG. 3, the elements 40 and the chips 20a to 20d have a quadrangular planar shape. Filters 51 to 54 are provided on the lower surfaces of the chips 20a to 20d, respectively. Pads 22a and 22e are formed diagonally on the lower surface of the chip 20a. Pads 22b and 22f, 22c and 22g, and 22d and 22h are arranged diagonally on the lower surfaces of the chips 20b, 20c and 20d. Bumps 24 are joined to the pads 22a to 22h. Pads 22a to 22d are pads for connecting to the common terminal Ant, and pads 22e to 22h are pads for connecting to terminals T1 to T4. By providing the pads 22a and 22e for inputting and outputting high frequency signals diagonally to the chip 20a, interference between the signal input to the chip 20a and the output signal is suppressed. The pads 22a to 22d are provided near the center of the substrate 10, and the pads 20e to 22h are provided near the four vertices of the substrate 10.

The element 40 has four sides 41a to 41d. The + X-side side 21a of the chip 20a is adjacent to the −X-side side 41a of the element 40 and the −X-side side 21f of the chip 20b. The −Y side side 21b of the chip 20b is adjacent to the + Y side side 41b of the element 40 and the + Y side side 21g of the chip 20c. The −X side side 21c of the chip 20c is adjacent to the + X side side 41c of the element 40 and the + X side side 21h of the chip 20d. The + Y-side side 21d of the chip 20d is adjacent to the −Y-side side 41d of the element 40 and the −Y-side side 21e of the chip 20a. Here, when two sides are adjacent to each other, it means that no other chip or element is provided between the two sides. The sides 21a to 21d are substantially parallel to the sides 41a to 41d to the extent of manufacturing error, and the sides 21f to 21h and 21e are substantially parallel to the sides 21f to 21h and 21e to the extent of the manufacturing error, respectively.

The planar shape of the chips 20a to 20d is rectangular, the long side directions of the chips 20a and 20c are the Y direction, and the long side directions of the chips 20b and 20d are the X direction. The + Y side of the chips 20a and 20b is located in a straight line, the + X side of the chips 20b and 20c is located in a straight line, and the −Y side of the chips 20c and 20d is approximately one. It is located in one straight line, and the sides of the chips 20d and 20a on the −X side are located in substantially one straight line. As a result, the planar shape of the region where the chips 20a to 20d and the element 40 are provided is rectangular.

The filter 51 of the chip 20a will be described as an example of the chips 20a to 20d and the filters 51 to 54. FIG. 4 is a circuit diagram of the filter according to the first embodiment. As shown in FIG. 4, the series resonators S1 to S5 are connected in series between the common terminal Ant and the terminal T1, and the parallel resonators P1 to P4 are connected in parallel. The series resonators S1 to S5 are divided in series into S1a and S1b, S2a and S2b, S3a and S3b, S4a and S4b, and S5a and S5b, respectively.

FIG. 5 is a plan view of the chip according to the first embodiment. In FIG. 5, the lower surface of the chip 20a is seen through from above. As shown in FIG. 5, an elastic wave resonator 80, a wiring 23, and a pad 22 are provided on the lower surface of the chip 20a. The elastic wave resonator 80 has an IDT (Inter Digital Transducer) 81 and a reflector 82. The wiring 23 electrically connects between the elastic wave resonators 80 or the elastic wave resonator 80 and the pad 22. A bump 24 is joined to the pad 22. The plurality of elastic wave resonators 80 include series resonators S1 to S5 and parallel resonators P1 to P4. The pad 22 includes a common pad Pant, a signal pad Pt, a ground pad Pgnd, and a dummy pad Pd. The common pad Pant corresponds to the pad 22a, and the signal pad Pt corresponds to the pad 22e. The dummy pad Pd is not connected to the elastic wave resonator 80 in the chip 20a, and bumps for ensuring mechanical strength are joined.

6 (a) and 6 (b) are diagrams showing an example of an elastic wave resonator. 6 (a) and 6 (b) are examples of surface acoustic wave resonators and piezoelectric thin film resonators, respectively.

As shown in FIG. 6A, the IDT 81 and the reflector 82 are formed on the substrate 89. The IDT 81 has a pair of comb-shaped electrodes 81a facing each other. The comb-shaped electrode 81a has a plurality of electrode fingers 81b and a bus bar 81c for connecting the plurality of electrode fingers 81b. Reflectors 82 are provided on both sides of the IDT 81. IDT81 excites surface acoustic waves on the substrate 89. The substrate 89 is a piezoelectric substrate such as a lithium tantalate substrate or a lithium niobate substrate. The IDT 81 and the reflector 82 are formed of, for example, an aluminum film or a copper film. The substrate 89 may be bonded to a support substrate such as a sapphire substrate, an alumina substrate, a spinel substrate, a crystal substrate, or a silicon substrate. A protective film or a temperature compensation film may be provided to cover the IDT 81 and the reflector 82. In this case, it functions as an elastic wave resonator 80 including a protective film or a temperature compensation film.

As shown in FIG. 6B, the piezoelectric film 86 is provided on the substrate 89. The lower electrode 84 and the upper electrode 88 are provided so as to sandwich the piezoelectric film 86. A gap 85 is formed between the lower electrode 84 and the substrate 89. The lower electrode 84 and the upper electrode 88 excite elastic waves in the thickness longitudinal vibration mode in the piezoelectric film 86. The lower electrode 84 and the upper electrode 88 are metal films such as a ruthenium film. The piezoelectric film 86 is, for example, an aluminum nitride film. The substrate 89 is, for example, a silicon substrate, a semiconductor substrate such as gallium arsenide, or an insulating substrate such as a sapphire substrate, an alumina substrate, a spinel substrate, or a glass substrate. As shown in FIGS. 6 (a) and 6 (b), the elastic wave resonator 80 includes an electrode that excites an elastic wave. Therefore, the elastic wave resonator 80 is covered with a gap 26 so as not to limit the vibration of the elastic wave.

7 to 8 (b) are plan views of the insulating layer according to the first embodiment. 7 is a top view of the insulating layer 10b, FIG. 8A is a top view of the insulating layer 10a, and FIG. 8B is a bottom view of the insulating layer 10a. In FIGS. 7 and 8 (a), the chips 20a to 20d and the element 40 are shown by broken lines.

As shown in FIG. 7, pads 12a to 12k and 12 are provided on the upper surface of the insulating layer 10b. An annular electrode 34 is provided in an annular shape on the peripheral edge of the insulating layer 10b. The sealing portion 30 is joined to the annular electrode 34. The pads 12a to 12h are joined to the pads 22a to 22h in FIG. 3 via the bumps 24. The pads 12j and 12k are joined to the electrode 42 of the element 40 via solder. The pad 12 is a ground pad, and the ground pad Pgnd and the dummy pad Pd of the chips 20a to 20d are joined to each other.

As shown in FIG. 8A, wirings 14e to 14h and 14z are provided on the upper surface of the insulating layer 10a. The insulating layer 10b is provided with through electrodes 13a to 13h and 13j. The insulating layer 10a is provided with through electrodes 15e to 15h and 15z. The wiring 14z is provided near the center of the upper surface of the insulating layer 10a. The wiring 14e extends along the −X side side of the upper surface of the insulating layer 10a. The wiring 14f extends along the + X side of the upper surface of the insulating layer 10a.

The wirings 14e to 14h are electrically connected to the pads 12e to 12h in FIG. 7 via through electrodes 15e to 15h, respectively. The wiring 14z is electrically connected to the pads 12a to 12d and 12j of FIG. 7 via the through electrodes 13a to 13d and 13j. Of the wirings 14z, the wirings between the through electrodes 13a to 13d and the through electrodes 13j are the wirings 14a to 14d, respectively. Wiring 14, through silicon vias 13 and 15 connected to the pad 12 (ground pad) in FIG. 7 are not shown.

As shown in FIG. 8B, terminals T1 to T4, a common terminal Ant, and a ground terminal Gnd are provided as terminals 16 on the lower surface of the insulating layer 10a. The terminal T1 is provided near the center of the side of the insulating layer 10a on the −X side. The terminal T2 is provided near the center of the + X side of the insulating layer 10a. The terminal T3 is provided near the vertices on the −X and −Y sides of the insulating layer 10a. The terminal T4 is provided near the vertices on the + X and −Y sides of the insulating layer 10a. The terminals T1 to T4 are electrically connected to the wirings 14e to 14h via the through electrodes 15e to 15h shown in FIG. 8A, respectively. The common terminal Ant is electrically connected to the wiring 14z via the through electrode 15z shown in FIG. 8A. The ground terminal Gnd is electrically connected to the pad 12 of FIG.

[Comparative Example 1]
A comparative example to be compared with Example 1 will be described. 9 (a) is a plan view of the multiplexer according to Comparative Example 1, and FIG. 9 (b) is a top view of the insulating layer 10a. FIG. 9A shows the substrate 10, the chips 20a to 20d, and the element 40. The chips 20a to 20d show the filters 51 to 54, the pads 22a to 22h, and the bumps 24 through the lower surface from above. In FIG. 9B, the chips 20a to 20d and the element 40 are shown by broken lines. The same applies to the following figure.

As shown in FIG. 9A, the chips 20a to 20d are arranged in the X direction. The element 40 is provided on the outside of the chip 20d in the + Y direction. The pads 22a to 22d are provided on the + Y side within the chips 20a to 20d. As shown in FIG. 9B, the wiring 14z extends in the X direction along the + Y side of the substrate 10. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.

In Comparative Example 1, the wiring 14z extends in the X direction. Therefore, the length of the wiring 14a between the through electrodes 13a and 13j and the length of the wiring 14d between the through electrodes 13d and 13j are longer than those in FIG. 8A of Example 1. In this way, the length of the wiring between the chips 20a to 20d and the element 40 varies. Therefore, it becomes difficult for the element 40 to match the filters 51 to 54. Further, since the wiring 14z extends along the + Y side side of the substrate 10, coupling between the wiring 14z and the external circuit on the + Y side of the substrate 10 is likely to occur.

[Comparative Example 2]
10 (a) is a plan view of the multiplexer according to Comparative Example 2, and FIG. 10 (b) is a top view of the insulating layer 10a. As shown in FIG. 10A, the element 40 is provided near the center of the −Y side side of the substrate 10. The chip 20c is provided on the + X side of the element 40, and the chip 20d is provided on the −X side of the element 40. The chips 20a and 20b are provided on the + Y side of the element 40. As shown in FIG. 10B, the wiring 14z is provided in the vicinity of the position in the −Y direction slightly from the center of the substrate 10. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.

In Comparative Example 2, pads 22a to 22d are provided near the center of the substrate. Therefore, as shown in FIG. 10B, the lengths of the wirings 14a to 14d are reduced. This facilitates matching of the filters 51 to 54 by the element 40. Further, the wiring 14z does not extend along the side of the substrate 10. As a result, it is possible to prevent the wiring 14z from coupling with the external circuit.

However, as shown in FIG. 10A, the distance 60c between the pads 22c and 22g of the chip 20c and the distance 60d between the pads 22d and 22h of the chip 20d are shortened. This facilitates coupling between the high frequency signal input to the filters 53 and 54 and the signal output from the filters 53 and 54. This results in poor isolation.

[Comparative Example 3]
FIG. 11A is a plan view of the multiplexer according to Comparative Example 3, and FIG. 11B is a top view of the insulating layer 10a. As shown in FIG. 11A, the element 40 is provided near the center of the substrate 10. The chips 20b and 20c are provided on the + X side of the element 40, and the chips 20a and 20d are provided on the −X side of the element 40. As shown in FIG. 11B, the wiring 14z is provided near the center of the substrate 10. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.

In Comparative Example 3, as shown in FIG. 11A, the distance 60c between the pads 22c and 22g of the chip 20c and the distance 60d between the pads 22d and 22h of the chip 20d can be increased. As a result, deterioration of isolation can be suppressed.

However, as shown in FIG. 11A, a region 62 is formed between the chips 20a and 20b and between the chips 20c and 20d. As a result, the size of the substrate 10 becomes large, and the size of the multiplexer becomes large.

According to the first embodiment, as shown in FIG. 3, the chip 20a (first chip) has a side 21a (fifth side) adjacent to the side 41a (first side) of the element 40 when the substrate 10 is viewed in a plan view. Have. The chip 20b (second chip) has a side 21b (sixth side) adjacent to the side 41b (second side) of the element 40 when the substrate 10 is viewed in a plan view. The chip 20c (third chip) has a side 21c (seventh side) adjacent to the side 41c (third side) of the element 40 when the substrate 10 is viewed in a plan view. The chip 20d (fourth chip) has a side 21d (eighth side) adjacent to the side 41d (fourth side) of the element 40 when the substrate 10 is viewed in a plan view. As shown in FIG. 8A, the wiring 14a (first wiring) that electrically connects the filter 51 and the element 40 and the wiring 14b (the wiring 14b) that electrically connects the filter 52 and the element 40 are included in the substrate 10. The second wiring), the wiring 14c (third wiring) for electrically connecting the filter 53 and the element 40, and the wiring 14d (fourth wiring) for electrically connecting the filter 54 and the element 40 are provided. ..

As a result, the wirings 14a to 14d can be provided near the center of the substrate 10. Therefore, the lengths of the wirings 14a to 14d can be reduced, and the matching by the element 40 becomes easy. Further, since the wirings 14a to 14d do not have to be provided along the side of the substrate 10, the coupling between the external circuit and the wirings 14a to 14d can be suppressed. Further, the chips 20c and 20d can be made larger than in Comparative Example 2. Therefore, deterioration of isolation can be suppressed. Further, since the region 62 as in Comparative Example 3 is not formed, the multiplexer can be miniaturized.

Further, the side 21a of the chip 20a is adjacent to the chip 20b, the side 21b of the chip 20b is adjacent to the chip 20c, the side 21c of the chip 20c is adjacent to the chip 20d, and the side 21d of the chip 20d is adjacent to the chip 20a. As a result, the gap between each chip 20a to 20d and the element 40 is reduced, and the multiplexer can be miniaturized.

The chip 20a has a pad 22a (first pad) provided in a region corresponding to the first corner closest to the element 40 when the substrate 10 is viewed in a plan view, and the filter 51 is electrically connected to the wiring 14a via the pad 22a. Connect to. The chip 20b has a pad 22b (second pad) provided in a region corresponding to the second corner closest to the element 40 when the substrate 10 is viewed in a plan view, and the filter 52 is electrically connected to the wiring 14b via the pad 22b. Connect to. The chip 20c has a pad 22c (third pad) provided in a region corresponding to the third corner closest to the element 40 when the substrate 10 is viewed in a plan view, and the filter 53 is electrically connected to the wiring 14c via the pad 22c. Connect to. The chip 20d has a pad 22d (fourth pad) provided in a region corresponding to the fourth corner closest to the element 40 when the substrate 10 is viewed in a plan view, and the filter 54 is electrically connected to the wiring 14d via the pad 22d. Connect to. As a result, the lengths of the wirings 14a to 14d connecting the filters 51 to 54 and the element 40 can be made more uniform. Therefore, matching by the element 40 becomes easy.

The chip 20a has a pad 22e (fifth pad) provided in a region corresponding to a fifth corner located on the diagonal of the first corner and the quadrangle when the substrate 10 is viewed in a plan view, and the filter 51 uses the pad 22e. It is connected to the terminal T1 via. The chip 20b has a pad 22f (sixth pad) provided in a region corresponding to a sixth angle located diagonally to the second angle when the substrate 10 is viewed in a plan view, and the filter 52 has a terminal via the pad 22f. It is connected to T1. The chip 20c has a pad 22g (seventh pad) provided in a region corresponding to a seventh corner located diagonally to the third corner when the substrate 10 is viewed in a plan view, and the filter 53 has a terminal via the pad 22g. It is connected to T3. The chip 20d has a pad 22h (eighth pad) provided in a region corresponding to an eighth angle located diagonally to the fourth angle when the substrate 10 is viewed in a plan view, and the filter 54 has a terminal via the pad 22h. It is connected to T4. Thereby, the coupling between the input signal and the output signal can be suppressed for each of the filters 51 to 54.

Although the inductor L has been described as an example of the element 40, the element may be a matching circuit 55 including at least one of a capacitor and an inductor. The element 40 includes an inductor L whose one end is electrically connected to the common terminal Ant and the other end is electrically connected to the ground. As a result, the matching circuit 55 can be miniaturized.

As shown in FIG. 3, the chips 20a and 20c are provided diagonally when the substrate 10 is viewed in a plan view. When the substrate 10 is viewed in a plan view, the chips 20b and 20d are provided diagonally. That is, the sides 41a and 41c of the element 40 are opposite sides, and the sides 41b and 41d of the element 40 are opposite sides. The filters 51 and 53 are a reception filter and a transmission filter of band B1 (first band), respectively. The filter 52 and the filter 54 are a reception filter and a transmission filter of a band B2 (second band) different from the band B1, respectively. As a result, the receiving terminal of the receiving filter of the same band and the transmitting terminal of the transmitting filter can be separated from each other. Therefore, the isolation between transmission and reception can be increased. In particular, when the bands B1 and / or B2 are in the FDD (Frequency Division Duplex) system, the reception band and the transmission band do not overlap in the band, and isolation between transmission and reception becomes a problem. Therefore, it is preferable that the filters 51 and 53 are the reception filter and the transmission filter of the band B1, and the filters 52 and 54 are the reception filter and the transmission filter of the band B2.

When the element 40 is, for example, an electronic component in which a ceramic dielectric layer is laminated, the lid 32 can be destroyed by stress from the lid 32 to the element 40. Therefore, in the first embodiment, as shown in FIG. 2, the lid 32 is provided in contact with the tip 20a to 20d, and a space is formed between the element 40 and the lid 32. As a result, the stress applied to the element 40 from the lid 32 can be suppressed. Therefore, the destruction of the element 40 can be suppressed.

The filters 51 to 54 are elastic wave filters including an elastic wave resonator such as an elastic surface wave resonator or a piezoelectric thin film resonator.

Although the examples of the present invention have been described in detail above, the present invention is not limited to such specific examples, and various modifications and modifications are made within the scope of the gist of the present invention described in the claims. It can be changed.

10 Substrate 12, 12a-12h Pad 13, 13a-13h, 13j Through Electrode 14, 14a-14h, 14z Wiring 15, 15e-15h, 15z Through Electrode 16 Terminal 20, 20a-20d Chip 21a-21h Side 22a-22h Pad 24 Bump 30 Sealing part 32 Lid 40 Element 41a-41d Side 42 Electrode 44 Solder 51-54 Filter

Claims (8)

With the board
A quadrangular element mounted on the substrate and having a first side, a second side, a third side, and a fourth side when the substrate is viewed in a plan view.
A square mounted on the board, provided with a first filter electrically connected between the common terminal and the first terminal, and having a fifth side adjacent to the first side when the board is viewed in a plan view. The first chip, which is the shape,
A second filter mounted on the board and electrically connected between the common terminal and the second terminal is provided, and has a sixth side adjacent to the second side when the board is viewed in a plan view. The second chip, which is square,
A third filter mounted on the substrate and electrically connected between the common terminal and the third terminal is provided, and has a seventh side adjacent to the third side when the substrate is viewed in a plan view. The third chip, which is square,
A fourth filter mounted on the substrate and electrically connected between the common terminal and the fourth terminal is provided, and has an eighth side adjacent to the fourth side when the substrate is viewed in a plan view. The fourth chip, which is square,
A first wiring provided in the substrate and electrically connecting the first filter and the element,
A second wiring provided in the substrate and electrically connecting the second filter and the element,
A third wiring provided in the substrate and electrically connecting the third filter and the element,
A fourth wiring provided in the substrate and electrically connecting the fourth filter and the element,
Equipped with a,
The element is an inductor in which one end is electrically connected to the common terminal and the other end is electrically connected to the ground.
The first wiring electrically connects one end of the first filter on the common terminal side and one end of the element on the common terminal side.
The second wiring electrically connects one end of the second filter on the common terminal side and one end of the element on the common terminal side.
The third wiring electrically connects one end of the third filter on the common terminal side and one end of the element on the common terminal side.
The fourth wiring is a multiplexer that electrically connects one end of the fourth filter on the common terminal side and one end of the element on the common terminal side. The fifth side of the first chip is adjacent to the second chip,
The sixth side of the second chip is adjacent to the third chip,
The seventh side of the third chip is adjacent to the fourth chip,
The multiplexer according to claim 1, wherein the eighth side of the fourth chip is adjacent to the first chip. The first chip has a first pad provided in a region corresponding to a first corner closest to the element when the substrate is viewed in a plan view, and the first filter passes through the first pad. Electrically connected to the wiring,
The second chip has a second pad provided in a region corresponding to a second angle closest to the element when the substrate is viewed in a plan view, and the second filter passes through the second pad. Electrically connect to the wiring,
The third chip has a third pad provided in a region corresponding to a third corner closest to the element when the substrate is viewed in a plan view, and the third filter passes through the third pad. Electrically connect to the wiring,
The fourth chip has a fourth pad provided in a region corresponding to a fourth corner closest to the element when the substrate is viewed in a plan view, and the fourth filter passes through the fourth pad to the fourth pad. The multiplexer according to claim 2, which is electrically connected to a wiring. The first chip has a fifth pad provided in a region corresponding to a fifth corner located diagonally to the first corner when the substrate is viewed in a plan view, and the first filter has the fifth pad. Is electrically connected to the first terminal via
The second chip has a sixth pad provided in a region corresponding to a sixth angle located diagonally to the second angle when the substrate is viewed in a plan view, and the second filter has the sixth pad. Is electrically connected to the second terminal via
The third chip has a seventh pad provided in a region corresponding to a seventh corner located diagonally to the third corner when the substrate is viewed in a plan view, and the third filter has the seventh pad. It is electrically connected to the third terminal via
The fourth chip has an eighth pad provided in a region corresponding to an eighth angle located diagonally to the fourth angle when the substrate is viewed in a plan view, and the fourth filter has the eighth pad. The multiplexer according to claim 3, which is electrically connected to the fourth terminal via the above. When the substrate is viewed in a plan view, the first side and the third side of the element are opposite sides, and the second side and the fourth side of the element are opposite sides.
The first filter and the third filter are a reception filter and a transmission filter of the first band, respectively.
The multiplexer according to any one of claims 1 to 4 , wherein the second filter and the fourth filter are a reception filter and a transmission filter of a second band different from the first band, respectively. The multiplexer according to any one of claims 1 to 5, wherein the first chip, the second chip, the third chip, and the fourth chip are flip-chip mounted on the substrate. Claims 1 to 6 wherein a lid is provided in contact with the first chip, the second chip, the third chip, and the fourth chip, and a space is formed between the element and the lid. The multiplexer according to any one of the above. The multiplexer according to any one of claims 1 to 7 , wherein the first filter, the second filter, the third filter, and the fourth filter are elastic wave filters.

Images