JP6932998B2 - Silicon Carbide MOSFET and its manufacturing method - Google Patents

Description

The present invention relates to a silicon carbide MOSFET and a method for producing the same.

Silicon carbide (SiC) semiconductors are attracting attention as next-generation power semiconductor materials. The bandgap of SiC is 3.25 eV for 4H-SiC, which is about three times larger than 1.12 eV of silicon (Si) used in the past, and the electric field strength is 2 to 4 mV / cm, which is nearly an order of magnitude higher than Si. Yes, it has an advantage in material properties compared to Si.

Therefore, in the case of a semiconductor element composed of SiC, the resistance (on resistance) of the element in a turn-on (hereinafter, also simply referred to as “on”) state is several hundredths of that of the semiconductor element composed of Si. It has the feature that it can be reduced to one. Further, the SiC semiconductor element can be used even in a high temperature environment of 200 ° C. or higher. Various devices such as rectifying devices such as diodes using SiC and switching devices such as transistors and thyristors have been prototyped so far.

It is known that there are several types of dislocations in a SiC substrate. Non-Patent Document 1 discloses that when a device is manufactured on a SiC substrate and the manufactured device is operated, dislocations in the substrate grow into stacking defects due to recombination of electron / hole pairs. There is. When stacking defects occur, the on-characteristics of the device are adversely affected, and the conduction loss of the power semiconductor module including the semiconductor element increases. Therefore, it is desirable that stacking defects do not occur.

As a technique for solving this problem, a method of manufacturing a SiC substrate (wafer) having no dislocation can be considered. For example, in Patent Document 1, basal plane dislocation (BPD) and basal plane dislocation (BPD) and basal plane dislocations (BPD) and A method for manufacturing a SiC epitaxial wafer having a low stacking defect density is disclosed.

As another method for suppressing the expansion of stacking defects, there is a technique related to the cell structure of a semiconductor element. For example, in Patent Document 2, the expansion of stacking defects is performed by providing a striped current limiting region in the active region. The method of preventing the above is disclosed. Further, in Patent Document 3, expansion of stacking defects is prevented by a method of forming a trench-like groove in the active region.

Further, Patent Document 4 and Patent Document 5 disclose an invention in which a Schottky contact region is provided in a region other than the active portion of a MOS (Metal-Oxide-Semiconductor) field effect transistor (MOSFET) of a semiconductor element. It is said that the Schottky contact region can reduce the current stress applied to dislocations when the device is energized, thus suppressing the expansion of stacking defects.

However, in the case of the method of Patent Document 1, although it is possible to improve the quality of the SiC wafer to a certain extent, dislocations have not yet been completely eliminated. Further, in the case of a method of separately forming a special structure inside the SiC as in the striped current limiting region of Patent Document 2, or forming a trench-shaped groove on the SiC surface side as in Patent Document 3. , The process is accompanied by great difficulties and the process cost is greatly increased.

Further, it is necessary to provide an ohmic contact region on the surface of the SiC semiconductor device due to the requirement of specifications. Therefore, in the case of the method of providing the Schottky contact region as in Patent Document 4 and Patent Document 5, both the ohmic contact region and the Schottky contact region are formed, and the burden on the process is significant.

Further, as disclosed in Patent Document 6, in a SiC semiconductor device such as a MOSFET, a terminal structure region may be selectively formed on the periphery of the active portion so as to surround the cell region which is the active portion. Since the terminal structure region is a structure for relaxing the electric field concentration at the terminal portion of the device and increasing the withstand voltage, it is highly necessary in the SiC semiconductor device. Therefore, in a SiC semiconductor device provided with a terminal structure region, there has been a strong demand for a technique capable of effectively suppressing the expansion of stacking defects.

Japanese Unexamined Patent Publication No. 2015-002207 Japanese Unexamined Patent Publication No. 2013-232574 Japanese Unexamined Patent Publication No. 2004-335720 International Publication No. 2007/0133367 Japanese Unexamined Patent Publication No. 2016-006854 Japanese Patent No. 5751763

Journal of Applied Physics, Vol. 99, 01101 (2006)

The present invention has been made by paying attention to the above-mentioned problems, and provides a silicon carbide MOSFET capable of effectively suppressing expansion of stacking defects in a silicon carbide MOSFET having a terminal structural region. The purpose is to do.

In order to solve the above problems, an aspect of the silicon carbide MOSFET according to the present invention according to the present invention is a first conductive type drift layer made of a silicon carbide semiconductor substrate and a second conductive type provided above the drift layer. Of the base region, the first conductive type source region selectively provided above the base region, the gate insulating film provided on the drift layer, the gate electrode provided on the gate insulating film, and the drift layer. A source electrode provided above, a second conductive base contact region provided by joining the source electrode above the base region above the drift layer, and a first conductive drain provided below the drift layer. An active portion having a drain electrode provided below the region and a drain region, a terminal structure region as a pressure resistant region provided outside the active portion, and an upper part of a drift layer between the active portion and the terminal structure region. It is a gist to include a second conductive type conduction induction region in which the upper surface is provided by being joined to the source electrode and the joint area with the source electrode is set to be larger than the joint area with the source electrode in the base contact region. And.

Further, in one aspect of the method for manufacturing a silicon carbide MOSFET according to the present invention, a second conductive type base region is formed on an upper portion of a first conductive type drift layer made of a silicon carbide semiconductor substrate, and a first first conductive type base region is formed on the upper portion of the base region. A conductive source region is selectively formed, a gate insulating film is formed on the drift layer, a gate electrode is formed on the gate insulating film, a source electrode is formed on the drift layer, and the drift layer is formed. A second conductive type base contact region is formed by joining with a source electrode on the base region at the upper part, a first conductive type drain region is formed under the drift layer, and a drain electrode is formed under the drain region. The step of forming the active portion by forming the active portion, the step of forming the terminal structure region as a pressure resistant region on the outside of the active portion, and the upper surface of the drift layer between the active portion and the terminal structure region, the upper surface of which is the source electrode. The gist of the present invention includes a step of forming a second conductive type conduction induction region so that the bonding area with the source electrode is larger than the bonding area with the source electrode in the base contact region.

According to the silicon carbide MOSFET according to the present invention, expansion of stacking defects can be effectively suppressed in a state where the terminal structural region is provided. Further, according to the method for manufacturing a silicon carbide MOSFET according to the present invention, a silicon carbide MOSFET having a terminal structure region capable of suppressing the burden of further additional steps in the manufacturing process and suppressing the expansion of stacking defects can be manufactured. can.

It is a top view schematically explaining the outline of the structure of the silicon carbide MOSFET (hereinafter, also referred to as "SiC-MOSFET") which concerns on 1st Embodiment. It is sectional drawing which schematically explains the outline of the structure of the SiC-MOSFET according to the first embodiment. It is sectional drawing of the drift layer for schematically explaining the width of the conduction induction region. FIG. 5 is a plan view schematically illustrating a state in which stacking defects are expanded in the SiC-MOSFET according to the first embodiment. It is a top view schematically explaining the outline of the structure of the SiC-MOSFET according to the first comparative example. It is sectional drawing which schematically explains the outline of the structure of the SiC-MOSFET which concerns on 1st comparative example. It is a top view schematically explaining the outline of the state in which the stacking defect is expanded in the SiC-MOSFET according to the first comparative example. It is a top view schematically explaining the outline of the structure of the SiC-MOSFET according to the second comparative example. It is a top view schematically explaining the outline of the structure of the SiC-MOSFET according to the third comparative example. It is a process cross-sectional view schematically explaining the manufacturing method of the SiC-MOSFET according to the first embodiment (No. 1). It is a process cross-sectional view schematically explaining the manufacturing method of the SiC-MOSFET according to the first embodiment (No. 2). It is a process cross-sectional view schematically explaining the manufacturing method of the SiC-MOSFET according to the first embodiment (No. 3). It is a process cross-sectional view schematically explaining the manufacturing method of the SiC-MOSFET according to the first embodiment (No. 4). FIG. 5 is a process cross-sectional view schematically illustrating a method for manufacturing a SiC-MOSFET according to the first embodiment (No. 5). It is a top view which schematically explains the outline of the structure of the SiC-MOSFET which concerns on the 1st modification. It is a top view schematically explaining the outline of the structure of the SiC-MOSFET which concerns on the 2nd modification. It is sectional drawing which schematically explains the outline of the structure of the SiC-MOSFET which concerns on the 3rd modification. It is sectional drawing which schematically explains the outline of the structure of the SiC-MOSFET which concerns on the 4th modification. It is a top view schematically explaining the outline of the structure of the SiC-MOSFET according to the second embodiment. It is sectional drawing which schematically explains the outline of the structure of the SiC-MOSFET according to the second embodiment. It is a top view schematically explaining the outline of the structure of the SiC-MOSFET according to the fifth modification. It is sectional drawing which schematically explains the outline of the structure of the semiconductor module which mounted the SiC-MOSFET according to the 1st or 2nd Embodiment.

The first and second embodiments of the present invention will be described below. In the description of the drawings below, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each device and each member, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that the drawings include parts having different dimensional relationships and ratios from each other.

Further, the directions of "left and right" and "up and down" in the following description are merely definitions for convenience of explanation, and do not limit the technical idea of the present invention. Therefore, for example, if the paper surface is rotated 90 degrees, "left and right" and "up and down" are read interchangeably, and if the paper surface is rotated 180 degrees, "left" becomes "right" and "right" becomes "left". Of course it will be. Further, in the following description, the case where the first conductive type is the n type and the second conductive type is the p type will be exemplified, but the conductive type is selected in the opposite relationship, and the first conductive type is the p type. The second conductive type may be n type. Further, + and-attached to n and p mean that the impurity element impurity density is relatively high or low, respectively, as compared with the semiconductor region to which + and-are not added.

− First Embodiment −
<Semiconductor device>
As shown in FIG. 1, the SiC-MOSFET according to the first embodiment is a semiconductor chip having a planar pattern and a rectangular shape as a whole. A rectangular active portion 100 is provided in the central portion of the main surface of the semiconductor chip, and the active portion 100 has a transistor structure and a parasitic diode structure. In FIG. 1, for the sake of explanation, a state in which the layer above the gate insulating film is removed and the surface layer of SiC is exposed is schematically shown, but as shown in FIG. 2, in reality, The transistor structure is laminated.

At both ends of the active portion 100 in the <11-20> direction, the upper well contact regions 13a and 13b of the p-type conduction induction region appear with the same width w. On the outside of the active portion 100 and the conduction induction region, ^{a terminal structure region 14 as a high-concentration p +} type pressure-resistant region is provided in a frame shape in a plane pattern.

As shown in FIG. 2, the active portion 100 includes an n ^- type drift layer 1, a plurality of high-concentration p ⁺ -type base regions 2a and 2b provided above the drift layer 1, and a base region 2a. , 2b is provided with a plurality of p-type channel regions 3a to 3c provided. Inside each of the channel regions 3a to 3c, n ⁺ type source regions 4a to 4c are selectively provided. ^{High-concentration p +} type base contact regions 5a and 5b are provided between the adjacent source regions 4a and 4c on the base regions 2a and 2b.

Gate insulating films 6a and 6b are provided on the upper surface of the drift layer 1 over the source regions 4a to 4c, the channel regions 3a to 3c, and the upper surface of the drift layer 1. Gate electrodes 7a and 7b are provided on the gate insulating films 6a and 6b, and interlayer insulating films 8a and 8b are provided on the surfaces of the gate electrodes 7a and 7b. Source electrodes 9 are provided on the interlayer insulating films 8a and 8b so as to be connected to the source regions 4a to 4c. A passivation film or the like is deposited as the outermost layer on the upper surface of the source electrode 9, and the main surface of the lower source electrode 9 is exposed in the window portion--opening--formed on the passivation film or the like. ..

^{An n +} type drain region 10 is provided in a layer under the drift layer 1, and a drain electrode 11 connected to the drain region 10 is provided under the drain region 10. In the active unit 100, a main current flows between the source regions 4a to 4c and the drain region 10 by applying a gate voltage to the gate electrodes 7a and 7b.

The conduction induction regions (12a, 13a) are provided by connecting the high-concentration p ⁺ type lower conduction region 12a provided near the upper surface of the drift layer 1 and the source electrode 9 on the lower conduction region 12a. It is provided with a high concentration p ⁺ type upper well contact region 13a. The lower conduction region 12a is provided at substantially the same depth and the same thickness as the base regions 2a and 2b. The upper well contact region 13a has substantially the same depth and the same thickness as the base contact regions 5a and 5b.

The lower conduction region 12a is electrically connected to the source bonding pad by the upper well contact region 13a. The doping concentration of the lower conduction region 12a and the upper well contact region 13a is set to be equal to or higher than the doping concentration of the base contact regions 5a and 5b. For example, when the doping concentration of the base contact regions 5a and 5b ^{is about 1.0 × 10 19} cm ^-3 , the doping concentration of the conduction induction region (12a, 13a) is 1.0 × 10 ¹⁹ cm ^-3 or more as a whole. Will be realized. Since the conduction induction region (12a, 13a) is 1.0 × 10 ¹⁹ cm ^-3 or more as a whole, the entire conduction induction region (12a, 13a) can be regarded as a p-type “well contact region”. can.

In the SiC-MOSFET according to the first embodiment, the total area of the conduction induction region (12a, 13a) to be joined to the source electrode 9 is larger than the total area of the base contact regions 5a and 5b of the active portion 100. Is controlled. That is, the parasitic diode in the conduction induction region (12a, 13a) has a larger junction area with the source electrode 9 than the parasitic diode in the active portion 100.

In the case of the SiC-MOSFET illustrated in FIG. 1, the total area of the two upper well contact regions 13a and 13b is realized to be larger than the total area of the three base contact regions 5a to 5c. In FIG. 1, for convenience of explanation, the upper surfaces of the upper well contact areas 13a and 13b and the base contact areas 5a to 5c are shaded.

Here, the area of the upper well contact region 13a of the left conduction induction region (12a, 13a) in FIG. 1 is S _13a , and the area of the upper well contact region 13b of the left conduction induction region is S _13b . Further, assuming that the area of the base contact region 5a on the left side is S _5a , the area of the base contact region 5b in the center is S _5b , and the area of the base contact region 5c on the right side is S _{5c inside the active portion 100 in FIG.}
(S _13a + S _13b )> (S _5a + S _5b + S _5c ) ... Equation (1)
Is established.

The upper limit of the total area of the upper well contact regions 13a and 13b of the two conduction induction regions is about the total area including the active portion 100 and the conduction induction region because it is necessary to secure the operation as a semiconductor device. It is set in the range of 70% to about 80%.

を満たすように設定される。 Further, as shown in FIG. 1, the lower conduction region 12a and the upper well contact region 13a of the SiC-MOSFET according to the first embodiment extend in the vertical direction with the same length as the active portion 100. It should be noted that this vertical direction is a direction orthogonal to the <11-20> direction of the SiC single crystal, and is also referred to as a "vertical direction" below. As shown in FIG. 3, the width w of the conduction induction region (12a, 13a) is determined by using the thickness d of the drift layer 1 and the inclination angle θ with respect to the <11-20> direction of the SiC substrate.

Is set to meet.

For example, when the thickness d of the drift layer 1 is 10 μm and the inclination angle θ is about 4 °, the width w is w ≧ 10 / tan 4 ° [μm] = about 143 [μm] according to the equation (2).
Therefore, the width w of the conduction induction region (12a, 13a) needs to be about 143 μm or more.

Here, in the MOS transistor structure, when the parasitic diode of the current path of the source electrode 9-base region 2a, 2b-drift layer 1-drain region 10-drain electrode 11 is energized in the forward direction, the electron-is operated in a bipolar manner. Recombination of hole pairs occurs. Dislocations in the SiC substrate expand to stacking defects due to recombination energy, but the expansion direction of the stacking defects is limited to the longitudinal direction orthogonal to the <11-20> direction.

In a normal MOSFET, since a parasitic diode is present in the active portion 100 having a MOS structure, a stacking defect 30 is generated directly under the active portion 100. Then, the on-resistance of the MOSFET increases, which leads to an increase in power loss. Therefore, in the SiC-MOSFET according to the first embodiment, the conduction induction region (12a, 13a) is provided, and the upper well contact region 13a for realizing ohmic contact is further provided in the conduction induction region (12a, 13a). prepare.

Then, as described using the formula (1), the total area of the upper well contact regions 13a and 13b is made larger than the area of the base contact regions 5a to 5c existing in the active portion 100. Therefore, the current when the parasitic diode is energized tends to flow to the upper well contact regions 13a and 13b. Dislocations, on the other hand, each have a current density threshold that initiates expansion into stacking defects. Therefore, the energization is concentrated in the conduction induction region (12a, 13a), and the current density of the parasitic diode in the active portion 100 is relatively lowered, so that the expansion of the stacking defect 30 in the active portion 100 is suppressed.

Even if the SiC-MOSFET according to the first embodiment satisfying the above equations (1) and (2) at the same time is ^{energized with a forward current of a parasitic diode of 400 [A / cm 2} ] at 175 ° C., it is active. No stacking defect 30 was generated in the portion 100, and the on-resistance did not increase. Moreover, when the fluctuation of the forward voltage drop of the parasitic diode was measured, the fluctuation was 0.5% or less, and the increase in resistance could be suppressed.

When the forward current was further increased and energized, as shown in FIG. 4, the occurrence of stacking defects 30 was observed in the conduction induction regions (12a, 13a) on the left side. However, no stacking defect occurred inside the active portion 100, and the on-resistance did not increase. Further, when the fluctuation of the forward voltage drop of the parasitic diode was measured in the SiC-MOSFET in the state shown in FIG. 4, the influence on the voltage drop was still small, and the fluctuation was 0.5% or less at 175 ° C. ..

(First comparative example)
Next, a SiC-MOSFET according to a comparative example in which conduction induction regions are not provided at both ends of the active portion will be described with reference to FIGS. 5 to 9. As shown in FIG. 5, the SiC-MOSFET according to the first comparative example is not provided with a conduction induction region, and 10 channel regions 3a to 3j and 10 source regions are formed on the surface of the active portion 101. 4a to 4j and five base contact areas 5a to 5e appear.

As shown in FIG. 6, the other structures of the SiC-MOSFET according to the first comparative example are the same as those of the SiC-MOSFET according to the first embodiment, and thus duplicate description will be omitted. When a forward current of a parasitic diode of 400 [A / cm ² ] is applied to the SiC-MOSFET according to the first comparative example, as shown in FIG. 7, a stacking defect 30a extending in the vertical direction inside the active portion 101 Occurred and the on-resistance increased.

(Second comparative example)
Further, as shown in FIG. 8, the SiC-MOSFET according to the second comparative example is provided with a p-type auxiliary contact region 5f having a very narrow width around the active portion 101. Different from. In the SiC-MOSFET according to the second comparative example, as in the case of the first comparative example, when the forward current of the parasitic diode is ^{energized by 400 [A / cm 2} ], a stacking defect 30 expanded in the vertical direction occurs. , On resistance increased.

(Third comparative example)
Further, as shown in FIG. 9, in the SiC-MOSFET according to the third comparative example, the lengths of the channel region 3g1,3h1, the source region 4g1,4h1 and the base contact region 5d1 of the cell structure on the left side of the active portion 101 are the second. 1 Shorter than in the case of the comparative example. Further, the lengths of the channel region 3i1, 3j1, the source region 4i1, 4j1 and the base contact region 5e1 of the cell structure on the right side are also shorter than in the case of the first comparative example, and the four corners of the rectangular active portion 101 are fan-shaped p-shaped. Each of the corner contact areas 5g1 to 5g4 is provided. In the SiC-MOSFET according to the third comparative example, as in the case of the first comparative example, when the forward current of the parasitic diode is ^{energized by 400 [A / cm 2} ], a stacking defect expanded in the vertical direction occurs. On resistance increased.

In the SiC-MOSFET according to the first embodiment, conduction induction regions (12a, 13a), which are diode regions, are provided between the active portion 100 and the terminal structure region 14, and the current at the time of reverse conduction is conduction induction. It is guided to the region (12a, 13a) side. Then, using the formula (1), the total area of the upper well contact region 13a to be joined to the source electrode 9 is made larger than the total area of the base contact regions 5a and 5b of the active portion 100 to be joined to the source electrode 9. Is controlled by.

Therefore, at the time of reverse conduction of the SiC-MOSFET, the current is positively induced in the conduction induction region (12a, 13a), and the energy for growing the stacking defect 30 is greatly consumed in the conduction induction region (12a, 13a). Since the energy for growing the stacking defect 30 in the active portion 100 is relatively reduced due to the energy consumption in the conduction induction region (12a, 13a), the expansion of the stacking defect 30 can be greatly suppressed.

In this respect, for example, considering the case where a diode structure for inducing a current other than the active portion 100 is simply connected in parallel, a conduction induction region (12a, 13a) is provided and the total area of the upper well contact region 13a is calculated. Extra wiring is required compared to the case of control. On the other hand, in the case of the SiC-MOSFET according to the first embodiment, it is possible to realize static characteristics equivalent to a diode structure connected in parallel, and because there is no wiring inductance, the current that transiently flows to the active portion 100 side is transferred. Can be reduced.

Further, in the SiC-MOSFET according to the first embodiment, a terminal structure region 14 which is a withstand voltage region is further provided on the peripheral edge of the semiconductor chip outside the conduction induction region (12a, 13a). Therefore, the withstand voltage of the semiconductor device can be further increased while suppressing the occurrence of the stacking defect 30 by the conduction induction region (12a, 13a).

Further, since the length of the conduction induction region (12a, 13a) in the vertical direction is the same as that of the active portion 100, the stacking defect 30 extending in a strip shape in the vertical direction is surely fixed inside and spread to the active portion 100. Can be prevented.

Further, when the width w of the conduction induction region (12a, 13a) satisfies the equation (2), the expansion of the stacking defect 30 extending along the terrace surface of the inclined epitaxial growth film is formed inside the conduction induction region (12a, 13a). It is fastened to. Therefore, the width w is largely secured so as to include the maximum expansion width of the stacking defect, so that the stacking defect 30 does not occur immediately below the active portion 100 adjacent in the <11-20> direction. Therefore, it is possible to prevent the influence on the on-characteristics of the MOSFET.

Further, in the SiC-MOSFET according to the first embodiment, the two conduction induction regions are arranged at both ends of the active portion 100 in a state of being separated as much as possible. Therefore, the heat generated in each conduction induction region is efficiently dispersed in the semiconductor chip, and the deterioration of the quality of the SiC-MOSFET can be prevented.

<Manufacturing method of semiconductor devices>
Next, a method for manufacturing the SiC-MOSFET according to the first embodiment will be described with reference to FIGS. 10 to 14. First, as the SiC substrate, for example, _{a semiconductor substrate 10 sub} ^{which is an n +} type 4H-SiC single crystal and whose surface is the (0001) plane and which is 4 ° off in the <11-20> direction is prepared. Then, as shown in FIG. 10, an n-type 4H-SiC drift layer 1 obtained by adding (doping) nitrogen (N), for example, onto _{a semiconductor substrate 10 sub with an epitaxial growth method having a thickness d of about 10 μm.} Epitaxially grow.

Next, as shown in FIG. 11, a mask 21a having an opening provided at a predetermined position is formed on the upper surface of the drift layer 1 by using a photolithography technique and an etching technique, and aluminum, for example, is formed through the opening. Ions of p-type impurity elements such as (Al) and boron (B) are selectively injected. By this ion implantation, a planned region forming the lower conduction region 12a and the base regions 2a and 2b, respectively, is formed later. In FIG. 11, the outer edge of each planned area is schematically illustrated by a broken line. Ion implantation was performed so that when the planned region was activated, the lower conduction region 12a and the base regions 2a and 2b had the same impurity density, the same depth, and the same thickness inside the drift layer 1. The acceleration voltage of the implanted ions is adjusted.

Next, the mask 21a is removed, and the acceleration voltage is suppressed so that the ions of the p-type impurity element are accumulated in the vicinity of the upper surface of the drift layer 1 through a new mask formed on the upper surface of the drift layer 1. And selectively inject. By this ion implantation, a planned region that later partially forms a channel region 3a to 3c is formed on the base regions 2a and 2b, respectively. Then, the mask for forming the channel regions 3a to 3c is removed.

Next, through a new mask formed on the upper surface of the drift layer 1, ions of n-type impurity elements such as phosphorus (P) and N are selectively placed inside the planned regions of the channel regions 3a to 3c. Inject to form a planned region that will later form the source regions 4a-4c. Then, the mask for forming the source regions 4a to 4c is removed.

Next, as shown in FIG. 12, through a new mask 21b formed on the upper surface of the drift layer 1, p-type impurity element ions are transferred from the source regions 4a to the inside of the planned regions of the channel regions 3a to 3c. Selectively inject during 4c. By this ion implantation, a planned region that later forms the upper well contact region 13a is formed on the lower conductive region 12a, and a planned region that later forms the base contact regions 5a and 5b is formed. In FIG. 12, the outer edge of each planned area is schematically illustrated by a broken line.

Then, the mask 21b is removed, and ions of a p-type impurity element are selectively injected into the peripheral edge of the _{semiconductor substrate 10 sub by using photolithography technology and etching technology to form a region to be formed as a terminal structure region 14 later.} Form. Then, each planned region is activated by activation annealing or the like to form the base regions 2a and 2b of the active portion, the channel regions 3a to 3c, the source regions 4a to 4c and the base contact regions 5a and 5b as shown in FIG. do. Activation also forms a lower conduction region 12a, an upper well contact region 13a and a terminal structure region 14.

_{Next, for example, a silicon oxide (SiO 2} ) film or the like is deposited on the surface of the drift layer 1 by thermal oxidation treatment or the like, and the deposited film is patterned by a photolithography technique, an etching technique or the like to form the gate insulating films 6a and 6b. Form. Next, for example, a doped polysilicon film or the like to which an n-type impurity element such as P is added to a high impurity density is deposited on the entire surface by a reduced pressure CVD method or the like. Then, the doped polysilicon film is patterned by etching or chemical mechanical polishing (CMP) or the like to form the gate electrodes 7a and 7b.

_{Next, for example, a SiO 2} film or the like is deposited on the entire surface by using a CVD method or the like, and this deposited film is patterned by using a photolithography technique and an etching technique, and the interlayer insulating films 8a and 8b are placed on the gate electrodes 7a and 7b. Is provided. Next, the lower surface of the semiconductor substrate 10 _sub is thinned and flattened by CMP or the like to form a drain region 10 as shown in FIG. Then, a metal film such as nickel (Ni) is formed under the drain region 10, and the formed metal film is patterned to form the drain electrode 11.

Then, after performing a predetermined annealing or the like as necessary, for example, an alloy film or the like containing Al as a main component element is deposited, and the source electrode 9 is formed by patterning into a predetermined shape by a photolithography technique, an etching technique, or the like. do. The source electrode 9 is provided over the drift layer 1, the base contact regions 5a and 5b, and the upper well contact region 13a. After that, a sintering process or the like by annealing is performed. The SiC-MOSFET according to the first embodiment can be obtained through the above series of steps.

In the method for manufacturing a SiC-MOSFET according to the first embodiment, ion implantation into a planned region forming a lower conduction region 12a and a base region 2a, 2b is simultaneously executed by the same process. Ion implantation into the planned regions forming the upper well contact region 13a and the base contact regions 5a and 5b is also simultaneously executed by the same treatment. Therefore, in manufacturing the SiC-MOSFET having the conduction induction region (12a, 13a), it is not necessary to provide a separate process having a particularly heavy burden. Therefore, it is possible to manufacture a SiC-MOSFET that can suppress the expansion of the stacking defect 30 while suppressing the burden of further additional steps.

<First modification>
Next, a modification of the SiC-MOSFET according to the first embodiment will be described with reference to FIGS. 15 to 18. As shown in FIG. 15, in addition to the structure of the SiC-MOSFET according to the first embodiment shown in FIG. 1, the SiC-MOSFET according to the first modification has < Auxiliary base contact areas 5h1, 5h2 extending in the 11-20> direction are provided.

The width L of the auxiliary base contact regions 5h1 and 5h2 is very narrow compared to the width w of the conduction induction region. For example, the width w of the conduction induction region is about 143 μm or more, but the width of the auxiliary base contact regions 5h1 and 5h2 is about 5 μm or less. Therefore, even if the area of the auxiliary base contact regions 5h1 and 5h2 is included in the total area of the base contact regions 5a and 5b of the active portion 100, the total area of the upper well contact regions 13a and 13b is the active portion. It is controlled to be larger than the 100 side.

Further, as in the case of the SiC-MOSFET shown in FIG. 2, in the conduction induction region (12a, 13a), the concentration of the lower conduction region 12a is controlled to be high so that the entire region functions as a well contact region. .. Since the other structure of the SiC-MOSFET according to the first modification is equivalent to the member having the same name in the SiC-MOSFET shown in FIGS. 1 to 4, duplicate description will be omitted.

Even if the SiC-MOSFET according to the first modification is energized with a forward current of the parasitic diode of 400 [A / cm ² ] at 175 ° C., the stacking defect 30 does not occur in the active portion 100, and the on-resistance increases. I didn't. In addition, the fluctuation of the forward voltage drop of the parasitic diode could be suppressed to 0.5% or less.

Also in the SiC-MOSFET according to the first modification, the current is positively induced in the conduction induction region at the time of reverse conduction. Therefore, the energy for growing the stacking defects 30 is greatly consumed in the conduction induction region, and the generation of the stacking defects 30 in the active portion 100 can be suppressed.

Further, according to the SiC-MOSFET according to the first modification, the structure of the base contact region of the active portion 100 can be flexibly changed, so that the correspondence to a desired specification can be enhanced. Other effects of the SiC-MOSFET according to the first modification are the same as those of the SiC-MOSFET according to the first embodiment. The auxiliary base contact regions 5h1 and 5h2 may or may not be connected to the left and right conduction induction regions.

<Second modification>
Like the SiC-MOSFET according to the second modification shown in FIG. 16, a conduction induction region may be provided in the center in addition to both ends of the semiconductor chip. In FIG. 16, an upper well contact provided in the center so as to divide the distance between the upper surfaces of the two upper well contact regions 13a and 13b at both ends and the two upper well contact regions 13a and 13b into two equal parts. The upper surface of the region 13c appears.

The active portion 100a is located between the upper well contact region 13a on the left side and the upper well contact region 13c in the center, and the active portion 100b is located between the upper well contact region 13b on the right side and the upper well contact region 13c in the center. Is located. All three conduction induction regions have the same width w satisfying the above formula (2). The other structure of the SiC-MOSFET according to the second modification is equivalent to the member having the same name in the SiC-MOSFET according to the first embodiment.

Also in the SiC-MOSFET according to the second modification, the total area of the upper well contact regions 13a to 13c to be joined to the source electrode is the joint area of the base contact regions 5a and 5c of the active portions 100a and 100b with the source electrode. It is controlled to be larger than the total. Therefore, at the time of reverse conduction, the current is positively induced in the conduction induction region, and the occurrence of stacking defects in the active portion 100 can be suppressed.

Further, according to the SiC-MOSFET according to the second modification, the conduction induction region can be increased to more reliably suppress the occurrence of stacking defects. Other effects of the SiC-MOSFET according to the second modification are the same as those of the SiC-MOSFET according to the first embodiment. The number of conduction induction regions may be three or more, or may be one.

<Third modification example>
The conduction induction region (22a, 23a) may be deeper than the base regions 2a, 2b, as in the SiC-MOSFET according to the third modification shown in FIG. Further, the lower conduction region 22a and the upper well contact region 23a of the conduction induction region (22a, 23a) are both high-concentration p ⁺⁺ type. The other structure of the SiC-MOSFET according to the third modification is equivalent to the member having the same name in the SiC-MOSFET according to the first embodiment.

In the SiC-MOSFET according to the third modification, the total area of the upper well contact region 23a to be joined to the source electrode 9 is the total area of the base contact regions 5a and 5b of the active portion 100 to be joined to the source electrode 9. It is controlled to be large. Therefore, at the time of reverse conduction, the current is positively induced in the conduction induction region (22a, 23a), and the occurrence of stacking defects in the active portion 100 can be suppressed.

Further, according to the SiC-MOSFET according to the third modification, since the conduction induction region (22a, 23a) is formed deeper than the base regions 2a, 2b, the current at the time of reverse conduction is transferred to the conduction induction region (22a, 23a). It becomes easier to guide to the side. Further, since the impurity concentration in the conduction induction region (22a, 23a) is further higher than that in the base contact regions 5a, 5b, the inducibility is further enhanced. Other effects of the SiC-MOSFET according to the third modification are the same as those of the SiC-MOSFET according to the first embodiment.

<Fourth modification>
Like the SiC-MOSFET according to the fourth modification shown in FIG. 18, the conduction induction region (22a, 23a) may be connected to the base regions 2a, 2b and the base contact regions 5a, 5b of the active portion 100. .. The conduction induction region (22a, 23a) shown in FIG. 18 has a structure equivalent to the conduction induction region (22a, 23a) of the SiC-MOSFET according to the third modification shown in FIG. The other structure of the SiC-MOSFET according to the fourth modification is equivalent to the member having the same name in the SiC-MOSFET according to the first embodiment.

That is, if the inducibility of the current at the time of reverse conduction to the conduction induction region (22a, 23a) side is enhanced, the active portion 100 and the conduction induction region (22a, The separation region between 23a) may be eliminated. Also in the SiC-MOSFET according to the fourth modification, the total area of the upper well contact region 23a to be joined to the source electrode 9 is the sum of the joint areas of the base contact regions 5a and 5b of the active portion 100 to the source electrode 9. It is controlled to be large. Therefore, at the time of reverse conduction, the current is positively induced in the conduction induction region (22a, 23a), and the occurrence of stacking defects in the active portion 100 can be suppressed.

Further, according to the SiC-MOSFET according to the fourth modification, the area of the active portion 100 can be secured larger by eliminating the need for the separation region between the active portion 100 and the conduction induction region (22a, 23a). Other effects of the SiC-MOSFET according to the fourth modification are the same as those of the SiC-MOSFET according to the first embodiment.

-Second embodiment-
As shown in FIG. 19, the conduction induction region of the SiC-MOSFET according to the second embodiment has a planar pattern, and has a cell shape provided in a plurality of upper conduction base regions 16 and inside the upper conduction base regions 16. It is different from the SiC-MOSFET according to the first embodiment in that the upper well contact region 15 is provided. The cell-shaped upper well contact region 15 has a substantially hexagonal columnar shape, and is provided so as to extend between the lower conduction region 12a and the upper surface of the drift layer 1 as shown in FIG.

The doping concentration of the upper conduction base region 16 is, for example, about ^{1.0 × 10 18} cm ^-3. The doping concentration of the cell-shaped upper well contact region 15 may be equal to or higher than the doping concentration of the base contact regions 5a and 5b. For example, if the doping concentration of the base contact regions 5a and 5b is ^{about 1.0 × 10 19} cm ^-3 , the doping concentration of the upper well contact region 15 is also set to about ^{1.0 × 10 19} cm ^{-3 or more.} Since the other structure of the SiC-MOSFET according to the second embodiment is equivalent to the member having the same name in the SiC-MOSFET according to the first embodiment, duplicate description will be omitted.

The SiC-MOSFET according to the second embodiment also satisfies the same relationship as in the above equation (1). That is, the total area of the upper surfaces of all the cell-shaped upper well contact regions 15 to be joined to the source electrode 9 is larger than the total area of the upper surfaces of the base contact regions 5a to 5c of the active portion 100 to be joined to the source electrode 9. It is controlled. Further, the width w of the conduction induction region (12a, 15, 16) is set so that the relationship of the above equation (2) is satisfied.

Also in the SiC-MOSFET according to the second embodiment, during reverse conduction, the current is positively induced in the conduction induction region (12a, 15, 16), and the energy for growing the stacking defect is the conduction induction region (12a). , 15, 16) are greatly consumed. Therefore, it is possible to suppress the occurrence of stacking defects in the active portion 100. Other effects of the SiC-MOSFET according to the second embodiment are the same as those of the SiC-MOSFET according to the first embodiment. The shape of the cell in the upper well contact region 15 is not limited to the hexagonal shape, and can be appropriately changed to another polygonal shape, a circular shape, an elliptical shape, or the like.

<Fifth modification>
In the SiC-MOSFET according to the second embodiment, the arrangement density in the vertical direction of the cell-shaped upper well contact regions 15a to 15c is constant as in the SiC-MOSFET according to the fifth modification shown in FIG. It does not have to be. However, it is preferable that the cell-shaped upper well contact regions 15a to 15c are arranged so that the density becomes higher as they are separated from the active portion 100, and conversely, the density becomes lower as they are closer to the active portion 100. ..

For example, the number of cells included in the range X in FIG. 21 is 5 cells in a series below the upper well contact area 15a on the left side and 4 cells in a series below the upper well contact area 15b in the center. , There are two series of cells following the upper well contact area 15c on the right side. As the cell density increases from the active portion 100 side toward the terminal structure region 14 side, injection of holes directly under the active portion 100 can be further suppressed, so that deterioration of MOSFET characteristics can be prevented more reliably.

-Other embodiments-
Although the present invention has been described by the disclosed embodiments described above, the statements and drawings that form part of this disclosure should not be understood as limiting the invention. It should be considered from this disclosure to those skilled in the art that various alternative embodiments, examples and operational techniques will become apparent.

For example, as shown in FIG. 22, the semiconductor chip 44 of the SiC-MOSFET according to the first and second embodiments is mounted on the insulating circuit board (41, 42, 43), and the power semiconductor module (41, 42, 43,44) can also be realized. The insulating circuit board (41, 42, 43) includes an insulating substrate 41, a surface metal foil 42 provided on the upper surface of the insulating substrate 41, and a back surface metal foil 43 provided on the lower surface of the insulating substrate 41. .. By providing the semiconductor chip 44 with a conduction induction region, expansion of stacking defects in the active portion is suppressed, so that conduction deterioration of the power semiconductor module can be suppressed and conduction loss can be reduced.

Further, in the first and second embodiments, the cells having a transistor structure have been described as having a striped shape, but the present invention is not limited to this, and for example, a polygonal shape or another shape may be adopted. Further, although the gate structure of the transistor has been described as a planar type, it may be a trench type. Further, although the n-type has been described as the first conductive type and the p-type as the second conductive type, the present invention holds even if the conductive type is inverted.

Further, in the first and second embodiments, the inclination direction that defines the inclination angle θ of the substrate has been described as the <11-20> direction from the (0001) plane or the (000-1) plane, but the inclination angle θ has been described. The present invention holds even if is defined in a direction other than the <11-20> direction. Further, although the inclination angle θ has been exemplarily described as 4 °, the inclination angle θ is not limited to this, and for example, the inclination angle θ can be set to about 8 °.

Further, the SiC-MOSFET according to the present invention may be configured by combining the partial structures of the respective SiC-MOSFETs shown in FIGS. 1 to 22. As described above, the present invention includes various embodiments not described above, and the technical scope of the present invention is defined only by the matters specifying the invention relating to the reasonable claims from the above description. It is a thing.

1 Drift layer 2a, 2b Base region 3a to 3j, 3g1 to 3j1 Channel region 4a to 4j, 4g1 to 4j1 Source region 5a to 5e, 5d1,5e1 Base contact region 5f Auxiliary contact region 5g1 to 5g4 Corner contact region 5h1,5h2 Auxiliary base contact area 6a, 6b Gate insulating film 7a, 7b Gate electrode 8a, 8b Interlayer insulating film 9 Source electrode 10 Drain area 10 _sub Semiconductor substrate 11 Drain electrode 12a Lower conduction area 13a, 13b, 13c Upper well contact area 14 Termination structure Regions 15, 15a, 15b, 15c Upper well contact region 16 Upper conduction base region 21a, 21b Mask 22a Lower conduction region 23a Upper well contact region 30, 30a Lamination defect 41 Insulation substrate 42 Front metal foil 43 Back metal foil 44 Semiconductor chip 100 , 100a, 100b Active part 101 Active part w Width of conduction induction region d Thickness of drift layer L Width of auxiliary base contact region θ Tilt angle

Claims (12)

A first conductive type drift layer made of a silicon carbide semiconductor substrate, a second conductive type base region provided above the drift layer, and a first conductive type source region selectively provided above the base region. , A gate insulating film provided on the drift layer, a gate electrode provided on the gate insulating film, a source electrode provided on the drift layer, and above the base region above the drift layer. Has a second conductive type base contact region provided in combination with the source electrode, a first conductive type drain region provided under the drift layer, and a drain electrode provided under the drain region. Active part and
A terminal structure region as a pressure resistant region provided outside the active portion, and
An upper surface is provided by joining with the source electrode on the upper part of the drift layer between the active portion and the terminal structure region, and the joining area with the source electrode is joining with the source electrode in the base contact region. The second conductive type conduction induction region, which is set larger than the area,
Equipped with a,
The width w of the conduction induction region along the inclination direction of the silicon carbide semiconductor substrate is between the thickness d of the drift layer and the inclination angle θ of the silicon carbide semiconductor substrate.

A silicon carbide MOSFET characterized in that the relationship of The conduction induction region has an upper well contact region having the upper surface to be joined to the source electrode.
The upper impurity concentration of the well contact region, the silicon carbide MOSFET according to claim 1, wherein at least the impurity concentration of the base contact region. The silicon carbide MOSFET according to claim 1 or 2 , wherein an auxiliary base contact region is further provided in the active portion. A first conductive type drift layer made of a silicon carbide semiconductor substrate, a second conductive type base region provided above the drift layer, and a first conductive type source region selectively provided above the base region. , A gate insulating film provided on the drift layer, a gate electrode provided on the gate insulating film, a source electrode provided on the drift layer, and above the base region above the drift layer. A second conductive type base contact region provided in combination with the source electrode, a first conductive type drain region provided under the drift layer, and a drain electrode provided under the drain region, respectively. With multiple active parts
A terminal structure region as a pressure resistant region provided outside the plurality of active parts,
A second conductive type having an upper surface bonded to the source electrode on the upper part of the drift layer and having a bonding area with the source electrode larger than the bonding area with the source electrode in the base contact region. Conduction induction region and
With
Three or more conduction induction regions are provided at equal intervals between the active portion and the terminal structure region, and between the active portions adjacent to each other .
The width w of the conduction induction region along the inclination direction of the silicon carbide semiconductor substrate is between the thickness d of the drift layer and the inclination angle θ of the silicon carbide semiconductor substrate.

Silicon carbide MOSFET characterized in that the relation holds. The silicon carbide MOSFET according to any one of claims 1 to 4 , wherein the conduction induction region is provided deeper than the base contact region. The silicon carbide MOSFET according to any one of claims 1 to 5 , wherein the conduction induction region and the base contact region are connected to each other. The silicon carbide MOSFET according to claim 2 , wherein the upper well contact region has a plurality of cell shapes. The silicon carbide MOSFET according to claim 7 , wherein the plurality of cell-shaped upper well contact regions are arranged so that the density increases from the active portion toward the terminal structure region. A power semiconductor module comprising the silicon carbide MOSFET according to any one of claims 1 to 8. A second conductive type base region is formed on the upper portion of the first conductive type drift layer made of a silicon carbide semiconductor substrate, a first conductive type source region is selectively formed on the upper portion of the base region, and the drift layer is formed. A gate insulating film is formed on the gate insulating film, a gate electrode is formed on the gate insulating film, a source electrode is formed on the drift layer, and a second conductive film is formed on the base region above the drift layer. The base contact region of the mold is formed by joining with the source electrode, the drain region of the first conductive mold is formed under the drift layer, and the drain electrode is formed under the drain region to form an active portion. And the process to do
A step of forming a terminal structure region as a pressure resistant region on the outside of the active portion, and
The upper surface of the drift layer between the active portion and the terminal structure region is bonded to the source electrode, and the bonding area with the source electrode is larger than the bonding area with the source electrode in the base contact region. The step of forming the second conductive type conduction induction region so as to be large, and
Only including,
The width w of the conduction induction region along the inclination direction of the silicon carbide semiconductor substrate is between the thickness d of the drift layer and the inclination angle θ of the silicon carbide semiconductor substrate.

A method for manufacturing a silicon carbide MOSFET, characterized in that the above relationship is established. The conduction induction region has a lower conduction region and an upper well contact region provided above the lower conduction region.
The method for manufacturing a silicon carbide MOSFET according to claim 10 , wherein the formation of the lower conduction region and the formation of the base region are performed by the same ion implantation. The method for manufacturing a silicon carbide MOSFET according to claim 11 , wherein the formation of the upper well contact region and the formation of the base contact region are performed by the same ion implantation.

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