JP6904119B2 - Solid-state image sensor and image sensor - Google Patents

Description

The present invention relates to a solid-state image sensor and an image pickup device.

The CMOS image sensor can be manufactured using a general CMOS process, and analog and digital circuits can be mixed in the same chip. Therefore, it has a great advantage that the number of peripheral ICs (Integrated Circuits) can be reduced.
A solid-state image sensor such as a CMOS image sensor is composed of a pixel portion having a pixel array in which pixels are arranged in the horizontal direction and the vertical direction, and a peripheral circuit that reads a pixel signal from a plurality of pixels in the pixel portion.

Among the image sensors, the CMOS line sensor has fewer pixels arranged in the vertical direction than the area sensor, so that the area of the pixel portion is smaller. On the other hand, since the peripheral circuit is similar to the area sensor, it occupies a large proportion of the chip. This is because, in general, a plurality of pixels arranged in the horizontal direction are read out at the same time, and therefore, a plurality of circuits corresponding to each pixel are prepared.
Under these circumstances, it is desired to reduce the peripheral circuits in order to reduce the chip area including the CMOS line sensor. As a reduction of peripheral circuits, it can be considered to reduce peripheral circuits by dividing a plurality of pixels arranged in the horizontal direction and reading out pixel signals with a phase shift in the horizontal direction.

However, when reading a pixel signal with a phase shift in the horizontal direction, another pixel (for example, one before or before or after reading a pixel signal from an arbitrary pixel) with a phase shift is read. Since the multiple previous pixels) drive the circuit and operate the circuit, there is a problem that noise is mixed in the pixel signal.
In the solid-state image sensor, a technique for suppressing noise from being mixed in a control signal for controlling pixel reading and a pixel signal read from a pixel has been developed (for example, Patent Documents 1 and 2).

However, since the conventional technique does not consider the case where the pixel signal is read out of phase in the CMOS line sensor, noise is mixed into the pixel signal read out from an arbitrary pixel from other pixels read out out of phase. It does not solve the problem.

An object of the present invention is to provide a solid-state image sensor capable of suppressing noise when a plurality of pixels arranged in the horizontal direction are sequentially read out as pixel signals with their phases shifted in the horizontal direction.

In order to solve the above-mentioned problems, the solid-state image sensor according to the present invention is used.
A pixel portion in which a plurality of pixels are formed into an array of at least one pixel row and a plurality of pixel columns, and the array is divided into a plurality of pixel column groups composed of at least one column of pixel strings,
A control signal for driving the plurality of pixels, a plurality of control lines to supply for each of the plurality of pixels row groups,
Through the plurality of control lines, and a pixel control unit for applying a pre-SL control signal,
A plurality of signal lines that transmit pixel signals output from each of the pixels,
Via the plurality of signal lines, and the read processing unit for reading the pixel signals,
Wherein the plurality of pixel row groups, and a plurality of power supply lines are wired specifically to provide power independently of at least an adjacent pixel row group,
The plurality of control lines and the plurality of signal lines are arranged independently in each pixel sequence group.
The pixel control unit applies the control signal with a phase shift between the plurality of pixel row groups via control lines independently arranged in each pixel row group, and applies the control signal to each of the plurality of pixel row groups. To drive each pixel
The read-out processing unit reads out the pixel signal for each of the plurality of pixel sequence groups via signal lines independently arranged in each pixel sequence group .

According to the present invention, it is possible to provide a solid-state image sensor capable of suppressing noise when a plurality of pixels arranged in the horizontal direction are sequentially read out as pixel signals with their phases shifted in the horizontal direction.

It is a figure explaining an example of the whole structure of the solid-state image sensor which reads out a pixel signal by shifting the phase from each other among a plurality of pixel train groups. It is a figure explaining the structural example of the pixel of the solid-state image sensor. It is a timing chart explaining the operation example of each pixel of the pixel sequence group [N-1], [N], [N + 1] of the solid-state image sensor of FIG. It is a figure explaining the power supply line to the pixel part of the solid-state image sensor of FIG. It is a figure explaining the noise path with the adjacent pixel string group in the solid-state image sensor of FIG. It is a figure explaining the timing at which the noise of FIG. 5 occurs. It is a figure explaining the structural example of the solid-state image sensor of Embodiment 1. It is a figure explaining another configuration example of the solid-state image pickup device of Embodiment 1. It is a figure explaining the specific example of the wiring to each pixel in one pixel string group of the solid-state image sensor of Embodiment 1. FIG. It is a figure explaining the structural example of the solid-state image sensor of Embodiment 2. It is a timing chart explaining an example of the shutter operation of the solid-state image sensor of Embodiment 3. It is a figure explaining an example of the constant current circuit provided in the pixel of the solid-state image sensor of Embodiment 3. It is a figure explaining an example of the stigma circuit provided in the pixel of the solid-state image sensor of Embodiment 3. It is a figure explaining the structural example of the solid-state image sensor of Embodiment 4. It is a figure explaining the structural example of the disconnection circuit of the power supply line applied to the solid-state image sensor of Embodiment 4. It is a figure explaining the structural example of the image pickup apparatus of Embodiment 5.

Hereinafter, embodiments will be described with reference to the drawings. For the sake of clarity, the following description and drawings have been omitted or simplified as appropriate. In each drawing, components and corresponding parts having the same configuration or function are designated by the same reference numerals, and the description thereof will be omitted.
First, a solid-state image sensor to which one embodiment of the present invention is applied will be described, and then each embodiment of the present invention will be described.

FIG. 1 is a diagram illustrating an example of an overall configuration of a solid-state image sensor that reads out pixel signals by shifting the phases of a plurality of pixel train groups.
The solid-state image sensor includes a pixel unit 10, a pixel control unit 20, a readout processing unit 30, an output unit 40, a plurality of control lines LTX, LRT, and a plurality of signal lines VOUT. Each component of the solid-state image sensor is formed on, for example, a semiconductor substrate.
In the following description, the X direction in the figure will be described as the “horizontal direction” and the Y direction will be described as the “vertical direction”. Further, the horizontal direction may be referred to as "main scanning direction" or "row direction", and the vertical direction may be referred to as "secondary scanning direction" or "column direction".

The pixel unit 10 includes a plurality of pixels that generate pixel signals according to incident light. The plurality of pixels form a pixel array in which at least one row of pixels in the horizontal direction and a plurality of columns of pixels in the vertical direction are arranged in two dimensions. Further, the pixel array is divided into a plurality of pixel sequence groups composed of one row or a plurality of rows of pixel rows among the plurality of rows of pixel rows. The plurality of pixel array groups are a plurality of pixel subarrays (subgroups) in which the pixel array is divided in the vertical direction (column direction).
In the present specification, a plurality of pixel strings are identified by using the number "N". In FIG. 1, an example in which a pixel array is composed of three pixel sequence groups (N-1, N, N + 1) is shown.
A plurality of pixels are identified by a pixel column group number, a row number, and a column number in each pixel column group. For example, the pixels [N-1, 3, 1] in the upper left of the figure represent the pixel column group number "N-1", the row number "3", and the column number "1" in each pixel column group. ing. For example, when representing an arbitrary pixel of the pixel column group [N], the pixel [N, *, *] is described, and the row number and the column number in each pixel column group are referred to as "*". Is expressed using.

Each pixel has, for example, a square shape and has the same size as each other. In each of the plurality of pixel train groups, the plurality of pixels are arranged at, for example, even intervals in the horizontal direction, and are arranged at, for example, at equal intervals in the vertical direction.
Pixels in different rows may be incident with different color components (blue, green, red, etc.) of light from the subject by a filter or the like.

Further, a plurality of wirings including a plurality of control lines LRT, LTX, and a plurality of signal lines VOUT are arranged in the pixel unit 10.

The plurality of control lines LRT and LTX are wired so that control signals for driving a plurality of pixels can be supplied to each of the plurality of pixel train groups. Specifically, the plurality of control lines LTX and LRT are connected to each pixel in each pixel sequence group. Each control line LTX and LRT is a linear conductor. In the present specification, for example, the control lines connected to the pixel sequence group [N] are described as LTX [N] and LRT [N].
In the connection between the plurality of control lines LRT, LTX and each pixel, in each one pixel column group, all the pixels in at least one row in each pixel column group are connected to one control line LTX, LRT. In the case of FIG. 1, for example, in the pixel column group [N], the control line LTX [N] is connected to all the pixels in all the rows in the pixel column group [N]. Further, in the pixel column group [N], the control line LRT [N] is connected to all the pixels in all the rows in the pixel column group [N]. The same applies to the other pixel sequence groups.
In each one pixel row group, the plurality of pixels are arranged so as to form a plurality of rows (two rows in FIG. 1) equal to or larger than the number of each of the control lines LTX and LRT.

The plurality of signal lines VOUT transmit the pixel signal output from the pixel to the reading processing unit 30. The plurality of signal lines VOUT are individually connected to each pixel in each pixel column group, and read out the pixel signals of the pixels arranged in each column corresponding to the row and column arrangement of the pixels. Each signal line VOUT is a linear conductor.
In the present specification, the signal line connected to an arbitrary pixel [N, *, *] of the pixel sequence group [N] is described as VOUT [N, *, *]. For example, the signal line connected to the pixels [N, 3, 1] is described as VOUT [N, 3, 1]. Although FIG. 1 shows a configuration example corresponding to each pixel, it may be described as VOUT [N] when indicating the correspondence with the number of the pixel string group.

The pixel control unit 20 controls the drive of pixels via a plurality of control lines LRT and LTX so as to shift the phase between a plurality of pixel train groups and output a pixel signal from each pixel.
Specifically, the pixel control unit 20 includes a plurality of amplifiers 21 and a pixel control circuit 22. The pixel control circuit 22 applies a control signal to each pixel of each pixel row group for each of a plurality of pixel row groups via the control lines LTX and LRT. As a result, the pixel control unit 20 operates each pixel of one pixel group to output a pixel signal (analog signal) so as to have a phase difference between the plurality of pixel groups. In each control line LTX and LRT, an amplifier 21 is provided between the pixel control circuit 22 and each pixel.

The read processing unit 30 reads the pixel signal output from each pixel by shifting the phase between the plurality of pixel string groups via the plurality of signal lines VOUT for each of the plurality of pixel string groups, and performs analog amplification and analog. Perform transfer processing. Specifically, the read processing unit 30 includes a plurality of amplifiers 31 and a transfer circuit 32. The transfer circuit 32 reads a pixel signal from each pixel of each pixel sequence group via each signal line VOUT so as to have a phase difference between the plurality of pixel sequence groups. The plurality of amplifiers 31 are provided between each pixel and the transfer circuit 32 in each signal line VOUT, and amplify the pixel signal read from each pixel in an analog manner. The transfer circuit 32 converts the pixel signals read out so as to have a phase difference between the plurality of pixel train groups into serial signals, and transfers them to the output unit 40 in an analog manner.

The output unit 40 is an interface with the outside of the solid-state image sensor, and performs analog signal processing or digital conversion processing. In the configuration example of FIG. 1, the output unit 40 includes an amplifier 41 that amplifies the signal input from the read processing unit 30. The output unit 40 may be provided with an additional analog signal processing circuit, or an analog / digital conversion circuit and a digital signal processing circuit, after the amplifier 41 for an interface with the outside of the solid-state image sensor. May be done.

As described above, in the solid-state image sensor of FIG. 1, each pixel of each pixel row group is driven and controlled by the pixel control unit 20 in order at the timing of shifting the phase through each control line LRT / LTX. The read-out processing unit 30 sequentially captures the read-out pixel signals into the signal line VOUT connected to each pixel and performs processing.
In the case of FIG. 1, the pixel unit 10, the pixel control unit 20, and the read processing unit 30 are arranged in the horizontal direction. Each control line LTX, LRT and each signal line VOUT includes a section (conductor portion) arranged along the horizontal direction.
In the solid-state image sensor of FIG. 1, in order to shift the reading timing of the pixels in the horizontal direction, the control lines LRT, LTX, and the signal line VOUT are connected to one side in the vertical direction of each pixel row group in the pixel unit 10. Further, in the control lines LRT and LTX, one vertical wiring is arranged in the vertical direction for each of a plurality of pixel groups, and in each pixel column group, all the pixels in the row arrangement in the row direction are connected to the vertical wiring in the row direction. Wired to do.

Next, the pixel configuration will be described. FIG. 2 is a diagram illustrating a configuration example of pixels of a solid-state image sensor.
Each pixel of the pixel unit 10 includes a photoelectric conversion element PD, a transfer transistor TX, a floating diffusion FD, a reset transistor RT, and an amplification transistor SF.
The photoelectric conversion element PD converts the light incident on each pixel into an electric charge to generate a signal electric charge. The photoelectric conversion element PD is, for example, a photodiode.
The transfer transistor TX is connected between the photoelectric conversion element PD and the floating diffusion FD. A control signal (drive signal) is applied from the pixel control unit 20 to the gate terminal of the transfer transistor TX via the control line LTX. The transfer transistor TX transfers an electric charge from the photoelectric conversion element PD to the floating diffusion FD in response to a control signal applied via the control line LTX.

The floating diffusion FD is a region on the semiconductor substrate that temporarily stores the electric charge transferred from the photoelectric conversion element PD.
The reset transistor RT is connected between the reset power supply VDDRT and the floating diffusion FD. A control signal (drive signal for reset) is applied from the pixel control unit 20 to the gate terminal of the reset transistor RT via the control line LRT. The reset transistor RT resets the potential of the floating diffusion FD to the potential of the reset power supply VDDRT in response to the control signal applied via the control line LRT.

The drain of the amplification transistor SF is connected to the power supply VDD, and the source of the amplification transistor SF is connected to the terminal VO. The terminal VO is connected to the signal line VOUT. The gate of the amplification transistor SF is connected to the floating diffusion FD. The amplification transistor SF constitutes a source follower together with a constant current source outside the pixel unit 10. The amplification transistor SF amplifies the voltage corresponding to the electric charge accumulated in the floating diffusion FD, and outputs the amplified voltage to the signal line VOUT.
The voltage output from each pixel is taken in as a pixel signal by the pixel read processing unit 30 through the signal line VOUT, analog amplification and analog transfer processing are performed, and is output from the output unit 40.

FIG. 3 is a timing chart for explaining an operation example of each pixel of the pixel sequence group [N-1], [N], and [N + 1] of the solid-state image sensor of FIG.
Each operation of FIG. 3 corresponds to each node in the circuit diagram of FIG. The control signals on the control lines LRT and LTX have a high level (H level) potential VDD and a low level (L level) potential GND. The pixel signal in the signal line VOUT includes a reset signal VOUTdark indicating the potential when the potential of the floating diffusion FD is reset, and an exposure signal VOUTsig indicating the potential when an electric charge is generated according to the incident light. Further, in FIG. 3, for each of the pixel sequence groups [N-1], [N], and [N + 1] of the pixel unit 10, the reset signal read times tDark [N-1], [N], and [N + 1] are shown. It represents the operation of the period including the read time tSig [N-1], [N], and [N + 1] of the signal level (exposure signal) of the pixel.

The pixel signal reading operation will be described in chronological order with reference to FIG.
First, an operation of reading a pixel signal from each pixel of the pixel string group [N] will be described.
-Reset and read of reset signal VOUTdark At time tRTON [N], the pixel control unit 20 shifts the potential of the control line LRT [N] from low level to high level to change the potential of the floating diffusion FD of each pixel. Reset to the potential of the power supply VDDRT (reset operation).
Next, at time tRTOFF [N], the pixel control unit 20 disconnects the floating diffusion FD of each pixel from the power supply VDDRT by shifting the potential of the control line LRT [N] from a high level to a low level.
After that, at the time tDark [N], the read processing unit 30 reads the reset signal VOUTdark from each pixel of the pixel sequence group [N] via the signal line VOUT (sampling operation).

-Charge transfer and reading of exposure signal VOUTsig At time tTXON [N], the pixel control unit 20 shifts the potential of the control line LTX [N] from low level to high level, so that the photoelectric conversion element responds to the incident light. The charge generated in the PD is transferred to the floating diffusion FD (charge transfer operation).
Next, at the time tTXOFF [N], the pixel control unit 20 disconnects the floating diffusion FD from the photoelectric conversion element PD by changing the potential of the control line LTX [N] from a high level to a low level.
After that, at the time tSig [N], the read processing unit 30 sends an exposure signal VOUTsig of a voltage changed according to the electric charge accumulated in the floating diffusion FD from each pixel of the pixel sequence group [N] via the signal line VOUT. (Sampling operation).

As described above, the pixel control unit 20 operates each pixel of each pixel row group via the control lines LRT and LTX so as to have a phase difference between the plurality of pixel row groups to obtain a pixel signal. Are generated respectively. Further, the read-out processing unit 30 sequentially reads out pixel signals output by the pixel control unit 20 so as to have a phase difference between the plurality of pixel sequence groups.
Next, with reference to FIG. 3, generation and reading of pixel signals having phase differences with each other among a plurality of pixel sequence groups will be described.

By setting the control signal of the control line LRT [N-1] to a high level during the period from the time tRTON [N-1] to the time tRTOFF [N-1], each pixel of the pixel sequence group [N-1] is set to a high level. The potential of the floating diffusion FD is reset. By setting the control signal of the control line LRT [N] to a high level during the period from time tRTON [N-1] to time tRTOFF [N], the potential of the floating diffusion FD of each pixel of the pixel sequence group [N] is increased. , Will be reset. Further, by setting the control signal of the control line LRT [N + 1] to a high level during the period from the time tRTON [N-1] to the time tRTOFF [N + 1], the floating diffusion FD of each pixel of the pixel sequence group [N + 1] can be set. The potential is reset.

At the time tDark [N-1], the reset signal VOUTdark of each pixel of the pixel sequence group [N-1] is read out. At the time tDark [N], the reset signal VOUTdark of each pixel of the pixel sequence group [N] is read out. At the time tDark [N + 1], the reset signal VOUTdark of each pixel of the pixel sequence group [N + 1] is read out.

Next, by setting the control signal of the control line LTX [N-1] to a high level during the period from the time tTXON [N-1] to the time tTXOFF [N-1], the pixel sequence group [N-1] can be set to a high level. Charges are transferred from the photoelectric conversion element PD of each pixel to the floating diffusion FD.
By setting the control signal of the control line LTX [N] to a high level during the period from the time tTXON [N-1] to the time tTXOFF [N], it floats from the photoelectric conversion element PD of each pixel of the pixel sequence group [N]. Charges are transferred to the diffusion FD.
By setting the control signal of the control line LTX [N + 1] to a high level during the period from the time tTXON [N-1] to the time tTXOFF [N + 1], it floats from the photoelectric conversion element PD of each pixel of the pixel sequence group [N + 1]. Charges are transferred to the diffusion FD.

At the time tSig [N-1], the exposure signal VOUTsig of each pixel of the pixel sequence group [N-1] is read out. At the time tSig [N], the exposure signal VOUTsig of each pixel of the pixel sequence group [N] is read out. At the time tSig [N + 1], the exposure signal VOUTsig of each pixel of the pixel sequence group [N + 1] is read out.

The read-out processing unit 30 preferably sets each of the plurality of pixel train groups via each signal line VOUT at a moment different from the moment when the signals of the control lines LTX [N] and LRT [N] rise and fall. Each pixel signal is read from the pixel. In other words, the timing of the operation of each pixel of the plurality of pixel strings is such that the time tDark [N] and tSig [N] are the time tRTON [N], tRTOFF [N], tTXON [N], and tTXOFF [N]. It is decided to be different from any of. If these times match, the potentials of the power supply and the substrate fluctuate due to the voltage fluctuation of the control lines of the pixel train groups adjacent to each other, and the signal of the pixel train group trying to read the pixel signal also fluctuates. , Image quality may deteriorate. According to the operation of FIG. 3, such fluctuations in potential and deterioration of image quality can be suppressed.

As described above, one aspect of the solid-state image sensor that reads out the pixel signals by shifting the phase between the plurality of pixel train groups is to set a plurality of pixels that generate pixel signals according to the incident light in the main scanning direction and the sub It is a solid-state image sensor including a pixel array arranged in two dimensions in the scanning direction, and has the following configuration.
The pixel array includes a plurality of pixel rows arranged in the main scanning direction, and each one of the plurality of pixel row groups includes a plurality of rows along the main scanning direction and a plurality of rows along the sub-scanning direction. It contains a plurality of pixels arranged in two dimensions so as to form a plurality of columns.
In the solid-state imaging device, in each one of the plurality of pixel string groups, the pixel string group is connected so that all the pixels in at least one row in the pixel column group are connected to one control line. A plurality of control lines connected to each pixel in the above, and a plurality of signal lines individually connected to each pixel in the pixel row group in each one pixel row group of the plurality of pixel row groups, and each control. By applying a control signal to each pixel of each pixel group via a line, each pixel of each pixel group is operated so as to have a phase difference between the plurality of pixel groups to generate a pixel signal. A pixel control circuit (pixel control unit) to generate each, and a readout circuit that reads out pixel signals from each pixel of each pixel group via each signal line so as to have a phase difference between a plurality of pixel groups. (Reading processing unit) is provided.
The solid-state image sensor shown in FIG. 1 is an example, and is not limited to this as long as the pixels can be read out for each pixel sequence group by shifting the phase between the plurality of pixel sequence groups.

As described with reference to FIGS. 1 to 3, the solid-state image sensor of FIG. 1 generates and reads pixel signals so as to have a phase difference between a plurality of pixel train groups, so that the read processing unit 30 The circuit in the latter stage can be shared among a plurality of pixel strings. For example, it is possible to process with one set or several sets such as the output circuit and the digital conversion circuit of the output unit 40 after the read processing unit 30. Therefore, as compared with the case where the circuit is provided for each row of the pixel units 10, the number of parts of the circuit is significantly reduced, and the solid-state image sensor with a reduced chip size is possible.

However, when the pixel signal is read out by shifting the phase between the plurality of pixel train groups described above, the period for reading the pixel signal from each pixel of the arbitrary pixel train group (for example, the pixel train group [N]) or the period thereof. In the front and back, a circuit is driven by the pixel drive unit 20 for each pixel of the pixel group to be read one before or a plurality of before an arbitrary pixel group, and a circuit operation is performed. It has been found that noise is mixed in the pixel signal read from each pixel of an arbitrary pixel sequence group by such circuit drive and circuit operation. Noise mixing will be described with reference to FIGS. 4 to 6.

FIG. 4 is a diagram illustrating a power supply line to the pixel portion of the solid-state image sensor of FIG.
In FIG. 4, the power supply to each pixel of the pixel unit 10 is supplied by using the common power supply line 51 common to each pixel row group. As the power supply, there are a power supply VDD, a reset power supply VDDRT, and a ground GND, and the power is supplied from the peripheral circuit or the pad of the pixel unit 10.
In FIG. 4, each pixel of the pixel unit 10 is divided into a photoelectric conversion element PD and a pixel circuit. The pixel circuits are a transfer transistor TX, a floating diffusion FD, a reset transistor RT, and an amplification transistor SF. Further, the pixel control unit 20 and the read processing unit 30 are represented by blocks, and the output unit 40 is omitted. The same applies to FIGS. 7, 8 and 14 referred to below.

FIG. 5 is a diagram illustrating a noise path between adjacent pixel sequences.
FIG. 5 shows, as an example, the relationship between an arbitrary pixel of the pixel string group [N] and an arbitrary pixel of the pixel string group [N + 1] in the power supply by the common power supply line 51 shown in FIG. ing.
As shown in FIG. 5, the floating diffusion FDs of the pixels of the adjacent pixel row group are connected via the power supply lines and the capacitances C1 to C4.
Specifically, the capacity C1 is the capacity between the power supply VDD and the floating diffusion FD, the capacity C2 is the capacity between the reset power supply VDDRT and the floating diffusion FD, the capacity C3 is the capacity between the terminal VO and the floating diffusion FD, and the capacity C4 is grounded. The capacitance between GND and the floating diffusion FD.
The potential fluctuation of the floating diffusion FD raises the potentials of the control lines LTX and LRT connected to the gate terminals of the reset transistor RT and the transfer transistor TX by the pixel control unit 20 in resetting the potential and transferring the electric charge from the photoelectric conversion element PD. It occurs by transitioning from level to low level and from low level to high level.

Due to the potential fluctuation of the floating diffusion FD, the power supply and the like fluctuate via the above-mentioned capacitances C1 to C4. The power supply fluctuation is transmitted to the floating diffusion FD via the capacitances C1 to C4 of the adjacent pixel train group that have not started the potential reset and charge transfer, and becomes noise. Here, the adjacent pixel train group that has not started the potential reset and charge transfer means that the potentials of the control lines LTX and LRT connected by the pixel control unit 20 to the gate terminals of the reset transistor RT and the transfer transistor TX are high. It is a group of adjacent pixel sequences that have not transitioned from level to low level and from low level to high level.
Further, as the potential of the floating diffusion FD fluctuates, the drive current flowing through the terminal VO to which the source of the amplification transistor SF controlled by the constant current circuit is connected also fluctuates. The current fluctuation of the terminal VO becomes the potential fluctuation of the power supply VDD, and the floating diffusion FD of the adjacent pixel train group fluctuates via the capacitance C1 to cause noise.

FIG. 6 is a diagram for explaining the timing at which noise is generated.
By representing the waveform of the signal line VOUT along the time axis, the influence of noise on the output signal (pixel signal) will be described.
In FIG. 6, noise affecting an arbitrary signal line VOUT of the pixel sequence group [N] is added to the timing chart of FIG. 3 with a solid line thicker than the waveform of the signal line VOUT.
As shown in FIG. 6, the noise to the signal line VOUT due to the pixel drive of the adjacent pixel sequence group changes like a thick solid line when paying attention to the pixel sequence group [N], for example. This change occurs in the pixel sequence group [N-1] and the pixel sequence group [N + 1] via the signal lines LRT [N-1] and [N + 1] and the signal lines LTX [N-1] and [N + 1]. A control signal is applied from the control unit 20, and the potential of the gate terminal of the reset transistor RT and the transfer transistor TX is generated immediately after the drive timing of transition from high level to low level and from low level to high level.
In order to make noiseless, it is necessary to prevent the influence of noise at the sampling hold time (reading time tDark, tSig) of the signal of the signal line VOUT of each pixel. The potential level of the signal line VOUT tries to return to the original potential level after the fluctuation of each generated noise, but for the fluctuation of the signal line VOUT that does not return even after this sampling hold time, Noise remains and the image quality deteriorates.

Therefore, the solid-state image sensor according to the embodiment of the present invention includes one or a plurality of pixels that are simultaneously read out when the plurality of pixels arranged in the horizontal direction are sequentially read out with their phases shifted in the horizontal direction. Separate the supply wiring for the power supply and grounding of the pixels for each pixel sequence group to be configured. This provides a solid-state image sensor capable of suppressing noise.
Specifically, in a solid-state image sensor capable of sequentially reading and controlling each pixel sequence group with a phase shift in the horizontal direction and sequentially reading and capturing pixel signals, the noise to be suppressed has the following characteristics.

First, noise is generated from a pixel sequence group other than the pixel sequence group that tries to read the signal of the pixel.
Next, the generated noise is generated by driving the control line connected to the transistor for reading the signal of the pixel which is the noise source, and is transmitted to the power supply and the ground of the transistor of the pixel.
From such a situation, in one embodiment, the power supply and grounding of the pixel to the transistor between the pixel sequence group that reads at least at the same time and the adjacent pixel row group or other pixel row group whose reading phases are out of phase. Separate the supply line.
As a result, the influence of noise generated when reading out other pixel strings is suppressed.
Hereinafter, each embodiment of the present invention will be described. In the following description, as an example of the pixel string group, the pixel sequence groups [N-1], [N], and [N + 1] will be used.

Embodiment 1.
FIG. 7 is a diagram illustrating a configuration example of the solid-state image sensor of the first embodiment. FIG. 7 shows a wiring configuration with three or more power supply lines as an example of wiring of power supply lines applied to the solid-state image sensor according to the present invention. The plurality of power supply lines are identified by using the number "M".
As shown in FIG. 7, the plurality of power supply lines of the solid-state image sensor are wired so that an arbitrary pixel sequence group is independent of the adjacent pixel sequence group and other pixel sequence groups.
In the configuration of FIG. 7, the plurality of power supply lines are composed of a power supply line [M-1] group, a power supply line [M] group, and a power supply line [M + 1] group. , The power supply line [M] group corresponds, the pixel row group [N-1] corresponds to the power supply line [M-1] group, and the pixel row group [N + 1] corresponds to the power supply line [M + 1]. ] Groups correspond.
It is desirable to secure a plurality of power supply lines so as to be independent of the pixel array group affected by noise due to voltage fluctuation due to pixel drive. Specifically, a plurality of power supply lines may be arranged so that any pixel array group is supplied with power from at least an adjacent pixel array group, preferably a power supply line different from other pixel array groups. desirable.

In the following description, a plurality of power supply lines may be described separately as a power supply source wiring and a power supply destination wiring. The power supply source wiring is wiring that supplies power from the power supply to the supply destination wiring. The supply destination wiring is wiring that supplies the power supplied from the power supply source wiring to each pixel of each pixel row group. For example, the power supply line [M] group includes the power supply source wiring 52 [M] and the power supply destination wiring 53 [M], and the same applies to the power supply line [M-1] group or the power supply line [M + 1] group. Is.
Further, when the pixel sequence group is not distinguished for each wiring, the number portion (for example, [M]) of the power supply line is omitted, such as "power supply source wiring 52" and "supply destination wiring 53". Described in.
The power supply source wiring 52 and the power supply destination wiring 53 have different names for the sake of simplicity, and both are included in the plurality of power supply lines of the present specification.

Due to the configuration of the power supply line shown in FIG. 7, the pixel group [N] is affected by noise due to voltage fluctuation due to pixel drive, for example, the pixel group [for example, the pixel signal is read out in the previous stage [ It is possible to suppress the influence of noise generated by power supply fluctuation due to pixel drive and circuit operation generated in N-1] and the pixel sequence group [N + 1] in the subsequent stage.

FIG. 8 is a diagram illustrating another configuration example of the solid-state image sensor of the first embodiment. With reference to FIG. 8, a wiring configuration in the case of two lines having the minimum power supply line will be described.
As shown in FIG. 8, the plurality of power supply lines are wired so that an arbitrary pixel array group is at least independent of adjacent pixel array groups. For example, assuming that the two power supply lines are an even number group of power supply lines and an odd number group of power supply lines, the odd number group of power supply lines corresponds to the odd numbered pixel group of power supply lines, and the odd number group of power supply lines corresponds to the odd numbered pixel group. Is configured to correspond to odd power groups. FIG. 8 shows a case where the number “N” is an odd number and the pixel string group [N] is supplied with power from the odd number group of power supply lines.
In the configuration of FIG. 8, the plurality of power supply lines of the solid-state image sensor are composed of a power supply line [1] group and a power supply line [2] group. Further, the power supply line [1] group includes the power supply source wiring 52 [1] and the supply destination wiring 53 [1], and the power supply line [2] group supplies the power supply source wiring 52 [2]. Includes pre-wiring 53 [2].
With the configuration shown in FIG. 8, the power supply becomes independent between the adjacent pixel sequence groups.

When the pixel signal of the pixel string group [N] is read by the configuration of the power supply line shown in FIG. 8, the power supply by the operation of reading the pixel signal in the adjacent pixel group [N-1] and the pixel group [N + 1]. Noise due to fluctuations such as grounding affects the odd group of power supply lines. However, it is an even-numbered group of power supply lines of the pixel sequence group [N] that reads out the pixel signal, and is independently wired as a power supply line different from the odd-numbered group of power supply lines. The effect of is suppressed.

FIG. 9 is a diagram illustrating a specific example of wiring to each pixel in one pixel sequence group of the solid-state image sensor of the first embodiment. In FIG. 9, a pixel sequence group [N] will be used for description.
In FIG. 9, a plurality of pixels constituting the pixel sequence group [N] are divided into a photoelectric conversion element PD and a pixel circuit as in FIGS. 7 and 8. The plurality of pixels are arranged in three rows of R (red), G (green), and B (black) from the bottom in the horizontal direction, and six columns of pixels of each color in the vertical direction. In FIG. 9, each pixel is identified by using a color component (R, G, B) instead of a row number, and is shown in the upper right corner of the rectangle of the photoelectric conversion element PD. For example, for the upper left pixel [N, B1] in the figure, "N" is the number of the pixel column group, "B1" is the color component "B" instead of the row number, and the column in each pixel column group. It is a symbol in which the number "1" is combined.
Further, regarding the wiring in the pixel column group [N], the wiring in the horizontal direction includes the power supply line L VDD, the control line LTX, and the power line L VDD, the control line LTX, from the side closer to the photoelectric conversion element PD in the area where the pixel circuit of each pixel of each row is arranged. The control line LRT and the reset power supply line L VDDRT are arranged. The wiring in the vertical direction is as shown in the figure.

Although not shown in FIG. 9, the power supply line L VDD and the reset power supply line L VDDRT are the power supply source wiring 52 [M] of the power supply line [M] group in the configuration example of FIG. 7, and the power supply in the configuration example of FIG. The wires are wired so that power is supplied from the power supply source wiring 52 [1] of the odd-numbered group of wires. As shown in FIGS. 7 and 8, the power supply line group [N] is a power supply line group wired at least independently of the adjacent pixel row groups [N-1] and [N + 1]. Is connected with.

The power supply line L VDD is a wiring for supplying an applied voltage for operating the amplification transistor SD, and is also referred to as a pixel power supply line. The power supply line L VDD is connected to the terminal of the power supply VDD of each pixel.
The reset power supply line L VDDRT is a wiring that gives a reset potential for resetting the floating diffusion FD by the reset transistor RT. The reset power supply line L VDDRT is connected to the terminal of the reset power supply VDDRT of each pixel.

Further, each supply line of the power supply line L VDD and the reset power supply line wired in each pixel row group is wired between the adjacent pixel row group and the adjacent pixel row group at least in order to make the power supply independent of the adjacent pixel row group. Has a disconnected layout configuration. More specifically, the horizontal wiring in each pixel row group is cut in the pixel row group and is not connected to the pixels of the adjacent pixel row group. This is because power is supplied from power supply lines that are different from each other among the plurality of pixel train groups.

Although not shown, it is preferable that the ground wiring for grounding the back gate of each transistor of the pixel is also wired independently of the ground wiring to the adjacent pixel train group. The ground wiring is wiring for fixing the back bias with the transfer transistor TX, the reset transistor RT, and the amplification transistor SE, and is also referred to as a pixel ground wire.
Further, in FIG. 9, the power supply line L VDD and the reset power supply line L VDDRT are wired independently between a plurality of pixel train groups, but one of the power supply line L VDD and the reset power supply line L VDDRT is independent. It does not exclude the case of wiring.

As shown in FIG. 9, the supply destination wirings 53 such as the power supply VDD and the reset power supply line L VDDRT for supplying the power supply VDD and the reset power supply VDDRT from the power supply source wiring 52 to each pixel are included in one pixel row group. It is wired independently of the pixel sequence group. Here, the supply destination wiring 53 includes wiring in each pixel row group such as the pixel power supply line, the reset power supply line, and the pixel grounding line described above. Therefore, the power supply line including the power supply source wiring 52 and the power supply destination wiring 53 becomes independent at least between the adjacent pixel train groups.

According to the present embodiment, since the plurality of power supply lines are wired at least independently of the adjacent pixel array groups, noise from the adjacent pixel array groups can be suppressed. Specifically, a pixel string group for reading a pixel signal (for example, a pixel string group [N]) and a pixel string group adjacent to the pixel string group (for example, a pixel string group [N-1], [N + 1]). It becomes independent from and, and it becomes possible to suppress the noise from the adjacent pixel sequence group.

Embodiment 2.
In this embodiment, the specifics of the GND tap applied to the solid-state image sensor will be described.
FIG. 10 is a diagram illustrating a configuration example of the solid-state image sensor of the second embodiment.
As shown in FIG. 10, a plurality of ground wires are arranged independently of one pixel array group and adjacent pixel array groups. The ground wiring is connected to the P + tap 62 through the contact 61 and is connected to the substrate. In FIG. 10, a part of each pixel is represented for the pixel row group [N] and the adjacent pixel row group [N + 1], and the ground wiring GND1 is connected to the well of each pixel of the pixel row group [N] to be grounded. The wiring GND2 shows a configuration example of connecting to the wells of each pixel of the pixel sequence group [N + 1].

In the solid-state image sensor, when the transistor is driven, the back bias of the transistor affects the back bias of the transistor of the adjacent pixel array group through a well forming a pixel or the like.
According to this embodiment, the fluctuation of the back bias can be suppressed by fixing the potential of the well from the ground wiring with the P + tap 62. Further, by wiring the ground wiring independently from the adjacent pixel group, when the ground wiring fluctuates due to the control drive of the pixels in an arbitrary pixel group, the ground wiring is transferred to the adjacent pixel group. Fluctuations can be suppressed.

Embodiment 3.
In this embodiment, as a response to the shutter operation performed by the solid-state image sensor, on / off of the drive current of the amplification transistor SF and the disguise of the pulse waveform of the control line LTX will be described.
FIG. 11 is a timing chart illustrating an example of the shutter operation of the solid-state image sensor according to the third embodiment. FIG. 12 is a diagram illustrating an example of a constant current circuit included in the pixels of the solid-state image sensor according to the third embodiment.

In the solid-state image sensor, a shutter operation is used to change the setting of the exposure period. In the shutter operation, the signal line LTX is pulsed before the signal charge of the pixel photoelectric conversion element PD is read out, the charge accumulated in the pixel photoelectric conversion element PD is discharged, and immediately after that, a new photoelectric conversion element is newly operated. This is an operation of accumulating an electric charge in the PD and reading out the electric charge accumulated in the photoelectric conversion element PD at the time of reading.
As shown in FIG. 11, a pulse operation of the signal line LTX is performed before the reset operation, and the charge accumulated in the photoelectric conversion element PD is temporarily discharged by this pulse operation. After that, the electric charge is accumulated in the photoelectric conversion element PD, and in the next pulse operation of the control line LTX, the electric charge accumulated in the photoelectric conversion element PD is read out. The exposure period is determined by the period of two pulses, the pulse operation before the reset operation and the next bals operation, by the signal line LTX. In FIG. 11, the exposure period is indicated by a dotted arrow between the signal line LTX and the signal line VOUT for each pixel sequence group.

The transistor CSL shown as one of the nodes in FIG. 11 is configured to turn on / off the drive current of the amplification transistor SF.
The transistor CSL is a transistor as an example of a constant current circuit in which a constant current is passed through the amplification transistor. For example, as shown in the circuit diagram of FIG. 12, the amplification transistor SF of the pixel is used as a source follower circuit, and the amplification transistor SF is driven. It is responsible for the constant current operation that allows a constant current to flow. The pixel configuration example shown in FIG. 12 is obtained by adding a transistor CSL to the configuration of FIG.
In the operation timing chart of the transistor CSL shown in FIG. 11, the voltage VCSL is the applied voltage for the constant current operation in which the transistor CSL flows a constant current to drive the amplification transistor SF, and the GND turns off the constant current. It is an applied voltage for the operation of causing.

When performing a pixel reset or read operation, the transistor CSL operates in a constant current state in which a voltage VCSL is applied to drive the amplification transistor SF. On the other hand, during the shutter operation, the transistor CSL operates so as to turn off the current flowing through the amplification transistor SF by setting the voltage to GND.
The pixel control unit 20 controls the operation of the transistor CSL described above so as to shift the phase between the plurality of pixel train groups and disconnect the amplification transistor SF from the constant current circuit.

As described above, by providing the pixel of the solid-state image sensor with the transistor CSL as a constant current circuit, it is possible to suppress noise due to the pulse operation of the control line LTX at the time of shuttering.
Specifically, even during the shutter operation, when the amplification transistor SF is driven and the control line LTX is pulsed, the potential of the floating diffusion FD as a capacitance fluctuates, and the signal line VOUT also follows. The potential fluctuates. Such potential displacement also affects the power supply VDD, which is the drain of the amplification transistor SF, and GND, which is the back gate of the amplification transistor SF. The other pixel sequence group becomes noise when affected by the above-mentioned potential fluctuation during the pixel signal reading operation.

Therefore, in the present embodiment, in order to turn off the drive current of the amplification transistor SF, at least during the pulse operation of the signal line LTX as the shutter operation, a transistor CSL as a constant current circuit is provided, and the applied voltage of the transistor CSL is set to GND. To.
As a result, the current fluctuation of the amplification transistor SF due to the potential fluctuation of the floating diffusion FD due to the bals operation of the signal line LTX during the shutter operation is eliminated, the voltage fluctuation of the power supply VDD of the amplification transistor SF and the GND of the back gate is suppressed, and noise is generated. It is suppressed.

Next, with reference to FIG. 13, the disguise of the pulse waveform of the control line LTX will be described.
FIG. 13 is a diagram illustrating an example of a stigma circuit included in the pixels of the solid-state image sensor of the third embodiment. The pixel control unit 20a shown in FIG. 13 represents only a portion related to the present embodiment, and other configurations are omitted.
The pixel control unit 20a includes a series circuit having a capacitance C5 and a resistor R1 as a sham circuit connected to the signal line LTX, and a switch SW1 for switching the connection to the series circuit. When a control signal is applied to the gate terminal of the transfer transistor TX via a plurality of signal lines, the syllabary circuit slows down the voltage change of the control signal, in other words, the voltage change has a gentle gradient in time. Works as a drive circuit.
Although the operation timing of the switch SW1 is not shown in FIG. 11, the switch SW1 is turned on during the shutter operation and connected to the series circuit of the capacitance C5 and the resistor R1. SW1 is turned off, and the series circuit of the capacitance C5 and the resistor R1 is disconnected. It is operated in opposite phase with the transistor CSL of FIG. 11 at the operation timing.
The pixel control unit 20 controls the on / off of the switch SW1.

In this way, the drive waveform when the transfer transistor TX is controlled via the control line LTX by the sham circuit included in the pixel control unit 20a is such that the switch SW1 is turned off during the pixel reset or read operation. , Not affected by the series circuit. On the other hand, when the shutter is operated, the switch SW1 is turned on, so that when the potential of the control line LTX changes from a low level to a high level and vice versa, there is no sudden voltage change, and the waveform is so-called. "Dullness" occurs. As a result, the potential fluctuation of the floating diffusion FD as a capacitance also becomes gentle in time due to "blunting", the fluctuation of the power supply VDD of the transistor SF and the GND of the back gate is suppressed, and the noise at the time of reading other pixel strings is suppressed. The influence of can be suppressed.
In this embodiment, as shown in FIG. 13, the solid-state image sensor shows a configuration example including a constant current circuit (transistor CSL) for each pixel and a drive circuit (smarting circuit) for the pixel control unit 20. However, even when either the constant current circuit or the drive circuit is provided, the effect of suppressing noise can be obtained.

Embodiment 4.
In this embodiment, an embodiment in which a power supply line disconnection circuit is added to the solid-state image sensor will be described.
FIG. 14 is a diagram illustrating a configuration example of the solid-state image sensor of the fourth embodiment. FIG. 15 is a diagram illustrating a configuration example of a power supply line disconnection circuit applied to the solid-state image sensor of the fourth embodiment.
As shown in FIG. 14, the disconnection circuit 70 is arranged between the power supply source wiring 52 and the supply destination wiring 53 in the power supply line.

As shown in FIG. 15, the disconnection circuit 70 has a configuration in which the power supply source wiring 52 is cut by the switch SW2, and the load capacity C6 is added to the supply destination wiring 53 side when the power supply source wiring 52 is disconnected.
In the solid-state image sensor, the pixel control unit 20 controls the on / off of the switches SW2 of the plurality of disconnection circuits 70, so that the solid-state image sensor is connected to the power supply and disconnected from the power supply for each of the plurality of power supply lines. It is configured to switch between.
Although FIG. 14 shows an example in which the disconnection circuit 70 is added to the configuration of FIG. 7, it is also possible to add the disconnection circuit 70 to the configuration of FIG.

A plurality of power supply lines are independently wired between adjacent pixel train groups, but the wires are directly connected to each other via a circuit other than the pixel unit 10 in which a plurality of pixel train groups are arranged. It will be standardized by. In such a case, the voltage may also fluctuate between the power supply source wirings, and when resetting or reading the pixels, the power supply source wirings and the switch SW2 corresponding to the pixel train group to read the pixel signals are connected. By turning it on and putting it in the connected state, the influence of noise due to the reading operation of the pixels of other pixel groups is suppressed.
The disconnection circuit applied to the solid-state image sensor of the present embodiment is effective when the number of wirings of the power supply line is large, and the connection operation is performed at the same operation timing as the CSL pulse of FIG. The influence of noise due to the driving operation of the pixel row group separated from the row group can be suppressed.

Embodiment 5.
In this embodiment, a configuration example of a camera system will be described as an example of an image pickup apparatus to which the solid-state image pickup device according to the embodiment is applied.
FIG. 16 is a diagram illustrating a configuration example of the imaging device according to the fifth embodiment.
The camera system includes a lens 1, an image pickup device 2, a drive unit 3, and a signal processing unit 4.
The image pickup device 2 is a device to which the solid-state image pickup device of each of the above-described embodiments can be applied.
The lens 1 forms an image of incident light on the imaging surface in the pixel region of the imaging device 2. The lens 1 is an example of an optical system that guides incident light to the photoelectric conversion element PD of the solid-state image sensor.
The drive unit 3 is a drive circuit that drives the image pickup device 2, and includes a timing generator that drives the circuit in the image pickup device 2. The timing generator generates a drive timing signal and drives the image pickup device 2 with a predetermined timing signal. The image pickup device 2 controls the drive of the pixels according to the drive timing signal.
The signal processing unit 4 is a signal processing circuit that processes an output signal (pixel signal) output from the image pickup device 2, and outputs an image signal obtained by subjecting the output signal of the image pickup device 2 to a predetermined signal processing.

The image signal output from the signal processing unit can be recorded in a recording medium such as a memory. The image signal is recorded on the recording medium through an analog-to-digital conversion circuit (AFE) for analog output and through digital signal processing (DFE) for digital output. The image information recorded on the recording medium can be hard-copied by a printer or the like.
Further, the image signal output from the signal processing unit can be displayed as a moving image on a monitor such as a liquid crystal display.

As described above, by mounting the solid-state image sensor of each of the above-described embodiments as the image pickup device in the image pickup device, a highly accurate image pickup device (for example, a camera) can be realized. Further, the solid-state image sensor of one embodiment can reduce the chip area and can contribute to the miniaturization of the image pickup device.

As described above, according to the solid-state image sensor of each of the above-described embodiments, when a plurality of pixels arranged in the horizontal direction are sequentially read out with their phases shifted in the horizontal direction, one or a plurality of pixels are read out at the same time. Noise can be suppressed by separating the power supply wiring and the grounding supply wiring of the pixels for each pixel array group composed of the pixels.

Although the invention made by the present inventor has been specifically described above based on the embodiment, it is said that the present invention is not limited to the above embodiment and can be variously modified without departing from the gist thereof. Not to mention. It is also possible to configure a solid-state image sensor by combining one or a plurality of the above embodiments.

10 Pixel unit 20, 20a Pixel control unit 30 Read processing unit 40 Output unit 51 Common power supply line 52 Power supply source wiring 53 Supply destination wiring 61 Contact 62 P + tap 70 Detachment circuit FD Floating diffusion,
LTX, LRT control line,
PD photoelectric conversion element,
RT reset transistor,
SF amplification transistor,
TX transfer transistor,
VOUT signal line,

Japanese Patent No. 5478905 Japanese Unexamined Patent Publication No. 2009-22521

Claims (8)

A pixel portion in which a plurality of pixels are formed into an array of at least one pixel row and a plurality of pixel columns, and the array is divided into a plurality of pixel column groups composed of at least one column of pixel strings,
A control signal for driving the plurality of pixels, a plurality of control lines to supply for each of the plurality of pixels row groups,
Through the plurality of control lines, and a pixel control unit for applying a pre-SL control signal,
A plurality of signal lines that transmit pixel signals output from each of the pixels,
Via the plurality of signal lines, and the read processing unit for reading the pixel signals,
Wherein the plurality of pixel row groups, and a plurality of power supply lines are wired specifically to provide power independently of at least an adjacent pixel row group,
The plurality of control lines and the plurality of signal lines are arranged independently in each pixel sequence group.
The pixel control unit applies the control signal with a phase shift between the plurality of pixel row groups via control lines independently arranged in each pixel row group, and applies the control signal to each of the plurality of pixel row groups. To drive each pixel
The read-out processing unit is a solid-state image sensor that reads out the pixel signal for each of the plurality of pixel row groups via signal lines independently arranged in each pixel row group. Each pixel is
A photoelectric conversion element that generates a signal charge from incident light, a floating diffusion, and
A transfer transistor that transfers the signal charge to the floating diffusion,
A reset transistor that resets the floating diffusion to the reset potential,
It has an amplification transistor that outputs a pixel signal corresponding to the charge of the floating diffusion.
The plurality of power supply lines include at least one of a plurality of pixel power supply lines for supplying an applied voltage for driving the amplification transistor and a plurality of reset power supply lines connected to the reset transistor and giving the reset potential. The solid-state imaging device according to claim 1. The solid-state image sensor according to claim 2, wherein the plurality of power supply lines include the transfer transistor, the reset transistor, and a plurality of pixel grounding lines for fixing a back bias with the amplification transistor. Each pixel included in the plurality of pixel train groups has a well of each pixel serving as a back gate of the transfer transistor, the reset transistor, and the amplification transistor, among the plurality of pixel ground lines. The solid-state image sensor according to claim 3, wherein the solid-state image sensor is connected to a pixel ground wire corresponding to the above. Each pixel further includes a constant current circuit that allows a constant current to flow through the amplification transistor.
Any one of claims 2 to 4, wherein the pixel control unit controls the amplification transistor so as to disconnect the amplification transistor from the constant current circuit by shifting the phase between the plurality of pixel train groups. The solid-state image sensor according to the above. The pixel control unit is characterized by including a drive circuit that slows down a voltage change of the control signal when the control signal is applied to the gate terminal of the transfer transistor via the plurality of signal lines. The solid-state imaging device according to any one of claims 2 to 5. The solid-state imaging device according to any one of claims 1 to 6, wherein the plurality of power supply lines further include a plurality of switches for switching between a connected state to a power source and a disconnected state. The solid-state image sensor according to any one of claims 1 to 7.
An optical system that guides incident light to each pixel of the solid-state image sensor,
A signal processing unit that processes the signal output from the solid-state image sensor, and
An image pickup device including a drive unit for driving the solid-state image pickup device.

Images