JP6891202B2 - Sealed package with stress reduction layer - Google Patents

Description

The present disclosure generally relates to electronic packaging. And more specifically, it relates to a microelectromechanical system (MEMS) package.

As is known in the art, an electromechanical system (MEMS) is an integrated microdevice or system that combines electronic and mechanical components. MEMS devices can be manufactured, for example, using standard integrated circuit batch processing techniques. Typical applications for MEMS devices include detecting, controlling, and driving on a microscale. Such MEMS devices may function individually or in an array to produce effects on a macro scale.

In the prior art, and as is known, many MEMS devices require a hermetically sealed environment to achieve the best performance. This may be a vacuum environment, a controlled pressure environment, or a controlled gas environment. The packaging environment also provides protection and an optimal operating environment for MEMS devices. Specific examples of these MEMS include infrared MEMS such as bolometers, those sometimes referred to as microbolometers, predetermined inertia MEMS such as gyros and accelerometers, and optical mechanical devices such as mobile mirror arrays. .. Previously, MEMS devices have been individually packaged in vacuum compact packages after the manufacture and dicing of MEMS device wafers. Often, however, the cost of packaging a MEMS device in a conventional metal or ceramic package can be on the order of about 10 to 100 times the device manufacturing cost. This is especially true when vacuum is required in the package.

Over the years, various types of infrared detectors have been developed. Many include a substrate having a focal plane array on it. The focal plane array contains a plurality of detector elements (detection devices), each corresponding to each pixel. The substrate contains an integrated circuit that is electrically connected to the detector element. Commonly known as a readout integrated circuit (ROIC), it integrates the signal from each detector element and multiplexes the signal from the chip with proper tuning and processing (mutiplex). Is what is used for.

As with certain microelectromechanical (MEMS) devices, the bolometer may need to be sealed in a vacuum or other controlled environment for best performance. Typical requirements for packaging bolometer arrays are the integration of IR window materials with a reliable sealing seal that can maintain a high vacuum for extended periods of time and good infrared transmission. , And high yield / low cost packaging. Both the reliability and cost of the MEMS device depend on the encapsulation (packaging) chosen. For MEMS-based bolometers, packaging may be done at the chip level or the UEFA level. A common method of packaging in this instance is to fabricate a protective, IR-transparent cap wafer, or window cap wafer (WCW), and to obtain an active IR detector bolometer region. Bond to the containing semiconductor instance or exposed surface of the device wafer prior to dicing. Cap wafers, sometimes also referred to as window or lid structures, are formed in it with cavities. As the cap wafer is flipped and joined to the device wafer, the cavity provides sufficient clearance to accommodate and protect the MEMS device within it. As described in US Pat. No. 5,701008, title "Integrated infrared mice and gas molecule getter grating in a vacuum package", inventor Ray et al., Published December 23, 1997. As described there, and with reference to FIGS. 1 and 2, the package assembly is shown and has a read-out integrated circuit (ROIC) substrate 2 of semiconductor material, preferably silicon. doing. An infrared (IR) detector array 14 is placed on the substrate 2 and includes a plurality of individual detector elements 6, also referred to as pixels. Although FIG. 2 shows only the detector pixels 6 of a 5 × 6 rectangular parallelepiped array in the detector region 10, typical IR integrated circuits generally have up to hundreds or thousands × hundreds or thousands of pixels 6. It is understood to include a planar IR detector array of. In most commercial applications, IR detectors are often uncooled and IR by detecting the resulting increase in temperature from the heat applied to the detector by IR radiation. Detect the intensity of radiation. A typical layer of uncooled IR detectors is a vanadium oxide (VOx) microbolometer (MB), where multiple individual detectors are often placed on top of the ROIC substrate by conventional semiconductor manufacturing processes. Is formed in an array. The MB array detects IR radiation by detecting the heat of IR generation and is also referred to as the focal plane array (FPA) or sensor chip assembly (SCA). The substrate 2 is an integrated circuit used to process the signal generated by the bolometer. In this case, the bolometer is a microbridge resistor whose resistance changes as the temperature changes. The incoming radiation causes a change in the temperature of the microbridge. Although other semiconductor materials such as silicon (Si) can be used, VOx is a commonly available and cost effective one used in most commercial IR detection applications. ..

As described in US Pat. No. 5,701008 referred to above, the vacuum sealing assembly includes a sealing seal 8 surrounding the IR detector array to seal the detector array from the atmosphere. The seal 8 may be, for example, indium, gold-tin, or other solder, and the height of the seal is precisely controlled when the seal is placed on the substrate 2 or, preferably the wafer 10. Will be done. The seal 8 supports a second substrate, a cap wafer, here an IR transmissive window, here eg silicon. With wafer level packaging, the window wafer 10 appears to have a coefficient of thermal expansion consistent with the FPA wafer, which is also silicon. UEFA 10 is a gettering material formed on a defined region of the surface of UEFA 10 having a predetermined surface region, as described in US Pat. No. 5,701008 referred to above. ), Not shown.

In the prior art, as is also known, Wafer Level Packaging (WLP) has been developed to handle the high cost of MEMS packaging by removing the conventional packaging. One such WLP package is described in U.S. Pat. No. 6,621,477, title "Vacuum vacuum packaging of integrated circuit components", inventor Gooch et al., Published February 18, 2003. In one WLP process, two wafers can be joined together using a bonding material to produce a bonded wafer. For example, one of UEFA is a semiconductor (eg, silicon) device, which has a detector device in the detector region of UEFA. The detector region is located in the central internal region of the device wafer along a read integrated circuit (ROIC) coupled to other wafers. The lid wafer is placed about the detector area of the device wafer using a sheet metal ring of solder. After molding the device in a semiconductor wafer, the wafer contains a thin overglass layer, such as silicon nitride or silicon oxynitride (SiON). To form the bottom layer of titanium, a conventional photolithographic process is used to form the seal ring metal, which acts as a substrate adhesive layer to the ROIC overglass. Next, an intermediate layer of nickel, which acts as a diffusion barrier, is followed by a layer of gold to suppress oxidation formation and strengthen the solder bond. After that, it is referred to as a "seal ring". A similar set of layers is formed on top of the lid wafer to provide a mating surface for the solder seal between the device and the lid wafer. After the formation of the seal ring, solder is applied to, for example, 80% gold and 20% tin, devices and / or lid wafers.

While the described WLP technology provides an effective package, the inventor has found that the edge of the seal ring is the device or ROCI due to the difference in coefficient of thermal expansion between the gold tin 7 solder and the semiconductor device wafer. It was confirmed that the stress was increased in the high stress region as shown in FIG. 3, which is in contact with the wafer. These stresses can result in unwanted crack growth in the overglass and in the underlay of the device or ROIC wafer, as shown in FIG. These cracks can break the interconnect traces in the dielectric layer (ILD) of the interlayer and the ILD of the ROIC, leading to failure.

More specifically, the inventor has confirmed in the prior art that the seal ring metal stack (about 0.5 μm thick) and the solder (up to 11 μm thick) have matching edges. When the solder cools below its melting temperature of about 280 degrees Celsius, the solder shrinks faster than the lower seal ring and ROIC (solder thermal expansion (CTE) is about 16 ppm, silicon CTE is about 3 ppm. ). And the solder is very stiff (gold tin solder has a large Young's modulus) and thus cannot be deformed to relieve stress. The shrinkage of the solder layer tends to pull on the edge of the solder joint, which is responsible for the stress point r and results in cracks at the edge of the joint. Simply increasing the thickness of the titanium (Ti) portion at the bottom of the seal ring has little effect on stress. This is because stress is still left with the solder tension of the seal ring, resulting in stress points. Localized on the ROIC surface by terminating soldering of metal edges adhering to the ROIC surface and providing an intervening layer, for example a titanium stress relaxation buffer layer. The steep edges that transfer stress to the region end on the ROIC surface and are covered with a more ductile material. The inventor further thickened the stress relaxation buffer layer in one embodiment, or thickened the titanium bonding material adhesive layer in another embodiment, when the matching edges were removed. It was confirmed that thickening the lower titanium layer by either of the above further reduces the stress. But only if the matching edges are removed first.

The structure is provided in accordance with the present disclosure. The structure is a substrate; a metal ring placed on the surface portion of the substrate around the surface portion of the substrate; a bonding material placed on the metal ring, having inner and outer edges. Joining material; And here, the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material.

In one embodiment, the first layer of the metal ring comprises a stress relaxation buffer layer placed over the surface portion of the substrate, the first layer being higher than the ductility of the surface portion at a predetermined temperature. It has ductility and is wider than the width of the bonding material. The stress relaxation buffer layer extends laterally beyond at least one of the inner and outer edges of the bonding material.

In one embodiment, the stress relaxation buffer layer has a coefficient of thermal expansion that is greater than the coefficient of thermal expansion of the surface portion of the substrate and smaller than the coefficient of thermal expansion of the bonding material.

In one embodiment, the outer region of the upper surface of the metal ring contains a material that suppresses the adhesion of the bonding material to the upper surface. And here, the portion of the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material.

In one embodiment, the structure comprises a bonding material masking layer over the top surface of the metal ring. The bonding material passes through a window in the masking layer that exposes a portion of the top surface of the metal layer, where the portion of the bonding material windows over the exposed portion of the top surface of the metal layer. Is passing through.

In one embodiment, the portion of the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material.

In one embodiment, the structure comprises a lid. And here, the joining material joins the substrate to the lid.

The stress relaxation buffer layer adheres effectively to the substrate and does not get wet depending on the bonding material. Further, the stress relaxation buffer layer has a preferably intermediate CTE between the coefficient of thermal expansion (CTE) of the surface portion of the substrate bonded to the stress relaxation buffer layer and the CTE of the solder or the bonding material, and It has the properties of a ductile material that locally produces areas of high stress, instead of cracking as in the case of brittle materials such as SiON and Silicon. A typical stress relaxation buffer layer material is titanium.

Using such a configuration, the stress generated between the substrate, eg, the semiconductor wafer, and the bonding layer is such that the edge of the bonding material contacts the stress relaxation buffer layer from the point where the edge of the bonding material contacts the semiconductor wafer. It is shifted to a point and, therefore, away from semiconductor buffers and any associated overglass or brittle material. Therefore, the stress relaxation buffer layer acts as a stress-reducing layer, shifting the high-stress region from the brittle overglass to the more ductile lower layer.

More specifically, when two wafers are joined to form a package and a solder with a high thermal contact rate is used to seal, the solder cools from its melting temperature. As it shrinks, it causes high levels of stress in the lower semiconductor wafer at the edges of the solder joint. The use of the stress relaxation buffer layer 1 isolates the high stress region at the edge of the solder joint from the lower brittle semiconductor wafer. This is due to the interposition of stress relaxation buffer layers, which have a higher level of ductility than the ductility of semiconductor wafers and a thermal shrinkage lower than that of the solder layer and still higher than that of the lower wafer. Thus, the present disclosure allows the integration of high CTE solder or other bonding materials with brittle overglasses on semiconductor structures. In addition, the process can be used for device wafers, lids, or both.

It should be understood that the term ring shape ("ring-happed") refers to and includes the shape surrounding the space. The shape may be circular, rectangular, square, elliptical, or may have an irregular shape, such as a winding or meandering shape.

Details of one or more embodiments relating to the present disclosure will be provided in the accompanying drawings and the following description. Other features, objects, and advantages of the present disclosure will be apparent from the description and drawings, and from the claims.

FIG. 1 is a simplified cross-sectional perspective view of a vacuum package for an IR detector array according to prior art. FIG. 2 is a simplified plan view of the IR detector array used in the assembly of FIG. 1 according to the prior art. FIG. 3 is a cross-sectional view of the IR detector array of FIG. 2, and the cross section is along line 3-3 in FIG. 2 according to the prior art. FIG. 4 is a plan view of a cross section of the sealed package according to the present disclosure, and the cross section is along line 4-4 in FIG. FIG. 5 is a side view of a cross section of the package of FIG. 4, and the cross section is along line 5-5 in FIG. FIG. 5A is an enlarged portion according to a side view of a cross section of FIG. 5, and the enlarged portion is surrounded by arrows 5A-5A in FIG. FIG. 6 is a cross-sectional side view of a sealed package according to another embodiment of the present disclosure. FIG. 6A is an enlarged portion according to a side view of a cross section of FIG. 6, and the enlarged portion is surrounded by arrows 6A-6A in FIG.

Similar reference symbols in various drawings indicate similar elements.

With reference to FIGS. 4 and 5, a hermetically sealed package 100 for the sealing device 102 is shown. Package 100 has a substrate 104 having device 102 in its central region; device 102; cap wafer 108 (FIG. 5); and a pair of metal rings, in this case a multilayer metal ring, 107DW metal ring. , 107 CW; The metal ring 107DW is located on the surface of the substrate 104 around the surface area 106 of the substrate 104, and the other metal ring 107CW is on the surface of the cap wafer 108 around the central area 106. It is located in. It should be understood that in some applications, the metal ring 107CW may not be needed. The metal ring 107DW, as more clearly shown in FIG. 5A, is a ring-shaped stress relaxation buffer layer 109DW (more specifically) placed on the surface of the substrate 104 and in direct contact. , On the overglass layer 116 of the substrate 104 and in direct contact); and on the top surface of the ring-shaped stress relaxation buffer layer 109DW; Including. The metal ring 107CW is a ring-shaped stress relaxation buffer layer 109CW on the surface of the cap wafer 108 around the central region 106; and a seal ring structure 110CW on the upper surface of the ring-shaped stress relaxation buffer layer 109CW). ;including. The bonding material 118 is placed between the two seal ring structures 110DW, 110CW, as shown in FIG. Therefore, as described in more detail below, the ring-shaped stress relaxation buffer layer 109CW is the underlayer material of the ring seal structure 110CW, and the ring-shaped stress relaxation buffer layer 109DW is the ring seal. It is a lower material of the structure 110DW. The stress relaxation buffer layers 109CW and 109DW, respectively, serve as stress relaxation buffer layers for the ring-shaped bonding material for the cap wafer 108 and the device wafer (or substrate 104), respectively.

More specifically, the substrate 104 provides a semiconductor device wafer 112, here, for example, silicon, a read-only integrated circuit ROIC; a device wafer 112 having a metal interconnect electrical conductivity trace to the ROIC component. Includes an interlayer dielectric layer (ILD) 114; and, as shown, an overglass layer 116, which is placed on top of the top surface. As shown, the device 102 is here, for example, an array of infrared (IR) detectors, where, for example, the bolometer is located in the central region 106 above the overglass 116. The cap wafer 108 is any infrared transmissive material and, as shown, has a cavity located above the device 102 and may include a getter material (not shown).

Each of the ring-shaped stress relaxation buffer layers 109DW, CW is a highly ductile material, in this case titanium, for reasons to be explained. The ring-shaped stress relaxation buffer layer 109DW is arranged on the overglass layer 116 as described above. Each one of the two seal ring structures 110DW and 110CW is a lower, substrate adhesive layer 122, placed on the stress relaxation buffer layer 109 on the overglass 116 and cap wafer 108, respectively. For example, titanium; as shown, a diffusion barrier layer 124, here, for example nickel (Ni) or platinum (Pt), placed on top of the substrate bonding layer 122, where the bonding material 118 is substrate bonded. To prevent diffusion into (or interact with) layers 122; and, as shown, an oxide block / bonding material adhesive layer 126, here, placed over diffusion barrier layer 124. For example, gold (Au), for preventing oxidation formation and promoting solder wetting; is included.

Note that each one of the ring-shaped stress relaxation buffer layers 109CW, 109DW pairs is wider than the seal ring structures 110CW, 110DW, respectively, and the bonding material 118. In this embodiment, the inner and outer edges 109a, 109b of the ring-shaped stress relaxation buffer layers 109CW, 109DW, respectively, exceed at least one of the inner and outer sides, and here, of the seal ring structures 110CW, 110DW. Step 224 is formed on either side of the seal ring structure 110CW or 110DW, each over both the inner and outer edges 110b by a length L. The stress relaxation buffer layer 109DW and the seal ring structure 110DW are more clearly shown in FIG. 5A.

More specifically, in this embodiment, the overglass 116 is here, for example, 2000 angstrom thick silicon nitride (SiON), one of each of the ring-shaped stress relaxation buffer layers 109DW and CW. Is a layer of titanium having a thickness greater than, for example, 500 angstroms here, and here, for example, a thickness of 2500 angstroms. Here, for example, each of the ring-shaped stress relaxation buffer layers 109DW and CW is formed using a photolithographic lift-off process. Considering the formation of the stress relaxation layer 109DW and recognizing that the stress relaxation layer 109CW is formed in a similar manner, the ring-shaped stress relaxation buffer layer 109DW is here, for example, of the overglass layer 116. It is formed by first forming a layer of photoresist, not shown, on top. A ring-shaped stress relaxation buffer layer 109DW remains in the region of the photoresist layer inside and outside the region of the device, thereby leaving a ring-shaped region on the wafer surface, in which the ring-shaped stress The relaxation buffer layer 109DW is formed and exposed. The entire surface of the wafer is then coated with titanium using either an evaporation or a physical vapor deposition (PVD) process. Note that part of the titanium will now be deposited on top of the patterned photoresist, and the other part will be deposited on the exposed ring-shaped portion of UEFA. The photoresist is then lifted off the wafer, thereby removing the titanium portion on the photoresist and leaving a ring-shaped stress relaxation buffer layer 109DW on the photoresist. The material can also be manufactured using a mechanical mask without the need for a photolithography process. Another lift-off process is then used to form the seal ring structure 110DW. Here, titanium deposited using either a vapor deposition or physical vapor deposition (PVD) process, eg, has a thickness of 2000 angstroms. Nickel with a thickness of 2500 angstroms deposited using either vapor deposition or physical vapor deposition (PVD) processes, and deposits using either vapor deposition or physical vapor deposition (PVD) processes. Gold with a thickness of 2500 angstroms follows. The width of the ring-shaped stress relaxation buffer layer 109DW is in the range of 300 micrometers here, and the width of the ring-shaped seal ring structure 110DW is here, for example, from the width of the ring-shaped stress relaxation buffer layer 109DW. Note that it is narrow (200 micrometers) and set back from the inner and outer edges 109a, 109b of the ring-shaped stress relaxation buffer layer 109DW, respectively. Here, for example, the inner and outer edges 110a and 110b of the seal ring structure 110DW are set back by length L, respectively, and here, for example, the inner and outer edges 110a of the ring-shaped stress relaxation buffer layer 109DW are set back. , 110b, respectively, 50 micrometers. This is to form step 224, as shown in FIG. 5A. Here, for example, step 224 with a width of 50 micrometers is formed. As a result, the sharp edges of the bonding material 118, eg solder (here eg gold / tin (here eg 80% gold, 20% tin)) set back from the edges of the ring-shaped stress relaxation buffer layer 109DW. And then lifted, respectively, onto the surfaces of the substrate 104 and the cap wafer 108. As a result, the high stress points described in FIG. 3 are shifted (lifted away from the overlay 116). The stress relaxation buffer layer 109DW is then effectively inserted into the path of the high stress points, thereby reducing the stress in the brittle SION overglass layer 116. The stress relaxation buffer layer 109DW is higher than the ductility of the SiON overglass layer 166 at a predetermined temperature, such as room temperature (20-23 degrees Celsius) or the temperature of the package 100 when the lid 108 is joined to the substrate 118. The coefficient of thermal expansion (CTE) of the stress relaxation buffer layer 109DW, which is inserted between the solder 118 and the substrate 118, is the CTE value of the solder and the overglass layer. Note that the value is between the CTE value of 116. Since the stress relaxation buffer layer 109DW has higher ductility than the SiON overglass layer 116, it is possible to further reduce the stress in the brittle SiON overglass layer 116 for small levels of local deformation. ..

As a result, the high stress points SP are shifted out of the fragile SiON layer 116 (where it was placed in FIG. 3) and into the more ductile stress relaxation buffer layer 109DW. The stress points associated with the sharp edges of the stress relaxation buffer layer 109DW are increased ductility of the stress relaxation buffer layer 109DW, thanks to the stress relaxation buffer layer 109DW having a CTE closer to the coefficient of thermal expansion of the lower substrate 104. Combined with relative thinness (here, for example, 2500 angstrom), it has been reduced to insignificant points. In addition, the small step 224 (FIG. 5) dislikes some solder because the surface is finished with titanium oxide after exposure to air, and therefore solder to counter the spread of molten solder 118 from the joints. It works as a solder dam. That is, the surfaces of 109CW and 109DW are titanium oxide, which is rapidly oxidized to titanium oxide, and titanium oxide is a material that suppresses adhesion by the bonding material 118.

The coefficient of thermal expansion (CTE) of AuSn (gold tin) solder is 16 ppm / K, the CTE of Ti (titanium) is ≈8.5 ppm / Fahrenheit (degree Kelvin), and the CTE of Silicon (silicon) is ≈2.6 ppm / Fahrenheit. Note that the degree and the CTE of SiON (silicon oxynitride) ≈ 2 ppm / Fahrenheit. The ring-shaped stress relaxation buffer layer 109DW includes a CTE (that is, overglass layer 116 (2 ppm / Fahrenheit)) of the surface portion of the substrate bonded to the ring-shaped stress relaxation buffer layer 109DW and a seal ring structure. Note that the bonding material 118 above 110 DW has a coefficient of thermal expansion (CTE) (≈8.5 ppm / Fahrenheit) between (approximately intermediate) the CTE (16 ppm / K).

Therefore, it should be noted that the difference in CTE between gold tin solder 118 and silicon is very large (6 times). These are the two main materials causing stress problems. Solder wants to shrink more than 6 times more than the attached silicon as it cools from the molten state of the solder. The stress relaxation buffer layer 109DW has a preferably intermediate coefficient of thermal expansion (CTE) between the CTE of the overglass layer 116 and the CTE of the solder or bonding material 118, and in the case of brittle materials such as silicon oxynitride and silicon. Note that the ductile stress relaxation buffer layer 109DW can locally generate high stress regions instead of cracking as in. The stress relaxation buffer layer 109CW has a higher ductility than the ductility of the silicon cap wafer 108, and the coefficient of thermal expansion (CTE) of the stress relaxation buffer layer 109CW is inserted between the solder 118 and the silicon cap wafer 108. Also note that it is.

With reference to FIG. 6, a sealed package 100'according to another embodiment of the present disclosure is shown. Here, the seal ring structure 110DW'has a titanium substrate bonding / diffusion barrier layer 122' (FIG. 6A), and in fact, the layer 122'is from the diffusion barrier layer 122 and the stress relaxation layer 109DW. It has become. Therefore, the substrate bonding / diffusion barrier layer 122'is actually titanium thickened to a layer having a thickness of approximately 4000 angstroms, and serves two purposes: the substrate bonding layer 122 and the stress relaxation layer 109DW. The solder mark 150, here for example titanium or titanium nitride, has a window formed therein using a photolithographic etching process or lift-off lithography to expose the lower portion of the bonding material adhesive layer 126. There is. It should be noted that when titanium is used for the solder mask 150, titanium oxide is quickly oxidized to titanium oxide, and titanium oxide suppresses the adhesion of the bonding material 118. Similarly, titanium nitride suppresses the adhesion of the bonding material 118.

Bonding material 118, here solder, for example, is deposited into the window onto the exposed portion of the bonding material adhesive layer 126. Note that the sealing material 116 is narrower than the metal ring 107DW'. The metal ring here includes a seal ring structure 110 DW'and a solder mark 150, which sets back the edge of the bonding material 118 from the edge of the metal ring 107 DW', as shown. It is also noted that this setback forms a solder dam equivalent to step 224 described above in connection with FIGS. 5 and 5A. It should be understood that a similar structure is used in this example for the metal ring on the cap wafer 108.

The structure according to the present disclosure is a substrate; a metal ring placed on the surface portion of the substrate around the surface portion of the substrate; placed on a metal ring having inner and outer edges. It should now be correctly understood that it contains a bonding material; and the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. One or more of the following features may include independent or combined with another feature. Here, the first layer of the metal ring includes a stress relaxation buffer layer arranged on the surface portion of the substrate, the first layer having higher ductility than the surface portion at a predetermined temperature. And wider than the width of the bonding material, the stress relaxation buffer layer extends laterally beyond at least one of the inner and outer edges of the bonding material. Here, the stress relaxation buffer layer has a coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the surface portion of the substrate and smaller than the coefficient of thermal expansion of the bonding material. Here, the region of the upper surface of the metal ring contains a material that suppresses the adhesion of the bonding material to the upper surface, and the portion of the metal ring is lateral beyond at least one of the inner and outer edges of the bonding material. It is spreading in the direction. The structure includes a bonding material masking layer over the top surface of the metal ring, and the bonding material passes through a window in the masking layer that exposes a portion of the top surface of the metal layer, and here. A portion of the bonding material passes through the window over the exposed portion of the top surface of the metal layer. Here, the portion of the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The structure includes a lid and a device placed on the substrate, where the joining material joins the substrate to the lid. Here, the stress relaxation buffer layer has a coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the surface portion of the substrate and smaller than the coefficient of thermal expansion of the bonding material. The structure includes a bonding material masking layer on top of the top surface. A bonding material masking layer is included on top of the metal ring, and the bonding material passes through a window in the masking layer that exposes a portion of the top surface of the metal layer, where the portion of the bonding material Passes through the window over the exposed portion of the top surface of the metal layer. Here, the stress relaxation buffer layer is placed on the surface portion of the substrate and is in direct contact with it. Here, the first layer of the metal ring includes a stress relaxation buffer layer disposed on the surface portion of the substrate. Here, the first layer of the metal ring is titanium. Here, the first layer of the metal ring is copper or aluminum. Here, the upper surface of the substrate is silicon oxynitride. Here, the substrate contains silicon. Here, the first layer of the metal ring is titanium having a thickness greater than 500 angstroms.

The structure according to the present disclosure should also be correctly understood to include: The structure includes a seal ring disposed on the substrate; stress relaxation buffer layer; stress relaxation buffer layer and around the surface portion of the substrate. Here, the stress relaxation buffer layer has a ductility higher than the ductility of the surface portion of the substrate at a predetermined temperature. The bonding material is placed on top of the seal ring, and the bonding material has inner and outer edges. And here, the stress relaxation buffer layer extends laterally beyond at least one of the inner and outer edges of the bonding material. In addition, the ring-shaped stress relaxation layer may have a CTE between the coefficient of thermal expansion (CTE) of the surface portion of the substrate and the CTE of the bonding material on the seal ring.

The structure according to the present disclosure should also be correctly understood to include: The structure is a substrate; a device placed on the substrate; a seal ring placed on the substrate around the device; a bonding material placed on the seal ring; a bonding material and a substrate. A layer disposed between and a layer that extends laterally beyond at least one of the inner and outer edges of the joining material; the lid; and the joining material has a substrate relative to the lid. To join. In addition, the layer has a CTE between the coefficient of thermal expansion (CTE) of the surface portion of the substrate and the CTE of the bonding material on the seal ring.

It should also be correctly understood that packages in accordance with this disclosure include: The package is a substrate; a device placed on the surface of the package; a metal ring placed around the device and above the surface portion of the substrate; a lid; a bonding material placed on the opposite ends of the metal ring. To include. Here, the metal ring extends laterally beyond at least one of the inner and outer edges of the joining material, and the joining material joins the lid to the substrate. One or more of the following features may be included independently or in combination with another feature. The feature is that the first layer of the metal ring includes a stress relaxation buffer layer placed on the surface portion of the substrate, the first layer having higher ductility than the ductility of the surface portion at a predetermined temperature. And, wider than the width of the bonding material, the stress relaxation buffer layer extends laterally beyond at least one of the inner and outer edges of the bonding material. Here, the stress relaxation buffer layer has a coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the surface portion of the substrate and smaller than the coefficient of thermal expansion of the bonding material. Here, the region of the upper surface of the metal ring includes a material that suppresses the adhesion of the bonding material to the upper surface, and the portion of the metal ring is laterally beyond at least one of the inner and outer edges of the bonding material. It is spreading. The package contains a bonding material masking layer over the top surface of the metal ring, the bonding material passes through a window in the masking layer that exposes the top surface portion of the metal layer, and the bonding material portion is It passes through the window over the exposed portion of the top surface of the metal layer.

Numerous embodiments of the present disclosure have been described. Nevertheless, it will be appreciated that various changes can be made without departing from the spirit and scope of this disclosure. For example, sealed packages can be used for a wide variety of devices. Not limited to these, infrared MEMS such as bolometers, those sometimes referred to as microbolometers, and predetermined inertia MEMS such as gyros and accelerometers, junction-only devices for packages, non-evacuated applications ( It includes (such as DLP) or a wafer-bonded MEMS in a vacuum package. In addition, other materials may be used for the stress relaxation buffer layers 109DW and / or 109CW. For example, copper or aluminum. In addition, other materials may be used for the substrate adhesive layer 122. For example, TiN. In this case, both Ti and Ni act as diffusion barriers for different stages of the manufacturing process. In addition, other materials may be used for the bonding material. For example, CuSn. In addition, other overglass materials may still be used. For example, SiN. Therefore, the other examples are within the scope of the following claims.

Claims (3)

A method to prevent cracks in the substrate,
It has a metal seal ring on the surface of the substrate and solder on the upper surface of the metal seal ring.
The solder and the metal seal ring have matching outer edges and
The method is
A step of providing a metal stress relaxation buffer layer between the metal seal ring and the surface of the substrate, wherein the outer edge of the metal stress relaxation buffer layer is the matching outer side of the solder and the metal seal ring. It extends outward from the edge by a sufficient distance to prevent cracking.
The metal seal ring is
An oxide block / bonding material adhesive layer arranged on the upper surface of the metal seal ring,
A diffusion barrier layer placed beneath the oxidation block / bonding material adhesive layer,
See containing and a substrate adhesive layer disposed between the diffusion barrier layer and the metal stress relaxation buffer layer,
The metal seal ring is completely spaced from the surface of the substrate.
Steps and
A step of providing a bonding material on the oxide block / bonding material adhesive layer of the metal seal ring , wherein the bonding material has a yield strength equivalent to that of the metal stress relaxation buffer layer .
A step of joining the metal seal ring to the lid structure using the joining material so as to form a sealed package .
Including
The metal stress relaxation buffer layer extends laterally beyond the bonding material by a length sufficient to prevent cracking of the substrate, and the metal sealing ring is provided with the lid structure using the bonding material. When joined to, the sealed package is formed and
The material of the metal stress relaxation buffer layer is titanium.
Method. The bonding material has a yield strength equivalent to that of the metal stress relaxation buffer layer.
The method according to claim 1. The metal stress relaxation buffer layer separates the stressed region at the edge of the bonding material from the bottom region of the substrate.
The method according to claim 1.

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