JP6858636B2 - Semiconductor storage device - Google Patents

Description

The present invention relates to a semiconductor storage device.

There is a semiconductor storage device having an ECC (Error Checking and Correcting) function that detects and corrects an error in data read from a memory cell for the purpose of improving performance and yield. For example, in a non-volatile memory such as MRAM (Magnetoresistive Random Access Memory), even a normal bit becomes defective with a certain probability (error rate), so an ECC circuit that executes the above ECC function is used. There is. As an example, there is an ECC circuit that detects and corrects a 1-bit error using a Hamming code.

There is also a code corresponding to error detection and correction of 2 bits or more. One example is the Golay code. By using the Golay code, it is possible to detect and correct a 3-bit error from 23 bits, which is a combination of an 11-bit inspection bit (sometimes called a parity bit) and a 12-bit data bit.

Japanese Unexamined Patent Publication No. 2008-117430 Japanese Unexamined Patent Publication No. 11-73797 Japanese Unexamined Patent Publication No. 2008-176828 Japanese Unexamined Patent Publication No. 2009-433585

By the way, in a conventional semiconductor storage device, error detection and correction are performed using an ECC circuit in order to increase the yield in a process such as a pre-shipment test. However, if the error bits corresponding to the number of correctable bits are corrected in the process, there is a problem that the error bits increased after the process (for example, the error bits increased after shipment) cannot be corrected.

In one aspect, it is an object of the present invention to provide a semiconductor storage device capable of correcting an increased error bit.

In one embodiment, a plurality of bits of error detection and correction up to a third bit number are supported based on the write data of the first bit number and the first data of the second bit number. The inspection bit generation circuit that generates the first inspection bit of the code, the memory cell unit that stores the write data and the first inspection bit, and the operating state set based on the set signal are the first. In the state, the second data having a value different from the first data by at least one bit is output, and when the operating state is the second state, the first data is higher than the second data. A setting circuit that outputs a third data having a different value from the data of the above and a small number of bits, a first read data corresponding to the write data and read from the memory cell unit, and the setting circuit. Generates the second inspection bit of the code based on the second data or the third data output by, and corresponds to the first inspection bit and is read from the memory cell unit. An error detection circuit that detects an error bit based on the third inspection bit and the second inspection bit and outputs a detection result, and at least the above error bits based on the detection result. Provided is a semiconductor storage device including an error correction circuit that corrects a first error bit included in the first read data.

In one aspect, the invention allows for correction of increased error bits.

It is a figure which shows an example of the semiconductor storage device of 1st Embodiment. It is a figure which shows an example of the semiconductor storage device of 2nd Embodiment. It is a figure which shows the 11-bit data pattern of the Golay code associated with each bit of the 12-bit data. It is a figure which shows an example of the XOR circuit which performs the XOR operation of 7 input 1 output. It is a figure which shows the correspondence relationship between each input of 7-input 1-output XOR arithmetic circuit, data bit, and output inspection bit. It is a figure which shows the 11-bit data pattern of the Golay code associated with each bit of 12-bit data and 11-bit inspection bit. It is a figure which shows an example of the XOR circuit which performs the XOR operation of 8 inputs and 1 output. It is a figure which shows the correspondence relationship between each input of an XOR arithmetic circuit of 8 inputs 1 output, each bit of read data and read inspection bit, and each bit of output syndrome. It is a figure which shows the correspondence relationship between a decoded signal based on a syndrome, and an error bit. It is a figure which shows an example of a syndrome decoder. It is a timing chart which shows an example of the operation of the syndrome decoder when a 2-bit error occurs. It is a timing chart which shows an example of the operation of the syndrome decoder when a 4-bit error occurs. It is a figure which shows an example of a virtual data error detection circuit and an error signal output circuit. It is a timing chart which shows an example of the operation of a virtual data error detection circuit and an error signal output circuit when a 4-bit error occurs. It is a figure which shows an example of an error correction circuit. It is a timing chart which shows an example of the operation of an error correction circuit when a 2-bit error occurs. It is a timing chart which shows an example of the operation of an error correction circuit when a 4-bit error occurs. It is a flowchart which shows an example of the chip grade sorting method. It is a figure which shows an example of the semiconductor storage device of 3rd Embodiment. It is a figure which shows an example of a selection circuit. It is a figure which shows an example of the error MAX flag generation circuit. It is a figure which shows an example of a flag output circuit. It is a flowchart which shows the operation flow of an example of the semiconductor storage device of 3rd Embodiment which has a redundant cell.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First Embodiment)
FIG. 1 is a diagram showing an example of a semiconductor storage device according to the first embodiment.

The semiconductor storage device 10 includes a data input / output unit 11, a virtual data setting circuit 12, an inspection bit generation circuit 13, a memory cell unit 14, a test mode setting circuit 15, an error detection circuit 16, and an error correction circuit 17. The virtual data setting circuit 12, the inspection bit generation circuit 13, the memory cell unit 14, the test mode setting circuit 15, the error detection circuit 16, and the error correction circuit 17 function as ECC circuits. Note that FIG. 1 shows a portion that accepts an address designation to the memory cell unit 14, a portion that accepts a write command or a read command, a circuit that selects a memory cell according to the address, a write circuit, a read circuit, and the like. Is omitted.

The data input / output unit 11 receives the write data wd written to the memory cell unit 14 from the outside of the semiconductor storage device 10, reads it from the memory cell unit 14, and receives the error-corrected read data rda from the outside of the semiconductor storage device 10. Output to.

The virtual data setting circuit 12 supplies the inspection bit generation circuit 13 with data (hereinafter referred to as virtual data) 18a having a predetermined number of bits to be added to the write data wd. In the example of FIG. 1, the virtual data 18a is a 4-bit value (0000) in which the value of each bit is 0.

The inspection bit generation circuit 13 generates an inspection bit wpb having a code corresponding to error detection and correction of a plurality of bits up to a predetermined number of bits based on the write data wd having a predetermined number of bits and the virtual data 18a. To do. Codes corresponding to error detection and correction of a plurality of bits include Golay code and BCH code. The write data wd is written to the memory cell unit 14 in units of 1 byte (8 bits), for example.

For example, when the inspection bit generation circuit 13 generates a Gorey code inspection bit wpb corresponding to error detection and correction up to 3 bits, 12 bits from 8-bit write data wd and 4-bit virtual data 18a. Generate the check bit wpb.

The memory cell unit 14 stores the write data wd and the inspection bit wpb. In the example of FIG. 1, the inspection bit wpb is written in the inspection bit storage unit 14a of the memory cell unit 14, and the write data wd is written in the data storage unit 14b of the memory cell unit 14. In the memory cell unit 14, for example, a plurality of memory cells (not shown) are arranged in an array. The memory cell is a storage element such as an MRAM cell, a FeRAM (Ferroelectric Random Access Memory) cell, or a DRAM (Dynamic Random Access Memory) cell.

The test mode setting circuit 15 outputs virtual data 18b having a value of at least one bit different from that of the virtual data 18a when the operating state set based on the setting signal set is the first state. Further, when the operating state is the second state, the test mode setting circuit 15 outputs virtual data 18c having a smaller number of bits with different values for the virtual data 18a than the virtual data 18b. The setting signal set is supplied from, for example, a control circuit (not shown) or the outside of the semiconductor storage device 10.

In the example of FIG. 1, the virtual data 18b is a 4-bit value (0001) in which the least significant bit of the virtual data 18a is inverted, and the virtual data 18c is a 4-bit value (0000) which is the same as the virtual data 18a. For example, when an error is intentionally generated, the first state is set in the test mode setting circuit 15, and when the error is not intentionally generated, the second state is supplied to the test mode setting circuit 15. ..

The error detection circuit 16 described above is based on the virtual data 18b or virtual data 18c output by the test mode setting circuit 15 and the read data rd (corresponding to the write data wd) read from the memory cell unit 14. Generates a check bit for the sign of. Then, the error detection circuit 16 detects the error bit based on the inspection bit and the inspection bit rpb read from the inspection bit storage unit 14a, and outputs the detection result.

The read data rd corresponds to the write data wd, and if there is no error bit, the read data rd has the same value as the write data wd. Further, the inspection bit rpb corresponds to the inspection bit wpb, and if there is no error bit, the inspection bit rpb has the same value as the inspection bit wpb.

The error correction circuit 17 corrects the error bits included in the read data rd among the error bits based on the detection result output by the error detection circuit 16. In the example of FIG. 1, the error correction circuit 17 receives the read data rd and outputs the read data rda in which the error bit of the read data rd is corrected.

The error correction circuit 17 may receive the inspection bit rpb, correct the error bit of the inspection bit rpb, and output the error bit.
Hereinafter, an example of the operation of the semiconductor storage device 10 according to the first embodiment will be described.

In the following description, the inspection bit generation circuit 13 will be described as generating the inspection bit wpb having a code that can detect and correct a 3-bit error.
For example, in the pre-shipment test for the semiconductor storage device 10, when the first state is set in the test mode setting circuit 15 based on the setting signal set, the error detection circuit 16 is supplied with virtual data 18b.

At this time, the error detection circuit 16 generates the inspection bit having the above-mentioned code based on the virtual data 18b and the read data rd. Then, the error detection circuit 16 detects an error bit based on the generated inspection bit and the inspection bit rpb read from the inspection bit storage unit 14a.

In the example of FIG. 1, since the virtual data 18b has a value of 1 bit different from that of the virtual data 18a, the error detection circuit 16 detects at least 1 bit of an error bit. In other words, the error detection circuit 16 can further detect an error bit of 2 bits.

Therefore, when there is no error bit in the inspection bit rpb and the 2-bit value of the read data rd is different from the write data wd (when a 2-bit error occurs), the error detection circuit 16 has a 3-bit error. Detect a bit. At this time, the error correction circuit 17 corrects the error by inverting the value of the 2-bit error bit included in the read data rd from 1 to 0 or 0 to 1 based on the detection result output by the error detection circuit 16. I do. Then, the error correction circuit 17 outputs the read data rda.

If the virtual data 18b as shown in FIG. 1 is used and the read data rd contains 3 or more error bits, an error of 4 or more bits occurs. Therefore, the error bits are normally set in the error detection circuit 16. Not detected. As a result, the error bit is not corrected normally, the read data rda is different from the write data wd, and a defect of the semiconductor storage device 10 is detected.

When the second state is set in the test mode setting circuit 15 based on the setting signal set after the pre-shipment test of the semiconductor storage device 10 as described above, the virtual data 18c is supplied to the error detection circuit 16. ..

At this time, the error detection circuit 16 generates the inspection bit having the above-mentioned code based on the virtual data 18c and the read data rd. Then, the error detection circuit 16 detects an error bit based on the generated inspection bit and the inspection bit rpb read from the inspection bit storage unit 14a.

In the example of FIG. 1, since the virtual data 18c has the same value as the virtual data 18a, the error detection circuit 16 does not detect the intentionally generated error bit. In other words, the error detection circuit 16 can detect a 3-bit error bit.

Therefore, even if a 1-bit error occurs in addition to the 2-bit error detected during the pre-shipment test, the error detection circuit 16 can detect the increased error bit. For example, when the inspection bit rpb has no error bit and the read data rd has a 3-bit error bit, the error correction circuit 17 has the 3-bit error based on the detection result output by the error detection circuit 16. Error correction is performed by inverting the bit value. Then, the error correction circuit 17 outputs the read data rda.

As described above, according to the semiconductor storage device 10 of the first embodiment, the inspection bit wpb is generated based on the write data wd and the virtual data 18a that is not written to the memory cell unit 14. Then, at the time of error detection and correction using the read inspection bit rpb, the number of intentional error bits is set using the virtual data 18b and 18c, so that the error correction capability (detection) for the read data rd is performed. The upper limit of error bits that can be corrected) can be changed. For example, as described above, changes can be made such as limiting the correction ability during the pre-shipment test and then maximizing the correction ability. This makes it possible to correct error bits that increase after shipment.

In the above description, an example using virtual data 18b that intentionally generates a 1-bit error has been described, but virtual data that generates an error bit of 2 bits or more may be used. An example will be described later.

(Second Embodiment)
FIG. 2 is a diagram showing an example of the semiconductor storage device of the second embodiment.
The semiconductor storage device 20 has an ECC function that detects and corrects errors using the Golay code. The semiconductor storage device 20 includes a data input / output unit 21, a virtual data setting circuit 22, an inspection bit generation circuit 23, a memory cell unit 24, a test mode setting circuit 25, an error detection circuit 26, and an error correction circuit 27.

Note that FIG. 2 shows a portion that accepts an address designation to the memory cell unit 24, a portion that accepts a write command or a read command, a circuit that selects a memory cell according to the address, a write circuit, a read circuit, and the like. Is omitted.

The data input / output unit 21 receives the write data WD written in the memory cell unit 24 in 8-bit units from the outside of the semiconductor storage device 20, reads it from the memory cell unit 24 in 8-bit units, and corrects the error. The RDa is output to the outside of the semiconductor storage device 20.

The virtual data setting circuit 22 supplies the inspection bit generation circuit 23 with 4-bit virtual data added to the write data WD.
The inspection bit generation circuit 23 generates an 11-bit inspection bit WPB having a Golay code based on, for example, 12-bit data in which 4-bit virtual data is added to the upper side with respect to the 8-bit write data WD. ..

The memory cell unit 24 stores the write data WD and the inspection bit WPB. In the example of FIG. 2, the inspection bit WPB is written in the inspection bit storage unit 24a of the memory cell unit 24, and the write data WD is written in the data storage unit 24b of the memory cell unit 24. In the memory cell unit 24, for example, a plurality of memory cells (not shown) are arranged in an array. The memory cell is a storage element such as an MRAM cell, a FeRAM cell, or a DRAM cell. Each memory cell is designated by an address terminal (not shown) of the semiconductor storage device 20 or an address supplied from a control circuit (not shown). Then, data is read from the designated memory cell by a read circuit (not shown), or data is written to the designated memory cell by a write circuit (not shown).

The test mode setting circuit 25 receives the setting signals seta, setb, and setc. The setting signals seta to setc are supplied from, for example, a control circuit (not shown) or the outside of the semiconductor storage device 20. Based on the values of the setting signals seta to setc, any one of the four states (test mode) as the operating state is set in the test mode setting circuit 25. Then, the test mode setting circuit 25 outputs 4-bit virtual data associated with the set test mode.

Each of the setting signals seta to setc is, for example, a 1-bit value of 0 or 1. In that case, each of the setting signals seta to setc can be considered to correspond to each bit value of the 3-bit setting signal. The 3-bit setting signal has a plurality of values according to the values of the setting signals seta to setc. Each of the plurality of values is associated with any one of the plurality of virtual data having different numbers of bits with respect to the virtual data output by the virtual data setting circuit 22.

FIG. 2 shows an example of the correspondence between the 3-bit value by the setting signals seta to setc and the virtual data. For example, when the virtual data output by the virtual data setting circuit 22 is “0000”, the 3-bit values in which the setting signal seta is 1 and the setting signals setb and setc are 0 are associated with the virtual data “0001”. There is. Further, a 3-bit value in which the setting signal setb is 1 and the setting signals seta and setc are 0 is associated with the virtual data “0011”. Further, a 3-bit value in which the setting signal setc is 1 and the setting signals seta and setb are 0 is associated with the virtual data “0111”. Further, the 3-bit value in which the setting signals seta to set are all 0 is associated with the virtual data "0000". Since the error can be detected and corrected by the Golay code up to 3 bits per 23 bits, it is assumed that the most significant bit of the virtual data output by the test mode setting circuit 25 is fixed at 0.

The test mode setting circuit 25 receives one of the four types of 3-bit values as described above, and selects and outputs the virtual data associated with the one value from the plurality of virtual data. ..

Hereinafter, the above four test modes (operating states for outputting any of the four types of virtual data) are referred to as a first test mode, a second test mode, a third test mode, and a normal mode.
The first test mode is a test mode in which a 1-bit error is intentionally generated. In the first test mode, the test mode setting circuit 25 outputs virtual data having a 1-bit value different from the virtual data output by the virtual data setting circuit 22.

The second test mode is a test mode in which a 2-bit error is intentionally generated. In the second test mode, the test mode setting circuit 25 outputs virtual data having a 2-bit value different from the virtual data output by the virtual data setting circuit 22.

The third test mode is a test mode in which a 3-bit error is intentionally generated. In the third test mode, the test mode setting circuit 25 outputs virtual data having a 3-bit value different from the virtual data output by the virtual data setting circuit 22.

The normal mode is a test mode in which an intentional bit error does not occur. In the normal mode, the test mode setting circuit 25 outputs virtual data having the same value as the virtual data output by the virtual data setting circuit 22.

For example, when the setting signal seta is 1 and the setting signals setb and setc are 0, the first test mode is set, and when the setting signal setb is 1 and the setting signals seta and setc are 0, the second test mode is set. Will be done. When the setting signal setc is 1 and the setting signals seta and setb are 0, the third test mode is set, and when the setting signals seta to setc are all 0, the normal mode is set.

The error detection circuit 26 generates a Golay code inspection bit based on the virtual data output by the test mode setting circuit 25 and the read data RD read from the memory cell unit 24. Then, the error detection circuit 26 detects an error bit based on the inspection bit and the inspection bit RPB read from the inspection bit storage unit 24a, and outputs an error signal based on the detection result.

The read data RD corresponds to the write data WD, and if there is no error bit, the read data RD has the same value as the write data WD. Further, the inspection bit RPB corresponds to the inspection bit WPB, and if there is no error bit, the inspection bit RPB has the same value as the inspection bit WPB.

The error detection circuit 26 includes a syndrome generation circuit 26a, a syndrome decoder 26b, a virtual data error detection circuit 26c, and an error signal output circuit 26d.
The syndrome generation circuit 26a generates a Golay code inspection bit based on the 8-bit read data RD and the 4-bit virtual data supplied from the test mode setting circuit 25. Then, the syndrome generation circuit 26a generates and outputs a syndrome based on the generated inspection bit and the inspection bit RPB.

The syndrome decoder 26b decodes the syndrome and outputs the detection result of the error bit.
The virtual data error detection circuit 26c is based on the error bit detection result output by the syndrome decoder 26b and the setting signals seta to setc, and whether or not an unintended error has occurred in the virtual data output by the test mode setting circuit 25. Is detected.

The error signal output circuit 26d outputs an error signal based on the error bit detection result output by the syndrome decoder 26b and the virtual data error detection result by the virtual data error detection circuit 26c.

The error correction circuit 27 corrects the error bits included in the read data RD, the inspection bit RPB, and the virtual data based on the error signal output by the error detection circuit 26. In the example of FIG. 2, the error correction circuit 27 receives the read data RD, the inspection bit RPB, and the virtual data, and outputs the read data RDa, the inspection bit RPBa, and the virtual data VDa in which the error bits are corrected. The inspection bit RPBa and virtual data VDa are not sent to the data input / output unit 21. That is, it is not output to the outside of the semiconductor storage device 20.

(11-bit data pattern used for Golay code and method of generating inspection bit WPB)
In the Golay code, each bit of the 12-bit data is associated with an 11-bit data pattern as shown below.

FIG. 3 is a diagram showing an 11-bit data pattern of the Golay code associated with each bit of the 12-bit data.
For example, bit D <0> is associated with 11 bits of “100001110101”, and bit D <11> is associated with 11 bits of “11000111010”.

Hereinafter, among the bits D <0> to D <11> in FIG. 3, for example, the lower 8 bits D <0> to D <7> are 8 in the semiconductor storage device 20 of the second embodiment. It shall correspond to the bit write data WD. Further, among the bits D <0> to D <11> in FIG. 3, the upper four bits D <8> to D <11> are virtual data in the semiconductor storage device 20 of the second embodiment. It corresponds to the 4-bit virtual data output by the setting circuit 22.

Further, as shown in FIG. 3, each bit of the above 11-bit data pattern associated with each of the bits D <0> to D <11> is the bit P <0> of the inspection bit WPB. It is assumed that they are associated with each of ~ P <10>.

Each of the inspection bits WPB bits P <0> to P <10> excludes the value of the bit D <0> to D <11> that is "1" in the above 11-bit data pattern. It can be obtained by performing an exclusive OR operation (hereinafter referred to as XOR operation).

For example, the value of bit P <0> can be obtained by XORing the values of bits D <0> to D <4>, D <7>, and D <10>. The value of the bit P <10> can be obtained by XORing the values of the bits D <0> to D <3>, D <6>, D <9>, and D <11>. Any value of bits P <0> to P <10> can be obtained by XORing seven values of bits D <0> to D <11>.

That is, the inspection bit WPB can be generated by using the XOR circuit that performs the XOR calculation of 7 inputs and 1 output as the inspection bit generation circuit 23.
FIG. 4 is a diagram showing an example of an XOR circuit that performs an XOR operation with 7 inputs and 1 output.

The XOR circuit 23a that performs the XOR calculation of 7 inputs and 1 output can be realized by the XOR circuits 23a1, 23a2, 23a3, 23a4, 23a5, 23a6 that perform the XOR calculation of 6 2-input 1-output.

The XOR circuit 23a1 performs an XOR operation on the input value in1 and the input value in2. The XOR circuit 23a2 performs an XOR operation on the input value in3 and the input value in4. The XOR circuit 23a3 performs an XOR operation on the input value in5 and the input value in6. The XOR circuit 23a4 performs an XOR operation on the output value of the XOR circuit 23a1 and the output value of the XOR circuit 23a2. The XOR circuit 23a5 performs an XOR operation on the input value in7 and the output value of the XOR circuit 23a3. The XOR circuit 23a6 performs an XOR operation on the output value of the XOR circuit 23a4 and the output value of the XOR circuit 23a5. The output value of the XOR circuit 23a6 becomes the output value out of the XOR circuit 23a with 7 inputs and 1 output.

FIG. 5 is a diagram showing the correspondence between each input of the 7-input / 1-output XOR arithmetic circuit, the data bit, and the output inspection bit.
For example, by using the values of the data bits D <0> to D <4>, D <7>, and D <10> shown in FIG. 3 as the input values in1 to in7, the bit P is used as the output value out. <0> is obtained. Further, by using the values of the data bits D <0> to D <3>, D <6>, D <9>, and D <11> shown in FIG. 3 as the input values in1 to in7, the bit P The value of <10> is obtained.

In order to generate all the bits P <0> to P <10> as shown in FIG. 5 at the same time, an XOR circuit having 11 7 inputs and 1 output may be used.
(Syndrome generation method)
FIG. 6 is a diagram showing an 11-bit data pattern of the Golay code associated with each bit of the 12-bit data and the 11-bit inspection bit.

The bits p <0> to p <10> correspond to the bits of the inspection bit RPB read from the inspection bit storage unit 24a.
For example, the bit p <0> is associated with 11 bits of “0000000000001”, and the bit p <10> is associated with 11 bits of “10000000000000”.

The bits d <0> to d <11> are 8-bit read data RD and 4-bit virtual data bits supplied from the test mode setting circuit 25. Of the bits d <0> to d <11>, for example, the lower 8 bits d <0> to d <7> correspond to the read data RD, and the upper 4 bits d <8>. ~ D <11> corresponds to virtual data.

The data pattern associated with each of the bits d <0> to d <11> is the same as the data pattern associated with each of the bits D <0> to D <11> shown in FIG. is there.

Further, each bit of the above 11-bit data pattern associated with each of the bits d <0> to d <11> and p <0> to p <10> is a bit S <0 of the 11-bit syndrome. > To S <10> are associated with each other. Each of the bits S <0> to S <10> of the syndrome is set to "1" in the above 11-bit data pattern among the bits d <0> to d <11> and p <0> to p <10>. It can be obtained by XORing the value of the bit that has become.

For example, the value of bit S <0> can be obtained by XORing the values of bits d <0> to d <4>, d <7>, d <10>, and p <0>. The value of bit S <10> can be obtained by XORing the values of bits d <0> to d <3>, d <6>, d <9>, d <11>, and p <10>. Any value of bits S <0> to S <10> can be obtained by XORing eight values of bits d <0> to d <11> and p <0> to p <10>. ..

That is, the syndrome can be generated by using the XOR circuit that performs the XOR operation of 8 inputs and 1 output as the syndrome generation circuit 26a.
FIG. 7 is a diagram showing an example of an XOR circuit that performs an XOR operation with 8 inputs and 1 output.

The XOR circuit 26a1 that performs the XOR calculation of 8 inputs and 1 output can be realized by the XOR circuit 26a2 that performs the XOR calculation of 7 inputs and 1 output and the XOR circuit 26a3 that performs the XOR calculation of 2 inputs and 1 output.

The XOR circuit 26a2 performs an XOR operation on the input values IN1, IN2, IN3, IN4, IN5, IN6, IN7. The output of the XOR circuit 26a2 corresponds to a 1-bit inspection bit PB generated based on the read data RD. The circuit configuration of the XOR circuit 26a2 is the same as that of the XOR circuit 23a shown in FIG.

The XOR circuit 26a3 performs an XOR operation between the input value IN0 and the inspection bit PB. The output of the XOR circuit 26a3 becomes the output value OUT (that is, 1 bit of the syndrome) of the XOR circuit 26a1 having 8 inputs and 1 output.

FIG. 8 is a diagram showing the correspondence between each input of the XOR arithmetic circuit having 8 inputs and 1 output, each bit of the read data and the read inspection bit, and each bit of the output syndrome.
For example, by using the values of bits p <0>, d <0> to d <4>, d <7>, and d <10> shown in FIG. 6 as the input values IN0 to IN7, the output value OUT can be set. , Bit S <0> is obtained. Further, by using the values of bits p <10>, d <0> to d <3>, d <6>, d <9>, and d <11> shown in FIG. 6 as the input values IN0 to IN7. , The value of bit S <10> is obtained.

In order to generate all the bits S <0> to S <10> as shown in FIG. 8 at the same time, 11 XOR circuits with 8 inputs and 1 output may be used.
(Method of detecting error bit by syndrome decoder 26b)
The 11-bit syndrome output by the syndrome generation circuit 26a can represent the detection results of 2048 error bits. The syndrome decoder 26b decodes the syndrome and outputs the detection result of the error bit.

FIG. 9 is a diagram showing the correspondence between the decoded signal based on the syndrome and the error bit.
The syndrome decoder 26b generates a decoded signal SO <<> based on the 11-bit syndrome. “*” Is a decimal value representing the 11-bit syndrome. For example, if bits S <0> to S <10> are all 0, then * = 0, and if bits S <0> are 1 and bits S <1> to S <10> are 0, then *. If = 1 and the bits S <0> to S <10> are all 1, then * = 2047.

The syndrome decoder 26b generates decoded signals SO <0> to SO <2047> in which one of them becomes 1 and the other becomes 0 based on the syndrome. Then, the syndrome decoder 26b outputs the detection result of the error bit based on the decoded signals SO <0> to SO <2047>. In FIG. 9, among the bits d <0> to d <11> and p <0> to p <10>, the bits marked with black squares have the decoded signals SO <0> to SO <2047>. Indicates the error bit.

For example, when the decode signal SO <15> is 1, it is indicated that the bits d <3>, d <6>, and p <5> are error bits. When the decode signal SO <0> is 1, it is indicated that there is no error bit.

FIG. 10 is a diagram showing an example of a syndrome decoder. In FIG. 10, a part of the syndrome decoder 26b is shown.
The syndrome decoder 26b has a decode signal generation circuit 30, a plurality of transistors (for example, transistors 31a, 31b, 31c, 31d, 31e, 31f, 31g, 31h, 31i, 31j, 31k, 31l, 31m, 31n, 31o). .. Further, the syndrome decoder 26b has a wire-OR type signal bus 32a1 to 32a23 and an error correction flag output circuit 33a1 to 33a23.

The decode signal generation circuit 30 determines the decode signals SO <0> to SO <based on the values of the syndrome bits S <0> to S <10> at the timing when the timing signal time (for example, the clock signal) becomes 1. This is a logic circuit that outputs 2047>. The decode signal generation circuit 30 resets all the decode signals SO <0> to SO <2047> to 0 at the timing when the timing signal time becomes 0.

The plurality of transistors are n-channel MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors). One of the decoded signals SO <1> to SO <2047> is supplied to each gate of the plurality of transistors, and the drain of each of the plurality of transistors is connected to any of the signal buses 32a1 to 22a23. .. Further, each source of the plurality of transistors is grounded (at a reference potential (for example, 0V)).

For example, the decode signal SO <1> is supplied to the gate of the transistor 31a, and the drain of the transistor 31a is connected to the signal bus 32a13. Further, the decoding signal SO <5> is supplied to the gates of the transistors 31f and 31g, the drain of the transistor 31f is connected to the signal bus 32a13, and the drain of the transistor 31g is connected to the signal bus 32a15.

Each of the signal buses 32a1 to 22a23 is connected to the corresponding one of the error correction flag output circuits 33a1 to 23a23. For example, the signal bus 32a1 is connected to the error correction flag output circuit 33a1, and the signal bus 32a23 is connected to the error correction flag output circuit 33a23. Hereinafter, the signals propagating on the signal buses 32a1 to 22a23 are referred to as signals edb <0> to ebd <11> and ebp <0> to ebp <10>.

The error correction flag output circuits 33a1 to 33a23 output an error correction flag as an error bit detection result based on the signals ebd <0> to ebd <11> and ebp <0> to ebp <10>.

For example, the error correction flag output circuit 33a23 includes transistors 33b and 33c, which are p-channel MOSFETs, and an inverter circuit 33d. The transistor 33c is a weak transistor.

The drain of the transistors 33b and 33c and the input terminal of the inverter circuit 33d are connected to the signal bus 32a23. A power supply voltage is supplied to the sources of the transistors 33b and 33c. A reset signal rstb is supplied to the gate of the transistor 33b from, for example, a control circuit (not shown), and the potentials of the gate of the transistor 33c and the output terminal of the inverter circuit 33d become the error correction flag errpa <10>.

Although not shown in FIG. 10, the same circuit configuration is used for the error correction flag output circuits 33a1 to 33a23 other than the error correction flag output circuits 33a23, and the error correction flag is output. Hereinafter, the outputs of the error correction flag output circuits 33a1 to 33a23 are referred to as error correction flags errda <0> to errda <11> and errpa <0> to errpa <10>. The error correction flags errda <0> to errda <11> are generated based on the signals ebd <0> to ebd <11>, and the error correction flags errpa <0> to errpa <10> are the signals ebp <0> to errpa <10>. Generated based on ebp <10>.

The error correction flags errda <0> to errda <11> indicate the presence or absence of an error in bits d <0> to d <11> of the read data RD and the virtual data supplied from the test mode setting circuit 25. Is. The error correction flags errpa <0> to errpa <10> indicate the presence or absence of an error in bits p <0> to p <10> of the inspection bit RPB. When the potential of the reset signal rstb is H (High) level, the error correction flag (potential) becomes H level among the error correction flags errda <0> to errda <11> and errpa <0> to errpa <10>. The bit of the read data RD, virtual data or inspection bit RPB corresponding to is an error bit.

For example, when the error correction flag errda <5> is H level, the bit d <5> of the read data RD is an error bit.
The decode signal SO <0> is not used to generate the error correction flags errda <0> to errda <11> and errpa <0> to errpa <10>, but to indicate the presence or absence of an error bit, It may be output to the outside of the semiconductor storage device 20.

FIG. 11 is a timing chart showing an example of the operation of the syndrome decoder when a 2-bit error occurs. FIG. 11 shows an example of the operation of the syndrome decoder when an error occurs in the two bits p <0> and p <2> of the inspection bit RPB.

FIG. 11 shows an example of time changes of the syndrome bits S <0> to S <10>, the reset signal rstb, the timing signal time, and the decode signals SO <0> to SO <2047>. Further, in FIG. 11, signals ebd <0> to ebd <11>, ebp <0> to ebp <10>, error correction flags errda <0> to errda <11>, errpa <0> to errpa <10>. An example of the time change of is shown.

In the initial state, the reset signal rstb is at the (potential) L (Low) level, the transistor 33b shown in FIG. 10 is turned on, the signal ebp <10> is at the (potential) H level, and the error correction flag errpa <10. > Is the L level. Similarly, the signals ebd <0> to ebd <10> and ebp <0> to ebp <9> are H levels, and the error correction flags errda <0> to errda <11> and errpa <0> to errpa <9>. Is the L level.

For example, the H level is the potential level of the power supply voltage, and the L level is the reference potential (for example, the ground potential). The H level corresponds to "1" and the L level corresponds to "0".

At the timing t1, after the read data RD and the inspection bit RPB are read from the memory cell unit 24, the syndrome is generated by the syndrome generation circuit 26a (timing t2). In the example of FIG. 11, among the bits S <0> to S <10> of the syndrome, the values of the bits S <0> and S <2> are H level (that is, “1”), and the values of the other bits are It is the L level (that is, "0").

At the timing t3, the timing signal time rises to the H level. As a result, the decode signal generation circuit 30 of the syndrome decoder 26b generates the decode signals SO <0> to SO <2047> based on the values of the bits S <0> to S <10>. In the example of FIG. 11, at the timing t4, only the decoded signal SO <5> has the H level, and the other decoded signals SO <0> to SO <2047> have the L level. At the timing t3, the reset signal rstb also rises to the H level.

When the decode signal SO <5> reaches the H level, the transistors 31f and 31g are turned on in the syndrome decoder 26b shown in FIG. Therefore, the signal buses 32a13 and 32a15 become the reference potential, and the signals ebp <0> and ebp <2> become the L level (timing t5). Then, the error correction flags errapa <0> and errpa <2> become the H level (timing t6). The signals ebp <0> and ebp <2> correspond to bits p <0> and p <2> of the inspection bit RPB. Therefore, the syndrome decoder 26b outputs a detection result indicating that the bits p <0> and p <2> of the inspection bit RPB are error bits.

At the timing t7, the timing signal time falls to the L level. As a result, the decoded signal SO <5> becomes the L level (timing t8). Further, at the timing t9, the reset signal rstb drops to the L level. As a result, the signals ebp <0> and ebp <2> return to the H level (timing t10), and the error correction flags errapa <0> and errapa <2> return to the L level (timing t11).

FIG. 12 is a timing chart showing an example of the operation of the syndrome decoder when a 4-bit error occurs. FIG. 12 shows each signal and value shown in FIG. 11 when an error occurs in 4 bits of the inspection bit RPB bits p <4>, p <5>, p <9>, and p <10>. An example of the time change of is shown.

In the initial state, the reset signal rstb is at the L level, and the signals ebd <0> to ebd <10> and ebp <0> to ebp <10> are at the H level, as in the timing chart shown in FIG. The error correction flags errda <0> to errda <11> and errpa <0> to errpa <10> are L levels.

At the timing t20, after the read data RD and the inspection bit RPB are read from the memory cell unit 24, the syndrome is generated by the syndrome generation circuit 26a (timing t21). In the example of FIG. 12, among the bits S <0> to S <10> of the syndrome, the bits S <10> and S <9> (denoted as “S <10: 9>”) and the bit S The values of <5> and S <4> (denoted as "S <5: 4>") are the H level (that is, "1"). The values of the other bits (denoted as "S <8: 6>" and "S <3: 0>") are at the L level (that is, "0").

At the timing t22, the timing signal time rises to the H level. As a result, the decode signal generation circuit 30 of the syndrome decoder 26b generates the decode signals SO <0> to SO <2047> based on the values of the bits S <0> to S <10>. In the example of FIG. 12, at the timing t23, only the decoded signal SO <1584> has the H level, and the other decoded signals SO <0> to SO <2047> have the L level. At the timing t22, the reset signal rstb also rises to the H level.

When the decode signal SO <1584> reaches the H level, a plurality of transistors (not shown) corresponding to the decode signal SO <1584> are turned on in the syndrome decoder 26b shown in FIG. As a result, the signals ebp <1>, ebp <3>, and ebd <11> become the L level (timing t24). Then, the error correction flags errpa <1>, errpa <3>, and errda <11> become the H level (timing t25). The signals ebp <1> and ebp <3> correspond to bits p <1> and p <3> of the inspection bit RPB. Further, the signal ebd <11> corresponds to the bit d <11>, which is the most significant bit of the 4-bit virtual data.

Therefore, the syndrome decoder 26b outputs a detection result indicating that the inspection bits RPB bits p <1> and p <3> and the most significant bit d <11> of the virtual data are error bits. become.

In this case, in the error correction circuit 27, the 4 bits of the inspection bit RPB bit p <4>, p <5>, p <9>, and p <10> in which the error actually occurs are not corrected, and the error is corrected. Bits p <1>, p <3>, and d <11> that the circuit 27 erroneously corrects are added as an error. Since the bit d <11> is a bit of virtual data, it is not output to the outside.

In order to notify the occurrence of such a 4-bit error to the outside of the semiconductor storage device 20, a virtual data error detection circuit 26c and an error signal output circuit 26d as described later are used. At the timing t26 of FIG. 12, the timing signal time has dropped to the L level. As a result, the decoded signal SO <1584> becomes L level (timing t27). Further, at the timing t28, the reset signal rstb drops to the L level. As a result, the signals ebp <1>, ebp <3>, and ebd <11> return to the H level (timing t29), and the error correction flags errapa <1>, errpa <3>, and errda <11> return to the L level. (Timing t30).

(Example of virtual data error detection circuit 26c and error signal output circuit 26d)
FIG. 13 is a diagram showing an example of a virtual data error detection circuit and an error signal output circuit.
In the virtual data error detection circuit 26c of FIG. 13, when the setting signal seta is 1 (H level) and the setting signals setb and setc are 0 (L level), the first test mode is set. Further, when the setting signal setb is 1 and the setting signals seta and set are 0, the second test mode is set. Further, when the setting signal setc is 1 and the setting signals seta and setb are 0, the third test mode is set, and when the setting signals seta to set are all 0, the normal mode is set.

Further, in the virtual data error detection circuit 26c of FIG. 13, the 4-bit data added to the write data WD from the virtual data setting circuit 22 is “0000”, and the virtual data output by the test mode setting circuit 25 in the first test mode is It is assumed to be "0001". Further, the virtual data output by the test mode setting circuit 25 in the second test mode is "0011", the virtual data output by the test mode setting circuit 25 in the third test mode is "0111", and the test mode setting circuit 25 in the normal mode. It is assumed that the virtual data output by is "0000". Since error detection and correction is possible with the Golay code up to 3 bits per 23 bits, it is assumed that the most significant bit of the virtual data output by the test mode setting circuit 25 is fixed at 0 (L level). ..

The virtual data error detection circuit 26c has an inverter circuit 26c1,26c2,26c3,26c4, a NAND circuit 26c5,26c6,26c7,26c8,26c9,26c10, 26c11,26c12. Further, the virtual data error detection circuit 26c has NOR circuits 26c13, 26c14, 26c15, 26c16, 26c17, 26c18.

The setting signals seta to setc are supplied to the three input terminals of the NOR circuit 26c13. The output terminal of the NOR circuit 26c13 is connected to one input terminal of the NAND circuit 26c5. An error correction flag errda <11> is supplied to the other input terminal of the NAND circuit 26c5 via the inverter circuit 26c4. The error correction flag errda <10> is supplied to the first of the three input terminals of the NAND circuit 26c6 via the inverter circuit 26c3, and the error correction flag errda <9> provides the inverter circuit 26c2 to the second. Supplied through. Thirdly, the error correction flag errda <8> is supplied via the inverter circuit 26c1.

The setting signal seta is supplied to one input terminal of the NAND circuit 26c7, and the error correction flag errda <11> is supplied to the other input terminal via the inverter circuit 26c4. The error correction flag errda <10> is supplied to the first of the three input terminals of the NAND circuit 26c8 via the inverter circuit 26c3, and the error correction flag errda <9> supplies the inverter circuit 26c2 to the second. Supplied through. Thirdly, the error correction flag errda <8> is supplied.

The setting signal setb is supplied to one input terminal of the NAND circuit 26c9, and the error correction flag errda <11> is supplied to the other input terminal via the inverter circuit 26c4. The error correction flag errda <10> is supplied to the first of the three input terminals of the NAND circuit 26c10 via the inverter circuit 26c3, and the error correction flag errda <9> is supplied to the second. Thirdly, the error correction flag errda <8> is supplied.

The setting signal setc is supplied to one input terminal of the NAND circuit 26c11, and the error correction flag errda <11> is supplied to the other input terminal via the inverter circuit 26c4. The error correction flag errda <10> is supplied to the first of the three input terminals of the NAND circuit 26c12, the error correction flag errda <9> is supplied to the second, and the error is supplied to the third. The correction flag errda <8> is supplied.

One input terminal of the NOR circuit 26c14 is connected to the output terminal of the NAND circuit 26c5, and the other input terminal is connected to the output terminal of the NAND circuit 26c6. One input terminal of the NOR circuit 26c15 is connected to the output terminal of the NAND circuit 26c7, and the other input terminal is connected to the output terminal of the NAND circuit 26c8. One input terminal of the NOR circuit 26c16 is connected to the output terminal of the NAND circuit 26c9, and the other input terminal is connected to the output terminal of the NAND circuit 26c10. One input terminal of the NOR circuit 26c17 is connected to the output terminal of the NAND circuit 26c11, and the other input terminal is connected to the output terminal of the NAND circuit 26c12.

The output terminals of the NOR circuits 26c14 to 26c17 are connected to the four input terminals of the NOR circuit 26c18. The output terminal of the NOR circuit 26c18 is connected to the error signal output circuit 26d.

Such a virtual data error detection circuit 26c detects whether or not an unintended error has occurred in the virtual data output by the test mode setting circuit 25 (whether or not the virtual data corresponds to the setting signals seta to set). Then, the virtual data error detection circuit 26c outputs a virtual data bit error flag errvd indicating the detection result. When the virtual data bit error flag errvd is H level, it indicates that an unintended error has occurred in the virtual data, and when the virtual data bit error flag errvd is L level, an unintended error has not occurred in the virtual data. Show that.

For example, when the first test mode, which is a test mode for intentionally generating a 1-bit error, is set, if the error correction flag errda <11> is H level, the output signal of the NAND circuit 26c7 is H level. It becomes. In this case, the output signal of the NOR circuit 26c15 becomes the L level regardless of the logic level of the output signal of the NAND circuit 26c8. In the first test mode, the set signals setb and setc are 0, and the output signals of the NOR circuits 26c14, 26c16, and 26c17 are at the L level. Therefore, the virtual data bit error flag errvd, which is the output signal of the NOR circuit 26c18, becomes H level. That is, it is detected that an unintended error has occurred in the virtual data.

The error correction flag errda <11> corresponds to bit d <11>, which is the most significant bit of virtual data. Since the most significant bit of the virtual data is fixed at 0 as described above, when an error occurs in bit d <11>, the error is an unintended error.

When the error correction flag errda <11> becomes the H level, the virtual data bit error flag errvd becomes the H level regardless of the test mode.
On the other hand, when the first test mode is set and the error correction flag errda <11> is L level, the output signal of the NAND circuit 26c7 becomes L level. In this case, the output signal of the NOR circuit 26c15 is determined by the logic level of the output signal of the NAND circuit 26c8. When the error correction flag errda <8> is H level and the error correction flags errda <9> and errda <10> are L level, the output signal of the NAND circuit 26c8 is L level. In other cases, the NAND circuit The output signal of 26c8 becomes H level.

When the output signal of the NAND circuit 26c8 is L level, the output signal of the NOR circuit 26c15 is H level, and the virtual data bit error flag errvd which is the output signal of the NOR circuit 26c18 is L level. When the output signal of the NAND circuit 26c8 is H level, the output signal of the NOR circuit 26c15 is L level, and the virtual data bit error flag errvd which is the output signal of the NOR circuit 26c18 is H level. That is, it is detected that an unintended error has occurred in the virtual data.

The error correction flags errda <9> and errda <10> correspond to bits d <9> and d <10>, which are two bits of virtual data. Since the bits d <9> and d <10> of the virtual data are bits that do not cause an intentional error when the first test mode is set, the bits d <9> and d <10> If there is an error in, the error is an unintended error.

The error signal output circuit 26d includes circuit units 26d1 to 26d8, 26d9 to 26d12, 26d13 to 26d23.
Each of the circuit units 26d1 to 26d23 is an OR circuit. In the example of FIG. 13, the OR circuit is realized by using the NOR circuit and the inverter circuit. For example, the circuit unit 26d1 has a NOR circuit 26da and an inverter circuit 26db, the circuit unit 26d9 has a NOR circuit 26dc and an inverter circuit 26dd, and the circuit unit 26d13 has a NOR circuit 26de and an inverter circuit 26df.

Each of the circuit units 26d1 to 26d8 is ORed with the virtual data bit error flag errvd and any one of the error correction flags errda <0> to errda <7>, and the error signals errd <0> to errd <7>. Output as one of.

For example, the circuit unit 26d1 outputs the logical sum of the virtual data bit error flag errvd and the error correction flag errda <0> as an error signal errd <0>. The circuit unit 26d8 outputs the logical sum of the virtual data bit error flag errvd and the error correction flag errda <7> as an error signal errd <7>.

When the virtual data bit error flag errvd becomes H level, the circuit units 26d1 to 26d8 have H level error signals errd <0> to errd <7 regardless of the values of the error correction flags errda <0> to errda <7>. > Is output.

Each of the circuit units 26d9 to 26d12 is ORed with the reference potential (L level potential) and any one of the error correction flags errda <8> to errda <11>, and the error signals errd <8> to errd < Output as one of 11>.

For example, the circuit unit 26d9 outputs the logical sum of the reference potential and the error correction flag errda <8> as an error signal errd <8>. The circuit unit 26d12 outputs the logical sum of the reference potential and the error correction flag errda <11> as an error signal errd <11>.

The circuit units 26d9 to 26d12 set the error signal corresponding to the error correction flags errda <8> to errda <11> that become the H level as the H level. For example, when the error correction flag errda <8> is H level, the error signal errd <8> becomes H level.

Each of the circuit units 26d13 to 26d23 uses the logical sum of the reference potential and any one of the error correction flags errpa <0> to errpa <10> as one of the error signals errp <0> to errp <10>. Output.

For example, the circuit unit 26d13 outputs the logical sum of the reference potential and the error correction flag errp <0> as an error signal errp <0>. The circuit unit 26d23 outputs the logical sum of the reference potential and the error correction flag errp <10> as an error signal errp <10>.

The circuit units 26d13 to 26d23 set the error signal corresponding to the error correction flags errpa <0> to errpa <10> that become the H level as the H level. For example, when the error correction flag errp <0> is H level, the error signal errp <0> becomes H level.

FIG. 14 is a timing chart showing an example of the operation of the virtual data error detection circuit and the error signal output circuit when a 4-bit error occurs.
FIG. 14 shows an example of the time change of the error correction flags errpa <0> to errpa <10> and errda <0> to errda <11>. Further, FIG. 14 shows an example of time changes of the virtual data bit error flag errvd, the error signals errd <0> to errd <11>, and errp <0> to errp <10>.

Of the L-level error correction flags errpa <0> to errpa <10> and errda <0> to errda <11>, the error correction flags errpa <1>, errpa <3>, and errda <11> are at timing t40. , Standing up to H level. As described above, when the error correction flag errda <11> becomes the H level, the virtual data bit error flag errvd becomes the H level regardless of the test mode. As a result, the error signals errd <0> to errd <7> become H level.

When the error correction flags errpa <1>, errpa <3>, and errda <11> reach the H level, the corresponding error signals errp <1>, errp <3>, and errd <11> become the H level. ..

At the timing t41, when the error correction flags errpa <1>, errpa <3>, and errda <11> fall to the L level, the virtual data bit error flag errvd also becomes the L level. Further, the error signals errd <0> to errd <7>, errd <11>, errp <1>, and errp <3> also reach the L level.

(Example of error correction circuit 27)
The error correction circuit 27 can be realized by a plurality of 2-input / 1-output XOR circuits.
FIG. 15 is a diagram showing an example of an error correction circuit. FIG. 15 shows a circuit portion that corrects an error of bits d <0> to d <7>.

The error correction circuit 27 has two inputs and one output XOR circuits 27a1 to 27a8.
In each of the XOR circuits 27a1 to 27a8, one of the bits d <0> to d <7> of the read data RD and the error correction flags (errd <0> to errd <7> corresponding to the bits Any one) is input. Bits dECC <0> to dECC <7>, which are output values of the XOR circuits 27a1 to 27a8, are 8-bit read data RDas.

Although not shown, the circuit portion for correcting the error of the bits d <8> to d <11> is realized by four XOR circuits, and the error signals errd <8> to errd <11> are used. Further, although not shown, the circuit portion for correcting the error of the inspection bits p <0> to p <10> is realized by 11 XOR circuits, and the error signals errp <0> to errp <10> are realized. Is used.

FIG. 16 is a timing chart showing an example of the operation of the error correction circuit when a 2-bit error occurs.
In FIG. 16, the time changes of the bits d <0> to d <7> of the read data RD, the error signals errd <0> to errd <7>, and the bits dECC <0> to dECC <7> of the read data RD are shown. An example is shown.

It is assumed that the expected values of the bits d <0> to d <7> of the read data RD (corresponding to the bits D <0> to D <7> of the write data WD) are all H level.
Further, the initial value of the error signals errd <0> to errd <7> is the L level.

Of the bits d <0> to d <7> of the read data RD read from the memory cell unit 24 at the timing t50, the values of the bits d <0> and d <2> are at the L level. That is, the bits d <0> and d <2> are error bits.

Further, at the timing t50, since the error signals errd <0> to errd <7> are at the L level, the bits dECC <0> to dECC <7>, which are the output values of the XOR circuits 27a1 to 27a8, are bit d <0. > ~ D <7> is the same as the value.

After that, due to the operation of the error detection circuit 26 described above, the error signals errd <0> and errd <2> change from the L level to the H level (timing t51).
As a result, among the bits dECC <0> to dECC <7>, which are the output values of the XOR circuits 27a1 to 27a8, the bits dECC <0> and dECC <2> are inverted from the L level to the H level (that is, from 0 to 1). (Timing t52). That is, 2-bit error correction is performed.

FIG. 17 is a timing chart showing an example of the operation of the error correction circuit when a 4-bit error occurs.
In FIG. 17, bits p <0> to p <10>, d <0> to d <11>, virtual data bit error flag errvd, error signal errp <0> to errp <10>, errd <0> to An example of time variation of error <11> is shown. Further, the check bit RPB error-corrected bits pECC <0> to pECC <10>, the read data RDa bits dECC <0> to dECC <7>, and the virtual data error-corrected bits dECC <8> to dECC. An example of the time change of <11> is shown.

It is assumed that the expected values of the bits p <0> to p <10> and d <0> to d <11> are all H levels.
Further, the initial values of the error signals errp <0> to errp <10> and errd <0> to errd <11> are L levels.

Of the bits p <0> to p <10> and d <0> to d <7> read from the memory cell unit 24 at the timing t60, the bits p <4>, p <5>, and p <9> , P <10> is the L level. That is, a 4-bit error has occurred.

Further, at the timing t60, since the error signals errp <0> to errp <10> are at the L level, the bits pECC <0> to pECC <10> are the same as the values of the bits p <0> to p <10>. It becomes. Further, at the timing t60, since the error signals errd <0> to errd <11> are at the L level, the bits dECC <0> to dECC <11> are the same as the values of the bits d <0> to d <11>. It becomes.

After that, due to the operation of the error detection circuit 26, the error signals errp <1>, errp <3>, and errd <11> become H level (timing t61). Further, at the timing t61, the virtual data bit error flag errvd becomes H level due to the operation of the virtual data error detection circuit 26c. As a result, due to the operation of the error signal output circuit 26d, the error signals errd <0> to errd <7> also become H level.

Since the error signals errp <1>, errp <3>, and errd <11> are at the H level, the bits pECC <1>, pECC <3>, and dECC <11> are changed from the H level by the operation of the error correction circuit 27. Invert to L level (ie 1 to 0) (timing t62). Since it is the bits p <4>, p <5>, p <9>, and p <10> that actually cause the bit error, a 3-bit error correction occurs. However, at the timing t62, all the bits dECC <0> to dECC <7> of the read data RDa are inverted from the H level to the L level due to the operation of the error signal output circuit 26d. Since the read data RDa is output from the semiconductor storage device 20, the occurrence of a 4-bit error is notified to the outside of the semiconductor storage device 20 by setting all the bits dECC <0> to dECC <7> to the L level. Can be done. In the above description, the error signal output circuit 26d inverts all the bits dECC <0> to dECC <7> from the H level to the L level, but the error is not limited to this and can be detected and corrected. By inverting more bits than 3 bits, the occurrence of a 4-bit error may be notified to the outside of the semiconductor storage device 20.

(Example of changing the test mode of the semiconductor storage device 20)
For example, when the second test mode is set in the test mode setting circuit 25 at the time of the pre-shipment test for the semiconductor storage device 20, virtual data “0011” is supplied to the error detection circuit 26.

When 8-bit read data RD is read from the memory cell unit 24, 12 bits (the above-mentioned bit d <0>) in which virtual data “0011” is added to the upper side of the read data RD are added to the syndrome generation circuit 26a. A value of ~ d <11>) is supplied. Further, the syndrome generation circuit 26a is supplied with the 11-bit inspection bit RPB (bits p <0> to p <10> described above) read from the memory cell unit 24. The inspection bit RPB read from the memory cell unit 24 is associated with the read data RD read from the memory cell unit 24.

The syndrome generation circuit 26a generates syndrome bits S <0> to S <10> by an XOR operation based on the correspondence as shown in FIG. Then, the syndrome decoder 26b has error correction flags errda <0> to errda <11> and errpa <0> to errpa <10> indicating an error bit detection result based on the bits S <0> to S <10>. Is output.

In the second test mode, since the virtual data “0011” is used, at least the error correction flag errda <8> out of the error correction flags errda <0> to errda <11> and errpa <0> to errpa <10>. , Error <9> is H level. If an error occurs in one of all 19 bits of the read data RD and the inspection bit RPB, the error correction flag corresponding to that bit becomes the H level.

The error correction circuit 27 has bits p <0> to p <10> and d <0> to d <11 based on the error signals errp <0> to errp <10> and errd <0> to errd <11>. Correct the error bit of> n.

For example, if an error bit of 1 bit occurs in the read data RD out of all 19 bits of the read data RD and the inspection bit RPB, the error correction circuit 27 performs error correction. In this case, the read data RDa obtained by error correction becomes the same as the write data WD, which is the expected value.

After the pre-shipment test of the semiconductor storage device 20, for example, the setting signals seta to set become all 0, and the normal mode is set. In the normal mode, virtual data “0000” is supplied to the error detection circuit 26.

In the normal mode, since the virtual data “0000” is used, the error correction flags errda <8> to errda <11> are at the L level when an error of 4 bits or more has not occurred. Further, when 1 to 3 bits of all 19 bits of the read data RD and the inspection bit RPB are error bits, the error correction flag corresponding to the bits becomes the H level.

The error correction circuit 27 uses the error correction circuit 27 when the check bit RPB has no error bits and the read data RD has up to 3 error bits among all 19 bits of the read data RD and the check bit RPB. The error is corrected correctly. Further, even if the inspection bit RPB has one error bit, the error bit and the error bits up to two bits generated in the read data RD can be correctly corrected. Further, even if the inspection bit RPB has 2 error bits, those error bits and up to 1 error bit generated in the read data RD can be correctly corrected.

In the above method, in the pre-shipment test, a 2-bit error intentionally added by the second test mode occurs, and it is possible to detect and correct all 19 bits of the read data RD and the inspection bit RPB. The number of bits is limited to 1 bit. After that, by changing the test mode to the normal mode, for example, even if the error bit does not increase in the inspection bit RPB and the error bit of the read data RD increases by 2 bits, the error can be corrected correctly. Further, even if the error bit of the inspection bit RPB increases by 1 bit, it is possible to cope with the increase of the error bit of 1 bit of the read data RD. Further, even if the error bit of the inspection bit RPB increases by 2 bits, normal operation can be performed without erroneously correcting the read data RD.

When the pre-shipment test is performed in the first test mode, an intentionally added 1-bit error occurs, and the error can be detected and corrected for all 19 bits of the read data RD and the inspection bit RPB. The number of bits is limited to 2 bits. After that, by changing the test mode to the normal mode, for example, even if the error bit does not increase in the inspection bit RPB and the error bit of the read data RD increases by 1 bit, the error can be corrected correctly. Further, even if the error bit of the inspection bit RPB increases by 1 bit, normal operation can be performed without erroneously correcting the read data RD.

Further, when the pre-shipment test is performed in the third test mode, an intentionally added 3-bit error occurs, and the error can be detected and corrected for all 19 bits of the read data RD and the inspection bit RPB. The number of bits is 0 bits. After that, by changing the test mode to the normal mode, for example, even if the error bit does not increase in the inspection bit RPB and the error bit of the read data RD increases by 3 bits, the error can be corrected correctly. Further, even if the error bit of the inspection bit RPB increases by 1 bit, it is possible to cope with the increase of the error bit of 2 bits of the read data RD. Further, even if the error bit of the inspection bit RPB increases by 2 bits, it is possible to cope with the increase of 1 bit of the error bit of the read data RD. Further, even if the error bit of the inspection bit RPB increases by 3 bits, normal operation can be performed without erroneously correcting the read data RD.

As described above, according to the semiconductor storage device 20 of the second embodiment, as in the semiconductor storage device 10 of the first embodiment, it is possible to detect and correct the error bits that have increased after shipment.
The pre-shipment test may be performed in the normal mode so that the semiconductor storage device 20 in which a 3-bit error occurs can also be shipped as a non-defective product to improve the yield.

In addition, the test mode is not limited to change before and after shipment, and one test uses the third test mode, and the next test changes to the second test mode, the first test mode, or the normal mode. You may.

This also allows, for example, chip grade sorting.
FIG. 18 is a flowchart showing an example of a chip grade sorting method.
Initially, the test is performed in the third test mode (step S1), and if it passes (that is, if there is no error bit in the read data RD and the inspection bit RPB), the change to the normal mode is performed and the semiconductor is used. The storage device 20 is shipped as a highly reliable chip. For example, even if the error bit suddenly increases, the semiconductor storage device 20 can correct the error bit up to 3 bits for each set of the 19-bit read data RD and the inspection bit RPB. Is. For example, a semiconductor storage device 20 that has passed the test in the third test mode is shipped for an in-vehicle chip that requires high reliability.

If the test in the third test mode fails (that is, an error bit occurs in the read data RD or the inspection bit RPB), the test in the normal mode is performed (step S2). If the normal mode test passes, the semiconductor storage device 20 is shipped as a low-cost chip. This is because the semiconductor storage device 20 that failed to pass the test in the third test mode is inferior in its ability to correct an increase in error bits than the device that passed the test in the third test mode.

When the semiconductor storage device 20 fails in the normal mode test (that is, when any of the sets of the read data RD and the inspection bit RPB has an error bit of 4 bits or more in total), the semiconductor. The storage device 20 is not shipped as a defective chip.

(Third Embodiment)
FIG. 19 is a diagram showing an example of the semiconductor storage device of the third embodiment. In FIG. 19, the same elements as those of the semiconductor storage device 20 of the second embodiment shown in FIG. 2 are designated by the same reference numerals.

The semiconductor storage device 40 of the third embodiment has a function of writing back the inspection bit RPBa after error correction and the read data RDa after error correction to the memory cell unit 24. The semiconductor storage device 40 of the third embodiment executes the above-mentioned write-back function when a 3-bit error, which is an upper limit of error correction, occurs due to the Golay code.

As an element for that purpose, the error correction circuit 41 of the semiconductor storage device 40 has an inspection bit correction unit 41a and a read data correction unit 41b. The error correction circuit 41 has a circuit unit for correcting an error in virtual data, but the illustration is omitted.

Further, the semiconductor storage device 40 has selection circuits 42a and 42b. Further, the error detection circuit 43 of the semiconductor storage device 40 has an error MAX flag generation circuit 43a. Further, the semiconductor storage device 40 has a busy signal output circuit 44 and a control circuit 45.

In the example of FIG. 19, the memory cell unit 24 may or may not have a redundant cell unit 24c including a plurality of redundant cells used in place of the memory cell having a fixed defect.
The inspection bit correction unit 41a and the read data correction unit 41b can be realized by a plurality of XOR circuits as shown in FIG.

The selection circuit 42a selects and outputs either the inspection bit WPB or the error-corrected inspection bit RPBa based on the flag ERRmax output by the error MAX flag generation circuit 43a.

The selection circuit 42b selects and outputs either the write data WD or the error-corrected read data RDa based on the flag ERRmax.
FIG. 20 is a diagram showing an example of a selection circuit.

FIG. 20 shows an example of the selection circuit 42a shown in FIG. The selection circuit 42b can also be realized by the same circuit as the selection circuit 42a.
The selection circuit 42a includes inverter circuits 42a1, 42a2, 42a3, 42a4, transistors 42a5, 42a6 which are n-channel MOSFETs, and transistors 42a7, 42a8 which are p-channel MOSFETs.

The value of bit P <*> is input to the input terminal of the inverter circuit 42a1, and the value of bit pa <*> is supplied to the input terminal of the inverter circuit 42a2. Bit P <*> is any of bits P <0> to P <10> of the 11-bit inspection bit WPB. Bit pa <*> is any of bits pa <0> to pa <10> of the error-corrected 11-bit inspection bit RPBa. The output terminal of the inverter circuit 42a1 is connected to one input / output terminal (drain or source) of the transistors 42a5 and 42a7, and the output terminal of the inverter circuit 42a2 is connected to one input / output terminal of the transistors 42a6 and 42a8. ing.

The other input / output terminals of the transistors 42a5 and 42a7 and the other input / output terminals of the transistors 42a6 and 42a8 are connected to the input terminals of the inverter circuit 42a4. Further, the flag ERRmax is supplied to the control terminals (gates) of the transistors 42a6 and 42a7 and the input terminals of the inverter circuit 42a3, and the control terminals of the transistors 42a5 and 42a8 are connected to the output terminals of the inverter circuit 42a3.

When the flag ERRmax is L level, the transistors 42a5 and 42a7 are turned on and the transistors 42a6 and 42a8 are turned off, so that the output of the inverter circuit 42a4 becomes the value of the bit P <<.

When the flag ERRmax is H level, the transistors 42a5 and 42a7 are turned off and the transistors 42a6 and 42a8 are turned on, so that the output of the inverter circuit 42a4 becomes the value of the bit pa <*>.

The selection circuit 42a has 11 circuits as described above corresponding to the bits P <0> to P <10> of the inspection bit WPB.
The error MAX flag generation circuit 43a of FIG. 19 indicates that when the number of error bits reaches the maximum number that can be detected based on the decoding signals SO <0> to SO <2047> generated by the syndrome decoder 26b. Generates the flag ERRmax, which is a detection signal indicating. In the semiconductor storage device 40 of the third embodiment, since the Golay code is used, the maximum number that can be detected is 3 bits. In the following, it is assumed that the error MAX flag generation circuit 43a outputs the H level flag ERRmax when the error bit is 3 bits.

FIG. 21 is a diagram showing an example of an error MAX flag generation circuit.
Note that FIG. 21 shows a part of the error MAX flag generation circuit 43a together with a part of the syndrome decoder 26b.

The error MAX flag generation circuit 43a has a plurality of transistors (for example, transistors 50a, 50b, 50c, 50d, 50e, 50f, 50g, 50h, 50i) and a wire-OR type signal bus 51a, 51b, 51c. Further, the error MAX flag generation circuit 43a includes a 0-bit error detection circuit 52a1, a 1-bit error detection circuit 52a2, a 2-bit error detection circuit 52a3, and a flag output circuit 53.

The plurality of transistors are n-channel MOSFETs. Of the decoded signals SO <0> to SO <2047>, one of the decoded signals indicating whether or not a 0-bit error, a 1-bit error, or a 2-bit error has occurred is supplied to each gate of the plurality of transistors. .. For example, as shown in FIG. 9, a signal indicating whether or not a 3-bit error has occurred, such as the decode signal SO <7>, is not supplied to any of the gates of the plurality of transistors. Each drain of the plurality of transistors is connected to any of the signal buses 51a to 51c. Further, each source of the plurality of transistors is grounded (at a reference potential (for example, 0V)).

For example, the decode signal SO <0> is supplied to the gate of the transistor 50a, and the drain of the transistor 50a is connected to the signal bus 51a.
The signal bus 51a is connected to the 0-bit error detection circuit 52a1, the signal bus 51b is connected to the 1-bit error detection circuit 52a2, and the signal bus 51c is connected to the 2-bit error detection circuit 52a3. .. Hereinafter, the signal propagating on the signal bus 51a is referred to as signal e0b, the signal propagating on the signal bus 51b is referred to as signal e1b, and the signal propagating on the signal bus 51c is referred to as signal e2b.

The 0-bit error detection circuit 52a1 outputs a signal err0 indicating whether or not a 0-bit error (that is, no error bit) has occurred, based on the signal e0b. The 1-bit error detection circuit 52a2 outputs a signal err1 indicating whether or not a 1-bit error has occurred, based on the signal e1b. The 2-bit error detection circuit 52a3 outputs a signal err2 indicating whether or not a 2-bit error has occurred, based on the signal e2b.

For example, the 2-bit error detection circuit 52a3 includes transistors 52b and 52c, which are p-channel MOSFETs, and an inverter circuit 52d. The transistor 52c is a weak transistor.

The drain of the transistors 52b and 52c and the input terminal of the inverter circuit 52d are connected to the signal bus 51c. A power supply voltage is supplied to the sources of the transistors 52b and 52c. A reset signal rstb is supplied to the gate of the transistor 52b, for example, from the control circuit 45, and the potential of the gate of the transistor 52c and the output terminal of the inverter circuit 52d becomes the signal err2.

The 2-bit error detection circuit 52a3 outputs an H-level signal err2 indicating that a 2-bit error has been detected when the reset signal rstb is at the H level and the signal e2b is at the L level.

Although not shown in FIG. 21, the 0-bit error detection circuit 52a1 and the 1-bit error detection circuit 52a2 have the same circuit configuration as the 2-bit error detection circuit 52a3.

The flag output circuit 53 outputs a flag ERRmax indicating whether or not the error bit is 3 bits based on the signals err0 to err2.
FIG. 22 is a diagram showing an example of a flag output circuit.

The flag output circuit 53 includes NAND circuits 53a, 53b, NOR circuits 53c, 53d, 53e, inverter circuits 53f, 53g, 53h, 53i, 53j, 53k, signal lines 53l, and transistors 53m, 53n, 53o.

A power supply voltage is supplied to three of the four input terminals of the NAND circuit 53a, and a timing signal time is supplied to one input terminal. The output terminal of the NAND circuit 53a is connected to one input terminal of the NOR circuit 53c. The other input terminal of the NOR circuit 53c is grounded, and the output terminal of the NOR circuit 53c is connected to one input terminal of the NAND circuit 53b. A power supply voltage is supplied to the other input terminal of the NAND circuit 53b, and the output terminal of the NAND circuit 53b is connected to the gate of the transistor 53m via the inverter circuit 53f.

The transistor 53m is an n-channel MOSFET. The drain of the transistor 53m is connected to the drain of the transistors 53n and 53o, which are p-channel MOSFETs, and the input terminal of the inverter circuit 53g via the signal line 53l. The source of the transistor 53m is grounded.

A power supply voltage is supplied to the sources of the transistors 53n and 53o, and a reset signal rstb is supplied to the gate of the transistors 53n. The gate of the transistor 53l and the output terminal of the inverter circuit 53g are connected to one input terminal of the NOR circuit 53e via the inverter circuits 53h to 53j. The transistor 53o is a weak transistor.

The output terminal of the inverter circuit 53k is connected to the other input terminal of the NOR circuit 53e. The potential of the output terminal of the NOR circuit 53e is the flag ERRmax. The output terminal of the NOR circuit 53d is connected to the input terminal of the inverter circuit 53k. Signals err0 to err2 are supplied to the three input terminals of the NOR circuit 53d.

In such a flag output circuit 53, when the signals err0 to err2 are all L level, that is, when there are error bits of 3 bits or more, the output of the inverter circuit 53k becomes L level. When the reset signal rstb is at H level and the timing signal time is at H level, the output of the inverter circuit 53j becomes L level after a delay time considering the timing at which the decode signal indicating the occurrence of a 3-bit error is output. As a result, the NOR circuit 53e outputs the H level flag ERRmax, which is a detection signal indicating the occurrence of a 3-bit error.

When the flag ERRmax reaches the H level, the busy signal output circuit 44 of FIG. 19 outputs a signal busy (for example, an H level signal) indicating that the semiconductor storage device 40 is in a busy state for writing back for a predetermined period of time. To do. The busy signal output circuit 44 is, for example, a pulse signal generation circuit that outputs a signal busy of the H level for a predetermined period when the flag ERRmax reaches the H level.

(Operation example of the semiconductor storage device 40 of the third embodiment)
Hereinafter, an example of the operation of the semiconductor storage device 40 will be described.
When 8-bit read data RD is read from the memory cell unit 24, the error detection circuit 43 contains the read data RD and 4-bit virtual data based on the set signals seta to setc from the test mode setting circuit 25. Be supplied. Further, the inspection bit RPB associated with the read data RD is also read from the memory cell unit 24 and supplied to the error detection circuit 43.

Although not shown in FIG. 21, the error MAX flag generation circuit 43a is controlled by the control signal setr and is effective when the control signal setr is 1. Further, the error MAX flag generation circuit 43a is invalid when the control signal setr is 0, and the flag ERRmax becomes the L level. In the pre-shipment test using the above-mentioned setting signals seta to setc, the setting signal setr becomes 0, and the error MAX flag generation circuit 43a becomes invalid. By changing the setting signal setr to 1 and shipping, the error MAX flag generation circuit 43a functions after shipping, and when the error bit reaches 3 bits, the error MAX flag becomes H level.

As described above, the syndrome generation circuit 26a of the error detection circuit 43 generates the syndrome bits S <0> to S <10> by the XOR operation based on the correspondence as shown in FIG. Then, the syndrome decoder 26b is based on the syndrome bits S <0> to S <10>, and is an error correction flag errda <0> to errda <11>, errpa <0> to errpa, which are error bit detection results. Output <10>.

The error signal output circuit 26d outputs error signals errd <0> to errd <11> based on the error correction flags errda <0> to errda <11> and the virtual data bit error flag errvd. Further, the error signal output circuit 26d outputs error signals errp <0> to errp <10> based on the error correction flags errpa <0> to errpa <10>.

The inspection bit correction unit 41a sets the inspection bit RPB based on the error signals errp <0> to errp <10> among the error signals errd <0> to errd <11> and errp <0> to errp <10>. Correct the error bit. Further, the read data correction unit 41b corrects the error bit of the read data RD based on the error signals errd <0> to errd <7>.

Further, in the error detection circuit 43 of the semiconductor storage device 40 of the third embodiment, the error MAX flag generation circuit 43a is a flag based on the decode signals SO <0> to SO <2047> generated by the syndrome decoder 26b. Generate ERRmax.

If the error bit is 2 bits or less out of the total of 23 bits including the read data RD, the inspection bit RPB, and the virtual data, the flag ERRmax becomes the L level. At this time, the selection circuit 42a selects and outputs the inspection bit WPB. As a result, the inspection bit WPB is written to the inspection bit storage unit 24a of the memory cell unit 24 by a writing circuit (not shown). Further, the selection circuit 42b selects and outputs the write data WD. As a result, the write data WD is written to the data storage unit 24b of the memory cell unit 24 by a writing circuit (not shown). Further, the signal busy output by the busy signal output circuit 44 is at the L level.

If the error bit is 3 bits out of a total of 23 bits including the read data RD, the inspection bit RPB, and the virtual data, the flag ERRmax becomes the H level. At this time, the selection circuit 42a selects and outputs the error-corrected inspection bit RPBa. As a result, the inspection bit RPBa is written to the inspection bit storage unit 24a of the memory cell unit 24 by a writing circuit (not shown). Further, the selection circuit 42b selects and outputs the error-corrected read data RDa. As a result, the read data RDa is written to the data storage unit 24b of the memory cell unit 24 by a writing circuit (not shown).

The inspection bit RPBa and the read data RDa are written to the memory cell at the address where the inspection bit RPB and the read data RD are read.
Further, the signal busy output by the busy signal output circuit 44 becomes H level. When the signal bush is H level, the supply of the write data WD from the outside via the data input / output unit 21 is stopped.

For example, if the pre-shipment test is performed in the second test mode and then the mode is changed to the normal mode, the semiconductor storage device 40 corrects the newly generated error bits after shipment to at least 2 bits per 23 bits. it can. When sudden errors are accumulated after shipment and the total number of error bits reaches 3 bits, the error-corrected inspection bit RPBa and read data RDa are written back to the memory cell unit 24.

Hereinafter, the effects of the semiconductor storage device 40 will be described.
Some semiconductor storage devices put stress on the memory cells at the time of reading, and in rare cases, the data stored in the memory cells may be corrupted by the reading, and a sudden error may occur. When the reading is repeated, the error occurs a plurality of times, and the error bits are accumulated. If the number of error bits exceeds the upper limit of ECC correction capability (3 bits when Golay code is used), a systematic memory error is caused.

In the semiconductor storage device 40 of the third embodiment, when the number of error bits reaches 3 bits, which is the upper limit of the correction capability, the check bit RPBa and the read data RDa that have been error-corrected by the error correction circuit 41 are stored in the memory cell unit. Written back to 24. That is, the operation corresponding to the refresh operation in the volatile memory is performed. As a result, if the sudden error is not a fixed defect of the memory cell itself, the accumulation of error bits can be reset to zero, and the occurrence of a systematic memory error can be prevented.

The memory cell unit 24 of the semiconductor storage device 40 may have redundant cells. In that case, the control circuit 45 of the semiconductor storage device 40 writes back to the inspection bit RPBa, the inspection bit storage unit 24a, and the data storage unit 24b of the read data RDa, and then reads the data again, and the flag ERRmax is set to the H level again. Detects whether or not it becomes. When the flag ERRmax becomes H level again, the control circuit 45 considers that a fixing defect of the memory cell itself has occurred, and performs a process of replacing the address of the memory cell with the address of the redundant cell. As a result, when data is written or read to the address of the memory cell, data is written to the redundant cell or data is read from the redundant cell.

FIG. 23 is a flowchart showing an operation flow of an example of the semiconductor storage device of the third embodiment having redundant cells.
When the read process is performed (step S10), the control circuit 45 determines whether or not the flag ERRmax is at the H level (step S11). In the read process, the read data RD and the inspection bit RPB associated with the read data RD are read from the memory cell unit 24.

When the flag ERRmax is H level, the error-corrected read data RDa and the inspection bit RPBa are written back to the memory cell unit 24 (step S12). In the process of step S12, the inspection bit RPBa and the read data RDa are written to the memory cell at the address where the inspection bit RPB and the read data RD are read.

When the flag ERRmax is at the L level, normal operations (write processing, read processing, etc.) according to the command input to the semiconductor storage device 40 are performed (step S17).
On the other hand, after the processing of step S12, the re-reading processing is performed under the control of the control circuit 45 (step S13). In the re-reading process, the inspection bit RPBa and the read data RDa written back to the memory cell unit 24 are read again.

Then, the control circuit 45 again determines whether or not the flag ERRmax is at the H level (step S14). When the flag ERRmax is the L level, the process of step S17 is performed.

When the flag ERRmax becomes H level again, for example, the control circuit 45 specifies the address of the redundant cell instead of the address of the memory cell in which the 3-bit error bit is stored. Then, a writing circuit (not shown) writes the error-corrected 3-bit values included in the inspection bit RPBa and the read data RDa to the redundant cell at the specified address (step S15). The values of the inspection bit RPBa and the other bits included in the read data RDa are written in the inspection bit storage unit 24a or the data storage unit 24b.

When the processing of replacing the address of the inspection bit storage unit 24a or the data storage unit 24b with the address of the redundant cell is performed for each row or column of the memory cell array, the same row or column as the memory cell in which the error bit is stored is performed. The value of the address is also read. The value is also written to the redundant cell at the specified row or column address.

After that, under the control of the control circuit 45, the writing circuit (not shown) writes the address of the inspection bit storage unit 24a or the data storage unit 24b replaced with the address of the redundant cell to the redundant cell (step S16). As a result, when the address of the inspection bit storage unit 24a or the data storage unit 24b replaced with the address of the redundant cell is specified next, for example, the control circuit 45 converts it to the address of the redundant cell and reads or writes it. To be able to do.

After the process of step S16, the process of step S17 is performed.
According to the above processing, it is possible to deal with improper fixing of the memory cell itself, and further improve the reliability of the semiconductor storage device 40.

Although one aspect of the semiconductor storage device of the present invention has been described above based on the embodiments, these are merely examples and are not limited to the above description.
For example, in the above description, a semiconductor storage device using a code corresponding to 3-bit error detection and correction has been mainly described, but the present invention is not limited thereto. For semiconductor storage devices that use a code that supports 2-bit error detection and correction or a code that supports 4-bit error detection and correction, the number of bits of virtual data and the number of bits that are intentionally generated so as to correspond to the code. This can be achieved by changing the above and changing the circuit as appropriate.

10 Semiconductor storage device 11 Data input / output unit 12 Virtual data setting circuit 13 Inspection bit generation circuit 14 Memory cell unit 14a Inspection bit storage unit 14b Data storage unit 15 Test mode setting circuit 16 Error detection circuit 17 Error correction circuit 18a to 18c Virtual data rd, rda read data rpb, wpb inspection bit set setting signal wd write data

Claims (9)

Based on the write data of the first bit number and the first data of the second bit number, the first inspection of the code corresponding to the error detection and correction of a plurality of bits up to the third bit number. An inspection bit generation circuit that generates bits, and
A memory cell unit that stores the write data and the first inspection bit, and
When the operating state set based on the setting signal is the first state, the second data in which the value of at least one bit is different from the first data is output, and the operating state is the second state. At this time, a setting circuit that outputs a third data having a smaller number of bits with a different value from the first data than the second data, and a setting circuit.
The number of the code is based on the first read data corresponding to the write data and read from the memory cell unit and the second data or the third data output by the setting circuit. 2 inspection bits are generated, and an error bit is detected based on the third inspection bit corresponding to the first inspection bit and read from the memory cell unit and the second inspection bit. And the error detection circuit that outputs the detection result,
Based on the detection result, an error correction circuit that corrects the error within the range of the third bit number if at least the first read data contains an error among the error bits.
A semiconductor storage device having. The semiconductor storage device according to claim 1, wherein the third data has the same value as the first data. The semiconductor storage device according to claim 1 or 2, wherein the upper limit number of bits of the second data having a value different from that of the first data is the number of the third bit. The setting signal has a plurality of values, and each of the plurality of values is associated with any one of a plurality of fourth data having different values and different numbers of bits with respect to the first data. ,
The setting circuit receives the first value of the plurality of values, is one of the plurality of fourth data, and selects the second data associated with the first value. The semiconductor storage device according to any one of claims 1 to 3, wherein the semiconductor storage device is output. When the error bit detected with respect to the second data does not match a bit having a value different from that of the first data, the error detection circuit leads the error correction circuit to the first read. The semiconductor storage device according to any one of claims 1 to 4, which inverts the values of all bits of data or bits larger than the third number of bits. In the error detection circuit, when the number of bits of the error bit exceeds the number of the third bit, the error correction circuit has more than all the bits of the first read data or the number of the third bit. The semiconductor storage device according to any one of claims 1 to 4, wherein the bit value is inverted. The error correction circuit, the first to correct the first error bit is Ru contained in the read data and outputs the second read data, of the error bit, first included in the third check bit Correct the error bit of 2 and output the 4th check bit.
When the number of the error bits reaches the third number of bits, the error detection circuit outputs a detection signal indicating that the number of the third bits has been reached.
The semiconductor storage device further
When the error detection circuit outputs the detection signal, the first selection circuit that selects the second read data instead of the write data and supplies it to the memory cell unit and the first selection circuit.
When the error detection circuit outputs the detection signal, the second selection circuit that selects the fourth inspection bit instead of the first inspection bit and supplies it to the memory cell unit and the second selection circuit.
The semiconductor storage device according to any one of claims 1 to 6. The memory cell portion has a redundant cell and has a redundant cell.
The semiconductor storage device further
When reading the second read data and the fourth inspection bit stored in the memory cell unit, it is determined again whether or not the detection signal is output, and when the detection signal is output. The semiconductor storage device according to claim 7, further comprising a control circuit that controls writing the values of the first error bit and the second error bit into the redundant cell after being corrected by the error correction circuit. The semiconductor storage device according to any one of claims 1 to 8, wherein the reference numeral is a Golay code, the first bit number is 8 bits, and the second bit number is 4 bits.

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