JP6850159B2 - Oscillator - Google Patents

Description

The present invention relates to an oscillator having a frequency spreading function.

Conventionally, in a DC-DC converter, when the switching frequency is fixed, there is a problem that noise due to switching is concentrated on the frequency and its harmonics. Therefore, conventionally, an oscillator having a frequency spreading (spread spectrum) function has been provided in a DC-DC converter.

FIG. 1 shows a configuration example of an oscillator having a frequency spreading function. The oscillator 10 shown in FIG. 1 includes an oscillation circuit 101 and a reference voltage generation unit 102. The oscillation circuit 101 includes a one-shot circuit SH, an error amplifier EA, a current mirror circuit CM, a transistor Q1, a resistor R1, a capacitor C1, a comparator CP1, and a transistor M1. The oscillation circuit 101 generates and outputs a clock signal CLK (oscillation signal) based on the reference voltage RTREF generated by the reference voltage generation unit 102.

The current mirror circuit CM is composed of a transistor Tr1 and a transistor Tr2. Both transistors Tr1 and Tr2 are composed of p-channel MOSFETs. The gates of the transistors Tr1 and Tr2 are connected to the drain of the transistor Tr1. The sources of the transistors Tr1 and Tr2 are connected to the application end of the power supply voltage Vdd.

The drain of the transistor Tr2 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the end where the ground potential is applied. The connection point between the drain of the transistor Tr2 and one end of the capacitor C1 is connected to the drain of the transistor M1 composed of the n-channel MOSFET. The source of the transistor M1 is connected to the application end of the ground potential.

Further, the connection point between the drain of the transistor Tr2 and one end of the capacitor C1 is also connected to the non-inverting input terminal (+) of the comparator CP1. The inverting input terminal (-) of the comparator CP1 is connected to the application end of the reference voltage VREF.

The output of the comparator CP1 is input to the one-shot circuit 1. The one-shot circuit 1 is a circuit that outputs a one-shot pulse whose high level is set for a certain period of time when the output of the comparator CP1 rises to the high level. The one-shot circuit 1 outputs a clock signal CLK as a one-shot pulse. The clock signal CLK is input to the gate of the transistor M1.

The reference voltage RTREF generated by the reference voltage generation unit 102 is input to the non-inverting input terminal (+) of the error amplifier EA. The output of the error amplifier EA is input to the gate of the transistor Q1 composed of the n-channel MOSFET. The drain of the transistor Q1 is connected to the drain of the transistor Tr1. The source of the transistor Q1 is connected to the inverting input terminal (−) of the error amplifier EA together with one end of the resistor R1. The other end of the resistor R1 is connected to the end where the ground potential is applied.

Explaining the operation of the oscillator 10 having such a configuration, the voltage RT generated at the source of the transistor Q1 is controlled to match the reference voltage RTREF by the circuit composed of the error amplifier EA and the transistor Q1. A current I1 is generated by the voltage RT and the resistor R1. That is, the current I1 is proportional to the reference voltage RTREF.

The current I1 is mirrored by the current mirror circuit CM1 to generate the current I2. The current I2 flows through the capacitor C1. The capacitor C1 whose electric charge is discharged is charged by the current I2. At this time, the voltage of the capacitor C1 rises at a speed proportional to the current I2.

When the voltage of the capacitor C1 rises and reaches the reference voltage VREF, the output of the comparator CP1 rises to the High level, and the one-shot circuit 1 outputs the clock signal CLK set to the High level for a certain period of time. The clock signal CLK turns on the transistor M1 and discharges the capacitor C1. As a result, the frequency (oscillation frequency) of the clock signal CLK is proportional to the reference voltage RTREF.

The reference voltage generation unit 102 generates a reference voltage REREF that changes with time. As a result, the frequency of the clock signal CLK is changed, and frequency diffusion is realized.

An example of the prior art related to the above is disclosed in Patent Document 1.

Japanese Unexamined Patent Publication No. 2016-76918

The reference voltage generation unit 102 can be configured by, for example, an analog circuit using a constant current circuit and a capacitor or the like. In this case, it is assumed that the reference voltage generation unit 102 generates, for example, the reference voltage REREF of a continuously changing triangular wave. In this case, FIG. 9 shows an example of the temporal transition of the frequency of the clock signal CLK output from the oscillation circuit 101. The circles shown in FIG. 9 indicate the frequency of the clock signal CLK (the same applies to the circles in the drawings described below).

FIG. 9 shows a case where the frequency (oscillation frequency) of the clock signal CLK and the frequency diffusion period T are synchronized. On the other hand, FIG. 10 also shows another example of the temporal transition of the frequency of the clock signal CLK output from the oscillation circuit 101. FIG. 10 shows a case where the frequency of the clock signal CLK and the frequency diffusion period T are not synchronized.

The broken lines shown in FIGS. 9 and 10 indicate the frequency levels that the clock signal CLK can take. The number of broken lines is larger in the case of not synchronizing as shown in FIG. 10 than in the case of synchronizing as shown in FIG. That is, since the number of frequency levels that the clock signal CLK can take is large, frequency diffusion is sufficiently performed. Depending on the conditions, synchronization may occur by chance, and in that case, frequency diffusion is not sufficiently performed as shown in FIG. For example, even if there is no problem at the time of product shipment, there may be a case where the product is synchronized in the market, which may cause a problem.

Therefore, it is conceivable to configure the oscillator 10 as shown in FIG. 2, for example. In the oscillator 10 shown in FIG. 2, the reference voltage generation unit 102 includes an oscillation unit 1, a counter 2, a logic circuit 3, and a DAC (D / A converter) 4.

The oscillation unit 1 generates an oscillation signal OS, which is a pulse signal having a predetermined cycle, and outputs the oscillation signal OS to the counter 2. The counter 2 counts the oscillation signal OS. The digital output of the counter 2 is input to the DAC 4 via the logic circuit 3. The DAC4 converts the digital input into a reference voltage RTREF which is an analog signal and outputs the digital input.

Here, FIG. 11 shows a configuration example of the counter 2, the logic circuit 3, and the DAC 4 in the reference voltage generation unit 102. The counter 201 shown in FIG. 11 corresponds to the counter 2, the DAC 401 corresponds to the DAC 4, and the XOR circuits 301A to 301D form the logic circuit 3.

The counter 201 outputs a count value consisting of 5 bits of bit 0 to bit 4. Further, a digital signal composed of 5 bits of bit 0 to bit 4 is input to the DAC 401. The counter 201 causes the most significant bit, bit4, to be directly input to bit0, which is the least significant bit of the input of the DAC401, and is input to one of the input terminals of the XOR circuits 301A to 301D. The counter 201 causes the other bits bit0 to bit3 to be input to the other input terminals of the XOR circuits 301A to 301D, respectively. Each output of the XOR circuits 301A to 301D is input to bit4 to bit1 of the DAC401.

The counter 201 counts the counter value from "00000" to "11111". At this time, the upper 4 bits of the input of the DAC 401, bits 4 to bit 1, are up-counted from "0000" to "1111" and then down-counted from "1111" to "0000". Further, bit0, which is the least significant bit of the input of the DAC401, is "0" during the upcounting of the upper 4 bits of the input of the DAC401, and bit0 is "1" during the downcounting of the upper 4 bits. Is. That is, when the input of the DAC is expressed as a decimal number, it increases by 2 from 0 to 30 and then decreases by 2 from 31 to 1.

The DAC 401 performs D / A conversion of the digital input consisting of bit0 to bit4 and outputs the reference voltage RTREF, and the frequency of the clock signal CLK is proportional to the reference voltage RTREF. Therefore, the temporal transition of the frequency of the clock signal CLK according to the count by the counter 201 is as shown in FIG.

FIG. 13 shows a case where the frequency of the clock signal CLK and the frequency diffusion period T10 are synchronized. Even in the case of synchronization in this way, since the frequency of the clock signal CLK is dispersed into 32, the frequency can be sufficiently diffused and the peak of noise can be suppressed. If they are not synchronized, the frequency of the clock signal CLK is distributed to a larger number, and the effect of frequency spreading becomes greater. However, there is a problem that the frequency diffusion period T10 becomes long and low frequency noise occurs in the audible band. It should be noted that noise in the audible band is generated when the frequencies are dispersed into 32 frequencies, and such noise is not always generated.

Therefore, for example, the counter 2, the logic circuit 3, and the DAC 4 in the reference voltage generation unit 102 can be configured as shown in FIG. In FIG. 12, the counter 202 corresponds to the counter 2, the DAC 402 corresponds to the DAC 4, and the logic circuit 3 is composed of the XOR circuits 302A and 302B.

The configuration shown in FIG. 12 is basically the same as that in FIG. 11, but the output of the counter 202 and the input of the DAC 402 are both set to 3 bits. The counter 202 counts from "000" to "111". At this time, the upper two bits of the input of the DAC 402 are up-counted from "00" to "11" and then down-counted from "11" to "00". The least significant bit of the input of the DAC 402 is "0" during the upcount and "1" during the downcount. Therefore, when the digital input of the DAC 402 is expressed as a decimal number, it increases by 2 from 0 to 6 and then decreases by 2 from 7 to 1.

The time transition of the frequency of the clock signal CLK in the oscillator 10 when the configuration shown in FIG. 12 is used is as shown in FIG. FIG. 14 shows a case where the frequency of the clock signal CLK and the frequency diffusion period T11 are synchronized.

As shown in FIG. 14, in one cycle T11 of frequency diffusion, the frequency is increased and decreased, and the frequency is dispersed into eight. Since one cycle T11 of frequency diffusion is shortened, it is possible to suppress the occurrence of low-frequency noise in the audible band as compared with the case shown in FIG. 13 described above. However, when the frequency of the clock signal CLK and the frequency diffusion period T11 are synchronized, the frequencies are dispersed into eight frequencies and are not sufficiently dispersed, so that there is a problem that the noise peak becomes large. That is, the effect of frequency diffusion is reduced.

In view of the above situation, it is an object of the present invention to provide an oscillator capable of improving the effect of frequency diffusion while suppressing low frequency noise in the audible band.

The oscillator of the present invention includes an oscillator circuit that outputs a first oscillation signal and an oscillator circuit.
The oscillator that outputs the second oscillation signal and the oscillator
A counter that counts the second oscillation signal and
A DAC (D / A converter) having an input connected to the output of the counter is provided.
The oscillation circuit generates the first oscillation signal based on the output of the DAC, and the oscillation circuit generates the first oscillation signal.
The DAC input has a first bit indicating an ascending / descending component and a second bit indicating an offset component.
The first bit is configured to be directly connected to the output of the counter via a logic circuit and / or directly (first configuration).

Further, in the first configuration, the output of the counter and the input of the DAC are each composed of N bits.
The lower K bit of the output of the counter is connected to the upper K bit of the input of the DAC.
The (NK) bits other than the lower K bits of the output of the counter are connected to the (NK) bits other than the upper K bits of the input of the DAC.
The upper K bit of the input of the DAC is the first bit.
The (NK) bit of the input of the DAC may be the second bit (second configuration).

Further, in the second configuration, the most significant bit in the lower K bit of the output of the counter is connected to the least significant bit of the upper K bit of the input of the DAC, and one input end of the XOR circuit is connected. Connected to
A bit other than the most significant bit in the lower K bit of the output of the counter may be connected to a bit other than the least significant bit in the upper K bit of the input of the DAC via the XOR circuit (the first). 3 configuration).

Further, in the second or third configuration, the (NK) bit of the output of the counter is connected to the (NK) bit of the input of the DAC by inverting the relationship between the upper and lower levels. It may be done (fourth configuration).

Further, in the first configuration, a counter different from the counter is further provided.
The output of the counter is composed of K bits.
The input of the DAC is composed of N bits.
The output of the other counter is composed of (NK) bits and is composed of (NK) bits.
The counter counts up and down,
The output of the counter is connected to the upper K bit of the DAC.
The other counter counts the edge of the most significant bit of the counter's output.
The output of the other counter is connected to a bit other than the upper K bit of the input of the DAC.
The upper K bit of the input of the DAC is the first bit.
Bits other than the upper K bit of the input of the DAC may be the second bit (fifth configuration).

Further, in the fifth configuration, the output of the counter may be directly connected to the upper K bit of the DAC (sixth configuration).

Further, in the fifth or sixth configuration, the output of the other counter may be connected to a bit other than the upper K bit of the DAC input by inverting the upper / lower relationship (upper / lower relationship). 7th configuration).

According to the oscillator of the present invention, it is possible to improve the effect of frequency diffusion while suppressing low frequency noise in the audible band.

It is a figure which shows one structural example of the oscillator which concerns on embodiment of this invention. It is a figure which shows one structural example of the oscillator which concerns on embodiment of this invention. It is a figure which shows the structure which used the counter and DAC which concerns on 1st Embodiment of this invention. It is a figure which shows the structure which used the counter and DAC which concerns on 2nd Embodiment of this invention. It is a table which shows the transition of the output bit of the counter which concerns on 1st Embodiment of this invention, and the input bit of DAC. It is a table which shows the transition of the output bit of the counter which concerns on 2nd Embodiment of this invention, and the input bit of DAC. It is a figure which shows the time transition of the frequency of the clock signal which concerns on 1st Embodiment of this invention. It is a figure which shows the time transition of the frequency of the clock signal which concerns on 2nd Embodiment of this invention. It is a figure which shows an example of the time transition of the frequency of the clock signal when the reference voltage generation part is composed of an analog circuit. It is a figure which shows another example of the time transition of the frequency of a clock signal when the reference voltage generation part is composed of an analog circuit. It is a figure which shows the structure which used the counter and DAC which concerns on 1st comparative example with this invention. It is a figure which shows the structure which used the counter and DAC which concerns on the 2nd comparative example with this invention. It is a figure which shows the time transition of the frequency of the clock signal which concerns on 1st comparative example with this invention. It is a figure which shows the time transition of the frequency of the clock signal which concerns on the 2nd comparative example with this invention.

An embodiment of the present invention will be described below with reference to the drawings. The configuration of the oscillator according to the embodiment of the present invention is basically the same as the configuration of the oscillator 10 shown in FIG. 2 described above. Since the configuration of the oscillator 10 itself has been described above, detailed description thereof will be omitted here. Hereinafter, embodiments relating to the configuration of the counter 2, the logic circuit 3, and the DAC 4 in the reference voltage generation unit 102 included in the oscillator 10 will be described.

<First Embodiment>
FIG. 3 shows a specific configuration of the counter 2, the logic circuit 3, and the DAC 4 according to the first embodiment of the present invention. The counter 21 shown in FIG. 3 corresponds to the counter 2, the DAC 41 corresponds to the DAC 4, and the logic circuit 3 is composed of the XOR circuits 31A and 31B.

The counter 21 outputs a count value consisting of 5 bits of bit 0 to bit 4. Further, a digital signal composed of 5 bits of bit 0 to bit 4 is input to the DAC 41. The lower 3 bits (bit 0 to bit 2) of the output of the counter 21 are connected to the upper 3 bits (bit 2 to bit 4) of the input of the DAC 41. Bit2, which is the most significant bit of the lower 3 bits of the output of the counter 21, is directly connected to bit2, which is the lowest bit of the upper 3 bits of the input of the DAC 41. Further, the output bit2 of the counter 21 is also connected to the input end of each of the XOR circuits 31A and 31B.

Of the lower three bits of the output of the counter 21, bit1 is connected to the other input end of the XOR circuit 31A. Of the lower three bits of the output of the counter 21, bit0 is connected to the other input end of the XOR circuit 31B. The output of the XOR circuit 31A is connected to bit 4 of the input of the DAC 41. The output of the XOR circuit 31B is connected to bit 3 of the input of the DAC 41. That is, the bits (bit1, bit0) other than the most significant bit in the lower 3 bits of the output of the counter 21 are the bits (bit4, bit3) other than the least significant bit in the upper 3 bits of the input of the DAC 41, and the XOR circuits 31A and 31B are used. Connected via.

That is, the most significant bit (bit1) among the lower 3 bits of the output of the counter 21 other than the most significant bit is the most significant bit among the upper 3 bits of the input of the DAC 41 other than the least significant bit. It is connected to (bit 4) via the XOR circuit 31A. Each time the lower 3 bits of the output of the counter 21 are shifted one bit at a time from the most significant bit other than the most significant bit, the shifted bit (bit0) is the lowest of the upper 3 bits of the input of the DAC 41. It is connected to a bit (bit3) shifted by one bit from the most significant bit other than the bit via the XOR circuit 31B.

Further, bit 4 of the upper 2 bits of the output of the counter 21 is connected to bit 0 of the lower 2 bits of the input of the DAC 41, and bit 3 of the output of the counter 21 is connected to bit 1 of the input of the DAC 41. That is, the upper 2 bits (bit4, bit3) of the output of the counter 21 and the lower 2 bits (bit1, bit0) of the input of the DAC 41 are connected by inverting the relationship between the upper and lower parts. That is, the 2 (= 5-3) bits other than the lower 3 bits of the output of the counter 21 are connected to the 2 (= 5-3) bits other than the upper 3 bits of the input of the DAC 41.

In such a configuration shown in FIG. 3, the transition of the output bit of the counter 21 and the input bit of the DAC 41 when the counter 21 counts is shown in FIG. In the table shown in FIG. 5, the rightmost column shows the numerical value representing the input of the DAC 41 in decimal.

The counter 21 counts from "00000" to "11111". During the count from "000000" to "00111" (referred to as the first count), the upper three bits of the input bits of the DAC 41 rise from "000" to "111" and then fall to "001". Similar ascents and descents of the input bits of the DAC 41 are from "01000" to "01111" (referred to as the second count), "10000" to "10111" (referred to as the third count), and "3rd count" by the counter 21. It is also performed during each count from "11000" to "11111" (referred to as the fourth count). That is, the upper three bits of the input of the DAC 41 correspond to the bits (first bits) indicating the ascending / descending components.

At this time, the lower two bits of the input of the DAC 41 are "00" in the first count, "10" in the second count, "01" in the third count, and "11" in the fourth count. That is, the lower two bits of the input of the DAC 41 correspond to the bit (second bit) indicating the offset component.

As a result, in the first count, the value represented by the decimal number of the input of the DAC 41 increases by 8 from 0 to 24 and then decreases by 8 from 28 to 4. In the second count, the decimal value is increased by 8 from 2 to 26 and then decreased by 8 from 30 to 6. The lower 2 bits "10" of the input of the DAC 41 in the second count have an offset of "+2" in decimal with respect to the lower 2 bits "00" of the input of the DAC 41 in the first count. Therefore, in the second count, the decimal value of the input of the DAC 41 has an offset of "+2" while maintaining the same rise and fall with respect to the first count.

Similarly, in the third count, the lower two bits of the input of the DAC 41 are "01", so that the decimal value of the input of the DAC 41 has an offset of "+1" with respect to the first count. As a result, in the third count, the decimal value of the input of the DAC 41 increases by 8 from 1 to 25 and then decreases by 8 from 29 to 5.

Similarly, in the fourth count, the lower two bits of the input of the DAC 41 are "11", so that the decimal value of the input of the DAC 41 has an offset of "+3" with respect to the first count. As a result, in the fourth count, the decimal value of the input of the DAC 41 increases by 8 from 3 to 27 and then decreases by 8 from 31 to 7.

The DAC 41 performs D / A conversion of the digital input consisting of bit0 to bit4 and outputs the reference voltage RTREF, and the frequency of the clock signal CLK is proportional to the reference voltage RTREF. Therefore, the temporal transition of the frequency of the clock signal CLK according to the count by the counter 21 is as shown in FIG. FIG. 7 shows a case where the frequency of the clock signal CLK and the frequency diffusion cycles T1 to T4 are synchronized.

In FIG. 7, one cycle T1 to T4 is a period corresponding to each of the first count to the fourth count. As described above, in each of the 1st cycles T2 to T4, the frequencies of the clock signal CLK have different offsets while maintaining the same rising and falling with respect to the 1st cycle T1. That is, the frequency (oscillation frequency) of the clock signal CLK (oscillation signal) has an ascending / descending component that rises / falls in one cycle and an offset component for each cycle.

In FIG. 7, noise of each frequency of 1/8, 1/16, and 1/32 of the frequency of one clock of the clock signal CLK is generated, but noise of 1/8 of the frequencies is dominant. It is possible to suppress the occurrence of low frequency noise in the audible region.

Further, the broken line shown in FIG. 7 indicates the level of the frequency generated in one cycle T1 to T4. As described above, in the present embodiment, even when the frequency of the clock signal CLK and the frequency diffusion cycles T1 to T4 are synchronized, the frequencies are set to 32 frequencies in the cycle consisting of one cycle T1 to T4. Be distributed. If not synchronized, the frequency will be distributed to a larger number. Therefore, the noise peak can be suppressed by sufficient frequency diffusion.

As described above, in the present embodiment, the effect of frequency diffusion can be improved while suppressing low frequency noise in the audible band.

<Second Embodiment>
FIG. 4 shows a specific configuration of the counter 2 and the DAC 4 according to the second embodiment of the present invention. The first counter 22 shown in FIG. 4 corresponds to the counter 2, and the DAC 42 corresponds to the DAC 4. In this embodiment, the logic circuit 3 is not configured. Further, a second counter 50 different from the first counter 22 is provided between the first counter 22 and the DAC 42.

The counter 22 outputs a count value consisting of 3 bits of bit0 to bit2. Further, a digital signal composed of 5 bits of bit 0 to bit 4 is input to the DAC 42. The second counter 50 outputs a count value consisting of 2 bits obtained by subtracting the number of output bits of the first counter 22 from the number of input bits of the DAC 42.

The 3 bits (bit 0 to bit 2) of the output of the first counter 22 are directly connected to the upper 3 bits (bit 2 to bit 4) of the input of the DAC 42. The second counter 50 counts the rising edge of the most significant bit (bit 2) of the output of the first counter 22. The second counter 50 outputs a count value composed of 2 bits (bit0, bit1). Each bit of the output of the second counter 50 is connected to the lower two bits (bit0, bit1) of the input of the DAC 42 by inverting the relationship between the upper and lower parts.

In such a configuration shown in FIG. 4, the transition of each output bit of the first counter 22 and the second counter 50 and the input bit of the DAC 42 when the first counter 22 counts is shown in FIG. In the table shown in FIG. 6, the rightmost column shows the numerical value representing the input of the DAC 42 in decimal.

The first counter 22 up-counts from "100" to "111", then down-counts to "001", and then up-counts to "011" (hereinafter referred to as the first count). Then, after up-counting from "100" to "111" again, down-counting to "001" and then up-counting to "011" (hereinafter referred to as a second count). Then, after up-counting from "100" to "111" again, down-counting to "001" and then up-counting to "011" (hereinafter referred to as a third count). Then, after up-counting from "100" to "111" again, down-counting to "001" and then up-counting to "011" (hereinafter referred to as a fourth count).

The output of the second counter 50 starts from "00", and the second counter 50 starts from the first count to the second count when the output of the first counter 22 is switched from "011" to "100". At the same time, the rising edge of bit2 is counted and the output is set to "01". Further, at the same time as changing from the second count to the third count, the rising edge of bit2 is counted and the output is set to "10". Further, at the same time as changing from the third count to the fourth count, the rising edge of bit2 is counted and the output is set to "11". Further, at the same time as the fourth count changes to the 0th count, the rising edge of bit2 is counted and the output is set to "00".

During the first count, the upper three bits of the input of the DAC 42 rise and fall in the same manner as the output of the first counter 22. At this time, the lower two bits of the input of the DAC 42 take a value of "00" in order. Also, during the second count, the upper 3 bits of the input of the DAC 42 rise and fall in the same manner as the output of the first counter 22. This rise and fall is the same as the rise and fall during the first count. At this time, the lower two bits of the input of the DAC 42 take a value of "10" in order. Further, during the third count, the upper three bits of the input of the DAC 42 rise and fall in the same manner as the output of the first counter 22. This rise and fall is the same as the rise and fall during the first count. At this time, the lower two bits of the input of the DAC 42 take the value of "01" in order. Further, during the fourth count, the upper three bits of the input of the DAC 42 rise and fall in the same manner as the output of the first counter 22. This rise and fall is the same as the rise and fall during the first count. At this time, the lower two bits of the input of the DAC 42 take the value of "11" in order. That is, the upper 3 bits of the input of the DAC 42 correspond to the bits (first bit) indicating the ascending / descending component, and the bits other than the upper 3 bits of the input of the DAC 42 correspond to the bits (second bit) indicating the offset component. Applicable.

The lower 2 bits "01" and "10" of the input of the DAC 42 in the second count are "+1" and "+2" in decimal numbers based on the lower 2 bits "00" of the input of the DAC 42 in the first count. Has an offset. The lower 2 bits "01" of the input of the DAC 42 in the third count have an offset of "+1" in decimal with respect to the lower 2 bits "00" of the input of the DAC 42 in the first count. The lower 2 bits "11" of the input of the DAC 42 at the 4th count have an offset of "+3" in decimal with respect to the lower 2 bits "00" of the input of the DAC 42 at the 1st count.

As a result, the decimal value of the input of the DAC 42 increases by "4" from "16" to "28" during the first count, decreases by "4" to "4", and decreases to "12". In response to the increase of "4" by "4", the offset of "+2" from the first count increases by "4" from "18" to "30" during the second count, and "6". Corresponds to descending by "4" to "14" and increasing by "4" to "14".

Then, during the third count, the offset of "+1" with respect to the first count increases by "4" from "17" to "29", decreases by "4" to "5", and "13". Corresponds to increasing by "4" up to.

Further, during the fourth count, the offset of "+3" with respect to the first count increases by "4" from "19" to "31", decreases by "4" to "7", and "15". Corresponds to increasing by "4" up to.

The time transition of the frequency of the clock signal CLK according to the count by the counter 22 is as shown in FIG. FIG. 8 shows a case where the frequency of the clock signal CLK and the frequency diffusion periods T5 to T8 are synchronized.

In FIG. 8, one cycle T5 to T8 is a period corresponding to each of the first count to the fourth count. As described above, in the 1st cycle T6 to T8, the frequency of the clock signal CLK has an offset while maintaining the same rising and falling with the 1st cycle T5 as a reference. That is, the frequency (oscillation frequency) of the clock signal CLK (oscillation signal) has an ascending / descending component that rises and falls in one cycle and an offset component for each cycle.

In FIG. 8, since noise having a frequency of 1/12 of the frequency of one clock of the clock signal CLK becomes dominant, it is possible to suppress the occurrence of low-frequency noise in the audible region.

Further, the broken line shown in FIG. 8 indicates the level of the frequency generated in one cycle T5 to T8. As described above, in the present embodiment, even when the frequency of the clock signal CLK and the frequency diffusion cycles T5 to T8 are synchronized, the frequencies are set to 28 frequencies in the cycle consisting of one cycle T5 to T8. Be distributed. If not synchronized, the frequency will be distributed to a larger number. Therefore, the noise peak can be suppressed by sufficient frequency diffusion.

As described above, even in this embodiment, the effect of frequency diffusion can be improved while suppressing low frequency noise in the audible band.

<Other variants>
Although the embodiments of the present invention have been described above, the embodiments can be modified in various ways within the scope of the gist of the present invention.

For example, in the configuration of FIG. 3 described in the first embodiment, the XOR circuits 31A and 31B are provided, but the counters 21 have bit2, bit1 and bit0, respectively, without providing the XOR circuit. It may be directly connected to bit4 and bit3. As a result, the upper 3 bits of the input of the DAC 41 indicating the rising / falling component rises from "000" to "110", then falls to "001", and then rises again to "111". Even in this way, the object of the present invention can be achieved.

Further, in the first embodiment, the lower two bits of the input of the DAC 41 indicating the offset component may be connected to the upper two bits of the output of the counter 21 without inverting the relationship between the upper and lower bits.

Further, in the second embodiment (FIG. 4), the upper three bits of the DAC 42 indicating the ascending / descending components may be connected to each of the output bits of the first counter 22 via an inverter. As a result, the upper 3 bits of the DAC 42 become a value that rises after falling and then falls again, but the object of the present invention is achieved. The inverter constitutes a logic circuit 3.

The present invention can be used, for example, in an oscillator used in a DC-DC converter.

1 Oscillator 2 Counter 3 Logic circuit 4 DAC (D / A converter)
10 Oscillator 101 Oscillator 102 Reference voltage generator SH One-shot circuit EA Error amplifier CM Current mirror circuit Tr1, Tr2 Transistor Q1 Transistor C1 Capacitor M1 Transistor CP1 Comparator R1 Resistance 21 Counter 41 DAC
31A, 31B XOR circuit 22 1st counter 42 DAC
50 Second counter 201, 202 Counters 301A to 301D, 302A, 302B XOR circuit 401, 402 DAC

Claims (7)

An oscillator circuit that outputs the first oscillation signal and
The oscillator that outputs the second oscillation signal and the oscillator
A counter that counts the second oscillation signal and
A DAC (D / A converter) having an input connected to the output of the counter is provided.
The oscillation circuit generates the first oscillation signal based on the output of the DAC, and the oscillation circuit generates the first oscillation signal.
The input of the DAC has a first bit, which is an upper bit indicating an ascending / descending component in one cycle, and a second bit, which is a lower bit indicating an offset component changing in each cycle.
The first bit is an oscillator that is directly connected to the output of the counter via a logic circuit and / or directly. The output of the counter and the input of the DAC are each composed of N bits.
The lower K bit of the output of the counter is connected to the upper K bit of the input of the DAC.
The (NK) bits other than the lower K bits of the output of the counter are connected to the (NK) bits other than the upper K bits of the input of the DAC.
The upper K bit of the input of the DAC is the first bit.
The oscillator according to claim 1, wherein the (NK) bit of the input of the DAC is the second bit. The most significant bit of the lower K bit of the output of the counter is connected to the least significant bit of the upper K bit of the input of the DAC and is also connected to one input end of the XOR circuit.
The second aspect of claim 2, wherein the bit other than the most significant bit in the lower K bit of the output of the counter is connected to the bit other than the least significant bit in the upper K bit of the input of the DAC via the XOR circuit. Oscillator. The second or third aspect of the present invention, wherein the (NK) bit of the output of the counter is connected to the (NK) bit of the input of the DAC by inverting the relationship between the upper and lower levels. Oscillator. Further equipped with a counter different from the counter,
The output of the counter is composed of K bits.
The input of the DAC is composed of N bits.
The output of the other counter is composed of (NK) bits and is composed of (NK) bits.
The counter counts up and down,
The output of the counter is connected to the upper K bit of the DAC.
The other counter counts the edge of the most significant bit of the counter's output.
The output of the other counter is connected to a bit other than the upper K bit of the input of the DAC.
The upper K bit of the input of the DAC is the first bit.
The oscillator according to claim 1, wherein the bits other than the upper K bit of the input of the DAC are the second bit. The oscillator according to claim 5, wherein the output of the counter is directly connected to the upper K bit of the DAC. The oscillator according to claim 5 or 6, wherein the output of the other counter is connected to a bit other than the upper K bit of the input of the DAC by inverting the relationship between the upper and lower parts.

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