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JP6840611B2 - Semiconductor devices and their manufacturing methods - Google Patents

Semiconductor devices and their manufacturing methods Download PDF

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JP6840611B2
JP6840611B2 JP2017084656A JP2017084656A JP6840611B2 JP 6840611 B2 JP6840611 B2 JP 6840611B2 JP 2017084656 A JP2017084656 A JP 2017084656A JP 2017084656 A JP2017084656 A JP 2017084656A JP 6840611 B2 JP6840611 B2 JP 6840611B2
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semiconductor layer
trench
electrode
insulating film
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JP2018182258A (en
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俊史 西口
俊史 西口
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Toshiba Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

実施形態は、半導体装置及びその製造方法に関する。 The embodiment relates to a semiconductor device and a method for manufacturing the same.

例えば電力制御用の半導体装置（パワーデバイス）として、ゲート電極の下にフィールドプレート電極を備えたＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）構造が提案されている。さらに、フィールドプレート電極の幅を深さ方向に段階的に小さくした構造の提案もなされている（特許文献１）。 For example, as a semiconductor device (power device) for power control, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure having a field plate electrode under the gate electrode has been proposed. Further, a structure in which the width of the field plate electrode is gradually reduced in the depth direction has been proposed (Patent Document 1).

特開２０１６−７２４８２号公報Japanese Unexamined Patent Publication No. 2016-72482

実施形態は、低オン抵抗且つ高耐圧の半導体装置及びその製造方法を提供する。 The embodiment provides a semiconductor device having low on-resistance and high withstand voltage and a method for manufacturing the same.

実施形態によれば、半導体装置は、第１電極と、前記第１電極上に設けられた第１導電形の第１半導体層と、前記第１半導体層上に設けられた第２導電形の第２半導体層と、前記第２半導体層上に設けられた第１導電形の第３半導体層と、前記第３半導体層に接する第２電極と、前記第３半導体層の側面に対向するゲート電極と、前記第３半導体層の前記側面と前記ゲート電極との間に設けられた第１絶縁膜と、前記ゲート電極の下において前記第１半導体層に形成され、前記第１電極に向かうにつれて段階的に幅が小さくなるトレンチ内に設けられたフィールドプレート電極と、前記第１半導体層と前記フィールドプレート電極との間に設けられた第２絶縁膜と、を備えている。前記第２絶縁膜における前記第１半導体層に接する側壁は、前記第１電極と前記第２電極とを結ぶ方向に沿った階段状の段差をもつ。前記フィールドプレート電極は、前記ゲート電極側に設けられた上部と、前記上部よりも前記第１電極側に設けられ、前記上部よりも幅が小さい下部と、を有する。前記第２絶縁膜は、前記フィールドプレート電極の前記上部と前記第１半導体層との間に設けられた第１部分と、前記フィールドプレート電極の前記下部と前記第１半導体層との間に設けられ、前記第１部分よりも膜厚が厚い第２部分と、を有する。前記第１半導体層は、第１領域と、前記第１領域と前記第２絶縁膜の前記側壁との間における前記第２絶縁膜の前記側壁に近接する領域に設けられ、前記第１領域よりも第１導電形不純物濃度が高い第２領域と、を有し、前記第２領域における前記第２絶縁膜の前記第１部分に近接する領域の第１導電形不純物濃度は、前記第１領域の第１導電形不純物濃度よりも高く、前記第２領域における前記第２絶縁膜の前記第２部分に近接する領域の第１導電形不純物濃度よりも低い。 According to the embodiment, the semiconductor device includes a first electrode, a first conductive type first semiconductor layer provided on the first electrode, and a second conductive type provided on the first semiconductor layer. A second semiconductor layer, a first conductive type third semiconductor layer provided on the second semiconductor layer, a second electrode in contact with the third semiconductor layer, and a gate facing the side surface of the third semiconductor layer. and electrodes, the a first insulating film provided between the side surface and the gate electrode of the third semiconductor layer, formed on Oite the first semiconductor layer under the gate electrode, the first electrode It includes a field plate electrode provided in a trench whose width gradually decreases toward the distance, and a second insulating film provided between the first semiconductor layer and the field plate electrode. The side wall of the second insulating film in contact with the first semiconductor layer has a stepped step along the direction connecting the first electrode and the second electrode. The field plate electrode has an upper portion provided on the gate electrode side and a lower portion provided on the first electrode side of the upper portion and having a width smaller than that of the upper portion. The second insulating film is provided between the first portion provided between the upper portion of the field plate electrode and the first semiconductor layer, and between the lower portion of the field plate electrode and the first semiconductor layer. It has a second portion having a film thickness thicker than that of the first portion. The first semiconductor layer includes a first region, provided in the region close to the side wall of the second insulating film in between the side walls of the first region and the second insulating film, than the first region also a second region first conductivity type impurity concentration is high, have a, the first conductivity type impurity concentration in the region adjacent to said first portion of said second insulating film in the second region, the first region It is higher than the concentration of the first conductive impurity in the second region and lower than the concentration of the first conductive impurity in the region close to the second portion of the second insulating film in the second region .

実施形態の半導体装置の模式平面図。The schematic plan view of the semiconductor device of an embodiment. 図１におけるＡ−Ａ断面図。FIG. 1 is a sectional view taken along the line AA in FIG. （ａ）および（ｂ）は、実施形態の半導体装置の製造方法を示す模式断面図。(A) and (b) are schematic cross-sectional views which show the manufacturing method of the semiconductor device of embodiment. （ａ）および（ｂ）は、実施形態の半導体装置の製造方法を示す模式断面図。(A) and (b) are schematic cross-sectional views which show the manufacturing method of the semiconductor device of embodiment. （ａ）および（ｂ）は、実施形態の半導体装置の製造方法を示す模式断面図。(A) and (b) are schematic cross-sectional views which show the manufacturing method of the semiconductor device of embodiment. （ａ）および（ｂ）は、実施形態の半導体装置の製造方法を示す模式断面図。(A) and (b) are schematic cross-sectional views which show the manufacturing method of the semiconductor device of embodiment. （ａ）および（ｂ）は、実施形態の半導体装置の製造方法を示す模式断面図。(A) and (b) are schematic cross-sectional views which show the manufacturing method of the semiconductor device of embodiment. （ａ）および（ｂ）は、実施形態の半導体装置の製造方法を示す模式断面図。(A) and (b) are schematic cross-sectional views which show the manufacturing method of the semiconductor device of embodiment. （ａ）および（ｂ）は、実施形態の半導体装置の製造方法を示す模式断面図。(A) and (b) are schematic cross-sectional views which show the manufacturing method of the semiconductor device of embodiment. 実施形態の半導体装置の製造方法を示す模式断面図。The schematic cross-sectional view which shows the manufacturing method of the semiconductor device of embodiment. 実施形態の半導体装置の製造方法を示す模式断面図。The schematic cross-sectional view which shows the manufacturing method of the semiconductor device of embodiment. 増速酸化率の不純物ドーズ量依存性のシミュレーション結果を示すグラフ。The graph which shows the simulation result of the impurity dose amount dependence of the rapid oxidation rate. 実施形態の半導体装置の模式断面図。Schematic cross-sectional view of the semiconductor device of the embodiment. 実施形態の半導体装置の模式断面図。Schematic cross-sectional view of the semiconductor device of the embodiment. （ａ）〜（ｃ）は、図１４に示す半導体装置の製造方法を示す模式断面図。(A) to (c) are schematic cross-sectional views showing a manufacturing method of the semiconductor device shown in FIG.

以下、図面を参照し、実施形態について説明する。なお、各図面中、同じ要素には同じ符号を付している。 Hereinafter, embodiments will be described with reference to the drawings. In each drawing, the same elements are designated by the same reference numerals.

以下の実施形態では第１導電型をＮ型、第２導電型をＰ型として説明するが、第１導電型をＰ型、第２導電型をＮ型としてもよい。 In the following embodiments, the first conductive type will be referred to as N type and the second conductive type will be referred to as P type, but the first conductive type may be P type and the second conductive type may be N type.

また、実施形態では半導体材料はシリコンとするが、半導体材料は、シリコンに限らず、例えば、炭化シリコン、窒化ガリウム、酸化ガリウムなどであってもよい。 Further, although the semiconductor material is silicon in the embodiment, the semiconductor material is not limited to silicon, and may be, for example, silicon carbide, gallium nitride, gallium oxide, or the like.

また、以下の実施形態において、不純物濃度はキャリア濃度と置き換えて言うことができる。キャリア濃度は、実効的な不純物濃度とみなすことができる。 Further, in the following embodiments, the impurity concentration can be said to be replaced with the carrier concentration. The carrier concentration can be regarded as an effective impurity concentration.

図１は、実施形態の半導体装置の模式平面図である。
図２は、図１におけるＡ−Ａ断面図である。 FIG. 1 is a schematic plan view of the semiconductor device of the embodiment.
FIG. 2 is a cross-sectional view taken along the line AA in FIG.

図１は、図２に表される要素のうち、ゲート電極３０、絶縁膜４１、ソース層２４、およびベースコンタクト領域２５の平面レイアウトを表す。また、ゲート電極３０の下に設けられたフィールドプレート電極５０を、図１において破線で表す。 FIG. 1 shows the planar layout of the gate electrode 30, the insulating film 41, the source layer 24, and the base contact region 25 among the elements shown in FIG. The field plate electrode 50 provided below the gate electrode 30 is represented by a broken line in FIG.

実施形態の半導体装置は、図２に示すように、第１電極としてのドレイン電極１１と、第２電極としてのソース電極１２との間に半導体層２０が設けられ、ドレイン電極１１とソース電極１２とを結ぶ方向（縦方向）に電流が流れる縦型半導体装置である。半導体層２０は、シリコン層である。 In the semiconductor device of the embodiment, as shown in FIG. 2, a semiconductor layer 20 is provided between the drain electrode 11 as the first electrode and the source electrode 12 as the second electrode, and the drain electrode 11 and the source electrode 12 are provided. This is a vertical semiconductor device in which a current flows in the direction (vertical direction) connecting the two. The semiconductor layer 20 is a silicon layer.

図１に示すＸ方向およびＹ方向は、半導体層２０の主面に対して平行な面内で互いに直交する方向を表す。 The X and Y directions shown in FIG. 1 represent directions orthogonal to each other in a plane parallel to the main surface of the semiconductor layer 20.

図１に示すように、複数のゲート電極３０、複数の絶縁膜４１、複数のソース層２４、および複数のベースコンタクト領域２５がＸ方向に周期的に配列されている。ゲート電極３０、絶縁膜４１、ソース層２４、およびベースコンタクト領域２５は、Ｙ方向に延びるストライプ状パターンで形成されている。また、図２に示すベース層２３も、ソース層２４およびベースコンタクト領域２５の下でＹ方向に延びている。 As shown in FIG. 1, a plurality of gate electrodes 30, a plurality of insulating films 41, a plurality of source layers 24, and a plurality of base contact regions 25 are periodically arranged in the X direction. The gate electrode 30, the insulating film 41, the source layer 24, and the base contact region 25 are formed in a striped pattern extending in the Y direction. The base layer 23 shown in FIG. 2 also extends in the Y direction under the source layer 24 and the base contact region 25.

１つのゲート電極３０を含む図２に示す１つのユニットにおいて、ゲート電極３０は、一対のソース層２４（ベース層２３）の間に配置されている。絶縁膜４１は、ソース層２４（ベース層２３）とゲート電極３０との間に配置されている。 In one unit shown in FIG. 2, which includes one gate electrode 30, the gate electrode 30 is arranged between a pair of source layers 24 (base layer 23). The insulating film 41 is arranged between the source layer 24 (base layer 23) and the gate electrode 30.

図２に示すように、半導体層２０は、Ｎ＋形のドレイン層２１およびＮ形のドリフト層２２を含む第１半導体層と、Ｐ形のベース層（第２半導体層）２３と、Ｎ＋形のソース層（第３半導体層）２４と、Ｐ＋形のベースコンタクト領域２５とを有する。 As shown in FIG. 2, the semiconductor layer 20 includes a first semiconductor layer including an N + type drain layer 21 and an N type drift layer 22, a P-type base layer (second semiconductor layer) 23, and N +. It has a shaped source layer (third semiconductor layer) 24 and a P + shaped base contact region 25.

ドレイン層２１およびソース層２４のＮ形不純物濃度は、ドリフト層２２のＮ形不純物濃度よりも高い。ベースコンタクト領域２５のＰ形不純物濃度は、ベース層２３のＰ形不純物濃度よりも高い。 The concentration of N-type impurities in the drain layer 21 and the source layer 24 is higher than the concentration of N-type impurities in the drift layer 22. The concentration of P-type impurities in the base contact region 25 is higher than the concentration of P-type impurities in the base layer 23.

ドレイン層２１は、ドレイン電極１１上に設けられ、ドレイン電極１１に接している。ドレイン電極２１上に、ドリフト層２２が設けられている。ドリフト層２２上に、ベース層２３が設けられている。ベース層２３上に、ソース層２４が設けられている。ベース層２３において、ソース層２４が設けられていない領域の表面にベースコンタクト領域２５が設けられている。 The drain layer 21 is provided on the drain electrode 11 and is in contact with the drain electrode 11. A drift layer 22 is provided on the drain electrode 21. A base layer 23 is provided on the drift layer 22. A source layer 24 is provided on the base layer 23. In the base layer 23, the base contact region 25 is provided on the surface of the region where the source layer 24 is not provided.

ゲート電極３０は、ベース層２３の側面に対向している。ゲート電極３０と、ベース層２３の側面との間に、絶縁膜（ゲート絶縁膜）４１が設けられている。ゲート電極３０上に、層間絶縁膜４５が設けられている。 The gate electrode 30 faces the side surface of the base layer 23. An insulating film (gate insulating film) 41 is provided between the gate electrode 30 and the side surface of the base layer 23. An interlayer insulating film 45 is provided on the gate electrode 30.

その層間絶縁膜４５を覆うようにソース電極１２が設けられ、ソース電極１２はソース層２４およびベースコンタクト領域２５に接している。 A source electrode 12 is provided so as to cover the interlayer insulating film 45, and the source electrode 12 is in contact with the source layer 24 and the base contact region 25.

ゲート電極３０の下に、フィールドプレート電極５０が設けられている。図２に示す例では、ゲート電極３０とフィールドプレート電極５０との間に絶縁膜４２が設けられ、ゲート電極３０とフィールドプレート電極５０は互いに分離されている。 A field plate electrode 50 is provided below the gate electrode 30. In the example shown in FIG. 2, an insulating film 42 is provided between the gate electrode 30 and the field plate electrode 50, and the gate electrode 30 and the field plate electrode 50 are separated from each other.

フィールドプレート電極５０はドリフト層２２内に設けられ、フィールドプレート電極５０とドリフト層２２との間には絶縁膜４３が設けられている。フィールドプレート電極５０はドリフト層２２に接していない。絶縁膜４３はシリコン酸化膜である。 The field plate electrode 50 is provided in the drift layer 22, and an insulating film 43 is provided between the field plate electrode 50 and the drift layer 22. The field plate electrode 50 is not in contact with the drift layer 22. The insulating film 43 is a silicon oxide film.

フィールドプレート電極５０の幅は、縦方向（深さ方向）に一様ではなく、縦方向に段階的に変化している。フィールドプレート電極５０の幅は、ゲート電極３０側の上部５０ａからドレイン電極１１側の下部５０ｂに向かって段階的に小さくなっている。フィールドプレート電極５０の側壁は、縦方向に沿った階段状の段差をもつ。 The width of the field plate electrode 50 is not uniform in the vertical direction (depth direction), but changes stepwise in the vertical direction. The width of the field plate electrode 50 gradually decreases from the upper portion 50a on the gate electrode 30 side toward the lower portion 50b on the drain electrode 11 side. The side wall of the field plate electrode 50 has a stepped step along the vertical direction.

フィールドプレート電極５０は少なくとも２つの異なる幅をもつ。図２に示す例では、フィールドプレート電極５０は３つの異なる幅をもつ。すなわち、フィールドプレート電極５０は、上部５０ａと、下部５０ｂと、中間部５０ｃとを有する。 The field plate electrode 50 has at least two different widths. In the example shown in FIG. 2, the field plate electrode 50 has three different widths. That is, the field plate electrode 50 has an upper portion 50a, a lower portion 50b, and an intermediate portion 50c.

上部５０ａは下部５０ｂよりもゲート電極３０側に設けられ、下部５０ｂは上部５０ａよりもドレイン電極１１側に設けられ、下部５０ｂの幅は上部５０ａの幅よりも小さい。上部５０ａと下部５０ｂとの間に中間部５０ｃが設けられ、中間部５０ｃの幅は上部５０ａの幅よりも小さく、下部５０ｂの幅よりも大きい。上部５０ａと下部５０ｂとの間に、２つ以上の異なる幅をもつ２つ以上の中間部が設けられてもよい。 The upper portion 50a is provided on the gate electrode 30 side of the lower portion 50b, the lower portion 50b is provided on the drain electrode 11 side of the upper portion 50a, and the width of the lower portion 50b is smaller than the width of the upper portion 50a. An intermediate portion 50c is provided between the upper portion 50a and the lower portion 50b, and the width of the intermediate portion 50c is smaller than the width of the upper portion 50a and larger than the width of the lower portion 50b. Two or more intermediate portions having two or more different widths may be provided between the upper portion 50a and the lower portion 50b.

絶縁膜４３は、フィールドプレート電極５０の上部５０ａとドリフト層２２との間に設けられた第１部分４３ａと、フィールドプレート電極５０の下部５０ｂとドリフト層２２との間に設けられた第２部分４３ｂと、フィールドプレート電極５０の中間部５０ｃとドリフト層２２との間に設けられた中間部分４３ｃとを有する。 The insulating film 43 has a first portion 43a provided between the upper portion 50a of the field plate electrode 50 and the drift layer 22, and a second portion provided between the lower portion 50b of the field plate electrode 50 and the drift layer 22. It has 43b and an intermediate portion 43c provided between the intermediate portion 50c of the field plate electrode 50 and the drift layer 22.

絶縁膜４３の膜厚は、ゲート電極３０側の第１部分４３ａからドレイン電極１１側の第２部分４３ｂに向かって段階的に厚くなっている。第２部分４３ｂの膜厚Ｔｂは、第１部分４３ａの膜厚Ｔａよりも厚い。中間部分４３ｃの膜厚Ｔｃは、第１部分４３ａの膜厚Ｔａよりも厚く、第２部分４３ｂの膜厚Ｔｂよりも薄い。図２に示す例では、絶縁膜４３の側壁は、縦方向に沿った階段状の段差をもつ。 The film thickness of the insulating film 43 is gradually increased from the first portion 43a on the gate electrode 30 side toward the second portion 43b on the drain electrode 11 side. The film thickness Tb of the second portion 43b is thicker than the film thickness Ta of the first portion 43a. The film thickness Tc of the intermediate portion 43c is thicker than the film thickness Ta of the first portion 43a and thinner than the film thickness Tb of the second portion 43b. In the example shown in FIG. 2, the side wall of the insulating film 43 has a stepped step along the vertical direction.

図２には、絶縁膜４３の３段階の膜厚差変化を示すが、絶縁膜４３の膜厚差変化は少なくとも２段階の変化であればよい。また、絶縁膜４３は４段階以上の膜厚差変化をもっていてもよい。 FIG. 2 shows a three-step change in the film thickness of the insulating film 43, but the change in the film thickness of the insulating film 43 may be at least two steps. Further, the insulating film 43 may have a film thickness difference change of 4 steps or more.

ドリフト層２２は、第１領域２２ｃと、その第１領域２２ｃと絶縁膜４３の側壁との間に設けられた第２領域２２ａとを有する。第２領域２２ａは、絶縁膜４３の側壁に近接する領域において、絶縁膜４３の側壁に沿って設けられている。第２領域２２ａのＮ形不純物濃度は、第１領域２２ｃのＮ形不純物濃度よりも高い。 The drift layer 22 has a first region 22c and a second region 22a provided between the first region 22c and the side wall of the insulating film 43. The second region 22a is provided along the side wall of the insulating film 43 in a region close to the side wall of the insulating film 43. The concentration of N-type impurities in the second region 22a is higher than the concentration of N-type impurities in the first region 22c.

第２領域２２ａは、絶縁膜４３の側壁に沿った方向にＮ形不純物の濃度勾配をもつ。第２領域２２ａのＮ形不純物濃度は、絶縁膜４３の第１部分４３ａに近接する領域から、絶縁膜４３の第２部分４３ｂに近接する領域に向かって段階的または連続的に高くなっている。 The second region 22a has a concentration gradient of N-type impurities in the direction along the side wall of the insulating film 43. The concentration of N-type impurities in the second region 22a gradually or continuously increases from the region close to the first portion 43a of the insulating film 43 toward the region close to the second portion 43b of the insulating film 43. ..

第２領域２２ａにおいて絶縁膜４３の第１部分４３ａに近接する領域のＮ形不純物濃度は、第２領域２２ａにおいて絶縁膜４３の第２部分４３ｂに近接する領域のＮ形不純物濃度よりも低い。 The concentration of N-type impurities in the region of the second region 22a close to the first portion 43a of the insulating film 43 is lower than the concentration of N-type impurities in the region of the second region 22a close to the second portion 43b of the insulating film 43.

ドリフト層２２は、さらに、絶縁膜４３のボトムに近接する領域に設けられ、第１領域２２ｃよりもＮ形不純物濃度が高い第３領域２２ｂを有する。第３領域２２ｂのＮ形不純物濃度は、第２領域２２ａにおいて絶縁膜４３の第１部分４３ａに近接する領域のＮ形不純物濃度よりも高い。 The drift layer 22 is further provided in a region close to the bottom of the insulating film 43, and has a third region 22b having a higher N-type impurity concentration than the first region 22c. The concentration of N-type impurities in the third region 22b is higher than the concentration of N-type impurities in the region close to the first portion 43a of the insulating film 43 in the second region 22a.

以上説明した半導体装置において、ドレイン電極１１とソース電極１２との間に電位差が与えられる。ドレイン電極１１に印加される電位は、ソース電極１２に印加される電位よりも高い。フィールドプレート電極５０はソース電極１２と電気的に接続され、フィールドプレート電極５０にはソース電極１２に与えられる電位と同じ電位が与えられる。 In the semiconductor device described above, a potential difference is given between the drain electrode 11 and the source electrode 12. The potential applied to the drain electrode 11 is higher than the potential applied to the source electrode 12. The field plate electrode 50 is electrically connected to the source electrode 12, and the field plate electrode 50 is given the same potential as the potential given to the source electrode 12.

半導体装置のオン動作時には、ゲート電極３０にしきい値電圧以上の電位が与えられ、ベース層２３におけるゲート電極３０に対向する領域に反転層（Ｎ形のチャネル）が形成される。そして、ドレイン層２１、ドリフト層２２、チャネル、およびソース層２４を通じて、ドレイン電極１１とソース電極１２との間を電流が流れる。 When the semiconductor device is on, a potential equal to or higher than the threshold voltage is applied to the gate electrode 30, and an inversion layer (N-type channel) is formed in a region of the base layer 23 facing the gate electrode 30. Then, a current flows between the drain electrode 11 and the source electrode 12 through the drain layer 21, the drift layer 22, the channel, and the source layer 24.

ゲート電極３０の電位がしきい値電圧より低い電位になると、チャネルがカットオフされ、半導体装置はオフ状態となる。このオフ状態のとき、ベース層２３とドリフト層２２とのＰＮ接合から、および絶縁膜４３とドリフト層２２との境界から、ドリフト層２２中に空乏層が広がり、半導体装置の耐圧が保持される。 When the potential of the gate electrode 30 becomes lower than the threshold voltage, the channel is cut off and the semiconductor device is turned off. In this off state, the depletion layer spreads in the drift layer 22 from the PN junction between the base layer 23 and the drift layer 22 and from the boundary between the insulating film 43 and the drift layer 22, and the withstand voltage of the semiconductor device is maintained. ..

フィールドプレート電極５０は、ドリフト層２２における縦方向の電位変化を緩やかにする。そして、フィールドプレート電極５０とドリフト層２２との間に設けられた絶縁膜４３の膜厚が、ソース電極１２側からドレイン電極１１側に向かって段階的に厚くなっているため、ドリフト層２２内における縦方向の電界強度分布を平坦に近い分布にすることができる。これは、ドリフト層２２内の縦方向の電界強度の積分値を大きくし、耐圧を向上させる。 The field plate electrode 50 moderates the change in potential in the vertical direction in the drift layer 22. Since the film thickness of the insulating film 43 provided between the field plate electrode 50 and the drift layer 22 gradually increases from the source electrode 12 side to the drain electrode 11 side, the inside of the drift layer 22 The electric field strength distribution in the vertical direction in the above can be made a distribution close to flat. This increases the integral value of the electric field strength in the vertical direction in the drift layer 22 and improves the withstand voltage.

また、ドリフト層２２において、絶縁膜４３の側壁に近接した領域（第２領域）２２ａのＮ形不純物濃度は、他の領域（第１領域）２２ｃのＮ形不純物濃度よりも高い。したがって、ドリフト層２２中に、縦方向に沿った抵抗が低い電流経路が形成され、オン抵抗を低減できる。 Further, in the drift layer 22, the concentration of N-type impurities in the region (second region) 22a close to the side wall of the insulating film 43 is higher than the concentration of N-type impurities in the other region (first region) 22c. Therefore, a current path having a low resistance along the vertical direction is formed in the drift layer 22, and the on-resistance can be reduced.

また、絶縁膜４３のボトムに近接した領域（第３領域）２２ｂのＮ形不純物濃度も、第１領域２２ｃのＮ形不純物濃度よりも高く、その第３領域２２ｂの一部は第２領域２２ａの下にも広がっている。そのため、第２領域２２ａとドレイン層２１との間の領域も低抵抗化できる。 Further, the concentration of N-type impurities in the region (third region) 22b close to the bottom of the insulating film 43 is also higher than the concentration of N-type impurities in the first region 22c, and a part of the third region 22b is in the second region 22a. It also extends underneath. Therefore, the resistance of the region between the second region 22a and the drain layer 21 can also be reduced.

実施形態の半導体装置によれば、ドリフト層２２の一部領域の不純物濃度を高くしつつも、前述した膜厚差をもつ絶縁膜４３による効果で耐圧の低下を抑制できる。すなわち、実施形態によれば、低オン抵抗と高耐圧とを両立した半導体装置を提供できる。 According to the semiconductor device of the embodiment, it is possible to suppress a decrease in withstand voltage due to the effect of the insulating film 43 having the above-mentioned film thickness difference while increasing the impurity concentration in a part of the drift layer 22. That is, according to the embodiment, it is possible to provide a semiconductor device having both low on-resistance and high withstand voltage.

次に、図３（ａ）〜図１１を参照して、実施形態の半導体装置の製造方法について説明する。 Next, a method of manufacturing the semiconductor device according to the embodiment will be described with reference to FIGS. 3A to 11.

図３（ａ）に示すように、ドリフト層２２にトレンチＴ１が形成される。例えば、ドリフト層２２の表面に形成したマスク層９１を用いたＲＩＥ（Reactive Ion Etching）法によりトレンチＴ１が形成される。 As shown in FIG. 3A, a trench T1 is formed in the drift layer 22. For example, the trench T1 is formed by the RIE (Reactive Ion Etching) method using the mask layer 91 formed on the surface of the drift layer 22.

そのトレンチＴ１内には、図３（ｂ）に示すように、側壁膜７１が形成される。側壁膜７１は、例えばシリコン酸化膜である。側壁膜７１は、マスク層９１の上面、トレンチＴ１の側壁およびボトムに沿ってコンフォーマルに形成される。 As shown in FIG. 3B, a side wall film 71 is formed in the trench T1. The side wall film 71 is, for example, a silicon oxide film. The side wall film 71 is conformally formed along the upper surface of the mask layer 91, the side wall and the bottom of the trench T1.

次に、図４（ａ）に示すように、トレンチＴ１のボトムに形成された側壁膜７１を例えばＲＩＥ法で除去する。マスク層９１上の側壁膜７１も除去される。トレンチＴ１のボトムにドリフト層２２が露出する。 Next, as shown in FIG. 4A, the side wall film 71 formed on the bottom of the trench T1 is removed by, for example, the RIE method. The side wall film 71 on the mask layer 91 is also removed. The drift layer 22 is exposed at the bottom of the trench T1.

次に、図４（ｂ）に示すように、トレンチＴ１の下にトレンチＴ２を形成する。マスク層９１および側壁膜７１をマスクにしたＲＩＥ法でトレンチＴ２が形成される。トレンチＴ２の幅は、トレンチＴ１の幅よりも小さい。 Next, as shown in FIG. 4B, the trench T2 is formed under the trench T1. The trench T2 is formed by the RIE method using the mask layer 91 and the side wall film 71 as masks. The width of the trench T2 is smaller than the width of the trench T1.

次に、図５（ａ）に示すように、マスク層９１の上面、およびトレンチＴ１内の側壁膜７１の側面にストッパー膜７２を形成する。その後、トレンチＴ１内およびトレンチＴ２内に側壁膜７３を形成する。側壁膜７３は、マスク層９１の上面、側壁膜７１の側面、トレンチＴ２の側壁およびボトムに沿ってコンフォーマルに形成される。例えば、ストッパー膜７２はシリコン窒化膜であり、側壁膜７３はシリコン酸化膜である。マスク層９１と側壁膜７３との間、および側壁膜７１と側壁膜７３との間に、ストッパー膜７２が形成されている。 Next, as shown in FIG. 5A, a stopper film 72 is formed on the upper surface of the mask layer 91 and the side surface of the side wall film 71 in the trench T1. After that, the side wall film 73 is formed in the trench T1 and in the trench T2. The side wall film 73 is conformally formed along the upper surface of the mask layer 91, the side surface of the side wall film 71, and the side wall and bottom of the trench T2. For example, the stopper film 72 is a silicon nitride film, and the side wall film 73 is a silicon oxide film. A stopper film 72 is formed between the mask layer 91 and the side wall film 73, and between the side wall film 71 and the side wall film 73.

次に、トレンチＴ２のボトムに形成された側壁膜７３を例えばＲＩＥ法で除去した後、図５（ｂ）に示すように、トレンチＴ２の下にトレンチＴ３を形成する。トレンチＴ２のボトムの側壁膜７３を除去するとき、マスク層９１上の側壁膜７３も除去される。このとき、マスク層９１上のストッパー膜７２はエッチングストッパーとして機能する。 Next, the side wall film 73 formed on the bottom of the trench T2 is removed by, for example, the RIE method, and then the trench T3 is formed under the trench T2 as shown in FIG. 5 (b). When the side wall film 73 on the bottom of the trench T2 is removed, the side wall film 73 on the mask layer 91 is also removed. At this time, the stopper film 72 on the mask layer 91 functions as an etching stopper.

トレンチＴ３は、ストッパー膜７２および側壁膜７３をマスクにしたＲＩＥ法で形成される。トレンチＴ３の幅は、トレンチＴ１の幅およびトレンチＴ２の幅よりも小さい。 The trench T3 is formed by the RIE method using the stopper film 72 and the side wall film 73 as masks. The width of the trench T3 is smaller than the width of the trench T1 and the width of the trench T2.

次に、図６（ａ）および図１０に示すように、トレンチＴ３の側壁にＮ形不純物として例えばヒ素またはリンがイオン注入法により注入される。不純物は、半導体層（ドレイン層２１、ドリフト層２２）の主面に対して傾斜した方向からトレンチＴ３の側壁に注入される。ドリフト層２２におけるトレンチＴ３の側壁に近接する領域に、イオン注入前のドリフト層２２のＮ形不純物濃度よりもＮ形不純物濃度が高い領域２２ａが形成される。トレンチＴ３のボトムにも不純物は注入される。 Next, as shown in FIGS. 6A and 10, for example, arsenic or phosphorus is implanted into the side wall of the trench T3 as an N-type impurity by an ion implantation method. The impurities are injected into the side wall of the trench T3 from a direction inclined with respect to the main surface of the semiconductor layer (drain layer 21, drift layer 22). In the region of the drift layer 22 close to the side wall of the trench T3, a region 22a having a higher N-type impurity concentration than the N-type impurity concentration of the drift layer 22 before ion implantation is formed. The impurities are also injected into the bottom of the trench T3.

トレンチＴ３の幅をＷ１、トレンチＴ１〜Ｔ３のトータルの深さをｄ１とすると、トレンチＴ３の側壁に対する不純物の入射角度θは、θ＝ｔａｎ−１（ｄ１／Ｗ１）で規定することができる。 Assuming that the width of the trench T3 is W1 and the total depth of the trenches T1 to T3 is d1, the incident angle θ of impurities with respect to the side wall of the trench T3 can be defined by θ = tan -1 (d1 / W1).

このとき、トレンチＴ１の側壁は側壁膜７１および側壁膜７３で覆われ、トレンチＴ２の側壁は側壁膜７３で覆われているため、トレンチＴ１の側壁およびトレンチＴ２の側壁には不純物は注入されない。 At this time, since the side wall of the trench T1 is covered with the side wall film 71 and the side wall film 73, and the side wall of the trench T2 is covered with the side wall film 73, impurities are not injected into the side wall of the trench T1 and the side wall of the trench T2.

次に、側壁膜７３を除去する。側壁膜７３が除去され、図６（ｂ）および図１１に示すように、トレンチＴ２の側壁が露出する。 Next, the side wall film 73 is removed. The side wall film 73 is removed, exposing the side walls of the trench T2, as shown in FIGS. 6 (b) and 11.

そして、トレンチＴ２の側壁にＮ形不純物として例えばヒ素またはリンがイオン注入法により注入される。このときも、不純物は、半導体層（ドレイン層２１、ドリフト層２２）の主面に対して傾斜した方向からトレンチＴ２の側壁に注入される。ドリフト層２２におけるトレンチＴ２の側壁に近接する領域に、イオン注入前のドリフト層２２のＮ形不純物濃度よりもＮ形不純物濃度が高い領域２２ａが形成される。 Then, for example, arsenic or phosphorus is implanted into the side wall of the trench T2 as an N-type impurity by an ion implantation method. Also at this time, the impurities are injected into the side wall of the trench T2 from the direction inclined with respect to the main surface of the semiconductor layer (drain layer 21, drift layer 22). In the region of the drift layer 22 close to the side wall of the trench T2, a region 22a having a higher N-type impurity concentration than the N-type impurity concentration of the drift layer 22 before ion implantation is formed.

このとき、トレンチＴ１の側壁は側壁膜７１および側壁膜７３で覆われ、トレンチＴ１の側壁には不純物は注入されない。 At this time, the side wall of the trench T1 is covered with the side wall film 71 and the side wall film 73, and impurities are not injected into the side wall of the trench T1.

トレンチＴ３の幅をＷ１、トレンチＴ２の側壁とトレンチＴ３の側壁との間の幅をＷ２、トレンチＴ１〜Ｔ３のトータルの深さをｄ１、トレンチＴ３の深さをｄ２とすると、トレンチＴ２の側壁に対する不純物の入射角度θ２は、θ２＝ｔａｎ−１（ｄ１−ｄ２／Ｗ１＋Ｗ２×２）で規定することができる。 Assuming that the width of the trench T3 is W1, the width between the side wall of the trench T2 and the side wall of the trench T3 is W2, the total depth of the trenches T1 to T3 is d1, and the depth of the trench T3 is d2, the side wall of the trench T2 The incident angle θ2 of the impurities with respect to the above can be specified by θ2 = tan -1 (d1-d2 / W1 + W2 × 2).

また、トレンチＴ２の側壁とトレンチＴ３の側壁に同時に不純物を注入することもできる。このときの不純物の入射角度θ１は、θ１＝ｔａｎ−１（ｄ１／Ｗ１＋Ｗ２）で規定することができる。 Impurities can also be injected into the side wall of the trench T2 and the side wall of the trench T3 at the same time. The incident angle θ1 of the impurities at this time can be defined by θ1 = tan -1 (d1 / W1 + W2).

いずれにしても、図１０および図１１に示す工程を経て、ドリフト層２２におけるトレンチＴ３の側壁に近接する領域のＮ形不純物濃度が、ドリフト層２２におけるトレンチＴ２の側壁に近接する領域のＮ形不純物濃度よりも高くなるようにする。イオン注入後、注入された不純物を拡散させる熱処理が行われる。 In any case, through the steps shown in FIGS. 10 and 11, the concentration of N-type impurities in the region of the drift layer 22 close to the side wall of the trench T3 is the N-type of the region of the drift layer 22 close to the side wall of the trench T2. Try to be higher than the impurity concentration. After ion implantation, heat treatment is performed to diffuse the implanted impurities.

その後、図６（ｂ）に示す状態で残っている側壁膜７１、ストッパー膜７２、およびマスク層９１を除去する。それら膜が除去され、図７（ａ）に示すように、トレンチＴ１〜Ｔ３が段を形成して深さ方向につながったトレンチＴが表れる。 After that, the side wall film 71, the stopper film 72, and the mask layer 91 remaining in the state shown in FIG. 6B are removed. These films are removed, and as shown in FIG. 7A, a trench T in which trenches T1 to T3 form a step and are connected in the depth direction appears.

トレンチＴの幅は深さ方向に向かって段階的に小さくなり、トレンチＴの側壁は深さ方向に沿った階段状の段差をもつ。 The width of the trench T gradually decreases in the depth direction, and the side wall of the trench T has a stepped step along the depth direction.

図７（ａ）に示す例では、３段階の幅をもつトレンチＴを示すが、トレンチＴは少なくとも２段階の幅をもっていればよい。 In the example shown in FIG. 7A, the trench T having a width of three steps is shown, but the trench T may have a width of at least two steps.

３段階の幅をもつトレンチＴの場合、相対的に下側のトレンチＴ３の側壁に対して図６（ａ）に示す１回目の傾斜イオン注入を行い、この後、相対的に上側のトレンチＴ２の側壁に対して図６（ｂ）に示す２回目の傾斜イオン注入を行う。 In the case of the trench T having a width of three stages, the first inclined ion implantation shown in FIG. 6A is performed on the side wall of the trench T3 on the relatively lower side, and then the trench T2 on the relatively upper side is implanted. The second inclined ion implantation shown in FIG. 6 (b) is performed on the side wall of the.

次に、トレンチＴの側壁に露出するシリコン層であるドリフト層２２に対して熱酸化反応を進行させ、図７（ｂ）に示すように、トレンチＴの側壁にシリコン酸化膜である絶縁膜４３を形成する。トレンチＴのボトム、およびドリフト層２２の上面にも絶縁膜４３が形成される。 Next, a thermal oxidation reaction is allowed to proceed with the drift layer 22 which is a silicon layer exposed on the side wall of the trench T, and as shown in FIG. 7B, the insulating film 43 which is a silicon oxide film is formed on the side wall of the trench T. To form. An insulating film 43 is also formed on the bottom of the trench T and the upper surface of the drift layer 22.

シリコン層の熱酸化速度はシリコン層の不純物濃度に依存する。不純物濃度が高い部分ほど熱酸化速度が速くなる。熱酸化処理時間が同じ条件において、不純物濃度が高い部分ほどシリコン酸化膜の膜厚が厚くなる。 The thermal oxidation rate of the silicon layer depends on the impurity concentration of the silicon layer. The higher the impurity concentration, the faster the thermal oxidation rate. Under the same conditions of thermal oxidation treatment time, the higher the impurity concentration, the thicker the silicon oxide film.

ドリフト層２２においてトレンチＴの側壁に近接する領域には、前述したイオン注入により、深さ方向にＮ形不純物の濃度勾配が形成されている。ドリフト層２２においてトレンチＴ３の側壁に近接する領域のＮ形不純物濃度は、ドリフト層２２においてトレンチＴ２の側壁に近接する領域のＮ形不純物濃度よりも高く、ドリフト層２２においてトレンチＴ２の側壁に近接する領域のＮ形不純物濃度は、ドリフト層２２においてトレンチＴ１の側壁に近接する領域のＮ形不純物濃度よりも高い。 In the region of the drift layer 22 close to the side wall of the trench T, a concentration gradient of N-type impurities is formed in the depth direction by the ion implantation described above. In the drift layer 22, the concentration of N-type impurities in the region close to the side wall of the trench T3 is higher than the concentration of N-type impurities in the region close to the side wall of the trench T2 in the drift layer 22, and in the drift layer 22 is close to the side wall of the trench T2. The concentration of N-type impurities in the region is higher than the concentration of N-type impurities in the region of the drift layer 22 close to the side wall of the trench T1.

したがって、トレンチＴ３の側壁に成長する絶縁膜（シリコン酸化膜）４３の第２部分４３ｂの膜厚は、トレンチＴ２の側壁に成長する絶縁膜４３の中間部分４３ｃの膜厚よりも厚く、トレンチＴ２の側壁に成長する絶縁膜４３の中間部分４３ｃの膜厚は、トレンチＴ１の側壁に成長する絶縁膜４３の第１部分４３ａの膜厚よりも厚くなる。絶縁膜４３の膜厚は、トレンチＴの深さ方向に向かって段階的に厚くなる。 Therefore, the film thickness of the second portion 43b of the insulating film (silicon oxide film) 43 that grows on the side wall of the trench T3 is thicker than the film thickness of the intermediate portion 43c of the insulating film 43 that grows on the side wall of the trench T2. The film thickness of the intermediate portion 43c of the insulating film 43 growing on the side wall of the trench T1 is thicker than the film thickness of the first portion 43a of the insulating film 43 growing on the side wall of the trench T1. The film thickness of the insulating film 43 gradually increases in the depth direction of the trench T.

図１２は、増速酸化率の不純物ドーズ量依存性のシミュレーション結果を示すグラフである。 FIG. 12 is a graph showing the simulation results of the impurity dose amount dependence of the accelerated oxidation rate.

縦軸は、絶縁膜４３の第１部分４３ａの成長速度を基準にした相対的な増速酸化率（％）を表す。 The vertical axis represents the relative accelerated oxidation rate (%) based on the growth rate of the first portion 43a of the insulating film 43.

横軸は、図６（ｂ）および図１１に示す２回目の不純物ドーズ量２ｎｄ−Ｑｄ（個／ｃｍ２）を表す。グラフ中に、図６（ａ）および図１０に示す１回目の不純物ドーズ量１ｓｔ−Ｑｄ（個／ｃｍ２）をプロットしている。１回目および２回目とも、加速電圧１０ｋｅＶでヒ素を注入した条件としている。 The horizontal axis represents the second impurity dose amount 2nd-Qd (pieces / cm 2 ) shown in FIGS. 6 (b) and 11. In the graph, the first impurity dose amount 1st-Qd (pieces / cm 2 ) shown in FIGS. 6 (a) and 10 is plotted. Both the first and second times are under the condition that arsenic is injected at an acceleration voltage of 10 keV.

図１２のシミュレーション結果より、トレンチＴ２の側壁に対する２ｎｄ−Ｑｄを１×１０１５（個／ｃｍ２）、トレンチＴ３の側壁に対する２ｎｄ−Ｑｄを１×１０１５（個／ｃｍ２）および１ｓｔ−Ｑｄを５×１０１５（個／ｃｍ２）とした場合には、絶縁膜４３の中間部分４３ｃの膜厚Ｔｃは第１部分４３ａの膜厚Ｔａの１．８倍に、第２部分４３ｂの膜厚Ｔｂは第１部分４３ａの膜厚Ｔａの２．３８倍にすることができる。 From the simulation results of FIG. 12, 2nd-Qd for the side wall of the trench T2 is 1 × 10 15 (pieces / cm 2 ), 2nd-Qd for the side wall of the trench T3 is 1 × 10 15 (pieces / cm 2 ) and 1st-Qd. When is 5 × 10 15 (pieces / cm 2 ), the film thickness Tc of the intermediate portion 43c of the insulating film 43 is 1.8 times the film thickness Ta of the first portion 43a, and the film thickness of the second portion 43b. The thickness Tb can be 2.38 times the film thickness Ta of the first portion 43a.

絶縁膜４３を形成した後、絶縁膜４３の内側に残っている空洞に電極材として例えば多結晶シリコンを埋め込む。その多結晶シリコンを例えばエッチバックで後退させ、図８（ａ）に示すように、トレンチＴ内に段付きのフィールドプレート電極５０が形成される。 After forming the insulating film 43, for example, polycrystalline silicon is embedded as an electrode material in the cavity remaining inside the insulating film 43. The polycrystalline silicon is retracted by, for example, etch back, and a stepped field plate electrode 50 is formed in the trench T as shown in FIG. 8 (a).

そのフィールドプレート電極５０の上面上に、図８（ｂ）に示すように絶縁膜４２を形成した後、その絶縁膜４２上のトレンチＴ内に、例えば多結晶シリコンのゲート電極３０を形成する。 An insulating film 42 is formed on the upper surface of the field plate electrode 50 as shown in FIG. 8B, and then, for example, a polycrystalline silicon gate electrode 30 is formed in the trench T on the insulating film 42.

その後、ドリフト層２２の表面にＰ形不純物を注入し、図９（ａ）に示すように、ドリフト層２２の表面にＰ形のベース層２３を形成する。さらに、そのベース層２３の表面にＮ形不純物を注入し、ベース層２３上にＮ形のソース層２４を形成する。 After that, P-type impurities are injected into the surface of the drift layer 22, and as shown in FIG. 9A, a P-type base layer 23 is formed on the surface of the drift layer 22. Further, an N-type impurity is injected into the surface of the base layer 23 to form an N-type source layer 24 on the base layer 23.

その後、図９（ｂ）に示すように、ゲート電極３０上およびソース層２４上に層間絶縁膜４５を形成する。層間絶縁膜４５、ソース層２４、およびベース層２３にはコンタクトトレンチ８１が形成される。コンタクトトレンチ８１は、層間絶縁膜４５およびソース層２４を貫通してベース層２３の途中まで達する。 After that, as shown in FIG. 9B, an interlayer insulating film 45 is formed on the gate electrode 30 and the source layer 24. A contact trench 81 is formed in the interlayer insulating film 45, the source layer 24, and the base layer 23. The contact trench 81 penetrates the interlayer insulating film 45 and the source layer 24 and reaches the middle of the base layer 23.

コンタクトトレンチ８１のボトムのベース層２３の表面に、図２に示すベースコンタクト２５を形成した後、コンタクトトレンチ８１内にソース電極１２を形成する。ソース電極１２は、ソース層２４の側面に接する。また、層間絶縁膜４５を平面方向に後退させて、ソース層２４の上面にソース電極１２が接するようにすることもできる。 After forming the base contact 25 shown in FIG. 2 on the surface of the base layer 23 at the bottom of the contact trench 81, the source electrode 12 is formed in the contact trench 81. The source electrode 12 is in contact with the side surface of the source layer 24. Further, the interlayer insulating film 45 can be retracted in the plane direction so that the source electrode 12 comes into contact with the upper surface of the source layer 24.

以上説明した実施形態の半導体装置の製造方法によれば、トレンチＴ２、Ｔ３の側壁に斜め方向から不純物を注入するとき、ベース層２３やソース層２４の形成領域には不純物が注入されない。そのため、チャネル抵抗やしきい値電圧の制御性に影響を与えない。 According to the method for manufacturing a semiconductor device of the above-described embodiment, when impurities are injected into the side walls of the trenches T2 and T3 from an oblique direction, the impurities are not injected into the formation regions of the base layer 23 and the source layer 24. Therefore, it does not affect the controllability of the channel resistance and the threshold voltage.

図１３は、実施形態の半導体装置の他の例を示す模式断面図である。 FIG. 13 is a schematic cross-sectional view showing another example of the semiconductor device of the embodiment.

絶縁膜４３を形成するときの熱酸化条件の制御により、図１３に示すように、絶縁膜４３の側壁に段差が形成されないようにすることもできる。 By controlling the thermal oxidation conditions when the insulating film 43 is formed, as shown in FIG. 13, it is possible to prevent a step from being formed on the side wall of the insulating film 43.

図１４は、実施形態の半導体装置のさらに他の例を示す模式断面図である。 FIG. 14 is a schematic cross-sectional view showing still another example of the semiconductor device of the embodiment.

図１４に示す例では、フィールドプレート電極５０は、ゲート電極３０と同じ材料（例えば多結晶シリコン）で一体に設けられている。したがって、フィールドプレート電極５０には、ゲート電極３０と同じ電位（ゲート電位）が与えられる。 In the example shown in FIG. 14, the field plate electrode 50 is integrally provided with the same material as the gate electrode 30 (for example, polycrystalline silicon). Therefore, the field plate electrode 50 is given the same potential (gate potential) as the gate electrode 30.

図１５（ａ）〜（ｃ）は、図１４に示す半導体装置の製造方法を示す模式断面図である。 15 (a) to 15 (c) are schematic cross-sectional views showing a method of manufacturing the semiconductor device shown in FIG.

図７（ｂ）に示す工程まで前述した実施形態と同様に進めた後、図１５（ａ）に示すように、トレンチＴ内に、フィールドプレート電極５０およびゲート電極３０となる電極材を埋め込む。電極材の上面は、ドリフト層２２の表面近くに位置させる。 After proceeding to the step shown in FIG. 7 (b) in the same manner as in the above-described embodiment, the electrode materials to be the field plate electrode 50 and the gate electrode 30 are embedded in the trench T as shown in FIG. 15 (a). The upper surface of the electrode material is located near the surface of the drift layer 22.

その後、ドリフト層２２の表面にＰ形不純物を注入し、図１５（ｂ）に示すように、ドリフト層２２の表面にＰ形のベース層２３を形成する。さらに、そのベース層２３の表面にＮ形不純物を注入し、ベース層２３上にＮ形のソース層２４を形成する。 After that, P-type impurities are injected into the surface of the drift layer 22, and as shown in FIG. 15B, a P-type base layer 23 is formed on the surface of the drift layer 22. Further, an N-type impurity is injected into the surface of the base layer 23 to form an N-type source layer 24 on the base layer 23.

その後、図１５（ｃ）に示すようにコンタクトトレンチ８１を形成し、図１４に示すベースコンタクト領域２５およびソース電極１２の形成が続けられる。 After that, the contact trench 81 is formed as shown in FIG. 15 (c), and the formation of the base contact region 25 and the source electrode 12 shown in FIG. 14 is continued.

以上説明した実施形態では、ＭＯＳＦＥＴ構造の半導体装置を例示したが、ＩＧＢＴ（Insulated Gate Bipolar Transistor）構造の半導体装置であってもよい。ＩＧＢＴ構造の半導体装置は、例えば、図２、１３、１４における電極１１とＮ＋形の層２１との間にＰ＋形の層を備える。 In the embodiment described above, a semiconductor device having a MOSFET structure has been exemplified, but a semiconductor device having an IGBT (Insulated Gate Bipolar Transistor) structure may be used. The semiconductor device having an IGBT structure includes, for example, a P + -shaped layer between the electrode 11 and the N + -shaped layer 21 in FIGS. 2, 13 and 14.

実施形態の半導体装置によれば、前記フィールドプレート電極は、前記第２電極と電気的に接続されている。 According to the semiconductor device of the embodiment, the field plate electrode is electrically connected to the second electrode.

実施形態の半導体装置によれば、前記フィールドプレート電極は、前記ゲート電極と一体に設けられている。 According to the semiconductor device of the embodiment, the field plate electrode is provided integrally with the gate electrode.

実施形態の半導体装置によれば、前記第２絶縁膜はシリコン酸化膜である。 According to the semiconductor device of the embodiment, the second insulating film is a silicon oxide film.

実施形態の半導体装置の製造方法によれば、前記トレンチの前記側壁に前記段差を形成する工程は、上側トレンチを形成する工程と、前記上側トレンチの側壁に第１側壁膜を形成する工程と、前記第１側壁膜をマスクにした異方性エッチングにより、前記上側トレンチの下に前記上側トレンチよりも幅が小さい下側トレンチを形成する工程と、を有する。 According to the method for manufacturing a semiconductor device of the embodiment, the steps of forming the step on the side wall of the trench include a step of forming an upper trench and a step of forming a first side wall film on the side wall of the upper trench. It comprises a step of forming a lower trench having a width smaller than that of the upper trench under the upper trench by anisotropic etching using the first side wall film as a mask.

実施形態の半導体装置の製造方法によれば、前記不純物を前記半導体層に注入する工程は、前記上側トレンチの前記側壁を前記第１側壁膜で覆った状態で、前記半導体層における前記下側トレンチの側壁に近接する領域に不純物を注入する工程と、前記第１側壁膜を除去した後、前記半導体層における前記上側トレンチの前記側壁に近接する領域に不純物を注入する工程と、を有する。 According to the method for manufacturing a semiconductor device of the embodiment, in the step of injecting the impurities into the semiconductor layer, the lower trench in the semiconductor layer is covered with the first side wall film of the upper trench. It includes a step of injecting impurities into a region close to the side wall of the semiconductor layer, and a step of injecting impurities into a region of the semiconductor layer close to the side wall of the upper trench after removing the first side wall film.

実施形態の半導体装置の製造方法によれば、前記第１側壁膜を除去した後、前記半導体層における前記下側トレンチの前記側壁に近接する前記領域にも不純物を注入する。 According to the method for manufacturing a semiconductor device of the embodiment, after removing the first side wall film, impurities are also injected into the region of the semiconductor layer close to the side wall of the lower trench.

実施形態の半導体装置の製造方法によれば、前記絶縁膜を形成した後、第１導電形の前記半導体層の表面に、第２導電形の半導体層を形成する工程と、前記第２導電形の半導体層の表面に、第１導電形の半導体層を形成する工程と、をさらに備えている。 According to the method for manufacturing a semiconductor device of the embodiment, a step of forming a second conductive semiconductor layer on the surface of the first conductive semiconductor layer after forming the insulating film, and a second conductive type semiconductor layer. A step of forming a first conductive semiconductor layer on the surface of the semiconductor layer of the above is further provided.

本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。 Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

１１…ドレイン電極、１２…ソース電極、２０…半導体層、２１…ドレイン層、２２…ドリフト層、２３…ベース層、２４…ソース層、２５…ベースコンタクト領域、３０…ゲート電極、４１〜４３…絶縁膜、４５…層間絶縁膜、５０…フィールドプレート電極 11 ... Drain electrode, 12 ... Source electrode, 20 ... Semiconductor layer, 21 ... Drain layer, 22 ... Drift layer, 23 ... Base layer, 24 ... Source layer, 25 ... Base contact region, 30 ... Gate electrode, 41-43 ... Insulating film, 45 ... interlayer insulating film, 50 ... field plate electrode

Claims (4)

第１電極と、
前記第１電極上に設けられた第１導電形の第１半導体層と、
前記第１半導体層上に設けられた第２導電形の第２半導体層と、
前記第２半導体層上に設けられた第１導電形の第３半導体層と、
前記第３半導体層に接する第２電極と、
前記第３半導体層の側面に対向するゲート電極と、
前記第３半導体層の前記側面と前記ゲート電極との間に設けられた第１絶縁膜と、
前記ゲート電極の下において前記第１半導体層に形成され、前記第１電極に向かうにつれて段階的に幅が小さくなるトレンチ内に設けられたフィールドプレート電極であって、前記ゲート電極側に設けられた上部と、前記上部よりも前記第１電極側に設けられ、前記上部よりも幅が小さい下部と、を有するフィールドプレート電極と、
前記第１半導体層と前記フィールドプレート電極との間に設けられた第２絶縁膜であって、前記フィールドプレート電極の前記上部と前記第１半導体層との間に設けられた第１部分と、前記フィールドプレート電極の前記下部と前記第１半導体層との間に設けられ、前記第１部分よりも膜厚が厚い第２部分と、を有する第２絶縁膜と、
を備え、
前記第２絶縁膜における前記第１半導体層に接する側壁は、前記第１電極と前記第２電極とを結ぶ方向に沿った階段状の段差をもち、
前記第１半導体層は、
第１領域と、
前記第１領域と前記第２絶縁膜の前記側壁との間における前記第２絶縁膜の前記側壁に近接する領域に設けられ、前記第１領域よりも第１導電形不純物濃度が高い第２領域と、
を有し、
前記第２領域における前記第２絶縁膜の前記第１部分に近接する領域の第１導電形不純物濃度は、前記第１領域の第１導電形不純物濃度よりも高く、前記第２領域における前記第２絶縁膜の前記第２部分に近接する領域の第１導電形不純物濃度よりも低い半導体装置。 With the first electrode
The first conductive type first semiconductor layer provided on the first electrode and
A second conductive type second semiconductor layer provided on the first semiconductor layer,
The first conductive type third semiconductor layer provided on the second semiconductor layer and
The second electrode in contact with the third semiconductor layer and
A gate electrode facing the side surface of the third semiconductor layer and
A first insulating film provided between the side surface of the third semiconductor layer and the gate electrode, and
Formed in Oite the first semiconductor layer under the gate electrode, the stepwise width toward the first electrode is a field plate electrode provided in the trench becomes smaller, provided on the gate electrode side A field plate electrode having an upper portion and a lower portion provided on the first electrode side of the upper portion and having a width smaller than that of the upper portion.
A second insulating film provided between the first semiconductor layer and the field plate electrode, the first portion provided between the upper portion of the field plate electrode and the first semiconductor layer, and A second insulating film provided between the lower portion of the field plate electrode and the first semiconductor layer and having a second portion having a film thickness thicker than that of the first portion.
With
The side wall of the second insulating film in contact with the first semiconductor layer has a stepped step along the direction connecting the first electrode and the second electrode.
The first semiconductor layer is
The first area and
Wherein provided in a region adjacent to the sidewall of the second insulating film between the side walls, the second region is a first conductivity type impurity concentration higher than the first region of the first region and the second insulating film When,
Have a,
The concentration of the first conductive impurity in the region close to the first portion of the second insulating film in the second region is higher than the concentration of the first conductive impurity in the first region, and the second in the second region. 2. A semiconductor device having a concentration lower than that of the first conductive impurity in a region close to the second portion of the insulating film. 前記第１電極と前記第１半導体層との間に設けられ、前記第１半導体層よりも第１導電形不純物濃度が高いドレイン層をさらに備え、
前記第１半導体層は、
前記第２絶縁膜のボトムに近接する領域に設けられ、前記第１領域よりも第１導電形不純物濃度が高く、前記ドレイン層よりも第１導電型不純物濃度が低い第３領域をさらに有する請求項１記載の半導体装置。 A drain layer provided between the first electrode and the first semiconductor layer and having a higher concentration of first conductive impurities than the first semiconductor layer is further provided.
The first semiconductor layer is
Provided in a region close to the bottom of the second insulating film, further comprising the than the first region a first conductivity type impurity concentration is rather high, the third region is lower first conductivity type impurity concentration than the drain layer The semiconductor device according to claim 1. 前記第１半導体層は、前記ドレイン層と前記第３領域との間に、前記ドレイン層および前記第３領域よりも第１導電形不純物濃度が低い領域を有する請求項２記載の半導体装置。The semiconductor device according to claim 2, wherein the first semiconductor layer has a region between the drain layer and the third region, which has a lower concentration of first conductive impurities than the drain layer and the third region. 半導体層にトレンチを形成する工程であって、前記トレンチの幅は深さ方向に向かって段階的に小さくなり、段差をもつ側壁を有するトレンチを形成する工程と、
前記半導体層における前記トレンチの段差をもつ前記側壁に近接する領域に不純物を注入し、前記半導体層の前記領域に、深さ方向に向かって段階的に不純物濃度が高くなる濃度勾配をもたせる工程と、
前記トレンチにおける段差を形成して深さ方向につながった前記側壁に近接する前記半導体層における前記不純物が注入された領域を熱酸化し、前記トレンチの前記側壁に、深さ方向に向かって段階的に膜厚が厚くなる絶縁膜を形成する工程と、
前記トレンチ内における前記絶縁膜の内側に、電極材を形成する工程と、
を備えた半導体装置の製造方法。 A step of forming a trench in a semiconductor layer, in which the width of the trench gradually decreases in the depth direction and a trench having a side wall having a step is formed.
A step of injecting impurities into a region of the semiconductor layer close to the side wall having a step of the trench, and giving the region of the semiconductor layer a concentration gradient in which the impurity concentration gradually increases in the depth direction. ,
The region in which the impurities are injected in the semiconductor layer close to the side wall connected in the depth direction by forming a step in the trench is thermally oxidized, and the side wall of the trench is stepwise toward the depth direction. The process of forming an insulating film with a thicker film thickness
A step of forming an electrode material inside the insulating film in the trench, and
A method for manufacturing a semiconductor device provided with.
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