JP6804395B2 - Solid-state image sensor - Google Patents

Description

The present technology relates to a solid-state image sensor.

A CMOS (Complementary Metal Oxide Semiconductor) solid-state image sensor known as a solid-state image sensor has a low power supply voltage and low power consumption. Therefore, it is used in various mobile terminal devices such as digital still cameras, digital video cameras, and camera-equipped mobile phones.
The CMOS solid-state image sensor includes pixels including a photodiode which is a photoelectric conversion unit and a plurality of pixel transistors. Then, it is configured to have a pixel unit in which a plurality of pixels are regularly arranged in a two-dimensional array, and a peripheral circuit unit arranged around the pixel unit.

Recently, a back-illuminated CMOS solid-state image sensor has attracted attention (see Patent Document 1 and Patent Document 2). In the back-illuminated CMOS solid-state image sensor, the light incident surface is on the side opposite to the side where the wiring is arranged (base surface) (base back surface). Therefore, the wiring of the pixel portion can be arranged on the photodiode, and the degree of freedom in layout is dramatically improved.
Further, with the miniaturization of the pixel size, a pixel sharing type CMOS solid-state imaging device in which a plurality of photodiodes share another group of pixel transistors other than the transfer transistor is also known (Patent Document 3, Patent Document). 4).

JP-A-2007-115994 Japanese Unexamined Patent Publication No. 2003-31785 Japanese Unexamined Patent Publication No. 2008-294218 Japanese Unexamined Patent Publication No. 2009-135319

In the back-illuminated CMOS solid-state image sensor described above, the capacitive coupling between the wirings cannot be ignored as the distance between the adjacent wirings becomes smaller as the pixel size becomes smaller. In the transfer wiring, the pulse voltage supplied to the transfer gate fluctuates due to the influence of other wiring. In particular, when the off voltage supplied to the transfer gate fluctuates, the potential in the substrate under the transfer gate fluctuates. Due to this potential fluctuation, the electric charge accumulated in the photodiode leaks to the floating diffusion (FD), the saturation signal amount (Qs) changes, and the variation in the saturation signal amount between the photodiodes becomes large. There are problems such as. As described above, if the saturation signal amount varies greatly from pixel to pixel, the image quality of the solid-state image sensor deteriorates.

The present technology provides a solid-state image sensor having a configuration capable of improving image quality.

The solid-state imaging device of the present technology has a first semiconductor substrate having a pixel region in which a plurality of pixels including a photoelectric conversion element are arranged, and a first multilayer wiring layer provided on the first semiconductor substrate. A second semiconductor chip portion having a first semiconductor chip portion, a second semiconductor substrate on which a logic circuit is formed, and a second multilayer wiring layer provided on the second semiconductor substrate is provided. .. The first multilayer wiring layer is provided on the side opposite to the side where light is incident on the photoelectric conversion element with respect to the first semiconductor substrate. The first multilayer wiring layer has a first wiring layer including a first wiring portion and a second wiring portion provided at intervals from the first wiring portion in a cross-sectional view, and is a second. The multilayer wiring layer of the above has a second wiring layer having a third wiring portion. Then, the first multilayer wiring layer side of the first semiconductor chip portion and the second multilayer wiring layer side of the second semiconductor chip portion face each other, and the first semiconductor chip portion and the second semiconductor chip portion are opposed to each other. The parts are laminated. Further, in the direction perpendicular to the joint surface between the first semiconductor chip portion and the second semiconductor chip portion in the cross-sectional view, the first wiring portion and the second wiring portion are located at positions where they all overlap with the third wiring portion. A solid-state imaging device provided with an interval from.

According to the solid-state image sensor described above, the transfer wirings are arranged in parallel with a uniform aperture width. Therefore, the coupling capacitance between the transfer wirings becomes constant, and the change in the saturation signal amount between the pixels becomes constant. Therefore, the amount of saturation signals between pixels becomes uniform, and the image quality of the solid-state image sensor can be improved.
Further, by using this solid-state image sensor, it is possible to improve the image quality of electronic devices.

According to the present technology, it is possible to provide a solid-state image sensor capable of improving image quality.

It is a top view which shows the structure of the solid-state image sensor of an embodiment. A and B are schematic views showing the structure of the solid-state image sensor. It is sectional drawing which shows the structure of the solid-state image sensor of an embodiment. A is a cross-sectional structure of the wiring layer. Reference numeral B is a planar structure of the wiring layer. It is a figure which shows the structure of the pixel structure of 4 pixel sharing unit. FIG. A is a plan view showing a configuration of a light-shielding structure of the solid-state image sensor of the first embodiment. B is a cross-sectional view of a wiring layer constituting the light-shielding structure. A is a plan view showing the structure of the light-shielding structure of the solid-state image sensor of the second embodiment. B is a cross-sectional view of a wiring layer constituting the light-shielding structure. A is a plan view showing the structure of the light-shielding structure of the solid-state image sensor of the third embodiment. B is a cross-sectional view of a wiring layer constituting the light-shielding structure. A is a plan view showing the structure of the light-shielding structure of the solid-state image sensor of the fourth embodiment. B is a cross-sectional view of a wiring layer constituting the light-shielding structure. It is a figure which shows the structure of an electronic device.

Hereinafter, an example of the best mode for carrying out the present technology will be described, but the present technology is not limited to the following examples.
The explanation will be given in the following order.
1. 1. Outline of solid-state image sensor 2. First Embodiment of a solid-state image sensor 3. 2. The second embodiment of the solid-state image sensor 4. Third Embodiment of the solid-state image sensor 5. Fourth Embodiment of the solid-state image sensor 6. Electronics

<1. Overview of solid-state image sensor>
The outline of the solid-state image sensor will be described below.
In a back-illuminated CMOS solid-state image sensor, it is common to form a horizontal overflow structure as a countermeasure against blooming. The horizontal overflow structure allows the charge to escape from under the transfer gate through floating diffusion. Therefore, in the back-illuminated CMOS solid-state image sensor, the potential fluctuation of the transfer gate is likely to occur due to the influence of the horizontal overflow structure. In this way, the transfer wiring that supplies the pulse voltage to the transfer gate is affected by the capacitive coupling between the wirings, and the saturation signal amount (Qs) changes and the saturation signal amount varies widely between the photodiodes. There is a possibility of.

In order to suppress the variation in the amount of saturation signals, it is necessary to make the potential fluctuation of the transfer gate uniform. If the potential fluctuation of the transfer gate is uniform, the fluctuation of the potential in the substrate under the transfer gate is the same, and the variation of the saturation signal amount is eliminated.

In order to make the potential fluctuation of the transfer gate uniform, it is necessary to take measures from the viewpoint of wiring arrangement in the pixel portion. Therefore, by devising the arrangement of the wiring in the pixel portion, the coupling capacitance between the transfer wiring and the other wiring is made uniform. If the coupling capacitance can be made uniform in this way, the potential fluctuation of the transfer wiring becomes the same at each transfer gate. Therefore, it is possible to suppress variations in the amount of saturation signals.

On the other hand, in solid-state image sensors, as one of the methods for miniaturizing multiple functions and multiple chips, efforts have begun to enable high-speed transmission by bonding and joining multiple chips together. .. In this case, since the photoelectric conversion element portion and the peripheral circuit portion are formed at very close positions, a problem peculiar to the image sensor occurs. Since the photoelectric conversion element treats minute carriers (electrons) as signals, the influence of heat and electromagnetic fields from surrounding circuits is likely to be mixed as noise. In addition, minute hot carrier light emission, which is hardly a problem in the normal circuit operation of transistors and diodes, has a great influence on the image sensor characteristics.

Hot carrier emission is emission caused by the generation and recombination of electrons and holes, or the state transition of either of them, which is emitted when carriers accelerated between the source and drain are impact-ionized at the drain end. This light emission is constantly occurring, although it is minute, even in a transistor that has no problem in terms of characteristics. Since the light emission diffuses in all directions, the effect becomes very small when the transistor is separated from the transistor. However, when the photoelectric conversion element and the circuit are placed very close to each other, the light emission does not diffuse so much and a considerable number of photons are injected into the photoelectric conversion element. Will be done.

As described above, since the diffusion of hot carrier light emission is insufficient, the generation distribution of hot carrier light emission due to the difference in the transistor arrangement density and the active rate of the circuit is reflected in the image as two-dimensional information. Therefore, a light-shielding configuration is required to keep the injection amount into the photoelectric conversion element below the detection limit.

In the prior art, for the purpose of suppressing the variation in the amount of saturation signals, the arrangement of the wiring in the pixel portion is devised to make the coupling capacitance between the transfer wiring and the other wiring uniform.
However, when the wiring arrangement of the prior art is used, at least one gap is generated between adjacent wirings, and a structure for shading is separately prepared in order to suppress the influence of hot carrier light emission as described above. There is a need to.
When a light-shielding film is added to form a light-shielding structure, the light-shielding film is formed of a material such as W, Cu, Ti, TiN, or C. The absorbing film may be formed by using a material that absorbs light instead of the light-shielding film, but in any case, there is a demerit in terms of cost and the like.
Therefore, in the present embodiment, a wiring structure capable of achieving both a uniform coupling capacitance and a light-shielding structure is configured without adding a new configuration for light-shielding.

<2. First Embodiment of Semiconductor Device>
[Outline configuration of solid-state image sensor]
FIG. 1 shows a schematic configuration of a MOS type solid-state image sensor applied to the solid-state image sensor of the present embodiment. This MOS type solid-state image sensor is applied to the solid-state image sensor of each embodiment. In the solid-state image sensor 1 of this example, a semiconductor substrate (not shown), for example, a pixel region (so-called pixel array) 3 in which pixels 2 including a plurality of photoelectric conversion units are regularly arranged in a two-dimensional array on a silicon substrate and a periphery thereof. It is configured to have a circuit unit. The pixel 2 includes, for example, a photodiode that serves as a photoelectric conversion unit, and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be composed of, for example, three transistors, a transfer transistor, a reset transistor, and an amplification transistor. In addition, a selection transistor can be added to form four transistors. Since the equivalent circuit of a unit pixel is the same as usual, detailed description thereof will be omitted. Pixel 2 can be configured as one unit pixel. Further, the pixel 2 may have a shared pixel structure. This pixel sharing structure is a structure in which a plurality of photodiodes share a floating diffusion constituting a transfer transistor and a transistor other than the transfer transistor.

The peripheral circuit unit includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.
The control circuit 8 receives an input clock and data for instructing an operation mode and the like, and outputs data such as internal information of the solid-state image sensor. That is, the control circuit 8 generates a clock signal or a control signal that serves as a reference for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do. Then, these signals are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

The vertical drive circuit 4 is composed of, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving a pixel to the selected pixel drive wiring, and drives the pixels in row units. That is, the vertical drive circuit 4 selectively scans each pixel 2 in the pixel region 3 in a row-by-row manner in the vertical direction, and passes through the vertical signal line 9 to serve as a photoelectric conversion unit of each pixel 2, for example, in a photodiode according to the amount of light received. A pixel signal based on the generated signal charge is supplied to the column signal processing circuit 5.

The column signal processing circuit 5 is arranged for each column of the pixel 2, for example, and performs signal processing such as noise removal for each pixel string with respect to the signal output from the pixel 2 for one row. That is, the column signal processing circuit 5 performs signal processing such as CDS for removing fixed pattern noise peculiar to pixel 2, signal amplification, and AD conversion. A horizontal selection switch (not shown) is provided in the output stage of the column signal processing circuit 5 so as to be connected to the horizontal signal line 10.

The horizontal drive circuit 6 is composed of, for example, a shift register, and by sequentially outputting horizontal scanning pulses, each of the column signal processing circuits 5 is sequentially selected, and pixel signals are output from each of the column signal processing circuits 5 as horizontal signal lines. Output to 10.

The output circuit 7 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10 and outputs the signals. For example, there are cases where only buffering is performed, black level adjustment, column variation correction, various digital signal processing, and the like are performed. The input / output terminal 12 exchanges signals with the outside.

Next, the structure of the MOS type solid-state image sensor according to the present embodiment will be described. 2A and 2B are schematic configuration diagrams showing the structure of the MOS type solid-state image sensor according to the present embodiment.

As shown in FIG. 2A, the MOS type solid-state image sensor 21 of the present embodiment has a pixel region 23 mounted on the first semiconductor chip portion 22, and a control circuit 24 and a signal processing circuit on the second semiconductor chip portion 26. The logic circuit 25 including the above is mounted. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are electrically connected to each other to form a MOS type solid-state image sensor 21 as one semiconductor chip.

Further, in the MOS type solid-state image sensor 27 in the embodiment, as shown in FIG. 2B, the pixel region 23 and the control circuit 24 are mounted on the first semiconductor chip portion 22, and the second semiconductor chip portion 26 is used for signal processing. A logic circuit 25 including a signal processing circuit for performing the above is mounted. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are electrically connected to each other to form a MOS type solid-state image sensor 27 as one semiconductor chip.

Further, although not shown, in the MOS type solid-state image sensor in another embodiment, the first semiconductor chip unit 22 includes a pixel region 23 and a control circuit unit suitable for controlling a pixel region that is a part of the control circuit. Is installed. Further, the second semiconductor chip unit 26 is equipped with a logic circuit 25 and a control circuit unit suitable for controlling a logic circuit which is another part of the control circuit. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are electrically connected to each other to form a MOS type solid-state image sensor 27 as one semiconductor chip.
The MOS type solid-state image sensor according to the above-described embodiment has a structure in which different types of semiconductor chips are laminated, and is characterized by a configuration described later.

[Cross-sectional configuration of solid-state image sensor]
FIG. 3 shows a first embodiment of the solid-state image sensor of the present embodiment, particularly the MOS type solid-state image sensor. The MOS type solid-state image sensor of the present embodiment is a back-illuminated solid-state image sensor. Although the configuration of FIG. 2B is applied to the MOS type solid-state image sensor of the present embodiment, the configuration of another configuration of FIG. Can also be applied. Second Embodiment Similarly, the above configuration can be applied to each of the following embodiments.

The solid-state image sensor according to the first embodiment is configured by laminating a first semiconductor chip portion 31 and a second semiconductor chip portion 45. The first semiconductor chip unit 31 is controlled by a photodiode PD serving as a photoelectric conversion unit and a pixel array (hereinafter referred to as a pixel region 23) in which a plurality of pixels composed of a plurality of pixel transistors are two-dimensionally arranged. The circuit 24 is formed.

The photodiode PD is formed by having an n-type semiconductor region 34 and a p-type semiconductor region 35 on the surface side of the substrate in the semiconductor well region 32. A gate electrode 36 is formed on the surface of a substrate constituting a pixel via a gate insulating film, and pixel transistors Tr1 and Tr2 are formed by a source / drain region 33 paired with the gate electrode 36. In FIG. 3, a plurality of pixel transistors are represented by two pixel transistors Tr1 and Tr2. The pixel transistor Tr1 adjacent to the photodiode PD corresponds to the transfer transistor, and its source / drain region corresponds to the floating diffusion FD. Each unit pixel is separated by the element separation region 38.

On the other hand, the control circuit 24 is composed of a plurality of MOS transistors formed in the semiconductor well region 32. In FIG. 3, a plurality of MOS transistors constituting the control circuit 24 are represented by MOS transistors Tr3 and Tr4. The MOS transistors Tr3 and Tr4 are formed by an n-type source / drain region 33 and a gate electrode 36 formed via a gate insulating film.

On the surface side of the substrate, a multilayer wiring layer 41 is formed in which a plurality of layers of wiring 40 are arranged via an interlayer insulating film 39. The wiring 40 is formed of, for example, copper wiring. The pixel transistor and the MOS transistor of the control circuit are connected to the required wiring 40 via a connecting conductor 44 penetrating the first insulating film 43a and the second insulating film 43b. The first insulating film 43a is formed of, for example, a silicon oxide film, and the second insulating film 43b is formed of, for example, a silicon nitride film serving as an etching stopper.

An antireflection film 61 is formed on the back surface of the semiconductor well region 32. In the region corresponding to each photodiode PD on the antireflection film 61, a waveguide 70 made of a waveguide material film (for example, SiN film or the like) 69 is formed. A light-shielding film 63 that shields the required region is formed in the insulating film 62 made of, for example, a SiO film on the back surface of the semiconductor well region 32. Further, a color filter 73 and an on-chip microlens 74 are formed via the flattening film 71 so as to correspond to each photodiode PD.

On the other hand, a logic circuit 25 including a signal processing circuit for signal processing is formed in the second semiconductor chip unit 45. The logic circuit 25 is configured by forming, for example, a plurality of MOS transistors in a p-type semiconductor well region 46 so as to be separated by an element separation region 50. Here, a plurality of MOS transistors are represented by MOS transistors Tr6, Tr7, and Tr8. Each of the MOS transistors Tr6, Tr7, and Tr8 is formed by having a pair of n-type source / drain regions 47 and a gate electrode 48 formed via a gate insulating film.

On the semiconductor well region 46, a multilayer wiring layer 55 is formed in which a plurality of layers of wiring 53 and wiring 57 having a barrier metal layer 58 are arranged via an interlayer insulating film 49. The MOS transistors Tr6, Tr7, and Tr8 are connected to the required wiring 53 via a connecting conductor 54 that penetrates the first insulating film 43a and the second insulating film 43b.

The first semiconductor chip portion 31 and the second semiconductor chip portion 45 are bonded to each other via, for example, an adhesive layer 60 so that the multilayer wiring layers 41 and 55 face each other. A stress correction film 59 for reducing the stress of bonding is formed on the bonding surface of the multilayer wiring layer 55 on the side of the second semiconductor chip portion 45. In addition to this, the bonding can also be performed by plasma bonding.

Further, the first semiconductor chip portion 31 and the second semiconductor chip portion 45 are electrically connected via the connecting conductor 68. That is, a connection hole is formed that penetrates the semiconductor well region 32 of the first semiconductor chip portion 31 and reaches the required wiring 40 of the multilayer wiring layer 41. Further, a connection hole is formed that penetrates the semiconductor well region 32 of the first semiconductor chip portion 31 and the multilayer wiring layer 41 and reaches the required wiring 53 of the multilayer wiring layer 55 of the second semiconductor chip portion 45. Connection conductors 68 that connect to each other are embedded in these connection holes, and the first semiconductor chip portion 31 and the second semiconductor chip portion 45 are electrically connected. The circumference of the connecting conductor 68 is covered with an insulating film 67 in order to insulate the semiconductor well region 32. Wiring 40 and 57 connected to the connecting conductor 68 correspond to vertical signal lines. The connecting conductor 68 may be connected to an electrode pad (not shown) or may be an electrode pad.

The connecting conductor 68 is formed after the first semiconductor chip portion 31 and the second semiconductor chip portion 45 are bonded together, and then the semiconductor well region 32 of the first semiconductor chip portion 31 is thinned. After that, a cap film 72, a flattening film 71, a color filter 73, and an on-chip microlens 74 are formed. In the semiconductor well region 32, an insulating spacer layer 42 is formed in a region surrounding the connecting conductor 68.

In the present embodiment, a light-shielding structure by wiring is formed in a region between the photodiode PD of the pixel region 23 and the logic circuit 25 of the peripheral circuit portion and covering the pixel region without gaps.
For example, in a solid-state imaging device, wiring 40 is arranged on the multilayer wiring layer 41 of the photoelectric conversion element in the pixel region so as to cover the pixel region without gaps. At this time, by using two or more wiring layers and arranging the wirings 40 so as to overlap each other to some extent, it is possible to prevent the influence of light diffraction and suppress the incident of light from the lower part.

Further, in the light-shielding structure, in order to make the coupling capacitance uniform, transfer wiring arranged at equal intervals in the same layer and other wiring arranged in different layers so as to have a certain overlap with the transfer wiring are combined. Configure. With this configuration, it is possible to form a light-shielding structure that blocks the light radiated during the operation of the active element of the peripheral circuit portion only by the wiring layer without adding a new light-shielding layer. With this structure, it is possible to prevent hot carrier light emission from being incident on the photodiode PD of the pixel. Examples of the active element include a MOS transistor and a diode for protection.

[Shading structure by wiring]
Examples of the configuration of the light-shielding structure by wiring are shown in FIGS. 4A and 4B. FIG. 4A is a diagram showing a cross-sectional structure of the wiring layer, and FIG. 4B is a diagram showing a planar structure of the wiring layer.
A light-shielding structure is configured by at least two layers of wiring 40A and 40B.
In this light-shielding structure, the stacking interval between the lower layer wiring 40A and the upper layer wiring 40B is defined as the distance 81 between the wirings. Similarly, the length at which the lower layer wiring 40A and the upper layer wiring 40B overlap in the plane direction is defined as the overlap amount 82. The distance between the lower layer wirings 40A is set to the opening width 83.

The amount of overlap 82 is determined by the distance 81 between the wirings and the opening width 83. Since hot carrier light is generated as a point light source, it is necessary to block light coming from an angle. Therefore, by making the overlap amount 82 larger than at least the distance 81 between the wirings, the light blocking property of the hot carrier light from the oblique direction is improved.
Further, the opening widths 83 of the wirings 40A formed in the same layer of the wirings are all arranged so as to be the same. Further, the overlapping amount 82 is uniformly formed. With this configuration, the positional relationship between the wirings 40A and 40B can be made uniform, and the coupling capacitance can be made uniform.

[Pixel sharing unit: Pixel configuration]
Next, the configuration of the pixel portion applied to the solid-state image sensor of the present embodiment will be described. FIG. 5 shows a configuration of a pixel portion composed of a 4-pixel sharing unit applied to the present embodiment. As shown in FIG. 5, 4-pixel sharing units in which 4-pixel photodiodes PD [PD1 to PD4] are arranged are arranged in a two-dimensional array to form a pixel portion.

The 4-pixel sharing unit has a configuration in which one floating diffusion FD is shared with a total of four photodiode PDs of 2 horizontal × 2 vertical. Then, it is configured to have four photodiodes PD1 to PD4, four transfer gate electrodes 75 to 78 for the four photodiodes PD1 to PD4, and one floating diffusion FD. The transfer transistors Tr11 to Tr14 are configured by the photodiodes PD1 to PD4, the floating diffusion FD, and the transfer gate electrodes 75 to 78. The floating diffusion FD is arranged in the central portion surrounded by the four photodiodes PD1 to PD4, and the transfer gate electrodes 75 to 78 are arranged at positions corresponding to the central portions of the photodiodes PD1 to PD4. Will be done.

Further, in FIG. 5, the selection transistor Tr23 and the amplification transistor Tr22 are arranged above the 4-pixel sharing unit. Then, the reset transistor Tr21 is arranged below the 4-pixel sharing unit. The selection transistor Tr23 includes a pair of source / drain regions 94 and 95 and a selection gate electrode 79. The amplification transistor Tr22 includes a pair of source / drain regions 95 and 96 and an amplification gate electrode 80. The reset transistor Tr21 includes a pair of source / drain regions 97 and 98 and a reset gate electrode 99. Each of the gate electrodes is formed of, for example, a polysilicon film. The FD1 is connected to the amplification gate electrode 80 of the amplification transistor Tr23 and the source region of the reset transistor Tr21.

The above-mentioned light-shielding structure is formed in the wiring layer in the region where the photodiode PD is formed. It is preferable that the light-shielding region formed by the wiring layer covers the entire region where the photodiode PD is formed.
However, the effect of the light-shielding structure can be obtained without covering the entire photodiode PD region. For example, it is preferable to shield at least a square region having a short side of the photodiode PD1 as one side on the photodiode PD1 as in the light-shielding region 100 shown in FIG. Similarly, in the photodiodes PD1 to 4, the square region having the short side of the photodiodes PD2 to 4 as one side is shielded from light. By forming a light-shielding structure by wiring on the light-shielding region 100, a sufficient light-shielding effect can be obtained. As described above, even when a light-shielding layer covering a part of the photodiode PD region is provided without covering the entire region where the photodiode PD is formed, the effect of the light-shielding structure can be obtained.

[Wiring configuration: Shading structure configuration example]
Next, a light-shielding structure by a wiring layer provided on the pixel portion in which the above-mentioned 4-pixel sharing unit is configured will be described.
In the back-illuminated CMOS solid-state imaging device, as shown in FIG. 3 above, a pixel transistor is formed on the front surface side of the semiconductor substrate, and a plurality of layers of wiring made of a metal layer are arranged above the pixel transistor via an interlayer insulating film. Layers are formed. A color filter layer and an on-chip lens are formed on the back surface side of the semiconductor substrate, and light is incident from the back surface side of the substrate. That is, the back-illuminated type has a configuration in which the wiring layer is formed on the side opposite to the light incident surface.

FIG. 6 shows a first embodiment of a light-shielding structure formed on the pixel portion. FIG. 6A is a plan view showing the configuration of various wirings formed on the 4-pixel sharing unit. FIG. 6B is a sectional view taken along line AA of the wiring structure shown in FIG. 6A. Further, the pixel portion of the 4-pixel sharing unit shown in FIG. 6A has the same configuration as that shown in FIG. 5 described above, and the same reference numerals are given to the same configuration, and detailed description thereof will be omitted.

The wiring forming the light-shielding structure on the pixel portion includes a transfer wiring and other wiring arranged in parallel with the transfer wiring. In this embodiment, pulse wiring and dummy wiring are used as the wiring arranged in parallel with the transfer wiring. The wiring other than the transfer wiring is not particularly limited, and various wirings provided in the CMOS solid-state image sensor, dummy wirings, and the like can be appropriately used.

As shown in FIG. 6A, in the pixel portion, transfer wirings 84 to 87 extending in the horizontal direction and arranged in parallel in the vertical direction when viewed from the upper surface are arranged at required intervals. For example, at least one of the four transfer wires 84 to 87 is arranged in parallel so as to cross over the photodiode PD. In this example, the transfer wires 84 and 87 are formed so as to cross the vicinity of the center of the photodiode PD.
The transfer wirings 84 to 87 are connected to the transfer gate electrodes 75 to 78 of the transfer transistors Tr11 to 14 of the 4-pixel sharing unit. At this time, it is preferable that the wiring widths and the intervals between the wirings of the four transfer wirings 84 to 87 are the same.

Further, as shown in FIG. 6A, pulse wirings 88 to 91 are provided adjacent to the transfer wirings 84 to 87. In FIG. 6, two pulse wirings 88, 89 and 90, 91 are arranged with respect to the transfer wirings 84 and 87 provided on the outside, respectively. The pulse wires 88 to 91 are arranged in parallel with the transfer wires 84 to 87. It is preferable that the pulse wirings 88 to 91 and the transfer wirings 84 to 87 have the same wiring width and spacing between the wirings.
As shown in FIG. 6B, in the first embodiment, the wirings such as the transfer wirings 84 to 87 and the pulse wirings 88 to 91 are all formed in the same wiring layer.

Further, as shown in FIGS. 6A and 6B, a dummy wiring 92 is formed in a wiring layer different from the transfer wirings 84 to 87 and the pulse wirings 88 to 91. As shown in FIG. 4, the dummy wiring 92 is arranged at a position where a part of the transfer wirings 84 to 87 and the pulse wirings 88 to 91 overlap each other. The dummy wiring 92 may be electrically floating, or may be fixed to the power supply voltage and ground.

In the light-shielding structure of the first embodiment, in the multilayer wiring layer, transfer wirings 84 to 87 and pulse wirings 88 to 91 are provided in the lower wiring layer, and dummy wiring 92 is provided in the upper wiring layer.
The lower layer transfer wirings 84 to 87, the pulse wirings 88 to 91, and the upper layer dummy wiring 92 are larger than the distance 81 between the wirings of the wiring layer, as in the wirings 40A and 40B shown in FIG. It is arranged with an overlapping amount of 82.
Further, the transfer wirings 84 to 87 and the opening widths 83 of the pulse wirings 88 to 91 are formed to have uniform lengths, respectively. Further, the opening width 83 of the dummy wiring 92 is formed to have a constant length.

By arranging the transfer wirings 84 to 87, the pulse wirings 88 to 91, and the dummy wiring 92 as described above, the photodiode PD is located between the photodiode PD and an active element such as a logic circuit located at a close distance to the photodiode PD. A light-shielding structure is configured in. Therefore, hot carrier light generated by a MOS transistor such as a logic circuit can be blocked by a wiring layer constituting a light-shielding structure. Further, the light generated during the operation of the protection diode can also be blocked by the wiring layer constituting the light-shielding structure. Therefore, it is possible to prevent hot carrier light emission from entering the photodiode PD of the pixel portion.

In particular, the transfer wirings 84 to 87, the pulse wirings 88 to 91, and the dummy wirings 92 are arranged so as to have an overlap amount 82 larger than the distance 81 between the wirings, so that they are oblique due to the influence of light diffraction. Can block hot carrier light from. Therefore, it is possible to provide a light-shielding structure capable of further suppressing the incident of hot carrier light on the photodiode PD.
Therefore, it is possible to provide a solid-state image sensor in which hot carrier light is prevented from being reflected in the pixel region and the image quality is improved.

Further, since the transfer wirings 84 to 87, the pulse wirings 88 to 91, and the opening width 83 of the dummy wiring 92 are each formed to have a uniform length, the positional relationship between the wirings can be made the same. .. Therefore, the coupling capacitance between the wirings can be made uniform, and the potential fluctuation of the transfer gate can be made uniform. Therefore, the potential fluctuation of the transfer wiring becomes the same at each transfer gate, and the variation in the saturation signal amount of each pixel can be suppressed.

<3. Second Embodiment of the solid-state image sensor>
Next, the configuration of the solid-state image sensor of the second embodiment will be described. Also in the second embodiment, the same solid-state image pickup device as in the first embodiment described above can be applied except for the configuration of the wiring forming the light-shielding structure. Therefore, in the following description, the configuration of the wiring forming the light-shielding structure will be described.

[Wiring: Shading structure configuration example]
FIG. 7 shows a wiring structure constituting a light-shielding structure provided on a pixel portion in which a pixel sharing unit is formed. FIG. 7A is a plan view showing the configuration of various wirings formed on the 4-pixel sharing unit shown in FIG. 5 described above. FIG. 7B is a sectional view taken along line AA of the wiring structure shown in FIG. 7A.

The transfer wirings 84 to 87 and the pulse wirings 88 to 91 are configured in the same arrangement as in the first embodiment described above. Then, a wiring layer in which the dummy wiring 92 is formed is provided on the upper layer of the wiring layer in which the transfer wirings 84 to 87 and the pulse wirings 88 to 91 are formed.

The dummy wiring 92 is formed by covering the photodiode PD of the 4-pixel sharing unit so as to cover the transfer wirings 84 to 87 and the pulse wirings 88 to 91. The formation region of the dummy wiring 92 is preferably equal to or larger than the light-shielding region shown in FIG. In particular, it is preferable to form the entire pixel portion. The dummy wiring 92 may be electrically floating, or may be fixed to the power supply voltage and ground.

Further, in the transfer wirings 84 to 87 and the pulse wirings 88 to 91, the opening width 83 between the wirings shown in FIG. 4 is formed to be constant. Since the dummy wiring 92 is formed so as to cover the entire transfer wirings 84 to 87 and the pulse wirings 88 to 91, the overlap amount 82 is uniform in all the wirings. Further, by making the widths of the transfer wirings 84 to 87 and the pulse wirings 88 to 91 larger than the distance 81 between the wirings, the overlapping amount 82 becomes larger than the distance 81 between the wirings.

As described above, by arranging the transfer wirings 84 to 87, the pulse wirings 88 to 91, and the dummy wiring 92, the positional relationship between the wirings can be made the same. Therefore, the coupling capacitance between the wirings can be made uniform, and the potential fluctuation of the transfer gate can be made uniform. Therefore, the influence of the potential fluctuation of the transfer wiring becomes the same at each transfer gate, and the variation in the saturation signal amount between the photodiodes can be suppressed.

Further, by forming the transfer wirings 84 to 87 and the dummy wirings 92 covering the pulse wirings 88 to 91, a light-shielding structure having an overlap amount 82 larger than the distance 81 between the wirings is formed on the pixel portion. To. Therefore, it is possible to prevent hot carrier light emission from entering the photodiode PD of the pixel portion. In particular, the configuration is effective in preventing the incident of hot carrier light from an angle due to the influence of light diffraction.

<4. Third Embodiment of the solid-state image sensor>
Next, the configuration of the solid-state image sensor of the third embodiment will be described. Also in the third embodiment, the same solid-state image pickup device as in the first embodiment described above can be applied except for the configuration of the wiring forming the light-shielding structure. Therefore, in the following description, the configuration of the wiring forming the light-shielding structure will be described.

[Wiring: Shading structure configuration example]
FIG. 8 shows a wiring structure constituting a light-shielding structure provided on a pixel portion in which a pixel sharing unit is formed. FIG. 8A is a plan view showing the configuration of various wirings formed on the 4-pixel sharing unit shown in FIG. 5 described above. FIG. 8B is a sectional view taken along line AA of the wiring structure shown in FIG. 8A.

As shown in FIG. 8, the transfer wirings 84 to 87 and the pulse wirings 88 to 91 are configured in the same arrangement as in the first embodiment described above. Then, a wiring layer in which the dummy wiring 92 is formed is provided on the upper layer of the wiring layer in which the transfer wirings 84 to 87 and the pulse wirings 88 to 91 are formed.

The light-shielding structure by wiring of the third embodiment is an example in which an opening is provided in a part of the light-shielding structure. Therefore, in the configuration shown in FIG. 8, in addition to the light-shielding structure of the second embodiment described above, an opening is provided on the pixel portion and outside the light-shielding region of the photodiode PD.
As described above, in the light-shielding structure by wiring, an opening may be provided on the pixel portion.

The dummy wiring 92 is formed by covering the photodiode PD of the 4-pixel sharing unit so as to cover the transfer wirings 84 to 87 and the pulse wirings 88 to 91. The formation region of the dummy wiring 92 is preferably equal to or larger than the light-shielding region shown in FIG. In particular, it is preferable to form the entire pixel portion. The dummy wiring 92 may be electrically floating, or may be fixed to the power supply voltage and ground.

Further, the dummy wiring 92 is provided with an opening 101 from which a part of the wiring is removed. In the light-shielding structure by wiring, the region where the upper wiring layer and the lower wiring layer do not overlap is the opening 101. That is, in the example of the third embodiment, the transfer wirings 84 to 87 and the pulse wirings 88 to 91 formed in the lower wiring layer and the region in which the dummy wiring 92 formed in the upper layer is not formed are shielded from light by wiring. The opening 101 of the structure.
Since it is difficult to partially remove the transfer wirings 84 to 87 and the pulse wirings 88 to 91, the opening 101 is formed by removing a part of the dummy wiring 92.

The opening 101 is preferably formed at a position other than on the photodiode PD of the pixel portion in order to block hot carrier light emission generated by a MOS transistor located at a close distance. However, the opening 101 is a photo of the aperture that does not affect the acquired image of the solid-state image sensor, for example, the aperture is formed on the photodiode PD to the extent that only hot carrier emission below the detection limit is incident. It may be provided on the diode PD.

For example, on the photodiode PD shown in FIG. 5 above, at least a square region having a short side of the photodiode PD as one side is a light-shielding region 100.
Further, for example, the opening position and the number of the openings 101 are not limited unless the center of the opening is on the photodiode PD.

However, in the positional relationship between the transfer wirings 84 to 87 and the pulse wirings 88 to 91, the opening width 83 between the wirings shown in FIG. 4 described above is formed to be constant. If the arrangement of the transfer wirings 84 to 87 and the pulse wirings 88 to 91 is uniform, there is no particular problem with the uniformity with the dummy wiring. In the area where the opening 101 is provided, the positional relationship between the transfer wiring and the dummy wiring is not kept uniform with other areas, but the uniformity between the transfer wiring and the dummy wiring is the coupling capacitance. It has almost no effect on the device and can be ignored.

As described above, by arranging the transfer wirings 84 to 87 and the pulse wirings 88 to 91, the positional relationship between the wirings can be made the same. Therefore, the coupling capacitance between the wirings can be made uniform, and the potential fluctuation of the transfer gate can be made uniform. Therefore, the influence of the potential fluctuation of the transfer wiring becomes the same at each transfer gate, and the variation in the saturation signal amount between the photodiodes can be suppressed.

Further, by forming the transfer wirings 84 to 87 and the dummy wirings 92 covering the pulse wirings 88 to 91, a light-shielding structure having an overlap amount 82 larger than the distance 81 between the wirings is formed on the pixel portion. To. Therefore, it is possible to prevent hot carrier light emission from entering the photodiode PD of the pixel portion. In particular, the configuration is effective in preventing the incident of hot carrier light from an angle due to the influence of light diffraction.

Also in the above-described first embodiment, a part of the dummy wiring 92 is removed to provide a region where the upper dummy wiring 92, the lower layer transfer wirings 84 to 87, and the pulse wirings 88 to 91 do not overlap. Thereby, the opening can be provided at an arbitrary position.

<5. Fourth Embodiment of Solid-state Image Sensor>
Next, the configuration of the solid-state image sensor of the fourth embodiment will be described. Also in the fourth embodiment, the same solid-state image pickup device as in the first embodiment described above can be applied except for the configuration of the wiring forming the light-shielding structure. Therefore, in the following description, the configuration of the wiring forming the light-shielding structure will be described.

[Wiring: Shading structure configuration example]
FIG. 9 shows a wiring structure constituting a light-shielding structure provided on a pixel portion in which a pixel sharing unit is formed. FIG. 9A is a plan view showing the configuration of various wirings formed on the 4-pixel sharing unit shown in FIG. 5 described above. FIG. 9B is a sectional view taken along line AA of the wiring structure shown in FIG. 9A.

Transfer wirings 84 to 87 and dummy wiring 92 are formed in the lower wiring layer. Then, pulse wirings 88 to 91 and dummy wirings 93 are formed in the upper wiring layer.

In the lower wiring layer, transfer wirings 84 to 87 extending horizontally when viewed from the upper surface and arranged in parallel in the vertical direction and dummy wirings 92 are alternately arranged at required intervals.
In the upper wiring layer, pulse wirings 88 to 91 extending in the horizontal direction when viewed from the upper surface and arranged in parallel in the vertical direction and dummy wirings 93 are alternately arranged at required intervals.

The transfer wirings 84 to 87 and the dummy wirings 93, and the transfer wirings 84 to 87 and the pulse wirings 88 to 91 are larger than the distance 81 between the wirings of the wiring layer, as in the wirings 40A and 40B shown in FIG. 4 above. It is arranged with an overlapping amount of 82. Similarly, the dummy wiring 92 and the pulse wiring 88 to 91, and the dummy wiring 92 and the dummy wiring 93 overlap more than the distance 81 between the wirings of the wiring layer as in the wirings 40A and 40B shown in FIG. 4 above. Arranged with a quantity of 82. As described above, in the upper and lower wiring layers, the overlapping amount 82 of each wiring is formed to have a constant length.

Further, the opening width 83 between the transfer wirings 84 to 87 and the dummy wiring 92 and the opening width 83 between the pulse wirings 88 to 91 and the dummy wiring 93 are formed to have a constant length. Further, the intervals between the transfer wirings 84 to 87 in the lower layer and the pulse wirings 88 to 91 in the upper layer are arranged to be constant.

As described above, by arranging the transfer wirings 84 to 87, the pulse wirings 88 to 91, and the dummy wirings 92 and 93, the positional relationship between the wirings can be made the same. Therefore, the coupling capacitance between the wirings can be made uniform, and the potential fluctuation of the transfer gate can be made uniform. Therefore, the influence of the potential fluctuation of the transfer wiring becomes the same at each transfer gate, and the variation in the saturation signal amount between the photodiodes can be suppressed.

Further, by forming the transfer wirings 84 to 87, the pulse wirings 88 to 91, and the dummy wirings 92 and 93, a light-shielding structure having an overlap amount 82 larger than the distance 81 between the wirings is formed on the pixel portion. Will be done. Therefore, it is possible to prevent hot carrier light emission from entering the photodiode PD of the pixel portion. In particular, the configuration is effective in preventing the incident of hot carrier light from an angle due to the influence of light diffraction.

As described above, in the two wiring layers constituting the light-shielding structure, the transfer wirings 84 to 87 and the pulse wirings 88 to 91 may be formed in different wiring layers. Then, a light-shielding structure may be formed in which the transfer wirings 84 to 87 and the pulse wirings 88 to 91 overlap each other. Further, dummy wiring may be formed on both wiring layers. Then, a light-shielding structure may be formed by overlapping the dummy wirings of the upper and lower layers.
As described above, in addition to the light-shielding structure by overlapping the transfer wirings 84 to 87 and the pulse wirings 88 to 91 and the dummy wiring 92 as in the first to third embodiments described above, a light-shielding structure by wiring is configured. Can be done.

<6. Electronics>
Next, an embodiment of an electronic device including the above-mentioned solid-state image sensor will be described.
The above-mentioned solid-state image sensor can be applied to, for example, a camera system such as a digital camera or a video camera, a mobile phone having an image pickup function, or an electronic device such as another device having an image pickup function. FIG. 10 shows a schematic configuration when a solid-state image sensor is applied to a camera capable of capturing a still image or a moving image as an example of an electronic device.

The camera 110 of this example includes a solid-state image sensor 111, an optical system 112 that guides incident light to a light receiving sensor unit of the solid-state image sensor 111, a shutter device 113 provided between the solid-state image sensor 111 and the optical system 112, and a solid-state camera. A drive circuit 114 for driving the image sensor 111 is provided. Further, the camera 110 includes a signal processing circuit 115 that processes the output signal of the solid-state image sensor 111.

The solid-state image sensor 111 shown in the first to fourth embodiments described above can be applied to the solid-state image sensor 111. The optical system (optical lens) 112 forms an image of image light (incident light) from a subject on an image pickup surface (not shown) of the solid-state image pickup device 111. As a result, the signal charge is accumulated in the solid-state image sensor 111 for a certain period of time. The optical system 112 may be composed of an optical lens group including a plurality of optical lenses. Further, the shutter device 113 controls the light irradiation period and the light blocking period of the incident light on the solid-state image sensor 111.

The drive circuit 114 supplies a drive signal to the solid-state image sensor 111 and the shutter device 113. Then, the drive circuit 114 controls the signal output operation of the solid-state imaging device 111 to the signal processing circuit 115 and the shutter operation of the shutter device 113 by the supplied drive signal. That is, in this example, the signal transfer operation from the solid-state imaging device 111 to the signal processing circuit 115 is performed by the drive signal (timing signal) supplied from the drive circuit 114.

The signal processing circuit 115 performs various signal processing on the signal transferred from the solid-state image sensor 111. Then, the signal (video signal) subjected to various signal processing is stored in a storage medium (not shown) such as a memory, or output to a monitor (not shown).

According to the electronic device such as the camera 110 described above, in the solid-state image sensor 111, it is possible to suppress the variation in the saturation signal amount due to the miniaturization of the pixel size. Further, in the solid-state image sensor, it is possible to suppress the incident of light such as hot carrier light from active elements such as MOS transistors and diodes into the photodiode during operation in the peripheral circuit section. Therefore, it is possible to provide a high-quality electronic device with improved image quality.

In each of the above-described embodiments, an example in which the light-shielding structure is composed of two wiring layers has been described, but the number of wiring layers used for the light-shielding structure may be three or more. Also in this case, the light-shielding structure can be configured by increasing the amount of overlapping of the wirings rather than the distance between the wirings of the wiring layer. Further, even when the light-shielding structure is composed of three or more wiring layers, if the wiring width and the wiring interval are uniformly formed between the transfer wiring and the other wirings constituting the light-shielding structure, the coupling capacitance can be made uniform. it can.

Further, in the above-described embodiment, the case where the pixel region, the control region, and the logic circuit are formed on separate substrates and these substrates are joined is described, but the pixel region, the control region, and the logic circuit are the same. It may be formed in the substrate of. Further, the pixel area, the control area, and the logic circuit do not have to be in the vertical direction, and may be in the same plane. In any case, it can be applied to the case where the pixel area, the control area, and the logic circuit are in close proximity to each other.

The present disclosure may also have the following structure.
(1) A pixel region in which a plurality of pixels including a photoelectric conversion element are arranged, a transfer wiring formed in parallel on the pixel region with a uniform opening width, and a wiring layer above the transfer wiring are formed. A solid-state imaging device including at least a part of the transfer wiring and other wiring provided at a position where they overlap in a plane position, and a light-shielding structure is formed in the pixel region by the transfer wiring and the other wiring.
(2) The solid-state image sensor according to (1), wherein the photoelectric conversion element is provided on the surface of the substrate on the first surface side, and the wiring layer is provided on the second surface of the substrate.
(3) A second substrate bonded to the second surface side of the substrate via the wiring layer is provided, the second substrate has a peripheral circuit portion, and the pixel region and the peripheral circuit portion The solid-state imaging device according to (2), wherein the light-shielding structure is formed between them.
(4) The solid-state imaging device according to any one of (1) to (3), which includes an active element for signal processing at a short distance of the photoelectric conversion element.
(5) The solid-state image pickup device according to (4), wherein the active element includes at least one of a field effect transistor and a diode.
(6) The solid-state image sensor according to any one of (1) to (5), which includes pulse wiring and dummy wiring as the other wiring.
(7) An electronic device including the solid-state image sensor according to any one of (1) to (6) and a signal processing circuit for processing an output signal of the solid-state image sensor.

1,111 solid-state imaging device, 2 pixels, 3,23 pixel area, 4 vertical drive circuit, 5 column signal processing circuit, 6 horizontal drive circuit, 7 output circuit, 8, 24 control circuit, 9 vertical signal line, 10 horizontal signal Wire, 12 input / output terminals, 21,27 MOS type solid-state imaging device, 22,31 first semiconductor chip section, 25 logic circuit, 26,45 second semiconductor chip section, 32,46 semiconductor well region, 33,47 , 94, 95, 97 Source / drain region, 34 n-type semiconductor region, 35 p-type semiconductor region, 36, 48 gate electrode, 38, 50 element separation region, 39, 49 interlayer insulating film, 40, 40A, 40B, 53 , 57 wiring, 41,55 multi-layer wiring layer, 42 insulating spacer layer, 43a first insulating film, 43b second insulating film, 44, 54, 68 connecting conductor, 58 barrier metal layer, 59 stress correction film, 60 adhesive layer , 61 antireflection film, 62,67 insulating film, 63 shading film, 69 waveguide material film, 70 waveguide, 71 flattening film, 72 cap film, 73 color filter, 74 on-chip microlens, 75 transfer gate electrode, 79 Selective gate electrode, 80 Amplified gate electrode, 81 Distance between wirings, 82 Overlapping amount, 83 Opening width, 84 Transfer wiring, 88 Pulse wiring, 92, 93 Dummy wiring, 99 Reset gate electrode, 100 Shading area, 101 Opening , 110 camera, 112 optical system, 113 shutter device, 114 drive circuit, 115 signal processing circuit, FD floating diffusion, PD1, PD2, PD1, PD4 photodiode, Tr1 pixel transistor, Tr11, Tr12, Tr13, Tr14 transfer transistor, Tr21 Reset transistor, Tr22 amplification transistor, Tr23 selection transistor

Claims (4)

A first semiconductor substrate having a pixel region in which a plurality of pixels including a photoelectric conversion element are arranged,
A first semiconductor chip portion having a first multilayer wiring layer provided on the first semiconductor substrate, and a first semiconductor chip portion.
The second semiconductor substrate on which the logic circuit was formed and
A second semiconductor chip portion having a second multilayer wiring layer provided on the second semiconductor substrate is provided.
The first multilayer wiring layer is provided on the side opposite to the side where light is incident on the photoelectric conversion element with respect to the first semiconductor substrate.
The first multilayer wiring layer has a first wiring layer and a third wiring layer.
The first wiring layer includes the first wiring portion and the first wiring portion in a direction parallel to the joint surface between the first semiconductor chip portion and the second semiconductor chip portion in a cross-sectional view. Including a second wiring section provided next to it at intervals, including
The third wiring layer comprises a fourth wiring portion and a fifth wiring portion provided adjacent to the fourth wiring portion at a distance from the fourth wiring portion in a direction parallel to the joint surface in a cross-sectional view. Including
The second multilayer wiring layer has a second wiring layer, and the second wiring layer includes a third wiring portion.
The first multilayer wiring layer side of the first semiconductor chip portion and the second multilayer wiring layer side of the second semiconductor chip portion face each other, and the first semiconductor chip portion and the first 2 semiconductor chip parts are laminated,
In a direction perpendicular to the joint surface in a cross-sectional view, the entire distance between the first wiring portion and the second wiring portion has an arrangement that overlaps with the third wiring portion.
In the direction perpendicular to the joint surface in the cross-sectional view, the entire distance between the fourth wiring portion and the fifth wiring portion overlaps with the distance between the first wiring portion and the second wiring portion. It has an arrangement that overlaps with the same third wiring portion arranged at the position.
The first wiring portion, the second wiring portion, the fourth wiring portion, and the fifth wiring portion include the distance between the first wiring portion and the second wiring portion and the distance between the first wiring portion and the second wiring portion. A solid-state imaging device having an arrangement in which the distance between the fourth wiring portion and the fifth wiring portion does not overlap in a direction perpendicular to the joint surface in a cross-sectional view. In a direction perpendicular to the joint surface, at least a part of the first wiring portion and the fourth wiring portion overlaps in a cross-sectional view, and the first wiring portion and the fourth wiring portion are cross-sectionally viewed. The solid-state imaging device according to claim 1, wherein the amount of overlap is larger than the distance between the facing surfaces of the first wiring portion and the fourth wiring portion in a cross-sectional view in the vertical direction. In claim 1, the length of the third wiring portion in a direction parallel to the joint surface in a cross-sectional view is larger than the length of the first wiring portion or the second wiring portion in the parallel direction. The solid-state imaging device described. In a cross-sectional view, the second wiring layer has a plurality of the third wiring portions, and the distance between the third wiring portions adjacent to each other is such that the first wiring portion and the second wiring portion are adjacent to each other. The solid-state imaging device according to claim 1, which is larger than the interval of.

Images