JP6777292B2

JP6777292B2 - PLL circuit and its frequency correction method

Info

Publication number: JP6777292B2
Application number: JP2016155552A
Authority: JP
Inventors: 佐藤　裕樹; 裕樹佐藤
Original assignee: Nisshinbo Holdings Inc; New Japan Radio Co Ltd; Japan Radio Co Ltd; Ueda Japan Radio Co Ltd
Current assignee: Nisshinbo Holdings Inc; New Japan Radio Co Ltd; Japan Radio Co Ltd; Ueda Japan Radio Co Ltd
Priority date: 2016-08-08
Filing date: 2016-08-08
Publication date: 2020-10-28
Anticipated expiration: 2036-08-08
Also published as: JP2018026620A

Description

本発明は、無線通信機の６０ＧＨｚ帯のローカル信号の生成に好適なＰＬＬ(Phase Locked Loop)回路及びその周波数補正方法に関する。 The present invention relates to a PLL (Phase Locked Loop) circuit suitable for generating a local signal in the 60 GHz band of a wireless communication device and a frequency correction method thereof.

ミリ波帯と呼ばれる６０ＧＨｚ帯を使用するような無線通信機を小型、低消費電力で設計する場合は、ダイレクトコンバージョン方式のアーキテクチャが採用されている。ダイレクトコンバージョン方式では、ベースバンド信号帯域を直接６０ＧＨｚ帯にアップコンバートして送信し、あるいは６０ＧＨｚ帯の受信信号を直接ベースバンド帯域にダウンコンバートするが、これらを実現するには、６０ＧＨｚ帯のローカル信号が必要となる。 When designing a wireless communication device that uses a 60 GHz band called a millimeter wave band with a small size and low power consumption, a direct conversion architecture is adopted. In the direct conversion method, the baseband signal band is directly up-converted to the 60 GHz band and transmitted, or the received signal in the 60 GHz band is directly down-converted to the baseband band. To realize these, the local signal in the 60 GHz band is used. Is required.

ローカル信号は、通信に要求されるＳＮＲ（信号対雑音比）を満足させるために、高精度、低位相雑音が求められるため、一般的には、電圧制御発振器（以下、ＶＣＯ：Voltage Controlled Oscllator)、分周器、位相比較器、チャージポンプ回路、ローパスフィルタ（以下、ＬＰＦ：Low pass filter）をループ接続して構成されるＰＬＬ回路を用いて、生成される。 Since local signals are required to have high accuracy and low phase noise in order to satisfy the SNR (signal to noise ratio) required for communication, generally, a voltage controlled oscillator (VCO: Voltage Controlled Oscllator) is used. , A frequency divider, a phase comparator, a charge pump circuit, and a low pass filter (hereinafter, LPF: Low pass filter) are connected in a loop to generate a PLL circuit.

ＶＣＯを低位相雑音化するためには、ＬＣ発振回路で構成するのが一般的であるが、Ｌ（コイル）を用いると、６０ＧＨｚ帯という高周波領域においては、表皮効果から実抵抗が増加し、そのＱが劣化してしまう。ＬＣ発振回路においては、コンデンサのＱに対してコイルのＱが小さいため、ＬＣ発振回路のＱはコイルのＱが支配的となる。このため、６０ＧＨｚ帯という高周波領域でＬＣ発振回路を使用すると、位相雑音特性が大きく劣化してしまい、６４ＱＡＭ変調のように多値化するとき大きな問題となる。 In order to reduce the phase noise of the VCO, it is common to configure it with an LC oscillator circuit, but when L (coil) is used, the actual resistance increases due to the skin effect in the high frequency region of the 60 GHz band. The Q deteriorates. In the LC oscillator circuit, the Q of the coil is smaller than the Q of the capacitor, so that the Q of the LC oscillator circuit is dominated by the Q of the coil. Therefore, if the LC oscillator circuit is used in the high frequency region of 60 GHz band, the phase noise characteristic is greatly deteriorated, which becomes a big problem when the value is increased as in 64QAM modulation.

このようなことから、ＶＣＯの位相雑音特性が劣化している場合、ＰＬＬ回路自体を低位相雑音化するには、ループ帯域を高周波側へ広げる必要があるが、ループ帯域幅は位相比較器の周波数より十分低い値にする必要があるため、限界値が存在する。このため、ＶＣＯの位相雑音をＰＬＬ回路では十分抑圧することができず、６４ＱＡＭ変調のように多値化するとき所望の位相雑音特性を得ることができない。 For this reason, when the phase noise characteristics of the VCO are deteriorated, it is necessary to widen the loop band to the high frequency side in order to reduce the phase noise of the PLL circuit itself, but the loop bandwidth is determined by the phase comparator. There is a limit because it needs to be well below the frequency. Therefore, the phase noise of the VCO cannot be sufficiently suppressed by the PLL circuit, and the desired phase noise characteristic cannot be obtained when the value is increased as in the case of 64QAM modulation.

そこで、これらの問題を解決する手段として、低周波のＶＣＯを使用したＰＬＬ回路によって２０ＧＨｚ帯の周波数信号を生成し、その２０ＧＨｚ帯の周波数信号を高周波帯発振の注入同期型ＶＣＯに入力して、４逓倍した低位相雑音の６０ＨＧｚ帯の周波数信号を生成し、これをローカル信号として使用することが提案されている（非特許文献１）。これは、６４ＱＡＭ変調のように多値化する場合に好適である。 Therefore, as a means for solving these problems, a frequency signal in the 20 GHz band is generated by a PLL circuit using a low frequency VCO, and the frequency signal in the 20 GHz band is input to the injection synchronous VCO for high frequency band oscillation. It has been proposed to generate a frequency signal in the 60 HGz band of low phase noise multiplied by 4, and use this as a local signal (Non-Patent Document 1). This is suitable for multi-valued cases such as 64QAM modulation.

また、ＰＬＬ回路の低消費電力化の観点から、分周器として注入同期型分周器（ＩＬＦＤ：Injection Locked Frequency Divider）が採用されることがある。注入同期型分周器は注入信号の立ち上がりエッジによる位相引き込み（プリング現象）を利用するトポロジであり、低位相雑音且つ低消費電力に適した分周器として知られている。 Further, from the viewpoint of reducing the power consumption of the PLL circuit, an injection synchronous frequency divider (ILFD) may be adopted as the frequency divider. The injection synchronous divider is a topology that utilizes phase pulling (pulling phenomenon) due to the rising edge of the injection signal, and is known as a divider suitable for low phase noise and low power consumption.

以上の注入同期型ＶＣＯや注入同期型分周器を正常動作させるには、それらのフリーラン周波数を予め所望の周波数に調整する必要があるが、それらのフリーラン発振周波数はウェハプロセス変動や周囲環境変化により変動する。そのため、ウェハプロセス変動や周囲環境変化による周波数変動量を補正する技術が必要となっている。その技術としては、例えば、特許文献１に記載のものがある。 In order for the above injection synchronous VCO and injection synchronous divider to operate normally, it is necessary to adjust their free run frequencies to desired frequencies in advance, but these free run oscillation frequencies are due to wafer process fluctuations and surroundings. It fluctuates due to changes in the environment. Therefore, there is a need for a technique for correcting the amount of frequency fluctuation due to wafer process fluctuations and changes in the surrounding environment. As the technique, for example, there is one described in Patent Document 1.

特許第５８４１９９３号公報Japanese Patent No. 5841993 "A 64QAM 60GHz CMOS Transceiver with 4-Channel Bonding" IEEE International Solid-State Circuits Conference (ISSCC),San Francisco CA. pp.346-347,Feb.2014"A 64QAM 60GHz CMOS Transceiver with 4-Channel Bonding" IEEE International Solid-State Circuits Conference (ISSCC), San Francisco CA. Pp.346-347, Feb. 2014

ところが、ウェハプロセス変動や周囲環境変化に対する補正手段として上記した従来技術を組み合わせると、次のようなＰＬＬ回路が構成される。 However, when the above-mentioned conventional techniques are combined as correction means for wafer process fluctuations and changes in the surrounding environment, the following PLL circuit is configured.

すなわち、基準周波数信号と帰還周波数信号との位相を比較する位相比較器と、該位相比較器の比較結果に応じた電圧を出力するチャージポンプ回路と、該チャージポンプ回路の出力電圧から低周波成分を取り出すローパスフィルタと、該ローパスフィルタの出力電圧に応じた周波数で発振するＶＣＯと、該ＶＣＯで発振した周波数信号を注入信号として入力して分周する注入同期型分周器と、該注入同期型分周器の出力信号を分周して前記帰還周波数信号とする通常の分周器とでＰＬＬループを形成し、ＶＣＯの出力周波数信号を注入同期信号として入力してそのＶＣＯで発振した周波数信号の整数倍の周波数信号を発振する注入同期型ＶＣＯを接続し、その注入同期型ＶＣＯの出力周波数信号をローカル信号として出力するＰＬＬ回路が構成される。 That is, a phase comparator that compares the phases of the reference frequency signal and the feedback frequency signal, a charge pump circuit that outputs a voltage corresponding to the comparison result of the phase comparator, and a low frequency component from the output voltage of the charge pump circuit. A low-pass filter that takes out a low-pass filter, a VCO that oscillates at a frequency corresponding to the output voltage of the low-pass filter, an injection-synchronized frequency divider that inputs a frequency signal oscillated by the VCO as an injection signal and divides the frequency, and the injection synchronization. A PLL loop is formed with a normal frequency divider that divides the output signal of the type divider to obtain the feedback frequency signal, and the output frequency signal of the VCO is input as an injection synchronization signal and the frequency oscillated by the VCO. A PLL circuit is configured in which an injection synchronous VCO that oscillates a frequency signal that is an integral multiple of the signal is connected and the output frequency signal of the injection synchronous VCO is output as a local signal.

そして、注入同期型分周器→ＶＣＯ→分周器注入同期型ＶＣＯの順序で、それらのフリーラン周波数補正を行うことが容易に想像できる。 Then, it is easy to imagine that the free-run frequency correction is performed in the order of injection synchronous divider → VCO → frequency divider injection synchronous VCO.

しかしながら、この手法では、図１１の（ｂ）に示すように、時間Ｔ２１で注入同期型分周器のフリーラン周波数補正を行い、時間Ｔ２２でＶＣＯのフリーラン周波数補正を行い、その後に時間Ｔ２３でＰＬＬ回路のロックアップを待ち、さらに時間Ｔ２４で注入同期型ＶＣＯの注入同期ＶＣＯのフリーラン周波数補正を行い、その後に、時間Ｔ２５で注入同期型ＶＣＯのロックアップを待つ必要がある。ロックアップのための時間Ｔ２３、Ｔ２５は、時間Ｔ２１，Ｔ２２、Ｔ２４に比べてかなり長い時間である。 However, in this method, as shown in FIG. 11B, the free-run frequency correction of the injection synchronous divider is performed at time T21, the free-run frequency correction of the VCO is performed at time T22, and then the time T23. It is necessary to wait for the lockup of the PLL circuit at, further to perform the free-run frequency correction of the injection synchronous VCO of the injection synchronous VCO at time T24, and then wait for the lockup of the injection synchronous VCO at time T25. The time T23, T25 for lockup is considerably longer than the time T21, T22, T24.

このように、長い時間のかかるロックアップ時間を２重に待つ必要があるので、結果として周波数補正が完了するまでにかかる時間が長くなる。また、この場合は、ＰＬＬループのフリーラン周波数補正に対応した補正シーケンスとそのＰＬＬループから外れている注入同期型ＶＣＯのフリーラン周波数の補正に対応した補正シーケンスが別個に必要となる。このため、回路規模の増大を招き、結果として消費電力の増大とチップコストの増大を招いてしまう問題がある。 In this way, it is necessary to wait twice for the lockup time, which takes a long time, and as a result, the time required for the frequency correction to be completed becomes long. Further, in this case, a correction sequence corresponding to the free-run frequency correction of the PLL loop and a correction sequence corresponding to the correction of the free-run frequency of the injection-synchronized VCO out of the PLL loop are separately required. Therefore, there is a problem that the circuit scale is increased, and as a result, the power consumption is increased and the chip cost is increased.

本発明の目的は、回路規模の増大を防いで低消費電力化を実現するとともに、フリーラン周波数の補正時間を大幅に短縮でき、最終的なロックアップまでの時間を短縮できるようにしたＰＬＬ回路及びその周波数補正方法を提供することである。 An object of the present invention is a PLL circuit that prevents an increase in the circuit scale, realizes low power consumption, can significantly shorten the correction time of the free run frequency, and can shorten the time until the final lockup. And its frequency correction method.

上記目的を達成するために、本願請求項１にかかる発明のＰＬＬ回路は、基準周波数信号と帰還周波数信号との位相を比較する位相比較器と、該位相比較器の比較結果に応じた電圧を出力するチャージポンプ回路と、該チャージポンプ回路の出力電圧から低周波成分を取り出すローパスフィルタと、該ローパスフィルタの出力電圧に応じた周波数で発振する第１ＶＣＯと、該第１ＶＣＯで発振した周波数信号を注入同期信号として入力して前記第１ＶＣＯで発振した周波数信号の整数倍の周波数信号を発振する注入同期型の第２ＶＣＯと、該第２ＶＣＯで発振した周波数信号を注入信号として入力して該注入信号の周波数を前記第１ＶＣＯの発振周波数と同じ周波数に分周する注入同期型の第１分周器と、前記第１ＶＣＯで発振した周波数信号又は前記第１分周器の出力周波数信号を注入信号として入力して該注入信号の周波数を分周する注入同期型の第２分周器と、前記基準周波数信号を分周する固定の第３分周器とを備え、前記第２分周器の出力周波数信号をそのまま又は第１任意数だけ分周して前記帰還周波数信号とするＰＬＬ回路において、前記第３分周器で分周された周波数信号の周波数で決まる所定期間の間、前記第２分周器の出力周波数信号又は前記第２分周器の出力周波数信号を第２任意数だけ分周した周波数信号のパルスをカウントするカウンタと、該カウンタのカウント値に応じて、前記第１ＶＣＯ、前記第２ＶＣＯ、前記第１分周器、及び前記第２分周器のフリーラン周波数を個々に補正するシーケンサと、を有し、該シーケンサは、前記第１ＶＣＯ、前記第２ＶＣＯ、及び前記第１分周器の出力を前記ＰＬＬ回路から分離した状態で、前記第２分周器をフリーラン発振させ、そのとき得られる前記カウンタのカウント値に応じて前記第２分周器のフリーラン周波数を補正する第１処理と、該第１処理の後に、前記第１ＶＣＯ及び前記第２ＶＣＯの出力を前記ＰＬＬ回路から分離し、且つ前記第１分周器をフリーラン発振させた状態で、前記第１分周器の出力周波数信号をフリーラン周波数が補正済の前記第２分周器に注入して、そのとき得られる前記カウンタのカウント値に応じて前記第１分周器のフリーラン周波数を補正する第２処理と、該第２処理の後に、前記第１ＶＣＯの出力を前記ＰＬＬ回路から分離し、且つ前記第１及び第２分周器をそれぞれ補正済のフリーラン周波数で発振させた状態で、前記第２ＶＣＯをフリーラン発振させ、そのとき得られる前記カウンタのカウント値に応じて前記第２ＶＣＯのフリーラン周波数を補正する第３処理と、該第３処理の後に、前記第１分周器の出力を前記ＰＬＬ回路から分離し、前記第２分周器を補正済のフリーラン周波数で発振させた状態で、前記第１ＶＣＯを固定電圧でフリーラン発振させて、前記第１ＶＣＯの出力周波数を前記第２分周器に入力させ、そのとき得られる前記カウンタのカウント値に応じて前記第１ＶＣＯのフリーラン周波数を補正する第４処理と、該第４処理の後に、前記ＰＬＬ回路のロックアップと前記第１ＶＣＯの出力周波数信号を注入信号とする前記第２ＶＣＯのロックアップとを同時に行う第５処理と、をコンピュータに実行させるプログラムを有することを特徴とする。 In order to achieve the above object, the PLL circuit of the invention according to claim 1 of the present application applies a phase comparator for comparing the phases of the reference frequency signal and the feedback frequency signal and a voltage corresponding to the comparison result of the phase comparator. A charge pump circuit that outputs, a low-pass filter that extracts low-frequency components from the output voltage of the charge pump circuit, a first VCO that oscillates at a frequency corresponding to the output voltage of the low-pass filter, and a frequency signal that oscillates at the first VCO. An injection-synchronized second VCO that inputs as an injection-synchronized signal and oscillates a frequency signal that is an integral multiple of the frequency signal oscillated by the first VCO, and an injection-synchronized second VCO that oscillates at the second VCO as an injection signal and the injection signal. The injection synchronous type first frequency divider that divides the frequency of the first VCO to the same frequency as the oscillation frequency of the first VCO, and the frequency signal oscillated by the first VCO or the output frequency signal of the first frequency divider are used as injection signals. An injection synchronous type second divider that inputs and divides the frequency of the injection signal and a fixed third divider that divides the reference frequency signal are provided, and the output of the second divider is provided. In the PLL circuit that divides the frequency signal as it is or by the first arbitrary number to obtain the feedback frequency signal, the second division is performed for a predetermined period determined by the frequency of the frequency signal divided by the third frequency divider. A counter that counts the pulse of the output frequency signal of the oscillator or the frequency signal obtained by dividing the output frequency signal of the second oscillator by a second arbitrary number, and the first VCO, the first VCO, according to the count value of the counter. It has a second VCO, the first divider, and a sequencer that individually corrects the free-run frequency of the second divider , and the sequencer includes the first VCO, the second VCO, and the first minute. With the output of the peripheral device separated from the PLL circuit, the second frequency divider is oscillated free-run, and the free-run frequency of the second frequency divider is corrected according to the count value of the counter obtained at that time. After the first process and the first process, the outputs of the first VCO and the second VCO are separated from the PLL circuit, and the first frequency divider is oscillated by free run. The output frequency signal of the oscillator is injected into the second frequency divider whose free run frequency has been corrected, and the free run frequency of the first oscillator is corrected according to the count value of the counter obtained at that time. After the second process and the second process, the output of the first VCO is separated from the PLL circuit, and the first and second dividers are oscillated at corrected free-run frequencies, respectively. In this state, the second VCO is oscillated in a free run, and the free run frequency of the second VCO is corrected according to the count value of the counter obtained at that time. After the third process, the first minute The output of the peripheral device is separated from the PLL circuit, the first VCO is oscillated at a fixed voltage in a state where the second frequency divider is oscillated at the corrected free-run frequency, and the output of the first VCO is oscillated. A fourth process of inputting a frequency to the second frequency divider and correcting the free-run frequency of the first VCO according to the count value of the counter obtained at that time, and after the fourth process, of the PLL circuit It is characterized by having a program for causing a computer to execute a fifth process of simultaneously performing lockup and lockup of the second VCO using the output frequency signal of the first VCO as an injection signal .

請求項２にかかる発明のＰＬＬ回路の周波数補正方法は、基準周波数信号と帰還周波数信号との位相を比較する位相比較器と、該位相比較器の比較結果に応じた電圧を出力するチャージポンプ回路と、該チャージポンプ回路の出力電圧から低周波成分を取り出すローパスフィルタと、該ローパスフィルタの出力電圧に応じた周波数で発振する第１ＶＣＯと、該第１ＶＣＯで発振した周波数信号を注入同期信号として入力して前記第１ＶＣＯで発振した周波数信号の整数倍の周波数信号を発振する注入同期型の第２ＶＣＯと、該第２ＶＣＯで発振した周波数信号を注入信号として入力して該注入信号の周波数を前記第１ＶＣＯの発振周波数と同じ周波数に分周する注入同期型の第１分周器と、前記第１ＶＣＯで発振した周波数信号又は前記第１分周器の出力周波数信号を注入信号として入力して該注入信号の周波数を分周する注入同期型の第２分周器と、前記基準周波数信号を分周する固定の第３分周器とを備え、前記第２分周器の出力周波数信号をそのまま又は第１任意数だけ分周して前記帰還周波数信号とするＰＬＬ回路の、前記第１ＶＣＯ、前記第２ＶＣＯ、前記第１分周器、及び前記第２分周器のフリーラン周波数を補正するＰＬＬ回路の周波数補正方法において、前記第３分周器で分周された周波数信号の周波数で決まる所定期間の間の、前記第２分周器の出力周波数信号又は前記第２分周器の出力周波数信号を第２任意数だけ分周した周波数信号のパルス数に応じて、前記第１ＶＣＯ、前記第２ＶＣＯ、前記第１分周器、及び前記第２分周器のフリーラン周波数を個々に補正するものであって、前記第１ＶＣＯ、前記第２ＶＣＯ、及び前記第１分周器の出力を前記ＰＬＬ回路から分離した状態で、前記第２分周器をフリーラン発振させ、そのとき得られる前記パルス数に応じて前記第２分周器のフリーラン周波数を補正する第１処理と、該第１処理の後に、前記第１ＶＣＯ及び前記第２ＶＣＯの出力を前記ＰＬＬ回路から分離し、且つ前記第１分周器をフリーラン発振させた状態で、前記第１分周器の出力周波数信号をフリーラン周波数が補正済の前記第２分周器に注入して、そのとき得られる前記パルス数に応じて前記第１分周器のフリーラン周波数を補正する第２処理と、該第２処理の後に、前記第１ＶＣＯの出力を前記ＰＬＬ回路から分離し、且つ前記第１及び第２分周器をそれぞれ補正済のフリーラン周波数で発振させた状態で、前記第２ＶＣＯをフリーラン発振させ、そのとき得られる前記パルス数に応じて前記第２ＶＣＯのフリーラン周波数を補正する第３処理と、該第３処理の後に、前記第１分周器の出力を前記ＰＬＬ回路から分離し、前記第２分周器を補正済のフリーラン周波数で発振させた状態で、前記第１ＶＣＯを固定電圧でフリーラン発振させて、前記第１ＶＣＯの出力周波数を前記第２分周器に入力させ、そのとき得られる前記パルス数に応じて前記第１ＶＣＯのフリーラン周波数を補正する第４処理と、該第４処理の後に、前記ＰＬＬ回路のロックアップと前記第１ＶＣＯの出力周波数信号を注入信号とする前記第２ＶＣＯのロックアップとを同時に行う第５処理と、を有することを特徴とする。 The frequency correction method of the PLL circuit according to claim 2 is a phase comparator that compares the phase of a reference frequency signal and a feedback frequency signal, and a charge pump circuit that outputs a voltage according to the comparison result of the phase comparator. A low-pass filter that extracts low-frequency components from the output voltage of the charge pump circuit, a first VCO that oscillates at a frequency corresponding to the output voltage of the low-pass filter, and a frequency signal oscillated by the first VCO are input as injection synchronization signals. Then, an injection-synchronized second VCO that oscillates a frequency signal that is an integral multiple of the frequency signal oscillated by the first VCO and a frequency signal oscillated by the second VCO are input as injection signals, and the frequency of the injection signal is set to the first. The injection synchronous type first divider that divides the frequency to the same frequency as the oscillation frequency of 1VCO and the frequency signal oscillated by the first VCO or the output frequency signal of the first divider are input as injection signals and the injection is performed. An injection-synchronized second divider that divides the frequency of the signal and a fixed third divider that divides the reference frequency signal are provided, and the output frequency signal of the second divider can be used as it is or The PLL circuit that corrects the free-run frequency of the first VCO, the second VCO, the first divider, and the second divider of the PLL circuit that divides by the first arbitrary number to obtain the feedback frequency signal. In the frequency correction method of, the output frequency signal of the second oscillator or the output frequency signal of the second oscillator for a predetermined period determined by the frequency of the frequency signal divided by the third oscillator. The free-run frequency of the first VCO, the second VCO, the first frequency divider, and the second frequency divider is individually corrected according to the number of pulses of the frequency signal obtained by dividing the frequency signal by a second arbitrary number. The number of pulses obtained by free-run oscillating the second divider with the outputs of the first VCO, the second VCO, and the first divider separated from the PLL circuit. After the first process of correcting the free-run frequency of the second frequency divider according to the above and the first process, the outputs of the first VCO and the second VCO are separated from the PLL circuit, and the first minute With the perimeter oscillating free-run, the output frequency signal of the first divider is injected into the second divider whose free-run frequency has been corrected, and according to the number of pulses obtained at that time. After the second process of correcting the free-run frequency of the first frequency divider and the second process, the output of the first VCO is separated from the PLL circuit, and the first and second dividers are separated from each other, respectively. Corrected free run lap A third process in which the second VCO is oscillated in a free-run state while oscillating at a wave number, and the free-run frequency of the second VCO is corrected according to the number of pulses obtained at that time, and after the third process, the above-mentioned The output of the first divider is separated from the PLL circuit, and the first VCO is oscillated at a fixed voltage in a state where the second divider is oscillated at a corrected free-run frequency. A fourth process in which the output frequency of 1 VCO is input to the second frequency divider and the free run frequency of the first VCO is corrected according to the number of pulses obtained at that time, and after the fourth process, the PLL circuit It is characterized by having a fifth process of simultaneously performing the lockup of the first VCO and the lockup of the second VCO using the output frequency signal of the first VCO as an injection signal .

本発明によれば、第１ＶＣＯ、第２ＶＣＯ、第１分周器、及び第２分周器のフリーラン周波数を、それらのフリーラン周波数に対応した周波数信号についてのパルスの所定時間内の数によって計測して補正するので、その検出を共用することができ、回路規模の増大化を防ぐことができ、チップコストの低減と低消費電流化に大きく貢献できる。また、第１ＶＣＯのロックアップ時に第２ＶＣＯのロックアップも同時に行うことができ、補正時間の増大による電力消費を削減することが可能となる。 According to the present invention, the free run frequencies of the first VCO, the second VCO, the first divider, and the second divider are determined by the number of pulses within a predetermined time for the frequency signals corresponding to those free run frequencies. Since the measurement is performed and corrected, the detection can be shared, the increase in the circuit scale can be prevented, and the chip cost can be reduced and the current consumption can be greatly reduced. Further, when the first VCO is locked up, the second VCO can be locked up at the same time, and it is possible to reduce the power consumption due to the increase in the correction time.

本発明の実施例のＰＬＬ回路の回路図である。It is a circuit diagram of the PLL circuit of the Example of this invention. （ａ）は図１のＰＬＬ回路の分周器１３の詳細回路図、（ｂ）は図１のＰＬＬ回路の分周器１２、分周器１３の動作波形図、（ｃ）は計測、補正、確認の説明図である。(A) is a detailed circuit diagram of the divider 13 of the PLL circuit of FIG. 1, (b) is an operation waveform diagram of the divider 12 and the divider 13 of the PLL circuit of FIG. 1, and (c) is measurement and correction. , It is explanatory drawing of confirmation. （ａ）は図１のＰＬＬ回路のシーケンサ１５の内部構成を示すブロック図、（ｂ）は図１のＰＬＬ回路のシーケンサ１５によるフリーラン周波数補正のフローチャートである。(A) is a block diagram showing an internal configuration of the sequencer 15 of the PLL circuit of FIG. 1, and (b) is a flowchart of free-run frequency correction by the sequencer 15 of the PLL circuit of FIG. 図１のＰＬＬ回路のシーケンサ１５によるＶＣＯ４、６、分周器８、９のフリーラン周波数補正のフローチャートである。It is a flowchart of the free run frequency correction of VCO4, 6, and dividers 8 and 9 by the sequencer 15 of the PLL circuit of FIG. 図１のＰＬＬ回路の注入同期型１／４分周器９の回路図である。It is a circuit diagram of the injection synchronous type 1/4 divider 9 of the PLL circuit of FIG. （ａ）、（ｂ）は図１のＰＬＬ回路の注入同期型１／３分周器９の特性図である。(A) and (b) are characteristic diagrams of the injection synchronous type 1/3 divider 9 of the PLL circuit of FIG. 図１のＰＬＬ回路の注入同期型１／３分周器８の回路図である。It is a circuit diagram of the injection synchronous type 1/3 divider 8 of the PLL circuit of FIG. （ａ）、（ｂ）は図１のＰＬＬ回路の注入同期型１／３分周器８の特性図である。(A) and (b) are characteristic diagrams of the injection synchronous type 1/3 divider 8 of the PLL circuit of FIG. 図１のＰＬＬ回路の注入同期型ＶＣＯ６の回路図である。It is a circuit diagram of the injection synchronous type VCO6 of the PLL circuit of FIG. 図１のＰＬＬ回路の注入同期型ＶＣＯ４の回路図である。It is a circuit diagram of the injection synchronous type VCO4 of the PLL circuit of FIG. （ａ）は図４のフローチャートを使用してＰＬＬ回路のフリーラン周波数の補正を行うタイムテーブル、（ｂ）は従来のＰＬＬ回路のフリーラン周波数の補正を行うタイムテーブルである。(A) is a timetable for correcting the free-run frequency of the PLL circuit using the flowchart of FIG. 4, and (b) is a timetable for correcting the free-run frequency of the conventional PLL circuit.

＜実施例＞
図１に本発明のＰＬＬ回路の１つの実施例を示す。図１において、１は入力する基準周波数信号ｆ１（３６ＭＨｚ）と帰還周波数信号ｆ９の位相を比較する比較器、２は位相比較器１から出力する位相進み信号又は位相遅れ信号に応じた電圧信号を出力するチャージポンプ回路、３はチャージポンプ回路２から出力する信号から高周波成分を除去するローパスフィルタ、４はローパスフィルタ３の出力電圧に応じた周波数信号ｆ４（２０ＧＨｚ帯）を発振するＶＣＯである。 <Example>
FIG. 1 shows one embodiment of the PLL circuit of the present invention. In FIG. 1, 1 is a comparator that compares the phases of the input reference frequency signal f1 (36 MHz) and the feedback frequency signal f9, and 2 is a voltage signal corresponding to the phase lead signal or phase delay signal output from the phase comparator 1. The output charge pump circuit 3 is a low-pass filter that removes high-frequency components from the signal output from the charge pump circuit 2, and 4 is a VCO that oscillates a frequency signal f4 (20 GHz band) corresponding to the output voltage of the low-pass filter 3.

５はＶＣＯの出力周波数信号ｆ４を増幅するバッファ回路、６はバッファ回路５から出力する周波数信号ｆ４を注入同期信号としてその注入同期信号の所定逓倍数（３倍）の高周波信号ｆ５（６０ＧＨｚ帯）を発振する注入同期型ＶＣＯである。本実施例ＰＬＬ回路では、この注入同期型ＶＣＯ６の発振周波数信号ｆ５をローカル信号として図示しない送受信機に出力する。 5 is a buffer circuit that amplifies the output frequency signal f4 of the VCO, and 6 is a high frequency signal f5 (60 GHz band) that is a predetermined multiple (3 times) of the injection synchronization signal using the frequency signal f4 output from the buffer circuit 5 as an injection synchronization signal. It is an injection synchronous VCO that oscillates. In the PLL circuit of this embodiment, the oscillation frequency signal f5 of the injection synchronous VCO6 is output as a local signal to a transmitter / receiver (not shown).

７は注入同期型ＶＣＯ６の出力発振周波数信号ｆ５を増幅するバッファ回路、８はバッファ回路７から出力する周波数信号ｆ５を注入同期信号として入力して３分周した周波数信号ｆ６（２０ＨＧｚ帯）を発振する注入同期型１／３分周器である。 Reference numeral 7 is a buffer circuit that amplifies the output oscillation frequency signal f5 of the injection synchronous VCO6, and 8 is a frequency signal f6 (20 HGz band) that is divided by 3 by inputting the frequency signal f5 output from the buffer circuit 7 as an injection synchronous signal and oscillating. It is an injection synchronous type 1/3 frequency divider.

９はＶＣＯ４から出力する周波数信号ｆ４又は注入同期型１／３分周器８から出力する周波数信号ｆ６を注入同期信号として入力して４分周した周波数信号ｆ７（５ＨＧｚ帯）を発振する注入同期型１／４分周器、１０は注入同期型１／４分周器９から出力する周波数信号ｆ７を５分周した周波数ｆ８信号（１ＨＧｚ帯）にする固定の１／５分周器、１１は１／５分周器１０から出力する周波数信号ｆ８を基準周波数信号ｆ１（３６ＭＨｚ）になるよう分周して位相比較器１の前記した帰還周波数信号ｆ９とする可変分周器である。 Reference numeral 9 denotes an injection synchronization in which the frequency signal f4 output from the VCO 4 or the frequency signal f6 output from the injection synchronization type 1/3 divider 8 is input as an injection synchronization signal and the frequency signal f7 (5HGz band) divided by 4 is oscillated. Type 1/4 divider, 10 is a fixed 1/5 divider that converts the frequency signal f7 output from the injection synchronous 1/4 divider 9 into a frequency f8 signal (1HGz band) divided by 5; Is a variable divider that divides the frequency signal f8 output from the 1/5 divider 10 so as to become a reference frequency signal f1 (36 MHz) to obtain the feedback frequency signal f9 described above in the phase comparator 1.

１２は基準周波数信号ｆ１（３６ＭＨ）を１２８分周して周波数信号ｆ２（２８１．２５ｋＨｚ）にする１／１２８分周器、１３は１／１２８分周器１２から出力する周波数信号ｆ２を１／２分周してデューティ比が５０％の周波数信号ｆ３を生成する１／２分周器、１４は１／２分周器１３から出力する周波数信号ｆ３のパルス幅（周波数ｆ３の周期の１／２、つまり周波数ｆ２の周期）の期間に１／５分周器１０から入力する周波数信号ｆ８のパルス数をカウントするカウンタである。 Reference numeral 12 is a 1/128 divider that divides the reference frequency signal f1 (36 MH) by 128 to obtain a frequency signal f2 (281.25 kHz), and 13 is a 1/128 divider that divides the frequency signal f2 output from the 1/128 divider 12 by 1 /. A 1/2 divider that divides by 2 to generate a frequency signal f3 with a duty ratio of 50%, and 14 is the pulse width of the frequency signal f3 output from the 1/2 divider 13 (1/1 of the period of the frequency f3). This is a counter that counts the number of pulses of the frequency signal f8 input from the 1/5 divider 10 during the period of 2, that is, the period of the frequency f2).

１／２分周器１３は、図２（ａ）に示すように、ＤＦＦ回路１３１とインバータ１３２で構成されている。前段の１／１２８分周器１２によって基準周波数信号ｆ１（＝３６ＭＨｚ）を１２８分周した周波数信号ｆ２（＝２８１．２５ｋＨｚ）が得られ、その周期Ｔ１は１／ｆ２（≒３．５５５μｓｅｃ）である。この周波数信号ｆ２が１／２分周器１３において２分周されることにより、デューティ比が５０％の周波数信号ｆ３となる。この周波数信号ｆ３のパルス幅Ｔ１は、図２（ｂ）に示すように、周波数信号ｆ２の周期に対応したパルス幅信号となり、カウンタ１４にイネーブル信号として入力する。カウンタ１４はこの周期Ｔ１の期間に１／５分周器１０から入力する周波数信号ｆ８のパルス数をカウントする。 As shown in FIG. 2A, the 1/2 frequency divider 13 includes a DFF circuit 131 and an inverter 132. A frequency signal f2 (= 281.25 kHz) obtained by dividing the reference frequency signal f1 (= 36 MHz) by 128 is obtained by the 1/128 divider 12 in the previous stage, and its period T1 is 1 / f2 (≈3.555 μsec). is there. By dividing the frequency signal f2 by 2 in the 1/2 frequency divider 13, the frequency signal f3 has a duty ratio of 50%. As shown in FIG. 2B, the pulse width T1 of the frequency signal f3 becomes a pulse width signal corresponding to the period of the frequency signal f2, and is input to the counter 14 as an enable signal. The counter 14 counts the number of pulses of the frequency signal f8 input from the 1/5 divider 10 during the period T1.

周期Ｔ１の期間にカウンタ１４に入力する周波数ｆ８のパルス数Ｐ１は、
Ｐ１＝（１／ｆ２）／（１／ｆ８）
＝（１２８／ｆ１）／（１／ｆ８）
＝１２８×（ｆ８／ｆ１）（１）
で求まるので、ＶＣＯ４の発振周波数ｆ４を２０．１６ＨＧｚとした場合の周波数ｆ８の期待値を１．００８ＧＨｚとすると、
Ｐ１＝１２８×（１．００８×１０⁹）／（３６×１０⁶）
＝３５８４
となる。つまり、１／２分周器１０から出力する周波数信号ｆ８の期待（目標）周波数が１．００８ＧＨｚのときのカウントＰ１は３５８４となり、これが期待カウント値Ｐ０となる。 The number of pulses P1 of the frequency f8 input to the counter 14 during the period T1 is
P1 = (1 / f2) / (1 / f8)
= (128 / f1) / (1 / f8)
= 128 × (f8 / f1) (1)
Therefore, assuming that the expected value of the frequency f8 is 1.08 GHz when the oscillation frequency f4 of VCO4 is 20.16 HGz,
P1 = 128 × (1.08 × 10 ⁹ ) / (36 × 10 ⁶ )
= 3584
Will be. That is, when the expected (target) frequency of the frequency signal f8 output from the 1/2 frequency divider 10 is 1.008 GHz, the count P1 is 3584, which is the expected count value P0.

そして、カウント値が１だけ増えてＰ１＝３５８５となったときの周波数信号ｆ８’は、式（１）から、
ｆ８’＝Ｐ１×ｆ１×（１／１２８）（２）
＝３５８５×３６×１０⁶／１２８＝１．００８２８１２５ＧＨｚ
となる。つまり、カウンタ１４の１カウントは２８１．２５ｋＨｚを示すことになり、カウンタ１４は２８１．２５ｋＨｚの分解能を有することになる。これを誤差で表せば、１カウント当たりの周波数ｆ８の検出誤差Ｅ１は、
Ｅ１＝｛（ｆ８’−ｆ８）／ｆ８｝×１００（％）
＝０．０２７９（％）
となり、きわめて高精度で周波数ｆ８を検出することができる。ＶＣＯ４の発振周波数ｆ４は２０．１６ＧＨｚ帯であるので、その周波数ｆ４の１カウント当たりの検出誤差Ｅ２は、
Ｅ２＝２０．１６ＧＨｚ×０．０００２７９＝５．６２ＭＨｚ
となる。 Then, the frequency signal f8'when the count value is increased by 1 to P1 = 3585 is obtained from the equation (1).
f8'= P1 x f1 x (1/128) (2)
= 3585 × 36 × 10 ⁶ /128=1.00828125GHz
Will be. That is, one count of the counter 14 indicates 281.25 kHz, and the counter 14 has a resolution of 281.25 kHz. Expressing this as an error, the detection error E1 of the frequency f8 per count is
E1 = {(f8'-f8) / f8} x 100 (%)
= 0.0279 (%)
Therefore, the frequency f8 can be detected with extremely high accuracy. Since the oscillation frequency f4 of VCO4 is in the 20.16 GHz band, the detection error E2 per count of the frequency f4 is
E2 = 20.16GHz x 0.000279 = 5.62MHz
Will be.

１５はシーケンサであり、フリーラン周波数補正時にカウンタ１４が時間Ｔ１だけ周波数ｆ８のパルスをカウントしたカウント値Ｐ１と期待カウント値Ｐ０との差分を求めて、現在の補正対象となっているＶＣＯ４、注入同期型ＶＣＯ６、注入同期型１／３分周器８、又は注入同期型１／４分周器９に、フリーラン周波数の補正信号を出力する。また、その補正処理のために、スイッチＳＷ１〜ＳＷ４のＯＮ／ＯＦＦ、バッファ回路５、７、注入同期型１／３分周器８のＯＮ／ＯＦＦの切替信号を出力する。 Reference numeral 15 denotes a sequencer, and the counter 14 obtains the difference between the count value P1 and the expected count value P0, which count the pulses of the frequency f8 for the time T1 at the time of free-run frequency correction, and injects the VCO4, which is the current correction target. The correction signal of the free run frequency is output to the synchronous VCO6, the injection synchronous 1/3 divider 8, or the injection synchronous 1/4 divider 9. Further, for the correction process, ON / OFF switching signals of switches SW1 to SW4, buffer circuits 5 and 7, and injection synchronous 1/3 frequency divider 8 are output.

図３（ａ）はシーケンサ１６におけるフリーラン周波数補正の機能ブロックであり、カウンタ１４のカウント値Ｐ１を判定するカウント値判定部１５１と、得られたカウント値Ｐ１に応じてフリーラン周波数の補正信号を出力する制御部１５２を備える。 FIG. 3A is a function block for free-run frequency correction in the sequencer 16, and is a count value determination unit 151 for determining the count value P1 of the counter 14, and a free-run frequency correction signal according to the obtained count value P1. The control unit 152 for outputting the above is provided.

図３（ｂ）は制御部１５２での補正処理のフローチャートである。フリーラン周波数補正が開始される（Ｓ１）と、現在のカウント値Ｐ１が図２（ｃ）の時刻ｔ１で判定され（Ｓ２）、そのカウント値Ｐ１が期待カウント値Ｐ０であれば終了する（Ｓ３）。しかし、そうでない場合は、得られたカウント値Ｐ１と期待カウント値Ｐ０との差分（Ｐ１−Ｐ０）を検出し（Ｓ４）、その差分に応じてフリーラン周波数の補正値を出力し（Ｓ５）、図２（ｃ）の時刻ｔ１〜ｔ２の期間で補正が行われる。そして、次のカウント期間Ｔ１が経過した時刻ｔ３において確認が行われ、Ｐ１＝Ｐ０であれば補正が完了する（Ｓ３）。 FIG. 3B is a flowchart of the correction process in the control unit 152. When the free run frequency correction is started (S1), the current count value P1 is determined at the time t1 in FIG. 2 (c) (S2), and if the count value P1 is the expected count value P0, it ends (S3). ). However, if this is not the case, the difference (P1-P0) between the obtained count value P1 and the expected count value P0 is detected (S4), and the correction value of the free run frequency is output according to the difference (S5). , The correction is performed in the period of time t1 to t2 in FIG. 2C. Then, the confirmation is performed at the time t3 when the next count period T1 has elapsed, and if P1 = P0, the correction is completed (S3).

フリーラン周波数の補正を行う際、後記する図５、図７の分周回路ではバイアス切替方式を採用しているので、差分（Ｐ１−Ｐ０）に応じてバイアス電圧を調整して行う。また、後記する図９、図１０のＶＣＯではキャパシタバンク切替方式を採用しているので、キャパシタバンク回路のステップ周波数をＦｓ（ＭＨｚ）とすると、
α・（Ｐ１−Ｐ０）／（Ｆｓ×１００）（３）
の計算式からその整数部を算出して、得られた整数値に応じた補正を行う。なお、αはＶＣＯ４とＰＬＬ回路との関係で決まる定数である。例えば、α＝１１２５、Ｆｓ＝５５ＭＨｚ、Ｐ１＝３６００の例では、式（３）は、
[１１２５／（５５×１００）]×（３６００−３５８４）＝３（小数点以下切下）
となり、キャパシタバンクを現在のステップから３段切り替えることになる。このようにして、ほとんどの補正処理は最長でも時刻ｔ３の時点で完了する。つまり、補正に要する時間は、通常では最長３×Ｔ１（≒１０．６６５μｓｅｃ）となる。ただし、補正はＰ１＝Ｐ０になるまで行われるので、３×Ｔ１を超える場合もあり得る。 When correcting the free-run frequency, since the bias switching method is adopted in the frequency dividing circuits of FIGS. 5 and 7 described later, the bias voltage is adjusted according to the difference (P1-P0). Further, since the VCO of FIGS. 9 and 10 described later adopts the capacitor bank switching method, assuming that the step frequency of the capacitor bank circuit is Fs (MHz),
α ・ (P1-P0) / (Fs × 100) (3)
The integer part is calculated from the formula of, and correction is performed according to the obtained integer value. In addition, α is a constant determined by the relationship between VCO4 and the PLL circuit. For example, in the example of α = 1125, Fs = 55 MHz, P1 = 3600, the equation (3) is
[1125 / (55 × 100)] × (3600-3584) = 3 (decimal point)
Therefore, the capacitor bank is switched from the current step by 3 steps. In this way, most of the correction processes are completed at the time t3 at the longest. That is, the time required for correction is usually a maximum of 3 × T1 (≈10.665 μsec). However, since the correction is performed until P1 = P0, it may exceed 3 × T1.

そして、ＶＣＯ４の周波数ｆ４、注入同期型ＶＣＯ６の周波数ｆ５、注入同期型１／３分周器８の周波数ｆ６、注入同期型１／３分周器９の周波数ｆ７は、注入同期型１／４分周器９の周波数信号ｆ８となったときに、同じ周波数帯であり、この周波数帯の周波数がカウンタ１４に入力するので、カウンタ１４を利用したこの図３に示す補正処理は、ＶＣＯ４、注入同期型ＶＣＯ６、注入同期型１／３分周器８、及び注入同期型１／４分周器９のフリーラン周波数の補正に共通に使用される。 The frequency f4 of the VCO4, the frequency f5 of the injection synchronous VCO6, the frequency f6 of the injection synchronous 1/3 divider 8, and the frequency f7 of the injection synchronous 1/3 divider 9 are the injection synchronous 1/4. When the frequency signal f8 of the frequency divider 9 is reached, it is in the same frequency band, and the frequency of this frequency band is input to the counter 14. Therefore, the correction process shown in FIG. 3 using the counter 14 is VCO4, injection. It is commonly used to correct the free-run frequency of the synchronous VCO 6, the injection synchronous 1/3 divider 8, and the injection synchronous 1/4 divider 9.

図４はシーケンサ１５によって、注入同期型１／４分周器９→注入同期型１／３分周器８→注入同期型ＶＣＯ６→ＶＣＯ４の順序で、それらのフリーラン周波数の補正処理を行うプログラムのフローチャートである。このプログラムの各処理は、コンピュータによって実行される。 FIG. 4 shows a program in which the sequencer 15 corrects the free-run frequencies in the order of injection synchronous 1/4 divider 9 → injection synchronous 1/3 divider 8 → injection synchronous VCO6 → VCO4. It is a flowchart of. Each process of this program is executed by a computer.

＜注入同期型１／４分周器９のフリーラン周波数の補正（第１処理）＞
補正処理が開始される（Ｓ１１）と、まず注入同期型１／４分周器９のフリーラン周波数の補正が行われる。このときは、スイッチＳＷ１〜ＳＷ４のすべてをＯＦＦに設定し、且つバッファ回路５の動作をＯＦＦさせて（Ｓ１２）、ＶＣＯ４、注入同期型ＶＣＯ６、及び注入同期型１／３分周器８の出力をＰＬＬ回路から分離した状態で、注入同期型１／４分周器９をフリーラン発振させる（Ｓ１３）。そして、その注入同期型１／４分周器９の出力周波数信号を１／５分周器１０で５分周して周波数信号ｆ８としてカウンタ１４に入力させる。 <Correction of free-run frequency of injection synchronous 1/4 divider 9 (first process)>
When the correction process is started (S11), the free-run frequency of the injection synchronous 1/4 divider 9 is first corrected. At this time, all the switches SW1 to SW4 are set to OFF, and the operation of the buffer circuit 5 is turned OFF (S12), and the outputs of the VCO4, the injection synchronous VCO6, and the injection synchronous 1/3 divider 8 are output. Is separated from the PLL circuit, and the injection synchronous 1/4 divider 9 is oscillated by free run (S13). Then, the output frequency signal of the injection synchronous 1/4 divider 9 is divided by 5 by the 1/5 divider 10 and input to the counter 14 as a frequency signal f8.

そして、カウンタ１４で期間Ｔ１の内に得られたカウント値Ｐ１をシーケンサ１５において図３で説明したように判定し、周波数信号ｆ８（注入同期型１／４分周器９のフリーラン周波数の１／５）が期待周波数であるときのカウント値Ｐ０と比較し、Ｐ１がＰ０になるように、注入同期型１／４分周器９の発振周波数を補正信号で補正する（Ｓ１４、Ｓ１５）。 Then, the counter 14 determines the count value P1 obtained during the period T1 in the sequencer 15 as described with reference to FIG. 3, and the frequency signal f8 (injection synchronous 1/4 divider 9 free-run frequency 1) is determined. Compared with the count value P0 when / 5) is the expected frequency, the oscillation frequency of the injection synchronous 1/4 divider 9 is corrected by the correction signal so that P1 becomes P0 (S14, S15).

図５に注入同期型１／４分周器９の回路構成を示す。Ｍ１〜Ｍ１４はＮＭＯＳトランジスタ、Ｒ１，Ｒ２はバイアス抵抗、Ｒ３〜Ｒ１０は負荷抵抗である。ＶＤＤは高電位電源電圧、ＶＳＳは低電位電源電圧、ＶＢ１，ＶＢ２はバイアス電圧である。この注入同期型１／４分周器９は差動型であるので、注入周波数信号ｆ６と発振（出力）周波数信号ｆ７は差動信号となっている。 FIG. 5 shows the circuit configuration of the injection synchronous 1/4 divider 9. M1 to M14 are NMOS transistors, R1 and R2 are bias resistors, and R3 to R10 are load resistors. VDD is a high-potential power supply voltage, VSS is a low-potential power supply voltage, and VB1 and VB2 are bias voltages. Since the injection synchronous type 1/4 divider 9 is a differential type, the injection frequency signal f6 and the oscillation (output) frequency signal f7 are differential signals.

ここでは、図６（ａ）に示すように、バイアス電圧ＶＢ１、ＶＢ２を制御することで、注入同期型１／４分周器９の発振フリーラン周波数を変化させる。そして、図６（ｂ）に示すように、出力周波数ｆ７（実際にはカウンタ１４に入力する周波数信号ｆ８）が期待周波数になるロック範囲に入るように、そのフリーラン周波数を補正する。 Here, as shown in FIG. 6A, the oscillation free-run frequency of the injection synchronous 1/4 divider 9 is changed by controlling the bias voltages VB1 and VB2. Then, as shown in FIG. 6B, the free-run frequency is corrected so that the output frequency f7 (actually, the frequency signal f8 input to the counter 14) falls within the lock range at which the expected frequency is reached.

このように補正することにより、実際の使用時に前段回路から入力する周波数信号ｆ６の周波数がロック範囲に入るようにすれば、出力周波数ｆ７が入力周波数ｆ６の１／４の周波数になる。 By making such a correction, if the frequency of the frequency signal f6 input from the pre-stage circuit during actual use is within the lock range, the output frequency f7 becomes 1/4 of the input frequency f6.

＜注入同期型１／３分周器９のフリーラン周波数の補正（第２処理）＞
図４に戻って、注入同期型１／４分周器９のフリーラン周波数の補正が完了すると、注入同期型１／３分周器９のフリーラン周波数の補正が行われる。このときは、スイッチＳＷ１〜ＳＷ３をＯＦＦに設定し、スイッチＳＷ４をＯＮに設定する。且つバッファ回路７も動作をＯＦＦさせて（Ｓ１６）、ＶＣＯ４、注入同期型ＶＣＯ６の出力をＰＬＬ回路から分離した状態で、注入同期型１／３分周器８をフリーラン発振させる（Ｓ１７）。そして、その注入同期型１／３分周器９の出力周波数信号を、フリーラン周波数補正済の注入同期型１／４分周器９で４分周し、さらに１／５分周器１０で５分周して、周波数信号ｆ８としてカウンタ１４に入力さる。 <Correction of free-run frequency of injection synchronous 1/3 divider 9 (second processing)>
Returning to FIG. 4, when the correction of the free run frequency of the injection synchronous 1/4 divider 9 is completed, the free run frequency of the injection synchronous 1/3 divider 9 is corrected. At this time, switches SW1 to SW3 are set to OFF, and switches SW4 are set to ON. The operation of the buffer circuit 7 is also turned off (S16), and the injection synchronous 1/3 divider 8 is oscillated free-run (S17) with the outputs of the VCO4 and the injection synchronous VCO6 separated from the PLL circuit. Then, the output frequency signal of the injection synchronous 1/3 divider 9 is divided by the injection synchronous 1/4 divider 9 with the free run frequency corrected, and further divided by the 1/5 divider 10. It is divided by 5 and input to the counter 14 as a frequency signal f8.

そして、カウンタ１４で期間Ｔ１の内に得られたカウント値Ｐ１をシーケンサ１５において図３で説明したように判定し、周波数信号ｆ８（注入同期型１／４分周器９のフリーラン周波数の１／５）が期待周波数であるときのカウント値Ｐ０と比較し、Ｐ１がＰ０になるように、注入同期型１／４分周器９の発振周波数を補正信号で補正する（Ｓ１８、Ｓ１９）。 Then, the counter 14 determines the count value P1 obtained during the period T1 in the sequencer 15 as described with reference to FIG. 3, and the frequency signal f8 (injection synchronous 1/4 divider 9 free-run frequency 1) is determined. Compared with the count value P0 when / 5) is the expected frequency, the oscillation frequency of the injection synchronous 1/4 divider 9 is corrected by the correction signal so that P1 becomes P0 (S18, S19).

図７に注入同期型１／３分周器８の回路構成を示す。Ｍ２１〜Ｍ３４はＮＭＯＳトランジスタ、Ｒ２１，Ｒ２２はバイアス抵抗、Ｌ１〜Ｌ８は負荷である。ここでは、高周波を扱うので、負荷として抵抗ではなくコイルＬ１〜Ｌ８を使用している。ＶＢ３，ＶＢ４はバイアス電圧である。この注入同期型１／３分周器８は差動型であるので、注入周波数信号ｆ５と発振周波数信号ｆ６は差動信号となっている。 FIG. 7 shows the circuit configuration of the injection synchronous 1/3 divider 8. M21 to M34 are NMOS transistors, R21 and R22 are bias resistors, and L1 to L8 are loads. Here, since high frequencies are handled, coils L1 to L8 are used as loads instead of resistors. VB3 and VB4 are bias voltages. Since the injection synchronous type 1/3 divider 8 is a differential type, the injection frequency signal f5 and the oscillation frequency signal f6 are differential signals.

ここでは、図８（ａ）に示すように、バイアス電圧ＶＢ３、ＶＢ４を制御することで、注入同期型１／３分周器８の発振フリーラン周波数を変化させる。そして、図８（ｂ）に示すように、出力周波数ｆ６（実際にはカウンタ１４に入力する周波数信号ｆ８）が所定の周波数になるロック範囲に入るように、そのフリーラン周波数を補正する。 Here, as shown in FIG. 8A, the oscillation free-run frequency of the injection synchronous 1/3 divider 8 is changed by controlling the bias voltages VB3 and VB4. Then, as shown in FIG. 8B, the free-run frequency is corrected so that the output frequency f6 (actually, the frequency signal f8 input to the counter 14) falls within the lock range where the frequency becomes a predetermined frequency.

このように補正することにより、実際の使用時に前段回路から入力する周波数信号ｆ６の周波数がロック範囲に入るようにすれば、出力周波数ｆ６が入力周波数ｆ５の１／３の周波数になる。 By making such a correction, if the frequency of the frequency signal f6 input from the pre-stage circuit during actual use is within the lock range, the output frequency f6 becomes 1/3 of the input frequency f5.

＜注入同期型ＶＣＯ６のフリーラン周波数の補正（第３処理）＞
図４に戻って、注入同期型１／３分周器８のフリーラン周波数の補正が完了すると、注入同期型ＶＣＯ６のフリーラン周波数の補正が行われる。このときは、スイッチＳＷ１，ＳＷ２をＯＦＦに設定し、スイッチＳＷ３，ＳＷ４をＯＮに設定し、且つバッファ回路７を動作をＯＮさせて（Ｓ２０）、ＶＣＯ６をＰＬＬ回路から分離した（バッファ回路５はステップＳ１２でＯＦＦになっている。）状態で、注入同期型ＶＣＯ８をフリーラン発振させる（Ｓ２１）。そして、その注入同期型ＶＣＯ６の発振周波数信号を、フリーラン周波数補正済の注入同期型１／３分周器８で３分周し、フリーラン周波数補正済の注入同期型１／４分周器９で４分周し、さらに１／５分周器１０で５分周して、周波数信号ｆ８としてカウンタ１４に入力させる。 <Correction of free run frequency of injection synchronous VCO6 (third processing)>
Returning to FIG. 4, when the correction of the free run frequency of the injection synchronous type 1/3 divider 8 is completed, the free run frequency of the injection synchronous type VCO 6 is corrected. At this time, the switches SW1 and SW2 are set to OFF, the switches SW3 and SW4 are set to ON, and the operation of the buffer circuit 7 is turned ON (S20) to separate the VCO 6 from the PLL circuit (the buffer circuit 5 is In the state of (turned off in step S12), the injection synchronous VCO8 is oscillated by free run (S21). Then, the oscillation frequency signal of the injection synchronous VCO6 is divided by 3 by the injection synchronous 1/3 divider 8 with the free run frequency correction, and the injection synchronous 1/4 divider with the free run frequency correction is used. The frequency signal f8 is divided by 4 and then divided by 5 with the 1/5 divider 10 to be input to the counter 14.

そして、カウンタ１４で期間Ｔ１の内に得られたカウント値Ｐ１をシーケンサ１５において図３で説明したように判定し、周波数信号ｆ８（注入同期型１／４分周器９のフリーラン周波数の１／４）が期待周波数であるときのカウント値Ｐ０と比較し、Ｐ１がＰ０になるように、注入同期型１／４分周器９の発振周波数を補正信号で補正する（Ｓ２２、Ｓ２３）。 Then, the counter 14 determines the count value P1 obtained during the period T1 in the sequencer 15 as described with reference to FIG. 3, and the frequency signal f8 (injection synchronous 1/4 divider 9 free-run frequency 1) is determined. Compared with the count value P0 when / 4) is the expected frequency, the oscillation frequency of the injection synchronous 1/4 divider 9 is corrected by the correction signal so that P1 becomes P0 (S22, S23).

図９に注入同期型ＶＣＯ６の回路構成を示す。Ｍ４１〜Ｍ５２はＮＭＯＳトランジスタ、Ｒ４１は制御電圧ＶＣ１を入力させる入力抵抗、Ｒ４２〜Ｒ４９はバイアス抵抗、Ｌ９〜Ｌ１０はタンク回路用コイル、ＶＤ１〜ＶＤ４は制御電圧ＶＣ１によって容量が変化する可変容量ダイオード、Ｃ１〜Ｃ１０はカップリングキャパシタである。また、６１は発振周波数帯切替用キャパシタバンク回路であり、ｎ個（ｎは任意の整数）のキャパシタＣ１１１〜Ｃ１１ｎ、ｎ個のキャパシタＣ１２〜Ｃ１２ｎ、ｎ個のスイッチＳＷ５１〜ＳＷ５ｎで構成されている。６２も発振周波数帯切替用キャパシタバンク回路であり、ｎ個のキャパシタＣ３１１〜Ｃ３１ｎ、ｎ個のキャパシタＣ４２〜Ｃ４２ｎ、ｎ個のスイッチＳＷ６１〜ＳＷ６ｎで構成されている。ＶＢ５，ＶＢ６はバイアス電圧である。この注入同期型ＶＣＯ６は差動型であるので、入力周波数信号ｆ４と出力周波数ｆ５は差動信号となっている。また、送受信機に出力するローカル信号は、直交信号Ｉ，Ｑとして出力される。この直交信号Ｉ，Ｑも差動信号である。 FIG. 9 shows the circuit configuration of the injection synchronous VCO6. M41 to M52 are MOSFET transistors, R41 is an input resistor that inputs the control voltage VC1, R42 to R49 are bias resistors, L9 to L10 are tank circuit coils, and VD1 to VD4 are variable capacitor diodes whose capacitance changes depending on the control voltage VC1. C1 to C10 are coupling capacitors. Reference numeral 61 denotes a capacitor bank circuit for switching the oscillation frequency band, which is composed of n capacitors (n is an arbitrary integer) C111 to C11n, n capacitors C12 to C12n, and n switches SW51 to SW5n. .. 62 is also a capacitor bank circuit for switching the oscillation frequency band, and is composed of n capacitors C311 to C31n, n capacitors C42 to C42n, and n switches SW61 to SW6n. VB5 and VB6 are bias voltages. Since the injection synchronous type VCO6 is a differential type, the input frequency signal f4 and the output frequency f5 are differential signals. Further, the local signals output to the transmitter / receiver are output as orthogonal signals I and Q. The orthogonal signals I and Q are also differential signals.

ここでは、制御電圧ＶＣ１を固定した状態で、発振周波数帯切替用キャパシタバンク回路６１、６２のキャパシタを切り替えることにより注入同期型ＶＣＯ６のフリーラン周波数を変化させる。フリーラン周波数の微調整は、前記した制御電圧ＶＣ１によって行う。 Here, the free-run frequency of the injection-synchronized VCO6 is changed by switching the capacitors of the oscillation frequency band switching capacitor bank circuits 61 and 62 while the control voltage VC1 is fixed. The free-run frequency is finely adjusted by the control voltage VC1 described above.

このように補正することによって、実際の使用時に前段回路から周波数信号ｆ４が注入されることにより、発振周波数ｆ５が注入周波数信号の周波数ｆ４の３逓倍の周波数になる。 By correcting in this way, the frequency signal f4 is injected from the pre-stage circuit during actual use, so that the oscillation frequency f5 becomes a frequency that is three times the frequency f4 of the injection frequency signal.

＜ＶＣＯ４のフリーラン周波数の補正（第４処理）＞
図４に戻って、注入同期型ＶＣＯ６のフリーラン周波数の補正が完了すると、ＶＣＯ４のフリーラン周波数の補正が行われる。このときは、スイッチＳＷ３，ＳＷ４をＯＦＦに設定し、且つバッファ回路７の動作をＯＦＦさせるとともに注入同期型１／３分周器８の動作をＯＦＦにして（Ｓ２４）、注入同期型ＶＣＯ６の出力をＰＬＬ回路から分離し、さらにバッファ回路５の動作をＯＮにした状態で（Ｓ２５）、フリーラン周波数の補正済の注入同期型ＶＣＯ６のロックアップを開始する（Ｓ２６）。 <Correction of free-run frequency of VCO4 (4th processing)>
Returning to FIG. 4, when the correction of the free-run frequency of the injection-synchronized VCO 6 is completed, the free-run frequency of the VCO 4 is corrected. At this time, the switches SW3 and SW4 are set to OFF, the operation of the buffer circuit 7 is turned OFF, and the operation of the injection synchronous 1/3 divider 8 is turned OFF (S24), and the output of the injection synchronous VCO 6 is output. Is separated from the PLL circuit, and the operation of the buffer circuit 5 is turned on (S25), and the lockup of the injection synchronous VCO6 whose free run frequency has been corrected is started (S26).

そして、位相比較器１の比較論理を固定するとともにチャージポンプ回路２の出力インピーダンスを高インピーダンスにし（Ｓ２７）、スイッチＳＷ１をＯＮしてＶＤＤ／２の電圧をローパスフィルタ３に入力して（Ｓ２８）、ＶＣＯ４を固定の制御電圧ＶＤＤ／２でフリーラン発振させる（Ｓ２９）と、ＶＣＯ４がほぼ中間周波数で発振する。そのＶＣＯ４の発振周波数信号を、ＯＮしているスイッチＳＷ２を経由してフリーラン周波数補正済の注入同期型１／４分周器９で４分周し、さらに１／５分周器１０で５分周して、周波数信号ｆ８としてカウンタ１４に入力させる。 Then, the comparison logic of the phase comparator 1 is fixed, the output impedance of the charge pump circuit 2 is set to high impedance (S27), the switch SW1 is turned on, and the voltage of VDD / 2 is input to the low-pass filter 3 (S28). When the VCO4 is oscillated by free run at a fixed control voltage VDD / 2 (S29), the VCO4 oscillates at a substantially intermediate frequency. The oscillation frequency signal of the VCO4 is divided by 4 by the injection synchronous 1/4 divider 9 with free run frequency correction via the ON switch SW2, and further divided by 5 by the 1/5 divider 10. The frequency is divided and input to the counter 14 as a frequency signal f8.

そして、カウンタ１４で期間Ｔ１の内に得られたカウント値Ｐ１をシーケンサ１５において図３で説明したように判定し、周波数信号ｆ８（注入同期型１／４分周器９のフリーラン周波数の１／４）が期待周波数であるときのカウント値Ｐ０と比較し、Ｐ１がＰ０になるように、ＶＣＯ４の発振周波数を補正信号で補正する（Ｓ３０、Ｓ３１）。ＶＣＯ４のフリーラン周波数が目標の周波数になった後は、ＰＬＬ回路のロックアップが開始される（Ｓ３２）。 Then, the counter 14 determines the count value P1 obtained within the period T1 in the sequencer 15 as described with reference to FIG. 3, and the frequency signal f8 (injection synchronous 1/4 divider 9 free-run frequency 1) is determined. Compared with the count value P0 when / 4) is the expected frequency, the oscillation frequency of VCO4 is corrected by the correction signal so that P1 becomes P0 (S30, S31). After the free-run frequency of the VCO4 reaches the target frequency, the lockup of the PLL circuit is started (S32).

図１０にＶＣＯ４の回路構成を示す。Ｍ６１〜Ｍ６３はＮＭＯＳトランジスタ、Ｒ５０は制御電圧ＶＣ２を入力させる入力抵抗、Ｌ１１はタンク回路用コイル、ＶＤ５、ＶＤ６は制御電圧ＶＣ２によって容量が変化する可変容量ダイオード、Ｃ１５、Ｃ１６はカップリングキャパシタである。また、４１は発振周波数帯切替用キャパシタバンク回路であり、ｎ個のキャパシタＣ１７１〜Ｃ１７ｎ、ｎ個のキャパシタＣ１８１〜Ｃ１８ｎ、ｎ個のスイッチＳＷ７１〜ＳＷ７ｎで構成されている。ＶＢ７はバイアス電圧である。このＶＣＯ４は差動型であるので、発振周波数信号ｆ４は差動信号となっている。 FIG. 10 shows the circuit configuration of VCO4. M61 to M63 are NMOS transistors, R50 is an input resistor that inputs the control voltage VC2, L11 is a coil for a tank circuit, VD5 and VD6 are variable capacitance diodes whose capacitance changes according to the control voltage VC2, and C15 and C16 are coupling capacitors. .. Reference numeral 41 denotes a capacitor bank circuit for switching the oscillation frequency band, which is composed of n capacitors C171 to C17n, n capacitors C181 to C18n, and n switches SW71 to SW7n. VB7 is a bias voltage. Since this VCO4 is a differential type, the oscillation frequency signal f4 is a differential signal.

ここでは、制御電圧ＶＣ２を固定しておいて、発振周波数帯切替用キャパシタバンク回路４１のキャパシタをスイッチＳＷ７１〜ＳＷ７ｎで切り替えることによりＶＣＯ４の発振フリーラン周波数を変化させる。このように補正することにより、実際の使用時に制御電圧ＶＣ２に応じた既定の発振周波数ｆ５の信号が発振される。 Here, the control voltage VC2 is fixed, and the oscillation free-run frequency of the VCO 4 is changed by switching the capacitor of the oscillation frequency band switching capacitor bank circuit 41 with the switches SW71 to SW7n. By correcting in this way, a signal having a predetermined oscillation frequency f5 corresponding to the control voltage VC2 is oscillated during actual use.

＜ロックアップ動作（第５処理）＞
注入同期型ＶＣＯ６のフリーラン周波数の補正が完了した後は、その注入同期型ＶＣＯ６は補正済の周波数でフリーラン発振を開始しており、その後、ＶＣＯ４のフリーラン周波数の補正が完了するとＰＬＬ回路のロックアップ（Ｓ３２）が開始するが、このとき注入同期型ＶＣＯ６もＶＣＯ４の発振周波数でロックアップされる。つまり、ＶＣＯ４と注入同期型ＶＣＯ６のロックアップが同時に行われる。 <Lockup operation (fifth process)>
After the correction of the free-run frequency of the injection-synchronized VCO6 is completed, the injection-synchronized VCO6 starts free-run oscillation at the corrected frequency, and after that, when the correction of the free-run frequency of the VCO4 is completed, the PLL circuit Lockup (S32) starts, and at this time, the injection-synchronized VCO6 is also locked up at the oscillation frequency of VCO4. That is, the VCO4 and the injection-synchronized VCO6 are locked up at the same time.

上述したように、本実施例では、注入同期型１／４分周器９→注入同期型１／３分周器８→注入同期型ＶＣＯ８→ＶＣＯ４の順序でフリーラン周波数の補正を行うので、ＶＣＯ４のフリーラン周波数の補正が完了してから、ＰＬＬロックアップと注入同期型ＶＣＯ８のロックアップを同時に行うことができる。 As described above, in this embodiment, the free-run frequency is corrected in the order of injection synchronous 1/4 divider 9 → injection synchronous 1/3 divider 8 → injection synchronous VCO8 → VCO4. After the correction of the free-run frequency of the VCO4 is completed, the PLL lockup and the lockup of the injection-synchronized VCO8 can be performed at the same time.

すなわち、図１１（ａ）に示すように、注入同期型１／４分周器９→注入同期型１／３分周器８→注入同期型ＶＣＯ６→ＶＣＯ４の順序でそれぞれのフリーラン周波数補正を行う時間Ｔ１１〜Ｔ１４は、図２（ｂ）を用いて前述したように、通常では最大でもそれぞれ３×Ｔ１（≒１０．６６５μｓｅｃ）であるが、注入同期型ＶＣＯ６、ＶＣＯ４のロックアップ時間はそれらよりも数倍近く長く（例えば、ループ帯域を１００ｋＨｚとしたときは４０μｓｅｃ）かかる。本実施例のシーケンスでは、このロックアップ時間Ｔ１５を共通化できるので、補正開始からロック完了までにかかる時間を短く（１０．６６２μｓｅｃ×４＋４０μｓｅｃ＝８２．６４８μｓｅｃ）することができる。 That is, as shown in FIG. 11A, each free-run frequency correction is performed in the order of injection synchronous 1/4 divider 9 → injection synchronous 1/3 divider 8 → injection synchronous VCO6 → VCO4. As described above with reference to FIG. 2B, the times T11 to T14 to be performed are usually at most 3 × T1 (≈10.665 μsec), respectively, but the lockup times of the injection-synchronized VCO6 and VCO4 are those. It takes nearly several times longer than (for example, 40 μsec when the loop band is 100 kHz). In the sequence of this embodiment, since the lockup time T15 can be shared, the time required from the start of correction to the completion of lock can be shortened (10.662 μsec × 4 + 40 μsec = 82.648 μsec).

注入同期型１／３分周器８を使用しないでＰＬＬ回路を構成した場合のフリーラン周波数の補正は、図１１（ｂ）を用いて前述したように、注入同期型分周器のフリーラン周波数補正→ＶＣＯのフリーラン周波数補正→ＰＬＬロックアップ→注入同期型ＶＣＯのフリーラン周波数補正→注入同期型ＶＣＯのロックアップの順序で行わなければならない。このため、ＰＬＬロックアップと注入同期型ＶＣＯのロックアップを時間Ｔ２３、Ｔ２５で個別に行う必要があるので、補正開始からロック完了までの時間が、本実施例の場合よりも長く（１０．６６２μｓｅｃ×３＋４０μｓｅｃ×２＝１１１．９８９μｓｅｃ）かかる。 When the PLL circuit is configured without using the injection synchronous 1/3 divider 8, the free run frequency is corrected by the free run of the injection synchronous divider as described above with reference to FIG. 11B. Frequency correction-> VCO free-run frequency correction-> PLL lockup-> injection synchronous VCO free-run frequency correction-> injection synchronous VCO lockup must be performed in this order. Therefore, since it is necessary to separately perform the PLL lockup and the lockup of the injection synchronous VCO at the times T23 and T25, the time from the start of correction to the completion of the lock is longer than that in the case of this embodiment (10.662 μsec). × 3 + 40 μsec × 2 = 111.989 μsec).

１：位相比較器、２：チャージポンプ回路、３：ローパスフィルタ、４：ＶＣＯ、５：バッファ回路、６：注入同期型ＶＣＯ、７：バッファ回路、８：注入同期型１／３分周器、９：注入同期型１／４分周器、１０：１／５分周器、１１：可変分周器、１２：１／１２８分周器、１３：１／２分周器、１３１：ＤＦＦ回路、１３２：インバータ、１４：カウンタ、１５：シーケンサ 1: Phase counter, 2: Charge pump circuit, 3: Low pass filter, 4: VCO, 5: Buffer circuit, 6: Injection synchronous VCO, 7: Buffer circuit, 8: Injection synchronous 1/3 divider, 9: Injection synchronous 1/4 divider, 10: 1/5 divider, 11: Variable divider, 12: 1/128 divider, 13: 1/2 divider, 131: DFF circuit , 132: Inverter, 14: Counter, 15: Sequencer

Claims

A phase comparator that compares the phase of the reference frequency signal and the feedback frequency signal, a charge pump circuit that outputs a voltage according to the comparison result of the phase comparator, and a low frequency component extracted from the output voltage of the charge pump circuit. A low-pass filter, a first VCO that oscillates at a frequency corresponding to the output voltage of the low-pass filter, and a frequency signal oscillated by the first VCO are input as injection synchronization signals, and the frequency is an integral multiple of the frequency signal oscillated by the first VCO. An injection synchronous type second VCO that oscillates a signal and an injection synchronous type that inputs a frequency signal oscillated by the second VCO as an injection signal and divides the frequency of the injection signal into the same frequency as the oscillation frequency of the first VCO. An injection-synchronized second frequency divider that divides the frequency of the injection signal by inputting the frequency signal oscillated by the first VCO or the output frequency signal of the first frequency divider as an injection signal. A device and a fixed third frequency divider that divides the reference frequency signal are provided, and the output frequency signal of the second frequency divider is divided as it is or by a first arbitrary number to obtain the feedback frequency signal. In the PLL circuit
The output frequency signal of the second divider or the output frequency signal of the second divider is divided by a second arbitrary number during a predetermined period determined by the frequency of the frequency signal divided by the third divider. A counter that counts the pulses of the frequency signal that goes around,
It has a sequencer that individually corrects the first VCO, the second VCO, the first frequency divider, and the free run frequency of the second frequency divider according to the count value of the counter .
The sequencer causes the second divider to oscillate free-run in a state where the outputs of the first VCO, the second VCO, and the first divider are separated from the PLL circuit, and the counter obtained at that time. The first process of correcting the free-run frequency of the second frequency divider according to the count value, and
After the first processing, the output frequency signal of the first divider is separated from the output of the first VCO and the second VCO from the PLL circuit, and the first divider is oscillated free-run. Is injected into the second divider whose free run frequency has been corrected, and the second process of correcting the free run frequency of the first divider according to the count value of the counter obtained at that time, and
After the second processing, the output of the first VCO is separated from the PLL circuit, and the first and second dividers are oscillated at the corrected free run frequencies, and the second VCO is freed. The third process of oscillating the run and correcting the free run frequency of the second VCO according to the count value of the counter obtained at that time,
After the third process, the output of the first frequency divider is separated from the PLL circuit, and the first VCO is oscillated at a corrected free-run frequency at a fixed voltage. A fourth process in which free-run oscillation is performed to input the output frequency of the first VCO to the second frequency divider, and the free-run frequency of the first VCO is corrected according to the count value of the counter obtained at that time.
After the fourth process, to have a program for executing a fifth process for performing said lock-up of the 2VCO to injection signal output frequency signal of the first 1VCO a lock-up of the PLL circuit at the same time, to a computer A PLL circuit characterized by.

A phase comparator that compares the phase of the reference frequency signal and the feedback frequency signal, a charge pump circuit that outputs a voltage according to the comparison result of the phase comparator, and a low frequency component extracted from the output voltage of the charge pump circuit. A low-pass filter, a first VCO that oscillates at a frequency corresponding to the output voltage of the low-pass filter, and a frequency signal oscillated by the first VCO are input as injection synchronization signals, and the frequency is an integral multiple of the frequency signal oscillated by the first VCO. An injection synchronous type second VCO that oscillates a signal and an injection synchronous type that inputs a frequency signal oscillated by the second VCO as an injection signal and divides the frequency of the injection signal into the same frequency as the oscillation frequency of the first VCO. An injection-synchronized second frequency divider that divides the frequency of the injection signal by inputting the frequency signal oscillated by the first VCO or the output frequency signal of the first frequency divider as an injection signal. A device and a fixed third frequency divider that divides the reference frequency signal are provided, and the output frequency signal of the second frequency divider is divided as it is or by a first arbitrary number to obtain the feedback frequency signal. In the frequency correction method of the PLL circuit that corrects the free-run frequency of the first VCO, the second VCO, the first divider, and the second divider of the PLL circuit.
Only a second arbitrary number of the output frequency signal of the second divider or the output frequency signal of the second divider during a predetermined period determined by the frequency of the frequency signal divided by the third divider. The free-run frequencies of the first VCO, the second VCO, the first frequency divider, and the second frequency divider are individually corrected according to the number of pulses of the divided frequency signal.
With the outputs of the first VCO, the second VCO, and the first divider separated from the PLL circuit, the second divider is oscillated free-run, and the number of pulses obtained at that time is increased. The first process to correct the free-run frequency of the second frequency divider, and
After the first processing, the output frequency signal of the first divider is separated from the output of the first VCO and the second VCO from the PLL circuit, and the first divider is oscillated free-run. Is injected into the second divider whose free run frequency has been corrected, and the second process of correcting the free run frequency of the first divider according to the number of pulses obtained at that time, and
After the second processing, the output of the first VCO is separated from the PLL circuit, and the first and second dividers are oscillated at corrected free-run frequencies, and the second VCO is freed. A third process of oscillating a run and correcting the free run frequency of the second VCO according to the number of pulses obtained at that time.
After the third process, the output of the first frequency divider is separated from the PLL circuit, and the first VCO is oscillated at a corrected free-run frequency at a fixed voltage. A fourth process in which free-run oscillation is performed to input the output frequency of the first VCO to the second frequency divider, and the free-run frequency of the first VCO is corrected according to the number of pulses obtained at that time.
The PLL circuit is characterized by having, after the fourth process, a fifth process of simultaneously performing the lockup of the PLL circuit and the lockup of the second VCO using the output frequency signal of the first VCO as an injection signal. Frequency correction method.