JP6736318B2 - Solid-state imaging device, method of manufacturing solid-state imaging device, and imaging system - Google Patents

Description

The present invention relates to a technique for reducing magnetic noise generated in ground wiring in a solid-state image sensor.

In recent years, further improvement in image quality has been desired in solid-state image pickup devices, and noise suppression is essential for realizing high image quality. As a method of suppressing such noise, a technique of suppressing noise caused by a power supply that drives a solid-state imaging device is described in, for example, Patent Document 1. In Patent Document 1, noise is suppressed by holding the reference signal of the read circuit in the hold capacitor.

JP, 2008-85994, A

In the conventional technique disclosed in Patent Document 1, noise generated in the signal line of the read circuit can be suppressed, but noise generated in the ground wiring is not considered. However, when a magnetic field is generated, the effect of magnetic noise on the ground wiring cannot be ignored. This is because when the ground wire forms a loop including the substrate inside or outside the solid-state image sensor, the induced electromotive force shown by Faraday's law is generated in the ground wire, and this occurs as magnetic noise in the sensor output image. This is because it ends up. Therefore, in Patent Document 1, there is a problem that the magnetic noise generated in the ground wiring cannot be reduced. Therefore, an object of the present invention is to obtain a solid-state image sensor capable of reducing the magnetic noise generated in the ground wiring, a method for manufacturing the solid-state image sensor, and an image pickup system.

A solid-state imaging device according to the present invention, a semiconductor substrate including a pixel well region and a peripheral well region, a pixel ground wiring arranged on the pixel well region, a peripheral ground wiring arranged on the peripheral well region, A plurality of pixel well contacts that connect the pixel ground wiring and the pixel well region, a plurality of peripheral well contacts that connect the peripheral ground wiring and the peripheral well region, and a plurality of columns are arranged in the pixel well region, A plurality of pixels, each of which outputs a pixel signal, a read circuit that is arranged in the peripheral well region, has a first input terminal that receives a pixel signal from the plurality of pixels, and a second input terminal that receives a reference signal; A reference signal circuit that has a first electrode that is arranged in the well region and that is supplied with a ground voltage and that outputs a reference signal to the second input terminal of the readout circuit; a first electrode of the reference signal circuit and a pixel ground line; A wiring line for connection, and a resistance value R1 of an electric path from one of the plurality of pixel well contacts to the first electrode, and one of the plurality of peripheral well contacts arranged closest to the first electrode. The resistance value R2 of the electric path to the first electrode satisfies the relationship of R1<R2.

According to the present invention, it is possible to obtain a solid-state image sensor, a method for manufacturing the solid-state image sensor, and an imaging system capable of reducing magnetic noise generated in the ground wiring.

It is a figure which shows typically the structure of the solid-state image sensor which concerns on the 1st Embodiment of this invention. It is a figure which shows typically the planar structure of the hold capacity|capacitance which concerns on the 1st Embodiment of this invention. It is a figure which shows typically the cross-section of the hold capacity|capacitance which concerns on the 1st Embodiment of this invention. It is a figure which shows typically the plane structure of the ground connection part which concerns on the 1st Embodiment of this invention. It is a figure which shows typically the cross-section of the package containing the solid-state image sensor which concerns on the 1st Embodiment of this invention. FIG. 3 is a diagram schematically showing an equivalent circuit of a ground loop and a ground potential distribution in the solid-state imaging device according to the first embodiment of the present invention. It is a figure which shows typically the plane structure of the ground connection part which concerns on the 2nd Embodiment of this invention. It is a figure which shows typically the plane structure of the ground connection part which concerns on the 3rd Embodiment of this invention. It is a figure which shows typically the plane structure of the ground connection part which concerns on the 4th Embodiment of this invention. It is a figure which shows typically the structure of the solid-state image sensor concerning the 5th Embodiment of this invention. It is a figure which shows typically the equivalent circuit and ground potential distribution of the ground loop in the solid-state image sensor concerning the 5th Embodiment of this invention. It is a figure which shows typically the magnetic noise contained in the input to the AD converter which concerns on the 5th Embodiment of this invention. It is a figure which shows typically the structure of the solid-state image sensor concerning the 6th Embodiment of this invention. It is a figure which shows typically the cross-section of the solid-state image sensor which concerns on the 6th Embodiment of this invention. It is a figure which shows typically the equivalent circuit of a ground loop in the solid-state image sensor concerning the 6th Embodiment of this invention, and ground potential distribution. It is a figure which shows the structure of the imaging system which concerns on the 7th Embodiment of this invention.

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited to the following embodiments, and can be modified as appropriate without departing from the scope of the invention. In the drawings described below, components having the same function are denoted by the same reference numeral, and the description thereof may be omitted or simplified.

[First Embodiment]
The solid-state imaging device according to this embodiment will be described with reference to FIGS. FIG. 1 is a diagram schematically showing the configuration of a solid-state imaging device 1 according to the first embodiment of the present invention. The solid-state imaging device 1 shown in FIG. 1 includes a pixel well region 101, a peripheral well region 100, a vertical scanning circuit 70, and a peripheral circuit control unit 71. The pixel well region 101 and the peripheral well region 100 are each a semiconductor region formed on a semiconductor substrate. The pixel ground line 51 is arranged so as to overlap the pixel well region 101 in a plan view with respect to the semiconductor substrate. The peripheral ground wiring 50 is arranged so as to overlap the peripheral well region 100 in a plan view of the semiconductor substrate. The pixel array is arranged in the pixel well region 101 where the pixel ground wiring 51 is arranged, and is configured by a plurality of pixels 10 being two-dimensionally arranged in the row direction and the column direction. Each pixel 10 includes a photoelectric conversion unit and an amplification unit that outputs a signal based on the charges generated by the photoelectric conversion unit. A signal corresponding to light is output from each pixel 10. The vertical scanning circuit 70 is composed of, for example, a shift register, and controls the drive of the pixels 10 in units of rows. This drive control includes a reset operation of the pixel 10, an accumulation operation, a signal reading operation from the pixel 10, and the like.

The differential amplifier circuit 30 is arranged in the peripheral well region 100 in which the peripheral ground wiring 50 is arranged. A plurality of differential amplifier circuits 30 are provided corresponding to a plurality of columns formed by a plurality of pixels 10. The differential amplifier circuit 30 reads out the signals from the plurality of pixels 10 included in the corresponding column with reference to the reference signal. More specifically, the differential amplifier circuit 30 amplifies the difference between the signal input to the non-inverting input terminal (+) and the signal input to the inverting input terminal (−), and the solid-state image sensor 1 external Is output to the video signal processing unit (see FIG. 13 described later). Here, pixel signals from a plurality of pixels 10 in the same column are input to the inverting input terminal (-) via a plurality of vertical signal lines 20 provided for each column. On the other hand, the control electrode of the hold capacitor 200 is connected to the non-inverting input terminal (+), and the reference signal is input via the switch transistor 300. The ground electrode of the hold capacitor 200 is connected to the pixel ground wire 51. The hold capacitor 200 and the switch transistor 300 form a reference signal circuit that outputs a reference signal to the non-inverting input terminal (+). A reference signal source that supplies a reference signal may be provided inside the solid-state imaging device 1. Alternatively, the reference signal may be supplied from outside the solid-state image sensor 1. In the differential amplifier circuit 30 shown in FIG. 1, the feedback section and the like are omitted.

By turning off the switch transistor 300, the hold capacitor 200 holds the reference signal Vref supplied from the reference signal source. Further, the switch transistor 300 is connected to the control electrode of the hold capacitor 200, and charges and discharges an electric charge according to the reference signal Vref held by the hold capacitor 200 according to the control pulse P1 output from the peripheral circuit control unit 71 (for example, , Patent Document 1). More specifically, when the switch transistor 300 is turned on before the signal reading operation from the pixel 10, the reference signal Vref is output to the non-inverting input terminal (+) of the differential amplifier circuit 30. At the same time, the hold capacitor 200 is charged with electric charges according to the reference signal Vref. When the hold capacitor 200 is charged with an electric charge according to the reference signal Vref, the reference signal Vref for the signal reading operation from the pixel 10 is output from the hold capacitor 200 even if the switch transistor 300 is turned off. .. Therefore, by turning off the switch transistor 300, noise due to the reference signal source can be reduced.

A plurality of peripheral well contacts 43 that connect the peripheral well region 100 and the peripheral ground wiring 50 are arranged on the peripheral well region 100. The peripheral ground wiring 50 is electrically connected to an external ground potential outside the solid-state imaging device 1 via the external ground terminal 60. On the other hand, on the pixel well region 101, a plurality of pixel well contacts 42 that connect the pixel well region 101 and the pixel ground wiring are arranged. In addition, the pixel ground wiring 51 is electrically connected to the peripheral ground wiring 50 via the ground connecting portion 52. The ground terminals of the photoelectric conversion unit and the amplification unit (hereinafter, simply referred to as “ground terminal of the pixel 10”) that configure each pixel 10 are electrically connected to the pixel ground wiring 51 via the pixel well contact 42. The pixel well region 101 constitutes the ground terminal of the pixel 10. The pixel well contacts 42 and the peripheral well contacts 43 do not necessarily have to be regularly arranged as shown in the figure.

FIG. 2 is a diagram schematically showing a planar structure of the hold capacitor 200 according to the first embodiment of the present invention. Further, FIG. 3 is a diagram schematically showing a cross-sectional structure of the hold capacitor 200 according to the first embodiment of the present invention. FIG. 3 shows a cross-sectional structure taken along the dashed-dotted line L-L′ in FIG. 2. The hold capacitor 200 includes a control electrode 54 and a ground electrode 53, as shown in FIG. A reference signal Vref is supplied to the control electrode 54 from a reference signal source. The ground electrode 53 is connected to the pixel ground wiring 51 via the first contact 48. The control electrode 54 is connected to the switch transistor 300 via the second contact 47 and the wiring 58.

The ground electrode 53 and the control electrode 54 are formed of a conductive material. Further, the first contact 48 may be one that can electrically connect the ground electrode 53 of the hold capacitor 200 to the pixel ground wiring 51. The first contact 48 and the pixel ground wiring 51 may be connected to each other via another wiring. In this embodiment, the ground electrode 53 and the first contact 48 are made of different materials. The edge of the ground electrode 53 can be defined by the interface of different materials. Generally, the ground electrode 53 and the first contact 48 are formed by different processes. For example, the ground electrode 53 is formed by patterning a metal layer. On the other hand, the first contact 48 is formed by embedding a metal in the through hole formed in the insulating layer. Alternatively, the ground electrode 53 and the first contact 48 may be made of the same material. For example, when the wiring is formed by the dual damascene method, the ground electrode 53 and the first contact 48 can be formed of the same material. In this case, a conductive material different from them, for example, a barrier metal may be arranged between them. In this specification, a plurality of processes for forming trenches having different widths in the dual damascene method used when forming wirings are treated as different processes. Alternatively, the ground electrode 53 and the pixel ground wiring 51 may be integrated in the same wiring layer. Thereby, the first contact 48 can be omitted. In this case, the ground electrode 53 and the pixel ground wiring 51 are formed at the same time. Further, the end of the ground electrode 53 is defined by projecting the end of the control electrode 54 which faces the ground electrode 53 in a direction perpendicular to the surface of the semiconductor substrate. Further, the end of the pixel ground wiring 51 is defined by projecting the pixel well region 101 in a direction perpendicular to the surface of the semiconductor substrate. Further, by disposing the hold capacitor 200 in the well region separated from the peripheral well region 100, it is possible to use the separated well region as the ground electrode 53. That is, the ground electrode 53 may be formed of a semiconductor region having a predetermined impurity concentration.

The second contact 47 may be any one that can electrically connect the control electrode 54 of the hold capacitor 200 to the wiring 58 to which the reference signal Vref is supplied. Here, the second contact 47 can be omitted by integrating it with the wiring 58 and the control electrode 54 to which the reference signal Vref is supplied.

FIG. 4 is a diagram schematically showing a planar structure of the ground connecting portion 52 according to the first embodiment of the present invention. As shown in FIG. 4, the ground connection portion 52 of the present embodiment is characterized in that it has an intermediate wiring 63 having a layout that meanders in the column direction and the row direction. The column direction is a direction along a column formed by the plurality of pixels 10. The row direction is a direction intersecting a column formed by the plurality of pixels 10. Usually, such a wiring layout is not performed because the layout area is increased. However, in the present embodiment, by arranging the intermediate wiring 63 in this manner, the peripheral ground wiring 50 and the pixel ground wiring 51 are connected with a high resistance so that magnetic noise generated in the ground wiring is generated as described later. I am trying to reduce it. The effects obtained by the present embodiment will be described below. When the solid-state image pickup device 1 is applied to an image pickup system such as a camera, examples of a magnetic noise source that affects the ground wiring include a magnetic field generated by a motor for driving a lens of the camera.

FIG. 5: is a figure which shows typically the cross-section of the package containing the solid-state image sensor 1 which concerns on the 1st Embodiment of this invention. FIG. 5 shows a configuration in which the solid-state imaging device 1 shown in FIG. 1 is supported by a package 80. Note that, in FIG. 5, the peripheral ground wiring 50, the pixel ground wiring 51, and the ground connection portion 52 shown in FIG. 1 are shown as a single ground wiring 55. The ground wire 55 is electrically connected to the external ground wire 90, which is an inner layer wire of the package, via the external ground terminal 60, the wire bonding 61, and the through via 62 of the package. Here, the wire bonding 61 connects the external ground terminal 60 and the through via 62. In such a package configuration, the ground wiring 55 and the external ground wiring 90 form a loop (hereinafter referred to as "ground loop").

FIG. 6 is a diagram schematically showing an equivalent circuit of the ground loop and the ground potential distribution in the solid-state imaging device 1 according to the first embodiment of the present invention. FIG. 6 shows an equivalent circuit for one column of pixels in the ground loop shown in FIG. In a field where a magnetic field exists, when the magnetic flux B penetrates the ground loop, an induced electromotive force V corresponding to the time change of the magnetic flux B is generated in the ground loop. This follows Faraday's law, and the relationship between the induced electromotive force V and the change ΔB of the magnetic flux B in the minute time Δt is represented by V=−ΔB/Δt.

When the magnetic flux B faces 180° in the opposite direction, the electromotive force and the current flow in opposite directions. Further, even when the magnetic flux B is inclined in an oblique direction with respect to the loop plane of the ground wiring, an electromotive force is generated by the component of the magnetic flux B in the direction perpendicular to the loop surface. This electromotive force causes a voltage distribution in the ground loop, which is originally the same potential, and the signal of the pixel 10 is swung by the ground potential distribution. In the output image of the solid-state image sensor 1, it appears as pattern noise in the image (magnetic noise). The external ground wire 90 does not necessarily have to be inside the package. Even when the solid-state imaging device 1 is connected to the PCB substrate, electromotive force is generated when the ground loop is formed as described above. Further, the ground loop does not necessarily have to be an electrically closed loop, and for example, even when the external ground wiring 90 is partially broken, the ground wiring 55 of the solid-state image sensor 1 is used. An induced electromotive force V may be generated between both ends of the.

Correspondence between the configuration of the solid-state imaging device 1 shown in FIG. 1 and the equivalent circuit of the ground loop shown in FIG. 6 will be described below. First, points A to C, O to Q, S, and S'on the ground loop shown in FIG. 1 will be described. As described above, the first contact 48 shown in FIG. 3 connects the ground electrode 53 of the hold capacitor 200 to the pixel ground wiring 51 in the pixel well region 101. The point of contact between the first contact 48 and the ground electrode 53 is point A. Strictly speaking, the point A shown in FIG. 1 is not located on the ground loop, but is located on the first contact 48 that connects the ground electrode 53 of the hold capacitor 200 to the ground loop. However, in the present embodiment, the pixel ground wiring 51 and the hold capacitor 200 are connected by a wiring having a low resistance, so that it can be considered that they have substantially the same potential. Therefore, in FIG. 6, point A is shown on the ground loop.

Next, in the pixel well region 101, among the plurality of pixel well contacts 42 connected to the pixel ground wiring 51, the pixel well contact 42 having the smallest electric resistance value up to the point A is set as the point B. Similarly, in the peripheral well region 100, among the plurality of peripheral well contacts 43 connected to the peripheral ground wiring 50, the peripheral well contact 43 arranged closest to the ground electrode 53 is set as a point C. In this embodiment, when the electric resistance values from the plurality of peripheral well contacts 43 to the ground electrode 53 are compared, the electric resistance value from the peripheral well contact 43 arranged at the point C to the ground electrode 53 is the minimum. Is. FIG. 1 shows points A, B, and C.

Next, among the peripheral well contacts 43 connected to the ground terminal of the differential amplifier circuit 30, the peripheral well contact 43 having the smallest electric resistance value up to the point A is set as the point Q. The ground terminal of the differential amplifier circuit 30 is, for example, the source region of the MOS transistor included in the differential amplifier circuit 30. The ground terminal of the differential amplifier circuit 30 is connected to the peripheral ground wiring. Further, the pixel well contact 42 connected to the ground terminal of the pixel 10 at the farthest position from the differential amplifier circuit 30 in the same column as the differential amplifier circuit 30 is defined as a point S. Similarly, the pixel well contact 42 connected to the ground terminal of the pixel 10 located closest to the differential amplifier circuit 30 in the same column as the differential amplifier circuit 30 is defined as a point S′. When there are a plurality of points S or S′, the peripheral well contact 43 having the smallest electric resistance from the ground terminal of the pixel 10 is represented as the point S or the point S′. FIG. 1 shows points Q, S, and S'.

Next, of the external ground terminals 60 that connect the peripheral ground wiring 50 to the reference potential outside the solid-state imaging device 1, the one that is connected to the ground terminal of the differential amplifier circuit 30 without passing through the pixel ground wiring 51. The external ground terminal 60 is defined as point P. Further, the external ground terminal 60, which is connected to the ground terminal of the differential amplifier circuit 30 via the pixel ground wiring 51, is defined as a point O. Point P and point O are shown in FIG.

Next, the electric resistance value between points in the equivalent circuit of the ground loop shown in FIG. 6 will be described with reference to FIGS. 1 and 6. The same symbols in FIGS. 1 and 6 represent the same things. First, the electrical resistance between points A and P will be described. The electric resistance value between points A and C is R2. In the present embodiment, since the electric resistance value of the intermediate wiring 63 is large, it can be considered that R2 is substantially equal to the electric resistance value of the intermediate wiring 63. Further, the electric resistance values between the points C and P and between the points C and Q are sufficiently smaller than the electric resistance value R2 and can be ignored in the equivalent circuit. Therefore, the electric resistance value between the points A and P is approximated to R2. Similarly, the electric resistance value from the point A to the peripheral ground wiring 50 is approximated to R2. Further, the electric resistance value from the point A to any peripheral well contact 43 connected to the peripheral ground wiring 50 is also approximated to R2.

Next, the electrical resistance between points A and S will be described. The electric resistance value between points A and B is R1, and the electric resistance value between points S'and S is R11. At this time, since the point B and the point S′ are arranged in the vicinity of each other, the electric resistance value between the points B and S′ is sufficiently smaller than the electric resistance value R11 between the points S′ and S, so that an equivalent circuit is obtained. The top can be ignored. Therefore, the electric resistance value between the points A and S is approximated to R11+R1.

Next, the electrical resistance between the points SO will be described. Since the point S-O is circuit-equivalent to the point S'-P described above, the point S-O is connected between the points A-S' (electrical resistance R1) and the points A-P ( It can be regarded as equivalent to the series connection of the electric resistance value R2). Therefore, the electric resistance value between the points SO is approximated to R1+R2.

Since the pixel ground wiring 51 has a uniform electric resistance in the plane, the electric resistance value of the ground wiring is generally proportional to the length of the wiring. Therefore, in general, R11>R1. Further, R1 actually includes the electric resistance value of the wiring from the ground electrode 53 of the hold capacitor 200 to the pixel ground wiring 51, but since it is sufficiently smaller than R11 and R1, it can be ignored in the equivalent circuit. ..

Considering the above-mentioned approximation, the electric resistance values R1, R11+R1, and R2 are, on the equivalent circuit, the electric resistance value between points A and S′, the electric resistance value between points A and S, and the point between points A and Q, respectively. Can be regarded as the electrical resistance value of. That is, the electric resistance values R1 and R11+R1 are the minimum electric resistance values from the pixel well contact 42 connected to the ground terminals of the plurality of pixels 10 in the same column as the differential amplifier circuit 30 to the first contact 48, respectively. It is approximated as the maximum value. The electric resistance values R1 and R11+R1 are resistance values of the electric path on the pixel ground wiring 51. The electric resistance value R2 is approximated as the minimum electric resistance value from the peripheral well contact 43 connected to the peripheral ground wiring 50 to the first contact 48, that is, the electric resistance value of the ground connection portion 52.

In this embodiment, the relationship of R1<R2 is satisfied. This effect will be described. The relationship between the electric resistance value between points and the induced electromotive force in the equivalent circuit of the ground loop shown in FIG. 6 will be described. As described above, when the magnetic flux B penetrates the ground loop, the induced electromotive force V corresponding to the time change of the magnetic flux B is generated in the ground loop. FIG. 6 shows the induced voltage difference V1 between the points A, S, the induced voltage difference V2 between the points A and P, and the induced voltage difference V3 between the points S and O of the induced electromotive force V generated in the ground loop. Shown respectively. These induced voltage differences V1 to V3 are expressed by the following formulas (1) to (3), because the induced electromotive force V is divided by the electric resistance value in each section.
V1=V×(R11+R1)/(R11+2×R1+2×R2) (1)
V2=V×R2/(R11+2×R1+2×R2) (2)
V3=V×(R2+R1)/(R11+2×R1+2×R2) (3)

Here, the signal from the pixel 10 input to the inverting input terminal (−) of the differential amplifier circuit 30 includes the induced voltage difference V1+V2 at the point S to which the ground terminal of the pixel 10 is connected, as magnetic noise. .. On the other hand, the reference signal input to the non-inverting input terminal (+) of the differential amplifier circuit 30 includes the induced voltage difference V2 at the point A to which the ground electrode 53 of the hold capacitor 200 is connected as magnetic noise. Therefore, the magnetic noise output Vout of the differential amplifier circuit 30 includes the induced voltage difference V1 between the points A and S, as shown in the following expression (4).
Vout=(V1+V2)-(V2)
=V1 (4)

Therefore, the above equation (1) is
V1=k×V (1')
However, k=(R11+R1)/(R11+2×R1+2×R2) <1
Then, it can be seen that the magnetic noise output Vout=k×V can be reduced by adjusting the electric resistance values R1, R11, and R2 to reduce the proportional constant k. Therefore, in the present embodiment, the intermediate wiring 63 is laid out in a meandering manner in the column direction and the row direction as shown in FIG. Is getting bigger.
R11+R1<R2 (5)

Thereby, for example, when R11+R1<R2, V1<V2 and V1<V3 are obtained from the above equations (1) to (3), and thus the magnetic noise output Vout (=V1) can be reduced. ..

In the equivalent circuit shown in FIG. 6, as the pixel 10 connected to the inverting input terminal (−) of the differential amplifier circuit 30, the pixel 10 at the farthest position in the same column as the differential amplifier circuit 30 (electrical resistance value Although R11+R1) is represented, another pixel 10 may be represented. For example, as the pixel 10 connected to the inverting input terminal (−), the pixel 10 (electrical resistance value R1) at the closest position in the same column as the differential amplifier circuit 30 may be represented. In this case, the following equation (6) is applied instead of the above equation (5).
R1<R2 (6)

Even in this case, for example, when R1<R2, similarly, V1<V2 and V1<V3 are satisfied, so that the magnetic noise output Vout (=V1) can be reduced.

As described above, the first feature of the present embodiment is that the ground electrode 53 of the hold capacitor 200 is connected to the pixel ground wiring 51 via the first contact 48. A second feature is that the electric resistance value R2 of the ground connection portion 52 that connects the pixel ground wiring 51 and the peripheral ground wiring 50 is set to be large so as to satisfy the above expression (6). As a result, magnetic noise generated in the ground wiring can be reduced.

Here, let us consider a case where the above-described first feature of the present invention is not satisfied. For example, this is a case where the ground electrode 53 of the hold capacitor 200 is connected to the peripheral ground wiring 50 (point Q) instead of the pixel ground wiring 51 (point A). At this time, the magnetic noise output Vout of the differential amplifier circuit 30 includes the induced voltage difference V1+V2 between the points S and Q in the equivalent circuit of FIG. 6, as shown in the following expression (7).
Vout=(V1+V2) (7)
=V×(R11+R1+R2)/(R11+2×R1+2×R2)

In this case, since the electric resistance values R1, R11, and R2 are included in the numerator and denominator of the above formula (7), the magnetic noise output Vout is reduced no matter how the electric resistance values R1, R11, and R2 are adjusted. You cannot do it.

Next, consider a case where the above-described second feature of the present invention is not satisfied. That is, this is a case where the electric resistance value R2 of the ground connection portion 52 does not satisfy the above expression (5) or (6) and is, for example, R11+R1>>R2. At this time, from (1) to (3), V1>V3>>V2 to 0. Therefore, even in this case, the magnetic noise output Vout cannot be reduced.

As described above, in the present embodiment, the read circuit (differential amplifier circuit) which is arranged in the peripheral well region where the peripheral ground wiring is arranged and which reads out the signal from the pixel in the same column by referring to the reference signal is provided. ing. Further, it has a first electrode (ground electrode) to which a ground voltage is supplied from the pixel ground wiring and a second electrode (control electrode) arranged so as to face the first electrode, and outputs a reference signal to the readout circuit. A reference signal circuit (hold capacitance) is provided. Further, the minimum value R2 of the electric resistance value from the pixel ground wiring to the peripheral ground wiring is increased so as to satisfy the above expression (6). As a result, it is possible to obtain a solid-state imaging device, a method for manufacturing the solid-state imaging device, and an imaging system that can reduce magnetic noise generated in the ground wiring without newly adding a circuit for noise reduction.

In addition, in FIG. 4, the ground connection portion 52 is configured by one intermediate wiring 63, but may be configured by a plurality of wirings. Further, the ground connection portion 52 may be electrically connected to the peripheral ground wiring 50 and the pixel ground wiring 51. Further, although the peripheral ground wiring 50 and the pixel ground wiring 51 are shown as being arranged in one layer, respectively, they may be arranged in a plurality of layers. Further, the peripheral ground wiring 50 and the pixel ground wiring 51 may have any shape.

Further, FIG. 1 shows a layout in which the peripheral well region 100 includes a first peripheral well region provided on one side of the pixel well region 101 and a second peripheral well region provided on the other side. It was However, the configuration is not necessarily limited to this. For example, even when the first peripheral well region and the second peripheral well region are connected to each other by bypassing the pixel well region 101, or when the peripheral well region 100 is composed of only the first peripheral well region, The same effect can be obtained.

[Second Embodiment]
The solid-state imaging device according to this embodiment will be described with reference to FIG. 7. FIG. 7: is a figure which shows typically the plane structure of the ground connection part 52b which concerns on the 2nd Embodiment of this invention. The present embodiment is different from the first embodiment in that the ground connection portion 52b is electrically connected to the external ground potential outside the solid-state imaging device 1 via the external ground terminal 60. .. The other points are the same as those in the first embodiment, and the description thereof will be omitted.

In the ground connection portion 52b shown in FIG. 7, the intermediate wiring 63 described in the first embodiment shown in FIG. 4 is electrically connected to the external ground potential outside the solid-state imaging device 1 via the external ground terminal 60. It is a thing. Even in this case, as in the first embodiment, the peripheral ground wiring 50 and the pixel ground wiring 51 are connected by the high resistance electric resistance value R2 corresponding to the distance of the intermediate wiring 63. Therefore, also in the present embodiment, since the above expression (6) is satisfied, the magnetic noise generated in the ground wiring can be reduced.

The intermediate wiring 63 may be a plurality of wirings. Further, the intermediate wiring 63 may be connected to a connection line that connects the peripheral ground wiring 50 and the external ground terminal 60 as shown in FIG. 7, or may be directly connected to the external ground terminal 60. .. This embodiment can be combined with the first embodiment.

[Third Embodiment]
The solid-state imaging device according to this embodiment will be described with reference to FIG. FIG. 8: is a figure which shows typically the plane structure of the ground connection part 52c which concerns on the 3rd Embodiment of this invention. The present embodiment is different from the first embodiment in that the intermediate wiring 64 passes through a well region 102 that is different from both the pixel well region 101 and the peripheral well region 100. The other points are the same as those in the first embodiment, and the description thereof will be omitted.

The ground connection portion 52c shown in FIG. 8 has a configuration in which the intermediate wiring 64 passes through a well region 102 different from the pixel well region 101 and the peripheral well region 100 shown in FIG. The well region 102 is not connected to the pixel well region 101 and the peripheral well region 100 via the well. The well region 102 is connected to the peripheral ground wiring 50 and the pixel ground wiring 51 by the well contact 44, respectively. The well region 102 and the peripheral ground wiring 50, and the well region 102 and the pixel ground wiring 51 do not necessarily need to be connected by a single well contact 44 as shown in FIG. .. For example, a plurality of well contacts 44 may be connected.

With the above configuration, the peripheral well region 100 and the pixel well region 101 are connected via the high resistance well region 102. As a result, also in the present embodiment, as in the first embodiment, the above equation (6) is satisfied, so that the magnetic noise generated in the ground wiring can be reduced. Note that there may be a plurality of well regions 102 as long as they satisfy the above conditions. This embodiment can be combined with the first and second embodiments.

[Fourth Embodiment]
The solid-state imaging device according to this embodiment will be described with reference to FIG. FIG. 9: is a figure which shows typically the plane structure of the ground connection part 52d which concerns on the 4th Embodiment of this invention. The present embodiment is different from the first embodiment in that the intermediate wiring 64 electrically connects different wiring layers via the well contact 45. The other points are the same as those in the first embodiment, and the description thereof will be omitted.

As shown in FIG. 9, the intermediate wiring 64 shown in FIG. 9 passes through the well contact 45 disposed between the peripheral ground wiring 50 and the pixel ground wiring 51. At this time, the peripheral ground wiring 50 and the pixel ground wiring 51 are arranged in different layers. As a result, the peripheral ground wiring 50 and the pixel ground wiring 51 are connected via the well contact 45 having high resistance. With the above configuration, also in the present embodiment, as in the first embodiment, since the above expression (6) is satisfied, magnetic noise generated in the ground wiring can be reduced. This embodiment can be combined with the first to third embodiments.

[Fifth Embodiment]
The solid-state imaging device according to this embodiment will be described with reference to FIGS. FIG. 10: is a figure which shows typically the structure of the solid-state image sensor 1b which concerns on the 5th Embodiment of this invention. In the first embodiment, the case where the readout circuit includes the differential amplifier circuit 30 that amplifies the signal from the pixel 10 with reference to the reference signal has been described. On the other hand, in the present embodiment, the case where the readout circuit includes an AD converter (analog-digital converter) 31 that performs A/D conversion (analog-digital conversion) of the signal from the pixel 10 with reference to the reference signal will be described. To do.

The solid-state imaging device 1b of this embodiment shown in FIG. 10 has a configuration in which the differential amplifier circuit 30 of the first embodiment shown in FIG. 1 is replaced with an AD converter 31. The AD converter 31 is arranged in the peripheral well region 100 and reads the signal from the pixel 10 in the same column by referring to the reference signal. More specifically, the AD converter 31 compares the signal from the pixel 10 with the RAMP signal output from the ramp signal generation circuit 201 to convert the analog signal from the pixel 10 into a digital signal. D-convert. In the AD converter 31 shown in FIG. 10, peripheral circuits are omitted and shown conceptually.

The ramp signal generation circuit 201 is arranged in the third well region 103 in which the ground wiring 56 is arranged. Here, the ground wiring 56 in the third well region 103 is connected to the pixel ground wiring 51 with low resistance. That is, the third well region 103 can be regarded as sharing the pixel ground line 51 with the pixel well region 101. The ground terminal of the ramp signal generation circuit 201 is connected to the ground wiring 56 connected to the pixel ground wiring 51 via the well contact 46. Therefore, the RAMP signal output from the ramp signal generation circuit 201 is generated with the pixel ground wiring 51 as the reference potential. The AD converter 31 and the ramp signal generation circuit 201 are controlled by the peripheral circuit control unit 71.

Here, when comparing the solid-state image sensor 1 of the first embodiment shown in FIG. 1 with the solid-state image sensor 1b of this embodiment shown in FIG. 10, the well contact 46 of FIG. Therefore, it can be understood that the method in the first embodiment can be applied as it is. Therefore, in the following description of this embodiment, the well contact 46 is referred to as the first contact 46, and the contact point between the first contact 46 and the pixel ground wiring 51 is point A. There may be a plurality of first contacts 46. In this case, one of the plurality of first contacts 46 is designated as the point A.

FIG. 11 is a diagram schematically showing an equivalent circuit of the ground loop and a ground potential distribution in the solid-state imaging device 1b according to the fifth embodiment of the present invention. The equivalent circuit of the ground loop according to the present embodiment shown in FIG. 11 is the first circuit shown in FIG. 6 except that the differential amplifier circuit 30 is the AD converter 31 and the hold capacitor 200 is the ramp signal generation circuit 201. It is the same as the equivalent circuit of the ground loop according to the embodiment. Therefore, the induced voltage differences V1 to V3 between the points on the ground loop are represented by the above equations (1) to (3), as in the first embodiment.

As described above, also in the present embodiment, the first feature is that the ground terminal of the ramp signal generation circuit 201 is connected to the pixel ground wiring 51 via the first contact 46. A second feature is that the electric resistance value R2 of the ground connection portion 52 that connects the pixel ground wiring 51 and the peripheral ground wiring 50 is set to a large value so as to satisfy the above expression (6). As a result, magnetic noise generated in the ground wiring can be reduced.

FIG. 12 is a diagram schematically showing magnetic noise included in the input to the AD converter 31 according to the fifth embodiment of the present invention. The AD converter 31 of the present embodiment compares the signal from the pixel 10 with the reference signal and performs A/D conversion. Here, in the signal from the pixel 10, the induced voltage difference V1+V2 at the point S connected to the ground terminal of the pixel 10 is included as magnetic noise. On the other hand, the reference signal includes the induced voltage difference V2 at the point A connected to the ground terminal of the ramp signal generation circuit 201 as magnetic noise. Therefore, the output of the AD converter 31 includes the induced voltage difference V1 between points A and S shown in the above equation (4), which is the difference between them, as the magnetic noise output Vout. In the following description, it is assumed that the magnetic flux B changes sinusoidally with time.

FIG. 12A shows ideal time change waveforms of the signal from the pixel 10 and the RAMP signal when magnetic noise is not included in both the signal from the pixel 10 and the reference signal. The AD converter 31 digitally converts the signal from the pixel 10 at time t1 when the signal from the pixel 10 and the RAMP signal match, and outputs the signal as a pixel signal.

FIG. 12B shows a time change waveform of the signal from the pixel 10 and the RAMP signal when only the signal from the pixel 10 contains magnetic noise. This corresponds to the case where the above-described first feature of the present invention is not satisfied. Specifically, this is the case where the ground terminal of the ramp signal generation circuit 201 shown in FIG. 11 is connected to the peripheral ground wiring 50 (point Q) instead of the pixel ground wiring 51 (point A). In this case, an induced voltage difference V1+V2 occurs at the point S connected to the ground terminal of the pixel 10. On the other hand, almost no induced voltage is generated at the point Q connected to the ground terminal of the ramp signal generation circuit 201. The AD converter 31 converts the signal from the pixel 10 at time t2 when the signal from the pixel 10 and the RAMP signal match each other into a digital signal and outputs the digital signal as a pixel signal. As a result, an error corresponding to time t1-t2 occurs with respect to the original output signal.

FIG. 12C shows time-varying waveforms of the signal from the pixel 10 and the RAMP signal when magnetic noise is included in both the signal from the pixel 10 and the reference signal. This corresponds to the case where the first feature of the present invention described above is satisfied. That is, this is the case where the ground terminal of the ramp signal generation circuit 201 shown in FIG. 11 is connected to the pixel ground wiring 51 (point A). In FIG. 12C, an induced voltage difference V1+V2 occurs at a point S connected to the ground terminal of the pixel 10. On the other hand, an induced voltage difference V2 is generated at a point A connected to the ground terminal of the ramp signal generation circuit 201. The AD converter 31 converts the signal from the pixel 10 at time t3 when the signal from the pixel 10 and the RAMP signal match each other into a digital signal and outputs the digital signal as a pixel signal. As a result, although an error corresponding to time t1-t3 occurs with respect to the original output signal, since t1-t3<t1-t2, magnetic noise generated in the ground wiring can be reduced.

The cause of such an error of t1-t3 is the induced voltage difference V1 generated at the electric resistance value R11+R1. Here, when the induced voltage difference V1 is sufficiently negligible, that is, when the second feature of the present invention described above is further satisfied, a sine wave substantially equal to both the signal from the pixel 10 and the RAMP signal is included. .. Under this condition, the error corresponding to the time t1 to t3 of the signal from the pixel 10 and the RAMP signal is almost the same as the ideal signal shown in FIG. The signal becomes a signal substantially corresponding to the time t1.

As described above, in the present embodiment, the read circuit (AD converter) that is arranged in the peripheral well region in which the peripheral ground wiring is arranged and that reads out the signal from the pixel in the same column by referring to the reference signal is provided. .. Further, the ground terminal is electrically connected to the pixel ground wiring via the first contact, and a reference signal circuit (ramp signal generation circuit) for outputting a reference signal to the readout circuit is provided. Further, the minimum value R2 of the electric resistance value from the pixel ground wiring to the peripheral ground wiring is increased so as to satisfy the above expression (6). As a result, it is possible to obtain a solid-state imaging device, a method for manufacturing the solid-state imaging device, and an imaging system that can reduce magnetic noise generated in the ground wiring without newly adding a circuit for noise reduction. It should be noted that this embodiment can be combined with the above second to fourth embodiments.

Although the ramp signal generation circuit 201 of this embodiment is formed in the third well region 103, the third well region 103 is formed in the pixel well region 101 and the peripheral well region 100. May be. However, in this case, the third well region 103 in which the ramp signal generation circuit 201 is configured and the peripheral well region 100 are not connected by a common well, that is, they need to be independent well regions. At this time, the third well region 103, which serves as an external ground of the ramp signal generation circuit 201, is connected by extending a low resistance wiring from the pixel ground wiring 51.

[Sixth Embodiment]
The solid-state imaging device according to this embodiment will be described with reference to FIGS. 13 to 15. FIG. 13: is a figure which shows typically the structure of the solid-state image sensor 1c which concerns on the 6th Embodiment of this invention. In this embodiment, the case where the pixel well region 101 and the peripheral well region 100 are arranged on different semiconductor substrates will be described.

A solid-state image sensor 1c of the present embodiment shown in FIG. 13 is an example of a stacked solid-state image sensor including a semiconductor substrate 1000 and a semiconductor substrate 2000. The semiconductor substrate 1000 and the semiconductor substrate 2000 are connected at least by the connection electrode 501. In this embodiment, the semiconductor substrate 1000 and the semiconductor substrate 2000 are further connected by the connection electrodes 500 and 502. Components related to the pixel 10, such as the pixel well region 101, the vertical scanning circuit 70, and the pixel ground wiring 51, are included in the semiconductor substrate 1000. On the other hand, the semiconductor substrate 2000 includes components related to the peripheral circuit such as the peripheral well region 100, the peripheral circuit control unit 71, the differential amplifier circuit 30, the peripheral ground wiring 50, and the hold capacitor 200.

The connection electrode 500 connects the pixel ground wiring 51 and the peripheral ground wiring 50. The connection electrode 501 connects the hold capacitor 200 and the pixel ground wiring 51. The connection electrode 502 connects the vertical signal line 20 and the inverting input terminal (−) of the differential amplifier circuit 30. The connection electrode 500 corresponds to the ground connection portion 52 in the first embodiment in terms of an equivalent circuit, and the connection electrode 501 corresponds to the first contact 48 in the first embodiment in terms of an equivalent circuit. Note that the pixel ground wiring 51 and the peripheral ground wiring 50 are configured to be connected by a plurality of connection electrodes 500 in order to reduce the wiring impedance of the power source, and in this embodiment, they are connected at two locations. The peripheral ground wiring 50 is electrically connected to an external ground potential outside the solid-state imaging device 1c via an external ground terminal 60. The other points are the same as those in the first embodiment, and the description thereof will be omitted.

FIG. 14: is a figure which shows typically the cross-section of the solid-state image sensor 1c which concerns on the 6th Embodiment of this invention. The semiconductor substrate 1000 and the semiconductor substrate 2000 are connected by the connection electrodes 500, 501, and 502 with the insulator 600 interposed therebetween. Although the connection electrodes 500, 501, and 502 are collectively shown in FIG. 14, the connection electrodes 500 are actually provided at two locations, and the connection electrodes 501 and 502 are provided corresponding to pixels to be arranged. The insulator 600 may be made of a magnetic shield (a material having high magnetic permeability) other than the periphery of the connection electrodes 500, 501 and 502.

FIG. 15 is a diagram schematically showing an equivalent circuit of a ground loop and a ground potential distribution in the solid-state imaging device 1c according to the sixth embodiment of the present invention. This is an example in which a ground loop is formed between the semiconductor substrate 1000 and the semiconductor substrate 2000 via the points U and T as compared with FIG. Similar to the first embodiment, the induced voltage differences V1 to V3 are expressed by the following equations (8) to (10).
V1=V×(R11+R1)/(R11+2×R1+2×R2) (8)
V2=V×R2/(R11+2×R1+2×R2) (9)
V3=V×(R2+R1)/(R11+2×R1+2×R2) (10)

Also in the case of the present embodiment, the values of the electric resistance values R1, R11, R2 are set so as to satisfy the above-described equations (5) and (6). The resistance value R1 of the electric path from one of the plurality of pixel well contacts 42 to the ground electrode 53 and the electric path of the electric path from the peripheral well contact 43 (point C) arranged closest to the ground electrode 53 to the ground electrode 53 The resistance value R2 satisfies the relationship of R1<R2. With such a configuration, the same effect as that of the first embodiment can be obtained. In other words, since the ground electrode 53 of the hold capacitor 200 is connected to the pixel ground wiring 51, magnetic noise generated in the ground wiring can be reduced.

As described above, in the present embodiment, since the area related to the peripheral circuit can be reduced by forming the stacked type solid-state imaging device with the connection electrodes, the chip size of the solid-state imaging device is smaller than that in the first embodiment. Can be suppressed.

Further, since it is possible to adjust the electric resistance value according to the arrangement positions of the connection electrodes 500 to 502 of the semiconductor substrates 1000 and 2000 and the electric resistance values R1 and R2 depending on the material of the connection electrode, the electric resistance value can be easily designed. it can. Therefore, the degree of freedom in design for reducing the proportional constant k of the above equation (1') is improved, and the same effect as that of the first embodiment can be obtained more effectively. The configuration of this embodiment can be applied to the fifth embodiment.

[Seventh Embodiment]
The imaging system according to this embodiment will be described below with reference to FIG. FIG. 16 is a diagram showing the configuration of the imaging system according to the seventh embodiment of the present invention. In this embodiment, an example of an imaging system to which the configurations shown in the first to sixth embodiments are applied will be described.

The imaging system 800 shown in FIG. 16 is configured to include, for example, an optical unit 810, an imaging device 820, a recording/communication unit 840, a timing control unit 850, a system control unit 860, and a reproduction/display unit 870. Here, the imaging device 820 includes the solid-state imaging device 1 (or 1b, 1c, the same applies hereinafter) and the video signal processing unit 830. A converter is used.

An optical unit 810, which is an optical system such as a lens, forms light of a subject on a pixel array in which a plurality of pixels of the solid-state image sensor 1 are two-dimensionally arranged to form a subject image. The solid-state imaging device 1 outputs a signal corresponding to the light imaged on the pixel array at a timing based on the signal from the timing control unit 850. The signal output from the solid-state image sensor 1 is input to the video signal processing unit 830, and the video signal processing unit 830 performs signal processing according to a method determined by a program or the like. The signal obtained by the processing in the video signal processing unit 830 is sent to the recording/communication unit 840 as image data. The recording/communication unit 840 sends a signal for forming an image to the reproduction/display unit 870, and causes the reproduction/display unit 870 to reproduce/display a moving image or a still image. The recording/communication unit 840 also receives a signal from the video signal processing unit 830 and communicates with the system control unit 860, and also performs an operation of recording a signal for forming an image on a recording medium (not shown). To do.

The system control unit 860 centrally controls the operation of the imaging system, and controls the driving of the optical unit 810, the timing control unit 850, the recording/communication unit 840, and the reproduction/display unit 870. The optical unit 810 is driven by, for example, a motor (not shown), and performs camera shake correction and focus position adjustment. In the first to sixth embodiments, examples of the magnetic noise source that affects the ground wiring include a magnetic field generated by this motor.

Further, the system control unit 860 includes, for example, a storage device (not shown) which is a recording medium, and a program or the like necessary for controlling the operation of the imaging system is recorded therein. Further, the system control unit 860 supplies a signal for switching the drive mode to the inside of the imaging system according to, for example, a user operation. Specific examples include changing the row to be read or the row to be reset, changing the angle of view due to electronic zoom, and shifting the angle of view due to electronic image stabilization. The timing control unit 850 controls the drive timing of the solid-state imaging device 1 and the video signal processing unit 830 based on the control of the system control unit 860.

1... Solid-state image sensor 10... Pixel 20... Vertical signal line 30... Differential amplifier circuit (readout circuit)
31 ... AD converter (readout circuit)
42... Pixel well contact 43... Peripheral well contact 50... Peripheral ground wiring 51... Pixel ground wiring 52... Ground connection part 60... External ground terminal 70... Vertical scanning circuit 71・・・Peripheral circuit control unit 100 ・・・Peripheral well region 101 ・・・Pixel well region 200 ・・・Hold capacitance (reference signal circuit)
201 ・・・Ramp signal generation circuit (reference signal circuit)
300... Switch transistors 500, 501, 502... Connection electrode 600... Insulator, magnetic shield 1000, 2000... Semiconductor substrate

Claims (17)

A semiconductor substrate including a pixel well region and a peripheral well region;
A pixel ground line disposed on the pixel well region,
A peripheral ground wiring disposed on the peripheral well region,
A ground connection portion that electrically connects the pixel ground wiring and the peripheral ground wiring,
A plurality of pixel well contacts that connect the pixel ground line and the pixel well region,
A plurality of peripheral well contacts connecting the peripheral ground wiring and the peripheral well region,
A plurality of pixels arranged in the pixel well region to form a plurality of columns, each of which outputs a pixel signal;
A read circuit arranged in the peripheral well region and having a first input terminal for receiving the pixel signals from the plurality of pixels and a second input terminal for receiving a reference signal;
A reference signal circuit arranged in the peripheral well region, having a first electrode supplied with a ground voltage, and outputting the reference signal to the second input terminal of the read circuit;
A wiring that connects the first electrode of the reference signal circuit and the pixel ground wiring,
Equipped with
The pixel ground wiring, the ground wiring including the peripheral ground wiring and the ground connection portion form a loop with an external ground wiring,
Of the plurality of pixel well contacts, the resistance value R1 of the electrical path having the smallest electric resistance value to the first electrode, and the one of the plurality of peripheral well contacts arranged closest to the first electrode. And the resistance value R2 of the electric path from one to the first electrode via the ground connection section satisfies the relationship of R1<R2,
A solid-state imaging device characterized by the above. Satisfying the relationship of R1<R2 for each of the plurality of pixel well contacts,
The solid-state imaging device according to claim 1, wherein The read circuit includes a differential amplifier circuit that amplifies a signal from the pixel with reference to the reference signal,
The reference signal circuit includes a capacitance including the first electrode and a second electrode that is arranged to face the first electrode and is connected to the second input terminal of the read circuit.
The solid-state imaging device according to claim 1, wherein The reference signal circuit has a switch transistor connected to the second electrode of the capacitor,
Holding the reference signal in the capacitor by controlling the switch transistor,
The solid-state imaging device according to claim 3, wherein. The readout circuit includes an analog-digital converter that performs analog-digital conversion on a signal from the pixel with reference to the reference signal,
The reference signal circuit includes a ramp signal generation circuit that generates a ramp signal that changes with time as the reference signal,
The solid-state imaging device according to claim 1, wherein The solid-state imaging device according to claim 1, wherein the pixel ground wiring and the peripheral ground wiring are electrically connected to each other via a ground connection portion. The ground connection portion meanders in a direction along the plurality of rows and in a crossing direction,
7. The solid-state image sensor according to claim 6, wherein The ground connection portion is electrically connected to an external ground potential via an external ground terminal,
The solid-state image sensor according to claim 6 or 7, characterized in that. 9. The solid-state imaging device according to claim 6, wherein the ground connection unit connects different wiring layers via a well contact. The ground connection portion includes a semiconductor region arranged on the semiconductor substrate.
10. The solid-state image sensor according to claim 6, wherein the solid-state image sensor is a solid-state image sensor. The peripheral well region includes a first peripheral well region and a second peripheral well region,
The pixel well region is disposed between the first peripheral well region and the second peripheral well region,
The peripheral ground line includes a first peripheral ground line arranged on the first peripheral well region and a second peripheral ground line arranged on the second peripheral well region.
The solid-state imaging device according to any one of claims 1 1 0, characterized in that. The readout circuit is connected to the peripheral ground line,
The solid-state imaging device according to any one of claims 1 1 1, characterized in that. The semiconductor substrate includes a first semiconductor substrate and a second semiconductor substrate,
The pixel well region is disposed on the first semiconductor substrate,
The peripheral well region is disposed on the second semiconductor substrate,
The solid-state imaging device according to any one of claims 1 1 2, characterized in that. A semiconductor substrate including a pixel well region and a peripheral well region;
A pixel ground line disposed on the pixel well region,
A peripheral ground wiring disposed on the peripheral well region,
A ground connection portion that includes an intermediate wiring having a resistance value R2 and electrically connects the pixel ground wiring and the peripheral ground wiring;
A plurality of pixel well contacts that connect the pixel ground line and the pixel well region,
A plurality of pixels arranged in the pixel well region to form a plurality of columns, each of which outputs a pixel signal;
A read circuit arranged in the peripheral well region and having a first input terminal for receiving the pixel signals from the plurality of pixels and a second input terminal for receiving a reference signal;
A reference signal circuit arranged in the peripheral well region, having a first electrode supplied with a ground voltage, and outputting the reference signal to the second input terminal of the read circuit;
A wiring that connects the first electrode of the reference signal circuit and the pixel ground wiring,
Equipped with
The pixel ground wiring, the peripheral ground wiring, and the ground connection portion form a loop with an external ground wiring,
Of the plurality of pixel well contacts, a resistance value R1 of an electric path having the smallest electric resistance value to the first electrode and an electric path of the electric path from the peripheral ground wire to the first electrode via the intermediate wire The resistance value R2 satisfies the relationship of R1<R2,
A solid-state imaging device characterized by the above. A solid-state imaging device according to any one of claims 1 1 4,
A video signal processing unit that processes an output signal from the reading circuit;
An imaging system comprising: A solid-state imaging device according to any one of claims 1 1 4,
An optical unit that forms an image of light from a subject on the solid-state image sensor,
A motor for driving the optical unit,
An imaging system comprising: Arranging a pixel array in which a plurality of pixels are two-dimensionally arranged in a row direction and a column direction in a pixel well region in which a pixel ground wiring is arranged;
Arranging a read circuit for reading out a signal from the pixel in the same column by referring to a reference signal in a peripheral well region in which a peripheral ground wiring is arranged;
A step of arranging a ground connection part including an intermediate wiring having a resistance value R2 and electrically connecting the pixel ground wiring and the peripheral ground wiring, the pixel ground wiring, the peripheral ground wiring, and the ground connection. Part forms a loop with an external ground wire, arranging a ground connection part, and
A step of electrically connecting a ground terminal of a reference signal circuit for outputting the reference signal to the readout circuit to the pixel ground wiring via a first contact, the plurality of pixels in the same column as the readout circuit. Of the pixel well contacts connecting the ground terminals of the above to the pixel ground wiring, the resistance value of the electric path having the smallest electric resistance value to the first contact is R1, and the ground terminal of the readout circuit is the peripheral ground wiring. When the minimum value of the electric resistance value from the peripheral well contact connected to the first contact to the first contact through the intermediate wiring is R2, the connection is made so as to satisfy R1<R2,
A method of manufacturing a solid-state imaging device, comprising:

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