JP6734180B2 - Analog adder circuit, ultrasonic probe using the same, and ultrasonic diagnostic apparatus - Google Patents

Description

According to the present invention, a reception signal from each transducer in an array, which is mounted on an ultrasonic probe which is a constituent element of an ultrasonic diagnostic apparatus and is repeatedly arranged one-dimensionally or two-dimensionally, is provided for each ultrasonic transducer. The present invention relates to a technique for realizing an analog adder circuit required for delay addition phasing that independently delays and performs focusing with a wide band and low power consumption.

The ultrasonic diagnostic apparatus is a medical diagnostic apparatus that is non-invasive to the human body and highly safe, and has a smaller apparatus scale than other medical image diagnostic apparatuses such as an X-ray diagnostic apparatus and an MRI (Magnetic Resonance Imaging) apparatus. It is an important device in today's medical care because it is a device that can display in real time the movement of the test object such as the pulsation of the heart or the movement of the fetus by a simple operation of applying the ultrasonic probe from the body surface. Plays a role.

In the ultrasonic diagnostic apparatus, a high-voltage drive signal is supplied to each of a plurality of transducers incorporated in the ultrasonic probe to transmit ultrasonic waves into the subject. The plurality of vibrating elements receive the reflected waves of the ultrasonic waves generated by the difference in the acoustic impedance of the living tissue in the subject, and generate an image based on the reflected waves received by the ultrasonic probe.

Specifically, in transmission, an acoustic pulse is focused by giving an independent delay to a plurality of transducers to drive the transducers, and ultrasonic beamforming and beam scanning are performed. In reception, in order to compensate for the difference in the distance from the reflection point in the living body to each transducer, independent delay is given to multiple transducers to align the signal phases coherently, and the phasing addition is performed. Perform processing. As described above, delay and addition of analog signals are essential signal processing in the ultrasonic diagnostic apparatus.

In recent years, an ultrasonic diagnostic apparatus capable of obtaining a three-dimensional stereoscopic image has been developed, and the inspection efficiency can be improved by specifying an arbitrary cross section from the three-dimensional stereoscopic image and obtaining a tomographic image. For three-dimensional imaging, it is necessary to change the transducers in the ultrasonic probe from a conventional one-dimensional array to a two-dimensional array, that is, a 2D array. To the square. In this case, since it is difficult to increase the number of cables connecting the ultrasonic probe and the main body device by the square, it is necessary to perform phasing addition in the ultrasonic probe to reduce the number of received signals in the main body. It has to be transferred to the device via a cable. In order to realize phasing addition in such an ultrasonic probe, the functions of transmission/reception and phasing addition are realized as a beamformer IC, and a transmission/reception circuit is arranged for each transducer in the IC. It is necessary to make an electrical one-to-one connection with the vibrator.

In the 2D array ultrasonic probe, it is necessary to mount an IC that performs phasing addition in the probe, and several thousand to 10,000 or more transceiver circuits are mounted in the IC. Since the probe is in direct contact with the body surface, it is necessary to suppress heat generation, and low power consumption of the IC is an important issue.

Also, although the higher the frequency of the ultrasonic wave, the greater the attenuation in the living body, the spatial resolution of the image obtained from the ultrasonic echo is improved. Therefore, the frequency of the ultrasonic wave should be as high as possible to reduce the band of the receiving circuit. I want to take it widely. It is necessary to realize a wideband receiving circuit with low power consumption as described above.

As a circuit that realizes the addition of analog signals required for phasing processing, a circuit that uses an operational amplifier to add signals by current is conceivable. Will grow. As a circuit that performs analog addition with low power consumption, a passive analog addition circuit in which signal charges are stored in a capacitor and signal addition is performed can be considered.

As an example of a circuit that cancels the charge history of such a capacitor, a delay circuit using a plurality of capacitors has been proposed in Japanese Patent Laid-Open No. 2004-242242.

International publication WO 2015/128974 A1

In the case of a circuit that passively adds charges using only a switch and a capacitor, there is no circuit that buffers with low impedance, so it is strongly affected by parasitic capacitance, and the bandwidth as an analog adder circuit may deteriorate due to parasitic capacitance. I'm worried. In particular, since the charge is shared between the capacitor that stores the signal charge and the parasitic capacitance, when a circuit of a discrete time sampling system that operates in synchronization with the clock is configured, the capacitor for signal charge and the parasitic capacitance are changed in the previous clock cycle. It is affected by the history of stored charge.

FIG. 13 is a drawing in which FIG. 16 of Patent Document 1 is redrawn from the viewpoint of the inventor in order to explain the problem of the present invention. The circuit of FIG. 13 holds analog voltages in order in a plurality of capacitors and delays the analog signal by reading out after a predetermined time. In the example of FIG. 13, the difference between the differential analog signal voltage inputs Vinp and Vinn is stored in the capacitor Cs as an electric charge, but since the accumulated electric charge changes depending on the initial state before the input signal is stored, the capacitor Cs changes. It has been shown that it is useful to reset the capacitor charge before the voltage level is stored as charge. That is, the output impedance of the front-end circuit is not ideal 0Ω, but has an impedance higher than 0Ω and thus depends on such an initial charge state.

The charges accumulated in Cs by being driven from the previous stage by turning on SWinp and SWinn are output to the latter stage as a voltage by turning on SWoutp and SWoutn, and the charges of Cs are reset by turning on SWrst. Then, SWinp and SWinn are turned on to return to the initial state before electric charges are accumulated in Cs.

However, when considering the load in the latter stage of the circuit of FIG. 13, for example, when a circuit having a large input capacitance is connected to Voutp and Voutn, or the distance to the next stage circuit is long, a large wiring parasitic capacitance is added. In this case, when SWoutp and SWoutn are turned on, the charge is shared by Cs and this load capacitance. However, even if the signal charge of Cs can be reset by SWrst, the charge accumulated in the load capacitance cannot be reset.

Patent Document 1 describes that it is desirable to perform reset after turning on SWoutp and SWoutn to output a signal or before accumulating a signal as an electric charge. However, regarding the load capacitance connected to the output, There is no description. Further, FIG. 13 of Patent Document 1 discloses a configuration in which an output is buffered by using an operational amplifier. However, when a circuit that consumes a steady bias current such as an operational amplifier is used, power consumption increases. There is a problem.

From this point of view, while using a sample hold circuit that accumulates a signal by charge, without using a buffer circuit that consumes a steady bias current such as an operational amplifier, even if the output load capacitance is large, It is required to cancel the charge history by resetting the charges accumulated in both the capacitor and the output load capacitance to realize a wideband circuit.

The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

One aspect of the present invention for achieving the above object is to provide a plurality of input terminals, a plurality of sample and hold circuit blocks corresponding to the plurality of input terminals, and outputs of the plurality of sample and hold circuit blocks as inputs. , An analog adder circuit having a multiplexer for generating one output. In this circuit, each of the plurality of sample and hold circuit blocks includes a first capacitor, a second capacitor, and a third capacitor. In addition, a first wiring that connects the first capacitance and the multiplexer, a second wiring that connects the second capacitance and the multiplexer, and a third wiring that connects the third capacitance and the multiplexer are provided. Then, for each of the first capacitance, the second capacitance, and the third capacitance, a first state in which the input terminal is connected and disconnected from the multiplexer, and a first state in which the multiplexer is connected and disconnected from the input terminal A switch for exclusively setting three states of the second state, which is connected to a predetermined potential and is disconnected from the input terminal and the multiplexer, is provided. Further, it is arranged between the first capacitor and the multiplexer, and in the third state, it is arranged between the first reset switch for connecting the first wiring to a predetermined potential and the second capacitor and the multiplexer. , A second reset switch for connecting the second wiring to a predetermined potential in the third state, and the third reset switch arranged between the third capacitor and the multiplexer. In the third state, the third wiring is predetermined. A third reset switch for connecting to a potential.

Another aspect of the present invention is a plurality of input terminals, each of which is connected to an ultrasonic transducer, a plurality of receiving circuits corresponding to the plurality of input terminals one-to-one, and a plurality of receiving circuits. The ultrasonic probes each include a signal capacitor that stores a charge based on a signal obtained from an input terminal and an output wiring that integrates outputs of the signal capacitors of a plurality of receiving circuits. In this ultrasonic probe, the electric charges accumulated in the signal capacitors of the plurality of receiving circuits are redistributed by the signal capacitors of the plurality of receiving circuits to integrate the signals obtained from the plurality of input terminals, The charge and discharge history of the charges of the signal capacitor and the parasitic capacitor is reset by periodically setting the charge of the parasitic capacitor of the output wiring to a predetermined value.

Yet another aspect of the present invention is an ultrasonic diagnostic apparatus including an ultrasonic probe and a main body device. In this device, the ultrasonic probe has a plurality of ultrasonic transducers, a plurality of sample hold circuit blocks corresponding to the respective ultrasonic transducers, and outputs of the plurality of sample hold circuit blocks as inputs. A multiplexer and an output wiring that connects the sample and hold circuit block and the multiplexer are provided. Then, the output of the multiplexer is input to the main body device via the post-stage circuit. In addition, each of the sample hold circuit blocks includes a signal capacitor that stores electric charge based on the detection signal of the ultrasonic transducer. Further, a reset switch for periodically connecting the output wiring to a predetermined potential is provided.

Realizes a wideband analog adder circuit with low power consumption.

It is a circuit diagram showing the composition of the analog adder circuit of the example of the present invention. 3 is a timing chart illustrating the operation of the analog adder circuit in FIG. 1. It is a top view which shows the physical layout example of the analog addition circuit of an Example. FIG. 6 is a circuit diagram showing a configuration of a discrete-time sampling analog adder circuit in the case where charge history is not reset, in order to explain the effect of charge history reset on the adder circuit band. 5 is a timing chart for explaining the operation of the analog adder circuit of FIG. 4 at the time of step input. 5 is a circuit block diagram showing a signal flow and a transfer function of the analog addition circuit of FIG. 4. FIG. 3 is a timing chart for explaining the operation of the analog adder circuit of FIG. 1 at the time of step input. 2 is a circuit block diagram showing a signal flow and a transfer function of the analog adder circuit of FIG. 1. FIG. FIG. 5 is a graph showing frequency characteristics of the analog adder circuits of FIGS. 1 and 4. FIG. 7 is a circuit diagram showing a configuration of an analog adder circuit with a differential input and a single end output as another embodiment of the present invention. FIG. 1 is a block diagram showing a system configuration example of an ultrasonic diagnostic apparatus to which an embodiment is applied. It is a block diagram showing an example of composition of a transmitting and receiving circuit of IC inside an ultrasonic probe to which an example is applied. It is a circuit diagram of a comparative example.

The outline of the representative ones of the inventions disclosed in the embodiments will be briefly described as follows. That is, in an analog adder circuit that adds an analog signal by charge using a sample and hold circuit, periodically reset both the charge of a capacitor that stores the signal charge and the load capacitance that is connected to the output of the sample and hold circuit. Eliminates the influence of charge history, and realizes wideband analog addition processing with low power consumption even when the load capacity of the analog addition circuit is large.

As a result, a wideband analog adder circuit can be realized only by a passive circuit composed of only switches and capacitors without using a buffer circuit that consumes a steady bias current. In addition, this makes it possible to realize a receiving circuit that handles high-frequency ultrasonic waves. Although the higher the frequency of ultrasonic waves, the greater the attenuation in the living body, the higher the spatial resolution of echo images, so the higher the spatial resolution. A sonic image diagnostic apparatus can be realized. Further, it is possible to reduce the power of the IC in which the analog addition circuit is mounted, and it is possible to suppress the heat generation of the ultrasonic probe in which the IC is mounted.

FIG. 1 shows the configuration of the discrete-time analog adder circuit in this embodiment. Vin0, Vin1,..., Vin(N-1) receives the analog voltage input to the N terminals and outputs a signal added to Vout. In the case of an ultrasonic diagnostic apparatus, an analog voltage input is a signal obtained from each of a plurality of ultrasonic transducers, and the adder circuit shown in FIG. 1 should be used to obtain information obtained from a predetermined portion of the inspection object. You can The adder circuit shown in FIG. 1 is built in the ultrasonic probe and is composed of, for example, a semiconductor integrated circuit. The added output signal output from Vout is sent to the main body of the apparatus via a cable or the like through a necessary rear stage circuit.

The N sample-and-hold circuit blocks 10 have the same configuration, and each receives an analog voltage input from the N terminal. Cs is a capacitor (signal capacitor) for holding the input signal voltage as electric charge, and Cp is assumed to be a wiring parasitic capacitance (parasitic capacitor). That is, as will be described later, in an IC for a 2D array ultrasonic probe, it is necessary to wire the addition output from the inside of the array to the outside of the array with a long wiring, and Vp0, Vout1, and Vout2 with Cp It is assumed that the book wiring has a large parasitic capacitance Cp because it is wired from the inside of the array to the outside of the array. Since the analog multiplexer 13 is arranged outside the array, and the subsequent circuit connected to Vout can be arranged closely, the load on Vout is small, and the sample-hold circuit block 10 to the reset switch 12 and the analog multiplexer 13 are connected. Is long, and only the wiring parasitic capacitance Cp in this portion becomes a problem.

In this example, the sample and hold circuit block 10 includes three sample and hold circuits. In the connection between the analog multiplexer 13 and the post-stage circuit of the analog multiplexer 13, the length of the three wires between the three sample-hold circuits and the analog multiplexer 13 is longer than the length of the wire between the analog multiplexer 13 and the post-stage circuit. I am configuring.

The reset switches 11 and 12 are controlled to be turned on or off by the control signals φ0, φ1 and φ2. The three interleaved sample and hold circuit block 10 arranged for each ultrasonic transducer is arranged in the array. Regarding the reset switches 11 and 12 for resetting the charge history, the reset switch 11 needs to be arranged in the array in order to reset the charge of Cs, and the reset switch 12 is not particularly limited, but the wiring parasitic capacitance Cp A switch that resets the charge and is preferably located outside the array. Also, VCM is the common potential of the signal.

Since the analog adder circuit redistributes the charges CsVin0, CsVin1,..., CsVin(N-1) accumulated in Cs by N Cs, there is no influence of the wiring parasitic capacitance Cp and Cp=0F. In that case, since the output Vout of (Equation 1) is obtained, it is a circuit that averages N inputs rather than adding them, but if it is considered that they are added and attenuated to 1/N. Since it is good, it is called an adder circuit for convenience.

FIG. 2 shows a timing chart for understanding the principle of the addition operation in this embodiment. Vin is a voltage input signal when Vin0, Vin1,..., Vin(N-1) in FIG. 1 are assumed to have the same waveform. The Vin signals of the same N systems are averaged, and ideally, a signal obtained by sampling Vin in a discrete time is output as Vout.

φ0, φ1, and φ2 are switch control signals, and are generated as three-phase pulse signals in synchronization with the clock CLK as illustrated. The three-phase signal corresponds to the sample, hold, and reset operations of the sample-hold circuit block 10 for three interleaves in FIG.

For example, as shown in the second clock cycle (I) from the left in FIG. 2, in the phase in which φ0 is at the Hi level and the capacitance node Vcs0 in FIG. 1 tracks the input Vin, Vcs1 changes the charge of Cs. In the resetting phase, Vcs2 is in the phase of outputting Vin held in Cs to Vout2.

In the next clock cycle (II), as shown in FIG. 2, only φ1 is at the Hi level, so Vcs0 is the hold phase, Vcs1 is the sample phase, and Vcs2 is the reset phase. In this way, the operation of three interleaves is repeated, and only the held state is alternately output to the long wirings Vout0, Vout1, and Vout2 of FIG. 1 by three interleaves. The analog multiplexer 13 of FIG. 1 multiplexes three of Vout0, Vout1, and Vout2 and outputs the addition result to Vout.

VCM in FIG. 1 is a signal common level and is a reset destination of Cs signal charges. In the reset phase, the VCM voltage (common voltage) is forcibly applied to Cs. By resetting to the common level of the signal in this way, the phase of the input signal sampling, that is, the initial potential of Cs when sampling the input signal is always the VCM centered on the signal amplitude. Since the settling at the time of sampling is started from 0 V or starting from the signal amplitude center instead of starting from the power supply voltage Vdd, the settling can be speeded up, and thus the reset destination is set to the common potential VCM. desirable.

With the above three interleave operations of sample, hold, and reset, the reset switch 11 in FIG. 1 that resets the capacitor Cs that stores signal charges, and the reset switch 12 that resets the wiring parasitic capacitance Cp, charge history of both Cs and Cp The charge addition operation with resetting can be realized passively, and a wideband discrete-time analog addition circuit can be realized.

In the waveforms of Vcs0, Vcs1, and Vcs2 in FIG. 2, after the input signal is tracked in the sample phase, the holding voltage is slightly shifted in the hold phase. This indicates that voltage variation occurs due to charge sharing between N×Cs and Cp. As will be described later, since the history of Cs and Cp is always reset before the sample phase, charge sharing is always performed with a fixed known Cp charge and N×Cs, which is not a problem. The problem is that Cp charges depending on the signal remain in the previous cycle.

FIG. 3 shows an example of the physical layout of the analog adder circuit of this embodiment. Such a circuit can be configured as, for example, a one-chip integrated circuit arranged in the ultrasonic probe. In this case, RxOUT0 to RxOUT3 form the output terminal of the IC. In the layout of FIG. 3, one-channel transmission/reception circuits 30 arranged for each ultrasonic transducer are arranged in an array. Further, it is assumed that the received signals of 4×4=16 channels are added and bundled into one. Here, it is assumed that the transmission/reception circuits for 16 channels belong to one sub-array 300 and four sub-arrays are arranged to form the array 310, but the number can be increased or decreased. The transmission/reception circuit 30 is connected to the ultrasonic transducer via bumps of the IC, respectively. Note that, for convenience, in this specification, a circuit in which output signals are bundled by addition and physically arranged in the array (excluding the ultrasonic transducer and the multiplexer 13) is referred to as a sub-array 300.

One of the transceiver circuits 30 is extracted and shown in the upper part of FIG. A sample and hold circuit block 10 is arranged in the 1-channel transmission/reception circuit 30, and this corresponds to the sample and hold circuit block 10 in FIG. Three output wirings from the sample hold circuit block 10 are short-circuited by 16 channels which is an addition unit, and wired to the outside of the array 310. As described above with reference to Cp in FIG. 1, a large parasitic capacitance is attached due to the long wiring on the array 310.

Each analog multiplexer 13 receives three output lines from one sub array 300 as an input. This corresponds to the analog multiplexer 13 of FIG. Although not shown, it is desirable that the reset switch 12 for resetting the wiring parasitic capacitance in FIG. 1 is arranged near the analog multiplexer 13. A cable buffer circuit 33 for buffering the IC output and driving a cable connecting the ultrasonic probe and the main body device is provided at the subsequent stage of the analog multiplexer 13.

Since the analog multiplexer 13 and the cable buffer circuit 33 can be placed close to each other outside the array 310, the parasitic capacitance at the output of the analog multiplexer 13 does not pose a big problem. If the analog multiplexer 13 is arranged in the array, the parasitic capacitance attached to the output of the analog multiplexer 13 becomes large, and the band of the adder circuit deteriorates. In this embodiment, the charge history of the capacitor for accumulating the signal charge and the parasitic capacitance of the wiring is reset by the 3-interleave operation, and the three output wirings with the reset charge history are analog-multiplexed into one output. Therefore, in order to bring out the effect of the present embodiment, it is desirable to wire three wires to the outside of the array 310 and multiplex outside the array as shown in FIG.

Further, regardless of the position of the sub-array 300, which is the unit of addition for bundling the channels of each transducer, the fact that the wiring parasitic capacitance from the sub-array 300 to the analog multiplexer 13 is an equal load means that the characteristics of each adder circuit are the same and the inter-sub-array This is desirable in view of the purpose of reducing the characteristic variation. As shown in FIG. 3, the three wirings which are the outputs of the sample hold circuit block 10 are arranged so that the wiring length from the sub-array 300 to the analog multiplexer 13 is equal in both the sub-array outside the array 310 and the sub-array inside the array 310. Can be made equal in length by wiring from the lower end of the array 310 to the opposite upper end (not shown).

In order to explain the effect of the charge history reset on the adder circuit band in the present embodiment, FIG. 4 shows a discrete time sampling analog adder circuit when the charge history is not reset, and FIG. 6 shows a transfer function corresponding to the circuit of FIG. 4, FIG. 7 shows a timing chart at the time of step input of FIG. 1 of this embodiment, and FIG. 8 shows a transfer function of FIG. 1 of this embodiment. Indicates a function.

In the comparative example of FIG. 4, the circuit 40 is an addition circuit in the transmission/reception circuit arranged for each transducer. This is a two-interleave operation of sample and hold, and in the phase in which the input signal is sampled in one capacitor Cs, the signal accumulated by the charge in the other Cs is output, and this output is short-circuited in each channel. Therefore, it is possible to realize addition, more accurately, averaging operation by redistributing charges. It is assumed that the output wiring of the circuit 40 is long because it is wired to the outside of the array and the wiring parasitic capacitance Cp is large.

FIG. 5 is a timing chart showing the operation when the same step input is applied to each input in the circuit of FIG. With φ0 and φ1, a 2-interleave operation of sampling the input signal and outputting the voltage held in the capacitor Cs is performed. At the nodes Vcs0 and Vcs1 of the capacitor Cs, for example, paying attention to Vcs0, the Vc potential follows the fluctuation Vs of the step input and settles in the clock cycle (I) which is the sample phase. However, in the clock cycle (II) of the hold phase for outputting the voltage held at Cs, the charge is shared by N×Cs and Cp, and the Vcs voltage changes. In the clock cycle (III) of the next sample phase, Vcs follows Vs, but in the next hold phase (IV), the charge accumulated in Cp in the previous hold phase and Cs corresponding to Vs are accumulated. Vs fluctuates to a potential determined by the charge share of the charged Cs·Vs. In this way, the charge in the previous hold phase is accumulated in the wiring parasitic capacitance Cp, and the potential determined by the charge share of N×Cs and Cp is always affected by the Cp charge history.

In the cycle of the first step output after the step input, since there is no electric charge remaining in Cp, the following (Equation 2) is obtained.

However, after that, the operation is such that the charge is repeatedly shared by N×Cs and Cp, and gradually approaches Vs as shown in the Vout waveform of FIG. That is, under the influence of the charge history of Cp, the output does not become an ideal step output when a step input is applied, but becomes a dull waveform that gradually approaches Vs. As the frequency response, the band as the analog adder circuit seems to be deteriorated by the Cp charge history, and the band is determined by the relationship between N×Cs and Cp.

FIG. 6 shows the transfer function of the circuit of FIG. Since there is a feedback path due to the charge history, the transfer function is affected by Cp.

FIG. 7 shows an operation timing chart when a step input is applied to the circuit of FIG. 1 of the present embodiment to which the reset operation is added. Vcs0, Vcs1, and Vcs2 are nodes of the signal charge storage capacitor Cs in FIG. After tracking to the maximum potential Vs of the step input in the sample phase (for example, Vcs0 of clock cycle (I)), the charge is shared by N×Cs and Cp and the potential decreases (for example, Vcs0 of clock cycle (II). ). However, Cs and Cp are always reset before performing the sample hold (for example, Vcs0 of clock cycle (III)), and the initial state of Cp charge is determined. Therefore, after the charge is shared by N×Cs and Cp, The potential is always the potential represented by (Equation 2).

As a result, without any influence of the charge history of Cp, an output that constantly stabilizes every cycle from the common potential VCM to the potential represented by (Equation 2) with respect to the step input as shown by the waveform Vout at the bottom of FIG. Instead of a blunt waveform gradually approaching Vs as shown in FIG. 5, it is possible to output a step output although it attenuates at a fixed attenuation rate as expressed by (Equation 2).

FIG. 8 shows the transfer function of the circuit of FIG. 1 which is the configuration of this embodiment. By resetting the charge history of Cs and Cp, the feedback path in FIG. 6 disappears, and the transfer function expressed by the following (Equation 3) is obtained. It has a fixed decay rate of (Equation 3) under the influence of the charge share of N×Cs and Cp.

FIG. 9 shows frequency characteristics of the circuit of FIG. 1 of this embodiment and the circuit of FIG. 4 in which the reset operation is not performed. When not reset, Vout follows Vs as shown in the timing chart of FIG. 5, and a DC gain of 0 dB can be realized. However, the band deteriorates under the influence of the charge history of Cp as seen in the rounding of the response to the step input. On the other hand, when the reset operation is performed, Vout does not rise above the potential represented by (Equation 2) as shown in the timing chart of FIG. 7, so the DC gain, that is, the attenuation rate is (Equation 3). However, since the step output response to the step input is obtained, the band is improved as compared with the case where it is not reset, and the actual band is not the charge history of Cp but the on resistance and the capacitor of the switch which are the constituent elements of the circuit. It is rate-controlled by a fixed time constant.

It should be noted that the actual numerical values of the capacitors and the like in (Equation 1) to (Equation 3) can be variously applied and are not limited depending on the design and use of the device.

FIG. 10 shows an embodiment different from FIG. 1 to which this embodiment is applied. Although FIG. 1 shows a single-ended input and single-ended output analog adder circuit, the embodiment of FIG. 10 has a differential input and single-ended output configuration.

In the ultrasonic diagnostic apparatus, tissue harmonic imaging (THI) is used in which imaging is performed using the second harmonic of a signal by utilizing the nonlinearity in the in-vivo propagation of ultrasonic waves. In order to detect the second harmonic of the signal, it is necessary to reduce the second harmonic due to the non-linearity of the receiving circuit, and it is widely known that the circuit differential is effective in suppressing the second harmonic. There is.

In the configuration of FIG. 10, the voltage between the differential analog signal voltage inputs Vinp and Vinn is held in the capacitor Cs. This is output to Vout0, Vout1, and Vout2 using the VCM potential as a common potential, and the multiplexer 103 performs multiplexing. With this configuration, a differential output circuit can be connected in front of the analog addition circuit. Since the differential circuit is highly effective in suppressing the second harmonic as described above, it is possible to realize a receiving circuit suitable for THI and improve image quality as an ultrasonic diagnostic apparatus.

FIG. 11 shows an ultrasonic probe having a two-dimensional array transducer for three-dimensional imaging and a system configuration to which the adding circuit of the above-described embodiment is applied. A transmission/reception circuit 30 is arranged for each transducer 111 in an ultrasonic probe 110 (a so-called probe that can be operated, for example, by holding it in a hand and applying it to a measurement site). Is sent to the AFE (analog front end) 115 in the main body device 114 via the analog multiplexer 13. The grouping unit of transducer channels to be added constitutes the sub-array 300.

An example of the device configuration will be described while supplementing the relationship with the analog adder circuits of FIGS. 1 and 3 already described. The transmission/reception circuit 30 includes the sample hold circuit block 10 shown in FIGS. 1 and 3, respectively. As shown in FIG. 3, the transmission/reception circuit 30 has an array-like arrangement and is arranged in the IC. The three wires 1100 connect the sample hold circuit block 10 and the analog multiplexer 13 in the IC 1101. The reset switches 11 and 12 shown in FIG. 1 are also arranged on the three wires. With this configuration, the electric charge of the output signal of the transmission/reception circuit 30 is redistributed by short-circuiting the three wires, and the operation is averaged. Of the three added outputs, the multiplexer 13 is inserted in order to conceal the period other than the voltage hold, and one multiplexer holding the voltage is taken out by the multiplexer.

The processor 117 in the main body device sends a control signal to the IC control logic circuit 118 that controls the IC 1101 in the ultrasonic probe, and the IC control logic circuit 118 responds to this by switching transmission/reception or delaying for ultrasonic focusing. Take control. Although not particularly limited, when the transmission circuit is the pulser type instead of the linear amplifier type, the waveform is sent to the pulser as a digital value, so the IC control logic circuit 118 includes a waveform memory that stores the waveform data transmitted by the pulser. ..

FIG. 12 shows the configuration of the transmission/reception circuit 30 in the sub array 300. The transmitter/receiver circuit 30 per oscillator is composed of a high voltage MOS, a transmitter circuit 122 that generates a high voltage signal and drives the oscillator 111, and is turned off during transmission to protect the low voltage system reception circuit from the high voltage signal and receive it. A transmission/reception separation switch 123 that sometimes allows a minute signal to pass, a low-voltage receiving low noise amplifier (Low Noise Amplifier: LNA) 124, a transmission signal that is delayed to perform beamforming, and a reception signal that is delayed to perform phasing A delay circuit 125 is included. The sample hold circuit block 10 is connected to the minute delay circuit 125. The received signal that has been phased in each minute delay circuit is multiplexed by the analog multiplexer 13 and transmitted to the main device.

The embodiment described above can provide an analog adder circuit with low power consumption and wide bandwidth. In particular, in an IC for a 2D array ultrasonic probe, a wide band addition process can be realized even when a long wiring is wired from the receiving circuit on the array to the outside of the array to increase the parasitic capacitance.

Further, in an analog adder circuit that adds an analog signal by charge using a sample hold circuit, periodically reset both the charge of the capacitor that stores the signal charge and the load capacitance that is connected to the output of the sample hold circuit. Can eliminate the influence of charge history.

The embodiment described above is effective when mounted on the IC in the ultrasonic probe connected to the ultrasonic diagnostic apparatus. By using this embodiment, it is possible to realize a wide band of the analog adder circuit required for phasing of ultrasonic wave reception with low power consumption. As a result, a receiving circuit that handles ultrasonic waves of high frequency can be realized, and an ultrasonic image diagnostic apparatus with high spatial resolution can be realized. Further, it is possible to reduce the power of the IC in which the analog addition circuit is mounted, and it is possible to suppress the heat generation of the ultrasonic probe in which the IC is mounted. That is, the present embodiment is effective as a technique for realizing a wideband analog adder circuit with low power consumption, and thus realizing a high-performance ultrasonic probe with low heat generation.

N Number of signals to be added Cs Signal voltage holding capacitor Cp Wiring parasitic capacitance Vin* Voltage input Vout* Voltage output Vcs* Capacitor voltage VCM Signal common potential φ* Switch on/off control signal CLK Reference clock ADD Analog addition circuit MUX Analog multiplexer BUF Buffer Vs step input voltage amplitude Z ⁻¹ 1 clock cycle delay AFE analog front end IC Integrated Circuit integrated circuit Tx transmission circuit T/R-SW transmission/reception separation switch Rx reception circuit LNA Low Noise Amplifier low noise amplifier DLY* analog delay circuit SW* switch

Claims (15)

Multiple input terminals,
A plurality of sample and hold circuit blocks corresponding to each of the plurality of input terminals,
The output of the plurality of sample and hold circuit blocks are input, and a multiplexer that generates one output is provided,
Each of the plurality of sample and hold circuit blocks includes a first capacitor, a second capacitor, and a third capacitor,
A first wiring connecting the first capacitor and the multiplexer, a second wiring connecting the second capacitor and the multiplexer, and a third wiring connecting the third capacitor and the multiplexer ,,
For each of the first capacity, the second capacity, and the third capacity,
A first state of connecting to the input terminal and disconnecting from the multiplexer;
A second state of connecting with the multiplexer and disconnecting with the input terminal;
A third state of connecting to a predetermined potential and disconnecting from the input terminal and the multiplexer,
Equipped with a switch to exclusively set the three states of
A first reset switch arranged between the first capacitor and the multiplexer, for connecting the first wiring to the predetermined potential in the third state;
A second reset switch arranged between the second capacitor and the multiplexer for connecting the second wiring to the predetermined potential in the third state;
A third reset switch arranged between the third capacitor and the multiplexer for connecting the third wiring to the predetermined potential in the third state;
Analog adder circuit. The first reset switch resets the electric charge of the parasitic capacitance of the first wiring,
The second reset switch resets the electric charge of the parasitic capacitance of the second wiring,
The third reset switch resets the electric charge of the parasitic capacitance of the third wiring,
The analog adder circuit according to claim 1. The plurality of sample hold circuit blocks are arranged in an array in a semiconductor integrated circuit device to form an array region,
The first reset switch, the second reset switch, and the third reset switch are arranged outside the array region,
The analog adder circuit according to claim 1. The switch for exclusively setting the three states is
A first connection switch disposed on the first wiring between the first capacitance and the first reset switch;
A second connection switch arranged on the second wiring between the second capacitor and the second reset switch;
A third connection switch disposed between the third capacitance and the third reset switch on the third wiring;
The analog adder circuit according to claim 3. A plurality of input terminals, each connected to an ultrasonic transducer,
A plurality of receiving circuits corresponding to the plurality of input terminals one-to-one,
A signal capacitor that stores electric charge based on a signal obtained from the input terminal, which is provided in each of the plurality of receiving circuits,
An output wiring that integrates the outputs of the signal capacitors of the plurality of receiving circuits,
By redistributing the charge stored in the signal capacitors of the plurality of receiving circuits by the signal capacitors of the plurality of receiving circuits, the signals obtained from the plurality of input terminals are integrated,
An ultrasonic probe characterized by resetting charge/discharge history of charges of the signal capacitor and the parasitic capacitor by periodically setting charges of the signal capacitor and the parasitic capacitor of the output wiring to a predetermined value. .. In claim 5,
When periodically setting the charge of the signal capacitor and the parasitic capacitor to a predetermined value,
An ultrasonic probe, characterized in that the voltage applied to the signal capacitor and the parasitic capacitor is set in the vicinity of a common voltage of an analog signal. In claim 5,
A discrete time sampling system that operates in synchronization with a clock is provided for the signal capacitor,
An ultrasonic probe characterized in that, in synchronization with the clock, three interleave operations of signal sampling, signal holding, and resetting of charge and discharge history of charges of the signal capacitor and the parasitic capacitor are alternately performed. In claim 7,
And three sample and hold circuits that alternately perform the three interleave operations,
Each of the three sample and hold circuits comprises the signal capacitor,
An ultrasonic probe characterized in that outputs of the three sample-hold circuits are alternately output by an analog multiplexer. In claim 8,
In the connection of the three sample and hold circuits, the analog multiplexer, and the subsequent circuit of the analog multiplexer,
An ultrasonic probe, wherein lengths of three wires between the three sample-hold circuits and the analog multiplexer are longer than lengths of wires between the analog multiplexer and the subsequent circuit. In claim 8,
Sample and hold circuit blocks that are a set of the three sample and hold circuits are arranged in an array,
An ultrasonic probe, wherein the wiring length from the sample hold circuit block to the analog multiplexer arranged outside the array is equal regardless of the position of the sample hold circuit block. In claim 5,
Each of the input terminals is a pair of differential input terminals,
The ultrasonic probe, wherein the differential input terminal is connected to two electrodes of the signal capacitor via a switch to hold a differential signal in the signal capacitor. An ultrasonic diagnostic apparatus comprising an ultrasonic probe and a main unit,
The ultrasonic probe is
A plurality of ultrasonic transducers,
A plurality of sample and hold circuit blocks corresponding to each of the ultrasonic transducers;
A multiplexer having as inputs the outputs of the plurality of sample and hold circuit blocks;
An output wiring connecting the sample-hold circuit block and the multiplexer,
Equipped with
The output of the multiplexer is input to the main body device via a post-stage circuit,
Each of the sample and hold circuit blocks includes a signal capacitor that stores a charge based on a detection signal of the ultrasonic transducer,
A reset switch for periodically connecting the output wiring to a predetermined potential,
An ultrasonic diagnostic apparatus characterized by the above. The sample and hold circuit blocks are arranged in an array,
The multiplexer is located outside the array of arrays,
The reset switch is a parasitic capacitor reset switch that is arranged outside the array-shaped array and connects the output wiring to the predetermined potential,
Further, a signal capacitor reset switch arranged inside the array-shaped array and connecting the signal capacitor to the predetermined potential is provided.
The signal capacitor reset switch and the parasitic capacitor reset switch operate in synchronization.
The ultrasonic diagnostic apparatus according to claim 12. The sample-hold circuit block includes a set of three signal capacitors,
The three signal capacitors are
A first state for sampling the signal from the ultrasonic transducer,
A second state for outputting a signal to the multiplexer,
A third state connected to the predetermined potential,
The following three states are exclusively set sequentially,
The ultrasonic diagnostic apparatus according to claim 13. The sample hold circuit block and the output wiring are formed in a semiconductor integrated circuit,
The ultrasonic diagnostic apparatus according to claim 14.

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