JP6722513B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

A MIM (Metal Insulator Metal) capacitor is known as a capacitor element in a semiconductor device. The MIM capacitor is a capacitor having a laminated structure of metal-insulator-metal. As a method of manufacturing a MIM capacitor according to the related art, for example, the one disclosed in Patent Document 1 is known.

In the method for manufacturing the MIM capacitor disclosed in Patent Document 1, the insulating material is deposited on the lower electrode film at a film forming temperature in the range of 430° C. to 500° C., which is higher than the normal film forming temperature of the capacitive insulating film. Then, a plurality of minute gaps are formed between the upper surface of the lower electrode film and a dielectric film (capacitor film) having an uneven upper surface is formed along with the gaps, and a lower portion is formed on the dielectric film. The same conductive material as the electrode film is deposited to form the upper electrode film.

In Patent Document 1, according to the MIM capacitor of the manufacturing method as described above, since the upper surface of the dielectric film is formed in a concavo-convex shape, a dielectric material having a substantially larger surface area than a flat dielectric film is formed. Since the film can be formed, the capacitance can be increased as compared with the conventional MIM capacitor of the same size.

JP, 2010-205763, A

By the way, modern semiconductor devices are becoming more and more miniaturized, and miniaturization is also required for individual circuit elements integrated in the semiconductor device. The MIM capacitor is no exception, and there is an urgent need to significantly reduce the element area, but it does not make sense that the capacitance of the MIM capacitor is reduced by downsizing.

In the MIM capacitor, in order to reduce the element area without reducing the capacitance, it is necessary to increase the capacitance per unit area. As a method of increasing the capacitance per unit area, for example, the film thickness of the insulating film may be reduced. However, if the thickness of the insulating film is reduced, a new problem arises that the breakdown voltage decreases.

In that respect, the MIM capacitor according to Patent Document 1 is devised so that the capacitance per unit area increases. However, in the MIM capacitor according to Patent Document 1, the distance between the lower electrode film and the upper electrode film becomes longer and the capacitance becomes smaller at the portion where the gap is provided between the lower electrode film and the dielectric film. There is a problem that it will end up. Further, since the dielectric film and the gap region have different permittivities, there is a problem in that the capacitance easily varies.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device that can be downsized while suppressing a decrease in capacitance.

According to a method of manufacturing a semiconductor device of the present invention, after forming a first insulating film on a substrate, a plurality of openings are provided in the first insulating film, and the first insulating film is filled with the plurality of openings. Forming a metal layer on the film, and etching the metal layer to remove the metal layer on the first insulating film and form a recess in the upper surface of the metal layer filling each of the plurality of openings. And a step of forming a lower layer electrode having a concave portion at a position corresponding to the concave portion on the upper surface of the metal layer, a second insulating film, and an upper electrode on the first insulating film in this order to form an MIM capacitor. And a process.

On the other hand, a semiconductor device according to the present invention is provided with a wiring formed on a substrate, a first insulating film formed on the substrate and covering the wiring, and provided on the first insulating film on the wiring. A plurality of openings that are filled with a metal and have a recess on the upper surface of the metal, and are formed in this order on the first insulating film, and correspond to the plurality of openings, respectively. And a MIM capacitor including a lower layer electrode having a recess at a position, a second insulating film, and an upper layer electrode.

According to the present invention, it is possible to provide a semiconductor device manufacturing method and a semiconductor device that can be downsized while suppressing a decrease in capacitance.

It is a longitudinal cross-sectional view showing an example of a schematic configuration of a semiconductor device according to an embodiment. FIG. 6 is a plan view showing an example of a via plug array of the semiconductor device according to the exemplary embodiment. FIG. 6 is a part of a vertical cross-sectional view showing an example of a manufacturing process of the semiconductor device according to the embodiment. FIG. 6 is a part of a vertical cross-sectional view showing an example of a manufacturing process of the semiconductor device according to the embodiment. FIG. 6 is a part of a vertical cross-sectional view showing an example of a manufacturing process of the semiconductor device according to the embodiment. It is a longitudinal cross-sectional view showing a configuration of a semiconductor device according to a comparative example.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

1 to 5, a method for manufacturing a semiconductor device including a MIM capacitor and a semiconductor device according to the present embodiment will be described. Before that, for understanding the semiconductor device according to the present embodiment. A semiconductor device 20 according to a comparative example including the MIM capacitor CAP according to the comparative example will be described with reference to FIG.

As shown in FIG. 6, the semiconductor device 20 includes a lower layer electrode 200, an insulating film 202, an upper layer electrode 204, via plugs 208 and 209, wirings 210 and 212, and an insulating film 206.

The MIM capacitor CAP according to the comparative example is formed by using the lower electrode 200 and the upper electrode 204 as both electrodes (electrode pair) and the insulating film 202 as a capacitor film. The lower-layer electrode 200 is, for example, a multilayer metal film formed by sandwiching an Al (aluminum)-based alloy film between refractory metals such as Ti (titanium) and TiN (titanium nitride) or laminated films thereof. From Ti/TiN/Al/TiN. The insulating film 202 is, for example, a SiON film (silicon oxynitride film), and the upper electrode 204 is, for example, a TiN film.

The upper layer electrode 204 is connected to the wiring 210 by a via plug 208 provided in the insulating film 206, and the lower layer electrode 200 is connected to the wiring 212 by a via plug 209 provided in the insulating film 206. The MIM capacitor CAP is connected to other circuit elements and the like of the semiconductor device 20 by the wirings 210 and 212.

In the MIM capacitor CAP according to the comparative example configured as described above, since the insulating film 202 as a capacitor film is formed flat, the capacitance of the MIM capacitor CAP is the size of the insulating film 202 in plan view. Determined by

Next, the semiconductor device 10 including the MIM capacitor C according to the present embodiment will be described with reference to FIGS. 1 to 5. 1 is a schematic configuration of a semiconductor device 10 including an MIM capacitor C according to the present embodiment, FIG. 2 is a via plug array in the semiconductor device 10, and FIGS. 3 to 5 are semiconductors according to the present embodiment. 1 schematically shows the main steps in the method for manufacturing the device 10.

In the semiconductor device 10 according to the present embodiment, other elements such as an active element such as a transistor and a passive element such as a resistor may be formed together with the MIM capacitor. Illustration is omitted and only the peripheral portion of the MIM capacitor is shown. Further, in this embodiment, a certain layer is formed “on another layer” or “on a substrate” not only when a certain layer is directly formed on another layer or a substrate, but also Including the case of being formed through three layers.

As shown in FIG. 1, the semiconductor device 10 includes a lower layer wiring 100, a via plug array 150, an insulating film 102, an MIM capacitor C, via plugs 118 and 119, an interlayer film 116, an insulating film 124, and upper layer wirings 120 and 122. It is configured. The semiconductor device 10 according to the present embodiment includes a substrate and a circuit element (active element such as transistor, passive element such as resistor) layer formed on the substrate, and the lower wiring 100 includes the circuit element layer. Although formed above, the substrate and the circuit element layer are not shown in FIG. 1.

The lower layer wiring 100 is a part of a wiring layer that connects each circuit element in the semiconductor device 10. In the present embodiment, the via plug array 150 is formed on the lower layer wiring 100. The lower wiring 100 and the periphery of the via plug array 150 are covered with an insulating film 102.

The via plug array 150 is a site where the via plugs 104 in which the openings (via holes) provided in the insulating film 102 are filled with metal are arranged in an array. Each via plug 104 that constitutes the via plug array 150 has a recess B1 in the upper part thereof. The position of the recess B1 corresponds to the recess B2 of the insulating film 112 of the MIM capacitor C. As described later, the recess B1 of the via plug 104 is provided to form the recess B2 in the insulating film 112 in the manufacturing process of the semiconductor device 10.

The MIM capacitor C according to the present embodiment includes a lower layer electrode 110, which is an electrode pair of the MIM capacitor C, an upper layer electrode 114, and an insulating film 112 as a capacitor film, and is arranged above the via plug array 150. ing. The upper portion of the MIM capacitor C is covered with the interlayer film 116.

As described above, the insulating film 112 of the MIM capacitor C is provided with the recess B2, and this recess allows the surface area of the insulating film 112 to be larger than that of the MIM capacitor CAP according to the comparative example having the same element area. Has been expanded. As a result, the MIM capacitor C according to the present embodiment can increase the capacitance as compared with the MIM capacitor CAP according to the comparative example.

The upper layer wirings 120 and 122 are part of a wiring layer that connects the respective circuit elements in the semiconductor device 10, and the MIM capacitor C is connected to other circuit elements of the semiconductor device 10 via the upper layer wirings 120 and 122. ing. That is, the upper layer wiring 120 is connected to the upper layer electrode 114 which is one electrode of the MIM capacitor C via the via plug 118, and the upper layer wiring 122 has the via plug 119 in the lower layer electrode 110 which is the other electrode of the MIM capacitor C. Connected through. The upper wirings 120 and 122 are covered with an insulating film 124 formed on the interlayer film 116.

Next, with reference to FIG. 2A, the via plug array 150 according to the present embodiment will be described in more detail. FIG. 2A shows a plan view of the via plug array 150 according to this embodiment. As shown in FIG. 2A, the via plug array 150 has a substantially square shape, and a plurality of via plug arrays 150 are arranged in an array at regular intervals (6×7=42 in this embodiment). The via plug 104 is included. The via plug array 150 is formed so as to be located inside the insulating film 112 in a plan view.

As shown in FIG. 1, each of the via plugs 104 has a recess B1 on the upper surface so that the recess B2 is developed in the insulating film 112 and the surface area of the insulating film 112 is enlarged. In the MIM capacitor C according to the present embodiment, by further arranging the via plugs 104 having the concave portions B1 in an array, the insulating film 112 also has concave portions B2 arranged in an array at positions corresponding to the concave portions B1. It is expressed to further increase the capacitance.

Although the present embodiment has been described by exemplifying a mode in which the cross-sectional shape (planar shape) of each via plug 104 of the via plug array 150 is a substantially square shape, the present invention is not limited to this, and a circular shape, an elliptical shape, or the like. It may be in the form of the shape. FIG. 2B shows a form in which the cross-sectional shape of the via plug 104 is a substantially regular hexagonal shape. As described above, by adopting the via plug 104a having a substantially regular hexagonal cross-sectional shape, the via plug array 150a in which the via plugs 104a are densely arranged can be obtained.

Next, a method of manufacturing the semiconductor device 10 including the MIM capacitor C according to the present embodiment will be described with reference to FIGS.

First, a circuit element (active element such as transistor, passive element such as resistor) is formed on a substrate (not shown), an insulating film is formed on the circuit element, and then a via contact for wiring is formed.
Next, after forming a metal film to be a wiring layer on the insulating film, the metal film is processed by photolithography and etching, and the lower wiring 100 connected to the via contact is formed on an insulating film 112 described later. Form at the corresponding position. After that, the insulating film 102 is formed on the lower layer wiring 100.

Next, using photolithography and dry etching, a plurality of vias V1 corresponding to a via plug array 150 described later are formed in the insulating film 102 on the lower layer wiring 100, and then the insulating film 102 including the inside of the via V1. An adhesion layer is formed on the top of the. The adhesion layer is a base layer that enhances the adhesion of a W (tungsten) layer to be formed next. As an example, a Ti film and a TiN film are formed by using a CVD (Chemical Vapor Deposition) method or the like. After that, as shown in FIG. 3A, a metal layer 130 for filling the via V1 is formed by using the CVD method or the like. The metal layer 130 is formed using W, for example.

Next, as shown in FIG. 3B, the entire surface is etched by dry etching (W etch back) to form a plurality of via plugs 104. At this time, the cross section of each of the plurality of via plugs 104 is, for example, a substantially square of 1 μm×1 μm, and the interval between adjacent via plugs 104 is, for example, 1 μm. At the time of the main etching, a recess (a depression) is generated to form a recess B1 in the via plug 104. The recess is generated, for example, by setting the W etch back time longer than usual. Through this step, the via plug array 150 (or the via plug array 150a) is formed on the lower layer wiring 100.

Next, as shown in FIG. 4A, a lower layer electrode 110 made of a multilayer metal film having a laminated film of a refractory metal of Ti and TiN, an Al-based alloy film, and a TiN film is formed by a sputtering method or the like. Form. The film structure of the lower electrode 110 is, for example, Ti/TiN/Al/TiN from the lower layer.

After that, the insulating film 112 is formed by the CVD method or the like. The insulating film 112 is formed using, for example, a SiON film. After that, the upper electrode 114 is formed by the sputtering method or the like. The upper electrode 114 is formed of, for example, a TiN film. The lower layer electrode 110 and the upper layer electrode 114 form an electrode pair of the MIM capacitor C according to the present embodiment, and the insulating film 112 forms a capacitor film of the MIM capacitor C according to the present embodiment.

Here, as shown in FIG. 4A, the presence of the recess B1 in the via plug array 150 also forms recesses in the lower layer electrode 110, the insulating film 112, and the upper layer electrode 114. Since the recess B2 is formed in the insulating film 112, the surface area of the insulating film 112 is larger than the surface area of the insulating film 202 (see FIG. 6) of the MIM capacitor CAP according to the comparative example having the same element area. As a result, the MIM capacitor C according to the present embodiment is configured so that the capacitance can be increased as compared with the MIM capacitor CAP according to the comparative example.

As shown in FIG. 4B, the insulating film 112 and the upper electrode 114 are processed by using photolithography and dry etching to form a desired MIM capacitor C shape.

Next, as shown in FIG. 5A, the interlayer film 116 is formed by the CVD method or the like.

Next, after forming vias V2 corresponding to the via plugs 118 and 119 in the interlayer film 116, a multilayer metal film is formed on the interlayer film 116 while filling the vias V2. Next, the multilayer metal film is processed by using photolithography and etching to form upper layer wirings 120 and 122. Next, as shown in FIG. 5B, the insulating film 124 is formed on the upper layer wirings 120 and 122, and the semiconductor device 10 according to the present embodiment is manufactured.

As described above in detail, according to the MIM capacitor C in the semiconductor device 10 according to the present embodiment, by increasing the surface area without thinning the insulating film, the unit area of the MIM capacitor without lowering the breakdown voltage. The capacity per hit can be increased. For example, if 16 square 1 μm×1 μm square via plugs 104 are arranged in a region corresponding to a 9 μm×9 μm square MIM capacitor C (capacitor film) and the recess depth is 1 μm, the surface area is 1.7. It can be doubled. As a result, the capacity per unit area is also increased about 1.7 times.

In the above embodiment it has been described by way of example a configuration using an SiON film as a capacitor film of the MIM capacitor is not limited to this, other insulating films, for example, SiN film (silicon nitride film) or, Ta ₂ O _{A 5} film (tantalum oxide film) or the like may be used.

Further, in the above-described embodiment, the via plug array in which the via plugs are arranged in an array has been described as an example, but the present invention is not limited to this, and for example, the via plugs are arranged in a checkered pattern or randomly arranged. It may be in the form.

Further, in the above-described embodiment, the form in which the upper layer wirings 120 and 122 are formed above the MIM capacitor C via the via plugs 118 and 119 and connected to other circuit elements of the semiconductor device 10 has been described as an example. It is not limited to this. For example, the lower layer electrode 110 and the upper layer electrode 114 may be extended to form a wiring and connected to another circuit element.

10, 20 Semiconductor device 100 Lower layer wiring 102 Insulating film 104 Via plug 110 Lower layer electrode 112 Insulating film 114 Upper layer electrode 116 Interlayer film 118, 119 Via plug 120, 122 Upper layer wiring 124 Insulating film 130 Metal layer 150, 150a Via plug array 200 Lower layer electrode 202 Insulating film 204 Upper layer electrode 206 Insulating films 208, 209 Via plugs 210, 212 Wirings B1, B2 Recess C, CAP MIM capacitors V1, V2 Vias

Claims (9)

Forming a first insulating film on a substrate, forming a plurality of openings in the first insulating film, and forming a metal layer on the first insulating film while filling the plurality of openings;
Etching the metal layer to remove the metal layer on the first insulating film and form a recess in the top surface of the metal layer filling each of the plurality of openings;
Forming a MIM capacitor by forming a lower layer electrode having a recess at a position corresponding to a recess on the upper surface of the metal layer, a second insulating film, and an upper electrode in this order on the first insulating film;
A method for manufacturing a semiconductor device including: The method of manufacturing a semiconductor device according to claim 1, wherein the plurality of openings are a plurality of openings arranged in an array inside the region of the second insulating film in a plan view. The method of manufacturing a semiconductor device according to claim 1, wherein a cross-sectional shape of the plurality of openings is any one of a rectangle, a circle, and a hexagon. Further including forming a first wiring on the substrate,
In the step of forming the metal layer, the first insulating film is formed on the first wiring, and then the plurality of openings reaching the first wiring are provided in the first insulating film. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a step of forming a metal layer on the first insulating film while filling the opening. Further comprising the step of forming a circuit element layer including a circuit element on the substrate,
The semiconductor device according to claim 4, wherein the step of forming the first wiring on the substrate is a step of forming the first wiring on the circuit element layer as a part of the wiring connecting the circuit elements. Manufacturing method. Etching a part of the second insulating film and a part of the upper layer electrode to expose a part of the lower layer electrode;
A step of forming an interlayer film on the entire surface,
Forming a first via contact connected to the upper layer electrode and a second via contact connected to the exposed lower layer electrode in the interlayer film;
A third insulating film is formed on the interlayer film, a second wiring connected to the first via contact and a third wiring connected to the second via contact on the third insulating film. The method of manufacturing a semiconductor device according to claim 1, further comprising: Wiring formed on the substrate,
A first insulating film formed on the substrate and covering the wiring;
A plurality of openings provided in the first insulating film on the wiring, the inside of which is filled with metal and which has a recess on the upper surface of the metal;
An MIM capacitor which is formed on the first insulating film in this order, and which includes a lower layer electrode having a recess at positions corresponding to the plurality of openings, a second insulating film, and an upper layer electrode,
Including a semiconductor device. The semiconductor device according to claim 7, wherein the plurality of openings are a plurality of openings arranged in an array inside the region of the second insulating film in a plan view. Further comprising a circuit element layer including a circuit element formed on the substrate,
The semiconductor device according to claim 7, wherein the wiring is a part of a wiring formed on the circuit element layer and connecting the circuit elements.

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