JP6715736B2 - Semiconductor device and power converter - Google Patents

Description

The present invention relates to a semiconductor device and a power conversion device.

As a performance required for a power semiconductor device, it is possible that a time that a load short-circuit accident can withstand without being destroyed, that is, a short-circuit withstand capability is sufficiently longer than a time from the occurrence of the accident to the operation of the circuit breaker. In the conventional semiconductor device, in order to satisfy the above performance, the short circuit withstand capability is increased in exchange for the reduction of the element performance such as ON resistance. As a method of increasing the short-circuit withstand capability without deteriorating the element performance of the semiconductor device, for example, as in Patent Document 1, a semiconductor device is provided with a protection circuit including a microcomputer, and when a load short-circuit is detected, the microcomputer outputs a gate voltage There is a method of lowering the current to suppress the current flowing through the semiconductor device.

On the other hand, Patent Documents 2 and 3 show semiconductor devices having a structure in which a diode is arranged between the gate and the source in order to protect the gate from a surge voltage.

Japanese Patent No. 4961646 JP, 2009-218307, A JP 2000-223705 A

When a microcomputer is used to suppress a short-circuit current as in Patent Document 1, it takes time from the occurrence of a short-circuit accident until the microcomputer lowers the gate voltage, and the semiconductor device is destroyed before the gate voltage decreases. there is a possibility. Further, in Patent Documents 2 and 3, since the diode arranged between the gate and the source of the semiconductor device is assumed to be a surge voltage rather than a short circuit accident, it is not sensitive to the temperature rise of the semiconductor device and is a semiconductor during a short circuit. There is no way to prevent device destruction.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of instantaneously reducing the gate voltage when a short-circuit accident occurs.

The semiconductor device according to the present onset bright includes a switching element, and a temperature sensing element connected between the gate electrode and the source electrode or the emitter electrode of the switching element of the switching element, the temperature sensing element, a temperature Is a device whose resistance decreases as the temperature rises. The switching device includes a drift layer of a first conductivity type and a well layer of a second conductivity type formed in a surface layer portion of the drift layer, and the temperature-sensitive element and the well An insulating film is not interposed between the temperature sensing element and the layer, and the temperature sensitive element is arranged between the cells of the switching element in an active cell region in which a plurality of cells of the switching element are formed. Is.

According to the present invention, when a short circuit accident occurs, the gate voltage is instantly lowered and the current flowing through the semiconductor device is suppressed, so that a sufficiently long short circuit withstand capability can be obtained.

It is a circuit diagram of a semiconductor device concerning the present invention. FIG. 3 is a top view of the semiconductor device according to the first and second embodiments of the present invention. FIG. 3 is a sectional view of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a sectional view of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a sectional view of the semiconductor device according to the first embodiment of the present invention. It is a top view which shows the modification of the semiconductor device which concerns on Embodiment 1 and 2 of this invention. FIG. 7 is a cross-sectional view showing a modified example of the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view showing a modified example of the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 6 is a sectional view of a semiconductor device according to a second embodiment of the present invention. It is a top view of the semiconductor device concerning Embodiments 3 and 4 of the present invention. FIG. 7 is a sectional view of a semiconductor device according to a third embodiment of the present invention. FIG. 7 is a sectional view of a semiconductor device according to a third embodiment of the present invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 4 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 4 of this invention. It is a block diagram which shows the structure of the power conversion system which concerns on Embodiment 5 of this invention.

In this specification, the “impurity amount per unit area [cm ⁻² ]” of each region indicates a value calculated by integrating the impurity concentration in each region in the depth direction. When the impurity concentration of each region has a concentration profile, the “impurity concentration [cm ⁻³ ]” of each region indicates the peak value of the impurity concentration in each region, and the “thickness” of each region is , The thickness up to the region where the impurity concentration is 1/10 or more of the peak value of the impurity concentration in the region. However, the value of the “impurity concentration” used when calculating the “dose amount [cm ⁻² ]” in each region is not the peak value of the impurity concentration but the actual impurity concentration.

In addition, in the present specification, the term “upper” does not prevent the presence of inclusions between the constituent elements. For example, the description “B provided on A” includes not only a structure in which B is directly provided on A but also a structure in which another element C is interposed between A and B. ..

In the embodiments described below, the case where the material of the switching element is silicon carbide which is a wide band gap semiconductor is shown. However, the material of the switching element according to the present invention is not limited thereto, and for example, other wide band gap semiconductors such as gallium nitride, aluminum nitride, aluminum gallium nitride, gallium oxide, and diamond can be used, in which case Also, the same effect as in the case of silicon carbide can be obtained.

In the following embodiments, the first conductivity type is N type and the second conductivity type is P type. However, conversely, the first conductivity type may be P type and the second conductivity type may be N type. ..

<Embodiment 1>
FIG. 1 is a circuit diagram showing the configuration of the semiconductor device 10 according to the first embodiment. As shown in FIG. 1, the semiconductor device 10 includes a switching element 1, a temperature sensitive element 2, a gate resistor 3, a gate terminal 4, a source terminal 5, and a drain terminal 6.

Here, as an example of the switching element 1, an N-channel MOSFET formed of silicon carbide is shown. However, the switching element 1 is not limited to the N-channel MOSFET, and may be, for example, a P-channel MOSFET or another switching element such as a JFET or an IGBT. In the case of the IGBT, the “source” of the MOSFET is read as “emitter” and the “drain” is read as “collector”.

The gate terminal 4 is connected to the gate electrode 1G of the switching element 1 via the gate resistor 3. However, the gate resistor 3 may be externally attached to the semiconductor device 10. The source terminal 5 is connected to the source electrode 1S of the switching element 1. The drain terminal 6 is connected to the drain electrode 1D of the switching element 1.

The temperature sensitive element 2 is connected between the gate electrode 1G and the source electrode 1S of the switching element 1 (when the switching element 1 is an IGBT, the temperature sensitive element 2 is connected between the gate electrode and the emitter electrode). ). In the present embodiment, the temperature sensitive element 2 is an element whose breakdown voltage decreases as the temperature rises, and can be constituted by, for example, a Zener diode. The Zener diode is an element in which the voltage of the cathode with respect to the anode does not exceed a specific voltage (this breakdown voltage is referred to as “breakdown voltage”). The breakdown voltage of the Zener diode decreases as the temperature rises.

FIG. 2 is a top view of the active cell in which the switching element 1 of the semiconductor device 10 according to the first embodiment is formed. Further, FIGS. 3, 4, and 5 are cross-sectional views of the active cell, which correspond to the cross-sections along the straight lines A, B, and C shown in FIG. 2, respectively. As shown in these drawings, semiconductor device 10 includes silicon carbide substrate 101, silicon carbide drift layer 102, P well layer 103, N well layer 104, well contact layer 105, gate insulating film 106, and It includes a Zener anode layer 107, a Zener cathode layer 108, a field insulating film 109, a gate electrode 110, an interlayer insulating film 111, a source electrode 112, and a drain electrode 113. Note that, in FIG. 2, the gate insulating film 106, the field insulating film 109, the gate electrode 110, the interlayer insulating film 111, the source electrode 112, and the drain electrode 113 are omitted, and the arrangement of each semiconductor region is shown. ..

Switching element 1 which is an N-channel MOSFET is formed using a substrate in which N-type silicon carbide drift layer 102 is formed on N-type silicon carbide substrate 101. A P well layer 103 is selectively formed in the surface layer portion of silicon carbide drift layer 102.

As shown in FIG. 4, an N well layer 104 and a P-type well contact layer 105 are selectively formed in the surface layer portion of the P well layer 103. Here, the N well layer 104 is arranged so as to surround the well contact layer 105 in a plan view. Gate insulating film 106 is formed on silicon carbide drift layer 102, and gate electrode 110 is formed thereon. Gate electrode 110 is formed so as to extend over each upper surface of N well layer 104, P well layer 103, and silicon carbide drift layer 102 with gate insulating film 106 interposed therebetween. The surface layer portion of the P well layer 103 located below the gate electrode 110 becomes a channel region 114 in which a channel is formed when the switching element 1 is turned on.

The gate electrode 110 corresponds to the gate electrode 1G shown in FIG. 1, and the gate resistor 3 is provided between the gate terminal 4 and the gate electrode 1G. As described above, the gate resistor 3 may be externally connected to the gate electrode 1G. Further, the gate resistance 3 may be incorporated in the gate electrode 110 by extending the path length of the gate electrode 110 or decreasing the conductivity.

The gate electrode 110 is covered with the interlayer insulating film 111, and the source electrode 112 is formed on the interlayer insulating film 111. The source electrode 112 corresponds to the source electrode 1S shown in FIG. 1 and is directly connected to the source terminal 5. A contact hole reaching the P well layer 103 and the N well layer 104 is formed in the interlayer insulating film 111, and the source electrode 112 is connected to the P well layer 103 and the N well layer 104 through the contact hole.

Further, drain electrode 113 is formed on the lower surface of silicon carbide substrate 101. The source electrode 112 corresponds to the drain electrode 1D shown in FIG. 1 and is directly connected to the drain terminal 6.

On the other hand, as shown in FIGS. 3 and 5, a Zener diode including a Zener anode layer 107 and a Zener cathode layer 108 is also formed on the P well layer 103. This Zener diode corresponds to the temperature sensitive element 2 in FIG. No insulating film is interposed between the Zener diode and the P well layer 103. That is, the Zener anode layer 107 is directly formed on the P well layer 103, and the Zener cathode layer 108 is formed on the Zener anode layer 107. The field insulating film 109 is formed so as to cover the Zener diode.

As can be seen from FIG. 5, the Zener anode layer 107 is connected to the source electrode 112 through the P well layer 103 and the well contact layer 105. The Zener cathode layer 108 is connected to the gate electrode 110 through a contact hole formed in the field insulating film 109.

The size and arrangement of each region shown in FIGS. 2 to 5 are merely examples, and can be changed within a range in which the circuit diagram shown in FIG. 1 is realized. For example, in the cross section of FIG. 5, the Zener anode layer 107 is directly bonded to the side surface of the source electrode 112 by retreating the field insulating film 109 in the lateral direction or projecting the Zener anode layer 107 in the lateral direction. You may By doing so, the resistance value between the Zener anode layer 107 and the source electrode 112 can be reduced.

Next, the operation of the semiconductor device 10 according to the first embodiment will be described.

Since the temperature sensitive element 2 is a Zener diode, when the potential of the gate terminal 4 of the semiconductor device 10 is set sufficiently higher than the breakdown voltage of the temperature sensitive element 2, the voltage of the gate electrode 1G with respect to the source electrode 1S becomes It has a value equal to the breakdown voltage of the temperature sensitive element 2. At this time, the voltage of the gate electrode 1G becomes higher than the threshold voltage, and the switching element 1 is turned on. When the potential of the drain terminal 6 is higher than that of the source terminal 5 and the switching element 1 is turned on, a current flows from the drain terminal 6 toward the source terminal 5.

When the load connected to the semiconductor device 10 is short-circuited, a large current flows through the switching element 1 to raise the temperature and the temperature of the temperature sensitive element 2 also rises. As a result, the breakdown voltage of the temperature sensitive element 2 decreases, so that the voltage of the gate electrode 1G decreases and the current flowing through the switching element 1 is suppressed. As a result, the short circuit withstand capability of the semiconductor device 10 is extended.

In the present embodiment, as shown in FIG. 2, the temperature sensitive element 2 (the Zener anode layer 107 and the Zener cathode layer 108) is arranged in the region of the active cell, and further, as shown in FIG. 3 and FIG. The element 2 is in contact with the P well layer 103 without interposing an insulating film. By disposing the temperature sensitive element 2 as described above, the heat conduction between the switching element 1 and the temperature sensitive element 2 becomes high, and the temperature of the temperature sensitive element 2 quickly follows the temperature of the switching element 1. Therefore, when a short circuit occurs and the temperature of the switching element 1 rises, the temperature of the temperature sensitive element 2 also rises quickly, and the gate voltage of the switching element 1 instantly drops.

If the temperature sensitive element 2 is installed outside the active cell region or if an insulating film is present between the temperature sensitive element 2 and the P well layer 103, the temperature sensitive element 2 and the switching element 1 are Since the heat conduction between the two becomes low, the time from the occurrence of the short circuit to the decrease in the voltage of the gate electrode 1G becomes long, and the short circuit resistance cannot be extended as much as the present invention.

Although FIG. 2 shows an example in which one Zener diode is provided for each MOSFET cell, the number of Zener diodes can be reduced. As shown in FIG. 6, if the N well layer 104 and the well contact layer 105 are formed at locations where the Zener diode is thinned out, MOSFET cells are also formed at those locations, so the ON resistance value of the semiconductor device 10 should be lowered. You can If the amount of heat generated at the time of short circuit is uniform in each cell, only one Zener diode may be arranged in the semiconductor device 10. However, the number of zener diodes to be arranged needs to be determined in consideration of the fact that the breakdown voltage of the zener diodes also depends on the current density flowing in the zener diodes.

Subsequently, a method of manufacturing the semiconductor device 10 according to the first embodiment will be described.

First, a substrate including an N-type silicon carbide substrate 101 and an N-type silicon carbide drift layer 102 epitaxially grown on the N-type silicon carbide substrate 101 is prepared. The N type impurity concentration of silicon carbide drift layer 102 is set lower than the N type impurity concentration of silicon carbide substrate 101. N-type impurity concentration and thickness of silicon carbide drift layer 102 are set according to the design breakdown voltage of semiconductor device 10. For example, the N-type impurity concentration of silicon carbide drift layer 102 is about 1.0×10 ¹⁴ cm ^{−3 to} 1.0×10 ¹⁶ cm ⁻³ , and the thickness of silicon carbide drift layer 102 is about 1 μm to 200 μm. be able to.

Next, a P-type P-well layer 103 and an N-type N-well layer are formed on the surface layer portion of the silicon carbide drift layer 102 by selective ion implantation of impurities (dopants) using an implantation mask patterned by photolithography. 104 and a P-type well contact layer 105 are formed respectively. A photoresist or a silicon oxide film can be used for the implantation mask, for example. Then, heat treatment is performed to electrically activate the impurities implanted in silicon carbide drift layer 102.

Next, P-type polysilicon is deposited on the silicon carbide drift layer 102 by a CVD (Chemical Vapor Deposition) method, and patterning is performed by photolithography and etching to form the Zener anode layer 107. The impurity concentration in the Zener anode layer 107 may be determined according to the breakdown voltage of the Zener diode to be realized, and is, for example, about 1.0×10 ¹⁷ cm ^{−3 to} 1.0×10 ²² cm ⁻³ .

Subsequently, the zener cathode layer 108 is formed by ion-implanting impurities into the surface layer portion of the zener anode layer 107 using an implantation mask. When the Zener anode layer 107 is formed by ion implantation, heat treatment is performed to electrically activate the implanted impurities.

Next, a field insulating film 109 made of, for example, a silicon oxide film is formed on the silicon carbide drift layer 102 by a thermal oxidation method or a deposition method. Then, the field insulating film 109 is patterned by photolithography and etching. After that, the gate insulating film 106 is formed by, for example, a thermal oxidation method or a deposition method. Then, the gate insulating film 106 is patterned by photolithography and etching. After that, a gate electrode 110 made of, for example, polysilicon is formed on the gate insulating film 106.

Next, interlayer insulating film 111 is formed on silicon carbide drift layer 102 by a CVD method or the like. Then, by selectively removing the interlayer insulating film 111 and the gate insulating film 106 by, for example, a dry etching method, a contact hole (source contact hole) for connecting the source electrode 112 to the N well layer 104 and the well contact layer 105. ) Is formed.

Subsequently, the source electrode 112 is formed on the interlayer insulating film 111 including the inside of the source contact hole. The source electrode 112 is connected to the N well layer 104 and the well contact layer 105 exposed at the bottom of the source contact hole by ohmic contact.

Further, in the process of forming source electrode 112, a silicide film is formed on the back surface of silicon carbide substrate 101 by the same method. Thereby, drain electrode 113 which makes ohmic contact with the back surface of silicon carbide substrate 101 is formed.

Through the above steps, the active cell of the semiconductor device 10 according to the first embodiment is completed.

In the above description, an example in which the Zener cathode layer 108 is formed on the surface layer portion of the Zener anode layer 107 by the ion implantation method is shown. However, for example, P-type polysilicon and N-type polysilicon are continuously deposited. The zener anode layer 107 and the zener cathode layer 108 may be formed by patterning them by photolithography and etching. In this case, as shown in FIG. 7, the Zener anode layer 107 and the Zener cathode layer 108 have the same shape pattern.

The Zener anode layer 107 and the Zener cathode layer 108 can also be formed of a material other than polysilicon, for example, crystalline silicon, crystalline SiC, polycrystalline SiC, or the like. By changing the materials of the Zener anode layer 107 and the Zener cathode layer 108, the breakdown voltage range that can be set by the Zener diode can be changed. Further, by using a SiC-based material having high heat resistance, high reliability can be obtained even in a high temperature environment.

The gate insulating film 106, the Zener anode layer 107, the Zener cathode layer 108, the field insulating film 109, and the gate electrode 110 may be formed by the following procedure. That is, first, the field insulating film 109 is formed on the silicon carbide drift layer 102 by, for example, a thermal oxidation method or a deposition method, and photolithography processing and patterning by etching are performed. Next, the gate insulating film 106 is formed by, for example, a thermal oxidation method or a deposition method, and the gate insulating film 106 is patterned by photolithography and etching. Subsequently, a Zener anode layer 107 and a Zener cathode layer 108 made of polysilicon are formed, and finally, a gate electrode 110 is formed and patterned.

By thus forming the gate insulating film 106 before the Zener anode layer 107 and the Zener cathode layer 108, the characteristics of the gate insulating film 106 and the characteristics of the interface between the channel region 114 and the gate insulating film 106 can be improved. The improvement treatment (for example, high temperature heat treatment, nitriding treatment, oxidation treatment, etc.) can be performed without considering the influence on the Zener anode layer 107 and the Zener cathode layer 108. In the case of this procedure, as shown in FIG. 8, the Zener anode layer 107 and the Zener cathode layer 108 are not covered with the field insulating film 109.

<Second Embodiment>
In the first embodiment, the Zener anode layer 107 and the Zener cathode layer 108 forming the temperature sensitive element 2 are formed on the P well layer 103. However, in the second embodiment, the Zener anode layer 107 and the Zener anode layer are formed. The cathode layer 108 is embedded in the P well layer 103.

Also in this case, the material of the Zener anode layer 107 and the Zener cathode layer 108 may be polysilicon, but crystalline silicon or polycrystalline SiC can be used instead of polysilicon. Alternatively, the Zener anode layer 107 and the Zener cathode layer 108 may be formed of silicon carbide using the material of the P well layer 103 as it is. When the Zener anode layer 107 and the Zener cathode layer 108 are formed of silicon carbide, the semiconductor device 10 can be operated in a high temperature environment as compared with the case of polysilicon. On the other hand, the use of polysilicon has an advantage that various designs are possible because it can be formed by deposition and is easily processed.

The other components of the semiconductor device 10 are the same as those in the first embodiment, and therefore the description thereof is omitted here.

9 and 10 are top views of active cells of the semiconductor device 10 according to the second embodiment. The top view of the semiconductor device 10 is similar to that of FIG. 2, and FIGS. 9 and 10 correspond to the cross sections along the straight lines A and C shown in FIG. 2, respectively. The cross section along line B is the same as in FIG.

Since the Zener anode layer 107 and the Zener cathode layer 108 are embedded in the P well layer 103, the interface between the Zener anode layer 107 and the Zener cathode layer 108 is short-circuited as compared with the semiconductor device 10 of the first embodiment. It becomes closer to the current path of time. Therefore, the temperature of the temperature sensitive element 2 more quickly follows the temperature change of the switching element 1. As a result, the short circuit breakdown of the switching element 1 can be prevented more reliably.

Subsequently, a method of manufacturing the semiconductor device 10 according to the second embodiment will be described.

First, P well layer 103, N well layer 104 and well contact layer 105 are formed on a substrate formed of silicon carbide substrate 101 and silicon carbide drift layer 102 in the same procedure as in the first embodiment.

Next, the Zener anode layer 107 and the Zener cathode layer 108 are formed in the P well layer 103. When the material of the Zener anode layer 107 and the Zener cathode layer 108 is polysilicon, a trench is formed in the P well layer 103 by etching, and then P-type polysilicon is buried in the trench to form the Zener anode layer 107. Then, the surface layer of the Zener anode layer 107 is ion-implanted using an implantation mask to form the Zener cathode layer 108. Then, heat treatment is performed to electrically activate the implanted impurities.

Alternatively, after forming a trench in the P well layer 103, by sequentially depositing P-type polysilicon and N-type polysilicon so as to fill the trench, and performing patterning by photolithography and etching on them, The Zener anode layer 107 and the Zener cathode layer 108 may be formed.

When the material of the Zener anode layer 107 and the Zener cathode layer 108 is the same as that of the P well layer 103, by performing selective ion implantation using an implantation mask in the upper layer portion of the P well layer 103, The anode layer 107 and the Zener cathode layer 108 may be formed.

After that, the gate insulating film 106, the field insulating film 109, the gate electrode 110, the interlayer insulating film 111, the source electrode 112, and the drain electrode 113 are formed by the same procedure as in the first embodiment. Thereby, the active cell of the semiconductor device 10 according to the second embodiment is completed.

<Third Embodiment>
In the third embodiment, as the temperature sensitive element 2, an element whose resistance value decreases as the temperature rises (that is, an element whose resistance value has a negative temperature coefficient) is used. A semi-insulating element is an example of an element whose resistance value decreases as the temperature rises. The semi-insulating element has a high resistance with few carriers in a certain temperature range (for example, a range of 100° C. or lower), but when the temperature rises, the number of carriers in the element increases and the resistance value decreases. The semi-insulating element has, for example, a resistance value of 1 MΩ or more at room temperature, but can be designed so that the resistance value becomes 10Ω or less at a temperature of 100° C. or more. The resistance at room temperature, the temperature at which the resistance value begins to decrease, and the resistance value after it decreases are controlled by changing the material of the semi-insulating element, the impurity concentration, the type of deep level existing in the band gap of the semi-insulating element, etc. can do.

FIG. 11 is a top view of the active cell of the semiconductor device 10 according to the third embodiment. 12 and 13 are cross-sectional views of the active cell and correspond to the cross-sections along the straight lines A and C shown in FIG. 11, respectively. The cross section along line B is the same as in FIG.

As can be seen from these figures, the configuration of the semiconductor device 10 according to the third embodiment is different from the configuration of the first embodiment in that the zener anode layer 107 and the zener cathode layer 108 are provided in the conductive layer 120 and the semi-insulating layer 121, respectively. It has been replaced with. The semi-insulating layer 121 corresponds to the temperature sensitive element 2 shown in FIG. Polysilicon can be used as the material of the conductive layer 120 and the semi-insulating layer 121. Further, similarly to the Zener anode layer 107 and the Zener cathode layer 108 of the first embodiment, it is possible to form the material other than polysilicon, for example, crystalline silicon, crystalline SiC, polycrystalline SiC or the like.

In the case where the temperature sensitive element 2 shown in FIG. 1 is an element whose resistance decreases as the temperature rises, the voltage of the gate electrode 1G based on the source electrode 1S is determined by the resistance ratio of the gate resistor 3 and the temperature sensitive element 2. It is a value obtained by dividing the voltage of terminal 4. During normal operation of the semiconductor device 10, the resistance value of the temperature sensitive element 2 is very high, so that the potential of the gate electrode 1G becomes substantially equal to the potential of the gate terminal 4. Therefore, by applying a voltage equal to or higher than the threshold voltage to the gate terminal 4, the switching element 1 is turned on.

When the load connected to the semiconductor device 10 is short-circuited, a large current flows through the switching element 1 to raise the temperature and the temperature of the temperature sensitive element 2 also rises. As a result, the resistance value of the temperature sensitive element 2 decreases, so that the voltage of the gate electrode 1G decreases and the current flowing through the switching element 1 is suppressed. As a result, the short circuit withstand capability of the semiconductor device 10 is extended.

Similar to the first embodiment, also in the second embodiment, as shown in FIG. 11, the temperature sensitive element 2 (conductive layer 120 and semi-insulating layer 121) is arranged in the region of the active cell, and further, as shown in FIG. In addition, the temperature sensitive element 2 is in contact with the P well layer 103 without interposing the insulating film. By disposing the temperature sensitive element 2 as described above, the heat conduction between the switching element 1 and the temperature sensitive element 2 becomes high, and the temperature of the temperature sensitive element 2 quickly follows the temperature of the switching element 1. Therefore, when a short circuit occurs and the temperature of the switching element 1 rises, the temperature of the temperature sensitive element 2 also rises quickly, and the gate voltage of the switching element 1 instantly drops.

Subsequently, a method of manufacturing the semiconductor device 10 will be described.

First, P well layer 103, N well layer 104 and well contact layer 105 are formed on a substrate formed of silicon carbide substrate 101 and silicon carbide drift layer 102 in the same procedure as in the first embodiment.

Next, polysilicon is deposited on the silicon carbide drift layer 102 by the CVD method, and patterning is performed by photoengraving and etching to form the conductive layer 120. The impurity concentration of the conductive layer 120 is, for example, about 1.0×10 ¹⁵ cm ^{−3 to} 1.0×10 ²² cm ⁻³ . The semi-insulating layer 121 can be formed on the surface layer portion of the conductive layer 120 by performing electron beam irradiation or ion implantation using an implantation mask. When electron beam irradiation or ion implantation is performed on the conductive layer 120, lattice atoms in the crystal are repelled and a large number of defect levels are formed, whereby part of the conductive layer 120 becomes the semi-insulating layer 121.

Further, the semi-insulating layer 121 is formed by depositing polysilicon as a material of the conductive layer 120, depositing polysilicon having a controlled semi-insulating property, and performing patterning by photolithography and etching on them. Good. When the semi-insulating layer 121 is formed by the deposition method as described above, only the semi-insulating layer 121 can be independently formed, and thus the conductive layer 120 may be omitted.

When the semi-insulating layer 121 is formed by ion implantation, the region for semi-insulating the conductive layer 120 can be shallower than the electron beam irradiation, and the depth can be controlled by the implantation energy and the implanted ion species. In general, the region where semi-insulation becomes shallower when the implantation energy is lower and the implantation ions are heavier. In addition, it is possible to more efficiently form the semi-insulating layer 121 by injecting atoms that form a deep level that traps carriers in the semiconductor, such as vanadium in silicon carbide. The energy level of the deep level varies depending on the implanted ion species, and the resistance value of the semi-insulating layer 121 at room temperature and the temperature at which the resistance value of the semi-insulating layer 121 starts to decrease depending on the position. Just select the ion species for implantation.

The impurity concentration of the semi-insulating layer 121 is, for example, about 1.0×10 ¹ cm ^{−3 to} 1.0×10 ⁸ cm ⁻³ . As the impurity concentration is lowered, the current flowing between the gate and the source of the switching element 1 can be suppressed at room temperature, but it becomes difficult to control the impurity concentration by the deposition method, and the dose amount is increased in the formation by electron beam irradiation or ion implantation. Therefore, it takes time to form the semi-insulating layer 121.

After that, the gate insulating film 106, the field insulating film 109, the gate electrode 110, the interlayer insulating film 111, the source electrode 112, and the drain electrode 113 are formed by the same procedure as in the first embodiment. Thereby, the active cell of the semiconductor device 10 according to the third embodiment is completed.

The order of the step of forming the gate insulating film 106 and the step of forming the conductive layer 120 and the semi-insulating layer 121 is the same as the step of forming the gate insulating film 106 and the formation of the Zener anode layer 107 and the Zener cathode layer 108 in the first embodiment. They can be interchanged in the same order as the steps.

The conductive layer 120 and the semi-insulating layer 121 can also be formed of a material other than polysilicon, for example, crystalline silicon, crystalline SiC, polycrystalline SiC, or the like. Depending on the material of the semi-insulating layer 121, the band gap, the types of defects/impurities that form deep levels, and the energy level of the deep levels are different, which makes the process effective for semi-insulating, at room temperature. Characteristics such as resistance value, temperature at which resistance changes significantly, and resistance value at high temperature also change. Therefore, the material of the semi-insulating layer 121 may be selected in consideration of use and ease of production.

<Embodiment 4>
In the third embodiment, the conductive layer 120 and the semi-insulating layer 121 forming the temperature sensitive element 2 are formed on the P well layer 103, but in the fourth embodiment, the conductive layer 120 and the semi-insulating layer are formed. 121 is embedded in the P well layer 103.

Also in this case, the material of the conductive layer 120 and the semi-insulating layer 121 may be polysilicon, but crystalline silicon or polycrystalline SiC can be used instead of polysilicon. Alternatively, the conductive layer 120 and the semi-insulating layer 121 may be formed of silicon carbide using the material of the P well layer 103 as it is. When the conductive layer 120 and the semi-insulating layer 121 are made of silicon carbide, the semiconductor device 10 can be operated in a high temperature environment as compared with the case of polysilicon. On the other hand, the use of polysilicon has an advantage that various designs are possible because it can be formed by deposition and is easily processed.

The other components of the semiconductor device 10 are the same as those in the third embodiment, and therefore the description thereof is omitted here.

14 and 15 are top views of active cells of the semiconductor device 10 according to the fourth embodiment. The top view of the semiconductor device 10 is similar to that of FIG. 11, and FIGS. 14 and 15 correspond to the cross sections along the lines A and C shown in FIG. 11, respectively. The cross section along line B is the same as in FIG.

By embedding the conductive layer 120 and the semi-insulating layer 121 in the P-well layer 103, the semi-insulating layer 121, which is the temperature sensitive element 2, has a current when short-circuited as compared with the semiconductor device 10 of the third embodiment. Get closer to the route. Therefore, the temperature of the temperature sensitive element 2 more quickly follows the temperature change of the switching element 1. As a result, the short circuit breakdown of the switching element 1 can be prevented more reliably.

Subsequently, a method of manufacturing the semiconductor device 10 according to the fourth embodiment will be described.

First, P well layer 103, N well layer 104 and well contact layer 105 are formed on a substrate formed of silicon carbide substrate 101 and silicon carbide drift layer 102, in the same procedure as in the first embodiment.

Next, the conductive layer 120 and the semi-insulating layer 121 are formed in the P well layer 103. When the material of the conductive layer 120 and the semi-insulating layer 121 is polysilicon, a trench is formed in the P well layer 103 by etching, and then the trench is filled with polysilicon to form the conductive layer 120. Then, electron beam irradiation or ion implantation using an implantation mask is performed on the surface layer portion of the conductive layer 120 to form the semi-insulating layer 121.

Alternatively, after forming a trench in the P well layer 103, polysilicon as the material of the conductive layer 120 and polysilicon controlled to be semi-insulating as the material of the semi-insulating layer 121 are sequentially filled so as to fill the trench. The conductive layer 120 and the semi-insulating layer 121 may be formed by depositing and patterning them by photolithography and etching. In this case, the conductive layer 120 may not be formed.

When the conductive layer 120 and the semi-insulating layer 121 are made of the same silicon carbide as the P well layer 103, selective electron beam irradiation or ion implantation using an implantation mask is performed on the upper layer portion of the P well layer 103. By doing so, the conductive layer 120 and the semi-insulating layer 121 may be formed. Also in this case, the conductive layer 120 may not be formed.

After that, the gate insulating film 106, the field insulating film 109, the gate electrode 110, the interlayer insulating film 111, the source electrode 112, and the drain electrode 113 are formed by the same procedure as in the first embodiment. As a result, the active cell of the semiconductor device 10 according to the fourth embodiment is completed.

<Embodiment 5>
The present embodiment is an application of the semiconductor device according to any of the first to fourth embodiments described above to a power conversion device. Although the present invention is not limited to a specific power converter, a case where the present invention is applied to a three-phase inverter will be described below as a fifth embodiment.

FIG. 16 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

The power conversion system shown in FIG. 16 includes a power supply 200, a power conversion device 300, and a load 400. The power supply 200 is a DC power supply and supplies DC power to the power converter 300. The power source 200 can be configured by various types, for example, a DC system, a solar battery, a storage battery, or a rectifier circuit or an AC/DC converter connected to an AC system. Good. Further, the power supply 200 may be configured by a DC/DC converter that converts DC power output from the DC system into predetermined power.

The power conversion device 300 is a three-phase inverter connected between the power supply 200 and the load 400, converts DC power supplied from the power supply 200 into AC power, and supplies AC power to the load 400. As shown in FIG. 16, the power conversion device 300 includes a main conversion circuit 301 that converts DC power into AC power and outputs the converted power, and a drive circuit 302 that outputs a drive signal that drives each switching element of the main conversion circuit 301. , And a control circuit 303 for outputting a control signal for controlling the drive circuit 302 to the drive circuit 302.

The load 400 is a three-phase electric motor driven by the AC power supplied from the power conversion device 300. The load 400 is not limited to a specific application, and is an electric motor mounted on various electric devices, and is used as, for example, a hybrid car, an electric car, a railway vehicle, an elevator, or an electric motor for an air conditioner.

Hereinafter, the details of the power conversion device 300 will be described. The main conversion circuit 301 includes a switching element and a free wheeling diode (not shown). When the switching element switches, the DC power supplied from the power supply 200 is converted into AC power and supplied to the load 400. Although there are various concrete circuit configurations of the main conversion circuit 301, the main conversion circuit 301 according to the present embodiment is a two-level three-phase full bridge circuit, and includes six switching elements and respective switching elements. It can consist of six freewheeling diodes in anti-parallel. The semiconductor device 10 according to any of the above-described first to fourth embodiments is applied to each switching element of the main conversion circuit 301. The six switching elements are connected in series for every two switching elements to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 301 are connected to the load 400.

The drive circuit 302 generates a drive signal for driving the switching element of the main conversion circuit 301, and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 301. Specifically, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrodes of the respective switching elements according to a control signal from a control circuit 303 described later. When maintaining the switching element in the ON state, the drive signal is a voltage signal (ON signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the OFF state, the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element. It becomes a signal (off signal).

The control circuit 303 controls the switching elements of the main conversion circuit 301 so that desired power is supplied to the load 400. Specifically, the time (ON time) in which each switching element of the main conversion circuit 301 should be in the ON state is calculated based on the power to be supplied to the load 400. For example, the main conversion circuit 301 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Then, at each time point, a control command (control signal) is output to the drive circuit 302 so that an ON signal is output to the switching element that should be in the ON state and an OFF signal is output to the switching element that is to be in the OFF state. The drive circuit 302 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.

In the power converter according to the present embodiment, the semiconductor device according to any one of the first to fourth embodiments is applied as the switching element of the main conversion circuit 301, so that the short-circuit withstand capability of the switching element is improved and a short-circuit accident occurs. Can be prevented from being destroyed.

In the present embodiment, an example in which the present invention is applied to a two-level three-phase inverter has been described, but the present invention is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may also be used. It may be applied. The present invention can also be applied to a DC/DC converter or an AC/DC converter when supplying electric power to a DC load or the like.

Further, the power conversion device to which the present invention is applied is not limited to the case where the above-mentioned load is an electric motor. It can be used as a device, and can also be used as a power conditioner for a solar power generation system, a power storage system, or the like.

It should be noted that, in the present invention, the respective embodiments can be freely combined, or the respective embodiments can be appropriately modified or omitted within the scope of the invention.

DESCRIPTION OF SYMBOLS 1 switching element, 2 temperature sensitive element, 3 gate resistance, 4 gate terminal, 5 source terminal, 6 drain terminal, 1G gate electrode, 1S source electrode, 1D drain electrode, 10 semiconductor device, 101 silicon carbide substrate, 102 silicon carbide drift Layer, 103 P well layer, 104 N well layer, 105 well contact layer, 106 gate insulating film, 107 Zener anode layer, 108 Zener cathode layer, 109 field insulating film, 110 gate electrode, 111 interlayer insulating film, 112 source electrode, 113 drain electrode, 114 channel region, 120 conductive layer, 121 semi-insulating layer, 200 power supply, 300 power conversion device, 301 main conversion circuit, 302 drive circuit, 303 control circuit, 400 load.

Claims (6)

A switching element,
A temperature sensitive element connected between the gate electrode of the switching element and the source electrode or emitter electrode of the switching element;
Equipped with
The temperature sensitive element is an element whose resistance decreases as the temperature increases,
The switching element includes a drift layer of a first conductivity type and a well layer of a second conductivity type formed in a surface layer portion of the drift layer,
An insulating film is not interposed between the temperature sensitive element and the well layer,
The semiconductor device, wherein the temperature sensitive element is arranged between cells of the switching element in an active cell region in which a plurality of cells of the switching element are formed. The temperature sensitive element is a semi-insulating element
The semiconductor device according to claim 1 . The semiconductor device according to claim 1, wherein the temperature sensitive element is embedded in the well layer. The semiconductor device according to any one of claims 1 to 3 , wherein the switching element is made of silicon carbide. The semiconductor device according to claim 1, wherein the temperature sensitive element is made of silicon carbide. A main conversion circuit which has the semiconductor device according to claim 1 and converts input power and outputs the converted power.
A drive circuit for outputting a drive signal for driving the semiconductor device to the semiconductor device;
A control circuit for outputting a control signal for controlling the drive circuit to the drive circuit;
Power conversion device equipped with.

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