JP6715567B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device.

2. Description of the Related Art Conventionally, as a semiconductor device having a MOS gate (insulated gate made of metal-oxide film-semiconductor) structure (hereinafter referred to as a MOS type semiconductor device) used for a power device, a MOS gate is embedded in a trench formed in a semiconductor substrate. Devices having a trench gate structure are known. In this MOS semiconductor device having a trench gate structure, generally, high breakdown voltage and low on-resistance have a trade-off relationship. As a MOS type semiconductor device in which such a trade-off relationship is improved, a MOS type semiconductor device is provided with a floating region of a conductivity type different from that of the drift layer, the floating region being provided so as to surround the bottom (drain side end) of the trench in which the MOS gate is buried. A device has been proposed (for example, refer to Patent Document 1 below).

The structure of a conventional MOS semiconductor device will be described. FIG. 6 is a sectional view showing a structure of a main part of a conventional semiconductor device. FIG. 6 shows a unit cell (functional unit of element) structure arranged in an active region in which a current flows in the ON state. FIG. 6 corresponds to FIG. 1 of Patent Document 1 below. As shown in FIG. 6, the conventional semiconductor device 100 includes a MOS gate structure on the first main surface side of the n ⁻ type drift layer 102 and an n ⁺ type drain layer 101 on the second main surface side. The MOS gate structure includes a p ⁻ type base region 103, an n ⁺ type source region 104, a trench 105, a deposition insulating layer 106, a gate insulating film 107, and a gate electrode 108. The n ⁺ type source region 104 is selectively provided inside the p ⁻ type base region 103.

Trench 105 penetrates n ⁺ type source region 104 and p ⁻ type base region 103 in the depth direction to reach n ⁻ type drift layer 102. The deposited insulating layer 106 is buried on the drain side of the trench 105. The gate electrode 108 is provided on the deposited insulating layer 106 (source side) inside the trench 105. The gate electrode 108 faces the p ⁻ type base region 103 and the n ⁺ type source region 104 with the gate insulating film 107 provided on the sidewall of the trench 105 interposed therebetween. Inside the n ⁻ -type drift layer 102, a p-type diffusion region in the floating state (hereinafter referred to as a p-type buried region) 109 is provided. The bottom of the trench 105 is located inside the p-type buried region 109. Reference numerals 110 and 111 are a source electrode and a drain electrode, respectively.

The conventional semiconductor device 100 has the following characteristics by having a structure in which the p-type buried region 109 in a floating state is provided inside the n ⁻ -type drift layer 102 (hereinafter referred to as a floating structure). A gate voltage is not applied in (or negative gate voltage was applied) OFF state, n ^- inside the type drift layer 102, p ^- the pn junction 121 between the type drift layer 102 ^- -type base region 103 and n A depletion layer (not shown) expands. This depletion p-type buried region 109 is a punch-through state by reaching the p-type buried region 109, p ^- buried p-type a pn junction 121 between the type drift layer 102 ^- -type base region 103 and n The potential up to the region 109 is fixed. Further, n ^- in the interior of the type drift layer 102, p-type buried region 109 and the n ^- depletion layer from the pn junction 122 between the type drift layer 102 (not shown) is increased.

In this way, the depletion layer spreads from the pn junction 121 between the p ⁻ type base region 103 and the n ⁻ type drift layer 102, so that the peak of the electric field intensity becomes near the pn junction 121. Further, the depletion layer spreads from the pn junction 122 between the p-type buried region 109 and the n ⁻ type drift layer 102, so that a peak of the electric field intensity is formed near the pn junction 122. That is, the peak of the electric field intensity can be dispersed in two places. Therefore, the maximum peak value of the electric field strength can be reduced, and the breakdown voltage can be increased. Further, since a high breakdown voltage can be secured, it is possible to increase the impurity concentration of the n ⁻ type drift layer 102 and achieve a low on resistance. Regarding the mechanism of such a floating structure, the calculation result of the electric field intensity distribution is disclosed in detail (for example, refer to Patent Document 2 below).

For example, in a typical MOS semiconductor device used in an inverter circuit or the like, the drain voltage Vd is generally changed by controlling the on/off of the semiconductor device by the gate voltage Vg. FIG. 7 is a characteristic diagram showing a voltage waveform of a conventional semiconductor device. Specifically, as shown in FIG. 7, in the ON state in which a gate voltage Vg equal to or higher than the threshold voltage is applied (hereinafter referred to as the first state A), the depletion layer does not spread in the n ⁻ type drift layer, The drain voltage Vd is low and the device operates in a low on-resistance state. On the other hand, while the off state is maintained without applying the gate voltage Vg (hereinafter, referred to as the second state B), the depletion layer spreads in the n ⁻ type drift layer (high on-resistance state). , The drain voltage Vd is kept high. That is, the breakdown voltage between the drain and the source is maintained by the expansion of the depletion layer. Then, by shifting from the OFF state to the ON state again (hereinafter, referred to as the third state C), the width of the depletion layer that has been widened in the second state is narrowed, so that the state of the low ON resistance is again generated. Works with. Then, the second state B and the third state C are alternately repeated. Thus, in the conventional MOS type semiconductor device (MOS-type semiconductor device not floating structure), when in the second state B, n ^- inside the type drift layer p ^- type base region and the n ^- the type drift layer A depletion layer spreads from the pn junction between them. Then, p when in the second state B ^- type base region and the n ^- width of the depletion layer spread from the pn junction between the type drift layer, p when the third state C ^- n -type base region ^- By supplying holes to the mold drift layer, the width is instantly narrowed.

However, in the conventional floating structure semiconductor device 100 shown in FIG. 6, it is more difficult to return from the high on-resistance state to the low on-resistance state in the third state C, as compared with the normal MOS type semiconductor device. The reason is as follows. In the conventional semiconductor device 100, in the second state B, the pn junction 121 between the p ⁻ type base region 103 and the n ⁻ type drift layer 102, the p type buried region 109, and the n ⁻ type drift layer 102 are formed. A depletion layer spreads from two locations between the pn junction 122 and the pn junction 122. Then, in the third state C, holes are externally supplied to the p ⁻ -type base region 103 connected to the source electrode 110, but the p-type buried region 109 is in a floating state. No holes are supplied to 109 from the outside. Therefore, in the third state C, the supply of holes from the p-type buried region 109 itself is sufficient to reduce the width of the depletion layer spreading to the drain side of the p-type buried region 109. Can not be supplemented in a short time. That is, the amount of holes to be supplied in order to narrow the width of the depletion layer in the third state C is insufficient, and the width of the depletion layer expanded to the drain side of the p-type buried region 109 is narrowed again. Takes time. As a result, as shown by the dotted line in FIG. 7, in the third state C, the drain voltage Vd gradually decreases and reaches the minimum value. Therefore, the state of low on-resistance is not immediately returned, and the transient on-resistance characteristic is adversely affected. In particular, when the chip size is large, the amount of holes to be supplied in order to narrow the width of the depletion layer in the third state C is large. Therefore, the larger the chip size, the more the supply of holes is delayed. In general, the chip size that adversely affects the on-resistance characteristics is about several mm square or more.

Further, as another device of the conventional floating structure, the p ⁻ -type base region is connected to the floating p-type diffusion region (p-type buried region) along the gate insulating film provided on the side wall of the trench. Thus, there has been proposed a device having a p ⁻ -type diffusion region serving as a hole supply path to the p-type diffusion region in the floating state when the p ⁻ -type diffusion region is in the on state (for example, refer to Patent Document 3 below).

The structure shown in Patent Document 3 below will be described. FIG. 8 is a cross-sectional view showing the structure of another example of the conventional semiconductor device. FIG. 8 shows a cross-sectional structure in which the gate electrode 108 embedded in the trench 105 having a linear planar shape is cut parallel to the longitudinal direction of the trench 105. FIG. 8 corresponds to FIG. 4 of Patent Document 3 below. The conventional semiconductor device 200 shown in FIG. 8 is different from the conventional semiconductor device 100 shown in FIG. 6 in that a p ^-- type diffusion region 112 is provided inside the n ^-- type drift layer 102. The p ^-- type diffusion region 112 is provided along the sidewall portion of the trench 105 of the deposited insulating layer 106, and connects the p ^-- type base region 103 and the p-type buried region 109.

The p ^-- type diffusion region 112 has an extremely low impurity concentration and becomes a region having an extremely high resistance due to the depletion layer spreading from the pn junction with the n ^-- type drift layer 102. Therefore, in the off state, the p-type buried region 109 is in the floating state as in the conventional semiconductor device 100 (Patent Documents 1 and 2 below) shown in FIG. Therefore, similarly to the floating structure described above, the breakdown voltage between the drain and the source is maintained, and the breakdown voltage can be increased. On the other hand, in the ON state, the p ^-- type diffusion region 112 fixes the p-type buried region 109 at the source potential, so that holes are supplied from the p-type buried region 109 to the n ^-- type drift layer 102. Therefore, the amount of holes supplied in the ON state can be increased.

In FIG. 8, reference numerals 115 to 119 are a trench, a deposited insulating layer, a gate insulating film, a gate electrode and a p-type buried region of the termination structure portion 202, respectively. The trench 115, the deposited insulating layer 116, the gate insulating film 117, the gate electrode 118, and the p-type buried region 119 of the termination structure 202 are the trench 105, the deposited insulating layer 106, the gate insulating film 107, the gate electrode 108, and the trench 105 of the active region 201. It has the same structure as the p-type buried region 109. The gate electrode 118 is provided in the trench 115 closest to the active region 201, and the deposited insulating layer 116 is embedded in the other trenches 115. The termination structure portion 202 is a region that surrounds the periphery of the active region 201, relaxes the electric field on the first main surface side of the n ⁻ type drift layer 102, and maintains the breakdown voltage.

JP, 2005-142243, A JP, 9-191109, A JP, 2007-242852, A

However, in Patent Documents 1 and 2 described above, although it is possible to reduce the electric field strength near the bottom of the trench 105, there is no description about preventing the extraction of minority carriers (holes) in the ON state. Further, even if the above Patent Documents 1 and 2 are applied to a device using the conductivity modulation effect such as an insulated gate bipolar transistor (IGBT), the conductivity modulation effect is not improved. Further, in the above-mentioned Patent Document 3, when applied to a device using a conductivity modulation effect such as an IGBT, a hole is extracted from the p-type buried region 109 fixed to the source potential in the ON state. Therefore, conductivity modulation is less likely to occur, and there is a problem that the on-resistance characteristic is deteriorated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of improving on-resistance characteristics in order to solve the above-mentioned problems of the related art.

In order to solve the above problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A second conductive type first semiconductor region is provided on the first major surface side of the first conductive type semiconductor layer. A second semiconductor region of the first conductivity type is selectively provided inside the first semiconductor region. The trench penetrates the second semiconductor region and the first semiconductor region and reaches the semiconductor layer. An insulating layer is buried in the bottom of the trench. A gate insulating film is provided inside the trench along the sidewall of the trench. A gate electrode is provided inside the trench, inside the gate insulating film, and on the surface of the insulating layer. A third semiconductor region of the second conductivity type is selectively provided inside the semiconductor layer so as to surround the bottom of the trench. The third semiconductor region faces the gate electrode with the insulating layer interposed therebetween. A fourth semiconductor region is provided on the second main surface side of the semiconductor layer. The first electrode is electrically connected to the first semiconductor region and the second semiconductor region. The second electrode is electrically connected to the fourth semiconductor region. Then, in the off state, a second conductivity type inversion layer is formed along the gate insulating film in a portion of the semiconductor layer sandwiched between the first semiconductor region and the third semiconductor region. The inversion layer electrically connects the first semiconductor region and the third semiconductor region. The third semiconductor region extends to the second semiconductor region side along the trench, is closer to the bottom of the trench than the interface between the insulating layer and the gate electrode, and is the interface of the gate insulating film from the interface. Terminated more than the thickness . The thickness of the gate insulating film is uniform along the sidewall of the trench. The insulating layer is thicker than the gate insulating film.

The semiconductor device according to the present invention is the semiconductor device according to the above-mentioned invention, wherein an impurity concentration higher than that of the semiconductor layer is selectively provided inside the semiconductor layer, apart from the first semiconductor region and the third semiconductor region. And a fifth semiconductor region of the first conductivity type having a high conductivity.

Further, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the fifth semiconductor region is provided between the first semiconductor region and the third semiconductor region of the semiconductor layer. To do.

Further, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the impurity concentration of the semiconductor layer and the thickness of the gate insulating film are set so that the inversion layer is generated in an off state. And

Also, in the semiconductor device according to the present invention, in the above-mentioned invention, the impurity concentration of the semiconductor layer, the thickness of the gate insulating film, and the work function of the gate electrode such that the inversion layer is generated in the off state are obtained. It is characterized by being set.

Further, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the third semiconductor region is in a floating state when it is in an on state.

According to the above-mentioned invention, since the third semiconductor region is in the floating state when in the on state, the extraction of minority carriers (holes) from the third semiconductor region to the first electrode does not occur. Therefore, the conductivity modulation is not hindered in a device using the conductivity modulation effect such as an IGBT. This makes it possible to prevent the on-resistance characteristics from deteriorating.

Further, a semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the fourth semiconductor region of the second conductivity type is provided.

According to the above-described invention, the carrier density inside the semiconductor layer can be increased by providing the fifth semiconductor region inside the semiconductor layer.

The semiconductor device according to the present invention has the effect of improving the on-resistance characteristics.

3 is a sectional view showing the structure of the semiconductor device according to the first exemplary embodiment; FIG. FIG. 7 is a cross-sectional view showing the structure of the semiconductor device according to the second exemplary embodiment. FIG. 9 is a cross-sectional view showing the structure of the semiconductor device according to the third exemplary embodiment. FIG. 9 is a cross-sectional view showing the structure of the semiconductor device according to the fourth exemplary embodiment. FIG. 11 is a cross-sectional view showing the structure of the semiconductor device according to the fifth exemplary embodiment. It is sectional drawing which shows the structure of the principal part of the conventional semiconductor device. It is a characteristic view which shows the voltage waveform of the conventional semiconductor device. It is sectional drawing which shows the structure of another example of the conventional semiconductor device.

Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, in a layer or region prefixed with n or p, it means that electrons or holes are majority carriers. Further, + and − attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

(Embodiment 1)
The structure of the semiconductor device according to the first embodiment will be described. FIG. 1 is a sectional view showing the structure of the semiconductor device according to the first embodiment. FIG. 1 shows a cross-sectional structure of a semiconductor device according to a first embodiment in an off state. The off state is a state in which the semiconductor device does not operate, and a state in which the gate voltage is at least 0 V or lower (a state in which the gate voltage is not applied to the gate electrode or a negative gate voltage is applied). The ON state is a state in which the semiconductor device operates, and is a state in which the gate voltage is equal to or higher than the threshold voltage (gate voltage≧threshold voltage). As shown in FIG. 1, in the semiconductor device according to the first embodiment, a MOS gate structure having a trench gate structure is provided on the first main surface side of the n ⁻ type drift layer (semiconductor layer) 2. The MOS gate structure has a p ⁻ type base region (first semiconductor region) 3, an n ⁺ type emitter region (second semiconductor region) 4, a trench 5, a deposited insulating layer (insulating layer) 6, a gate insulating film 7 and a gate electrode. It consists of 8.

A p ⁺ type collector layer (fourth semiconductor region) 1 is provided on the second main surface side of the n ⁻ type drift layer 2. The p ⁺ -type collector layer 1 may be a diffusion region formed in the surface layer of the second main surface of the n ⁻ -type drift layer 2 by, for example, ion implantation, or the semiconductor device according to the first embodiment is manufactured (manufactured). It may be configured by a p ⁺ type starting substrate (semiconductor chip) prepared for the purpose. If the p ⁺ -type collector layer 1 and the p ⁺ -type starting substrate, n ^- -type drift layer 2 is an epitaxial layer deposited for example the front surface of the p ⁺ -type starting substrate comprising the p ⁺ -type collector layer 1 .. The p ⁻ type base region 3 is provided on the first main surface side of the n ⁻ type drift layer 2. p ^- type base region 3, n ^- may be an epitaxial layer deposited on the first major surface of the type drift layer 2, n ^- the surface layer, for example, ion implantation of the first main surface of the type drift layer 2 It may be a formed diffusion region.

The lower the impurity concentration of the p ⁻ type base region 3, the lower the threshold voltage, but when the gate voltage is set to at least 0 V or less, the channel () is formed in the portion of the p ⁻ type base region 3 facing the gate electrode 8. It is preferable that the n-type inversion layer) is low (not in the on state). The n ⁺ type emitter region 4 is selectively provided inside the p ⁻ type base region 3. The n ⁺ type emitter region 4 may be an epitaxial layer or a diffusion region formed by ion implantation, for example. Trench 5 penetrates n ⁺ type emitter region 4 and p ⁻ type base region 3 to reach n ⁻ type drift layer 2. The deposited insulating layer 6 is provided inside the trench 5 on the collector side. That is, the deposited insulating layer 6 is embedded in the bottom of the trench 5 (end on the collector side).

The gate electrode 8 is provided on the surface (emitter side) of the deposited insulating layer 6 inside the trench 5. Gate electrode 8 opposes p ⁻ type base region 3, n ⁺ type emitter region 4 and n ⁻ type drift layer 2 with gate insulating film 7 provided on the side wall of trench 5 interposed therebetween. That is, the end of the gate electrode 8 on the collector side is located on the collector side of the pn junction 21 between the p ⁻ type base region 3 and the n ⁻ type drift layer 2. Inside the n ⁻ type drift layer 2, a p type diffusion region (p type buried region (third semiconductor region)) 9 is selectively provided apart from the p ⁻ type base region 3. The p-type buried region 9 is buried inside the n ⁻ -type drift layer 2 so as to surround the bottom of the trench 5 and faces the gate electrode 8 with the deposition insulating layer 6 in between. That is, the bottom of the trench 5 is located inside the p-type buried region 9.

The p-type buried region 9 may extend to the emitter side along the inner wall of the trench 5 so as not to face the gate electrode 8 with the gate insulating film 7 provided on the side wall of the trench interposed therebetween. That is, the thickness t1 of the deposited insulating layer 6 is so thick that the p-type buried region 9 and the gate electrode 8 do not face each other with the gate insulating film 7 provided on the sidewall of the trench 5 interposed therebetween. The p-type buried region 9 has a function of relaxing an electric field applied to the n ⁻ type drift layer 2. The p-type buried region 9 may be, for example, a diffusion region formed by ion implantation. The impurity concentration of the p-type buried region 9 can be variously changed according to design conditions, and may be high enough to prevent degeneration of the energy level (the Fermi level does not move into the valence band). For example, the impurity concentration of the p-type buried region 9 is high enough not to deplete the entire p-type buried region 9 even when a high voltage is applied to the collector, for example, approximately the same as the impurity concentration of the n ⁻ -type drift layer 2. It is set above.

A p-type inversion layer 12 is formed along the gate insulating film 7 in the off state in a portion of the n ⁻ -type drift layer 2 between the p ⁻ -type base region 3 and the p-type buried region 9. (Hatched portion in the figure). This p-type inversion layer 12 electrically connects the p ⁻ -type base region 3 and the p-type buried region 9. Therefore, in the off state, the p-type buried region 9 is fixed to the emitter potential. In order to generate the p-type inversion layer 12 in the portion of the n ⁻ type drift layer 2 sandwiched between the p ⁻ type base region 3 and the p type buried region 9 in the off state, the n ⁻ type drift layer 2 is formed. Impurity concentration, the thickness t2 of the gate insulating film 7, and the work function of the gate electrode 8 are set appropriately. Specifically, the impurity concentration of the portion of the n ⁻ type drift layer 2 sandwiched between the p ⁻ type base region 3 and the p type buried region 9 causes the p type inversion layer 12 when the off state (( That is, there is a hole) and is set low.

n ^- type drift layer 2, p ^- impurity concentration type base region 3 and the p-type buried region 9 and the portion sandwiched by the, n ^- may be different from the impurity concentration of the other parts of the type drift layer 2 .. For example, n ^- when the impurity concentration of the type drift layer 2 is in the range of degree 1 × 10 ¹⁴ / cm ³ or more 1 × 10 ¹⁶ / cm ³ or less, n ^- type drift layer 2, p ^- type base region 3 The impurity concentration of the portion sandwiched between the p-type buried region 9 and the p-type buried region 9 is, for example, about 1×10 ¹⁷ /cm ³ or less. The thickness t2 of the gate insulating film 7 is such that the p-type inversion layer 12 is formed in the portion of the n ⁻ type drift layer 2 sandwiched between the p ⁻ type base region 3 and the p type buried region 9 in the off state. It may be set so thin that it causes it. That is, the thickness t2 of the gate insulating film 7 only needs to satisfy the above conditions, and may be smaller than the thickness of the deposited insulating layer 6 or the same as the deposited insulating layer 6, for example. ..

For example, the thickness t2 of the gate insulating film 7 is 100 nm, and the impurity concentration of the portion of the n ⁻ type drift layer 2 sandwiched between the p ⁻ type base region 3 and the p type buried region 9 is 1×10 ¹⁷ /cm 3. ^{When set to 3} , the p-type inversion layer 12 is formed when the gate voltage is about −10V. If the impurity concentration of the portion of the n ⁻ type drift layer 2 sandwiched between the p ⁻ type base region 3 and the p type buried region 9 is about 1×10 ¹⁷ /cm ³ or less, the gate voltage is up to about −15 V. The p-type inversion layer 12 can be formed even in an application (product) for shifting to a lower level. Further, when the impurity concentration of the n ⁻ type drift layer 2 is uniformly about 5×10 ¹⁴ /cm ³ or less (for example, breakdown voltage 13 kV class), the p type inversion layer 12 is formed even if the gate voltage is about −2 V. Can be formed.

Even if the gate voltage is about 0 V, the p-type inversion layer 12 can be formed by appropriately setting the work function of the gate electrode 8. In this case, the gate electrode 8 is, for example, a part (n between the p ⁻ type base region 3 and the p type buried region 9 of the n ⁻ type drift layer 2 due to a work function difference from the n ⁻ type drift layer 2 (n It may be formed of an electrode material having a work function that causes holes in the ⁻ type drift layer 2 (in the vicinity of the interface with the gate insulating film 7). Specifically, as an electrode material of the gate electrode 8, for example, a p-type silicon carbide (SiC) semiconductor having a high impurity concentration of about 1×10 ¹⁸ /cm ³ or a doped polysilicon doped with p-type impurities is used. -Si) or the like may be used. The emitter electrode (first electrode) 10 is in contact with the p ⁻ type base region 3 and the n ⁺ type emitter region 4, and is electrically insulated from the gate electrode 8 by an interlayer insulating film (not shown). The collector electrode (second electrode) 11 is in contact with the p ⁺ -type collector layer 1.

Although not particularly limited, for example, when the semiconductor device according to the first embodiment has a breakdown voltage of 13 kV class, the n ⁺ type emitter region 4 and the p ⁺ type collector layer 1 have sufficiently high impurity concentrations (1×10 ¹⁸ /cm ³ or more). And the thickness is about 0.1 μm or more. The impurity concentration of the p ⁻ type base region 3 is about 1×10 ¹⁵ /cm ³ or more and 1×10 ¹⁷ /cm ³ or less, depending on the thickness t2 of the gate insulating film 7. The thickness of the n ⁻ type drift layer 2 is about 100 μm or more and 150 μm or less. The impurity concentration of the n ⁻ type drift layer 2 is within the above-mentioned range, preferably about 5×10 ¹⁴ /cm ³ or less. The depth of the trench 5 is about 1 μm or more and 3 μm or less. The thickness t2 of the gate insulating film 7 is about 50 nm or more and 200 nm or less. The impurity concentration of the p-type buried region 9 is about 1×10 ¹⁸ /cm ³ or more.

Next, the operation of the semiconductor device according to the first embodiment will be described. The emitter electrode 10 is in a state of being grounded to the ground or a state of being applied with a negative voltage (emitter potential≦0). The collector electrode 11 is in a state where a positive voltage is applied (collector potential>0). In this state, the pn junction 21 between the p ⁻ type base region 3 and the n ⁻ type drift layer 2 is reverse biased. Therefore, a depletion layer (not shown) spreads inside the p ⁻ type base region 3 and the n ⁻ type drift layer 2, and the path (channel) of electrons that are conduction carriers is blocked. At this time, when no gate voltage is applied to the gate electrode 8 or a negative gate voltage is applied (gate voltage≦0 V), no current flows between the emitter and collector. That is, the off state is maintained. While the off-state is maintained, the p ⁻ type inversion layer 12 is provided along the gate insulating film 7 in the portion of the n ⁻ type drift layer 2 sandwiched between the p ⁻ type base region 3 and the p type buried region 9. Are formed, and the p ⁻ type base region 3 and the p type buried region 9 are electrically connected. For this reason, the p-type buried region 9 is fixed at substantially the same base (emitter) potential as the p ⁻ -type base region 3, and the pn junction 22 between the p-type buried region 9 and the n ⁻ -type drift layer 2 is also reverse biased. It

On the other hand, when the voltage applied to the gate electrode 8 is equal to or higher than the threshold voltage (gate voltage≧threshold voltage), the p ⁻ type base region 3 is sandwiched between the n ⁺ type emitter region 4 and the n ⁻ type drift layer 2. An n-type inversion layer (channel (not shown)) is formed along the gate insulating film 7 at a portion (a portion facing the gate electrode 8). As a result, the n ⁺ -type emitter region 4, the n-type inversion layer, and the n ⁻ -type drift layer 2 serve as an electron path for conduction carriers. That is, the electrons emitted from the emitter electrode 10 move to the collector electrode 11 through the n ⁺ type emitter region 4, the n type inversion layer and the n ⁻ type drift layer 2, and a current flows between the emitter and the collector. This state is the ON state. In the on state, the p-type inversion layer 12 does not occur in the portion of the n ⁻ -type drift layer 2 sandwiched between the p ⁻ -type base region 3 and the p-type buried region 9, so that the p-type buried region 9 floats. It becomes a state. Then, by again setting the voltage applied to the gate electrode 8 to at least 0 V or less (gate voltage≦0 V), the on state is changed to the off state. In this way, the voltage applied to the gate electrode 8 controls on/off of the semiconductor device.

Even when the gate voltage is higher than 0 and lower than the threshold voltage (0<gate voltage<threshold voltage), the n-type inversion layer (channel) is not formed as in the case where the gate voltage is 0 V or less. However, in reality, after the command value for off control (gate voltage<threshold voltage) is applied from the outside to the gate electrode 8, until the gate voltage becomes 0 V, the semiconductor device according to the first embodiment Is in a transition state until it stops operating, and is not completely stopped. Therefore, in the above description, although at least 0V following conditions in the OFF state which is the gate voltage operation is completely stopped in a semiconductor device according to the first embodiment, n ^- the type drift layer 2 of p-type The gate voltage when the inversion layer 12 is formed is equal to the gate voltage (that is, the threshold voltage) when the n-type inversion layer (channel) is formed in the p ⁻ type base region 3 (on state). If the gate voltage is lower than the threshold voltage (gate voltage<threshold voltage), the off state may be set as long as it is adjustable.

Further, in the above description, a device using a conductivity modulation effect such as an IGBT is described as an example, but the present invention is applied to an insulated gate field effect transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor). May be. In this case, an n ⁺ type drain layer is provided instead of the p ⁺ type collector layer 1, and the n ⁺ type emitter region 4, the emitter electrode 10 and the collector electrode 11 are used as an n ⁺ type source region, a source electrode and a drain electrode, respectively. A silicon (Si) semiconductor may be used as the semiconductor material of the semiconductor device according to the first embodiment, or a semiconductor having a wider bandgap than silicon (hereinafter, referred to as a wide bandgap semiconductor) such as a silicon carbide semiconductor. ) May be used.

As described above, according to the first embodiment, since the p-type buried region is in the floating state when in the ON state, extraction of minority carriers (holes) from the p-type buried region to the emitter electrode occurs. Absent. Therefore, the conductivity modulation is not hindered in a device using the conductivity modulation effect such as an IGBT. This makes it possible to prevent the on-resistance characteristics from deteriorating. That is, the ON resistance characteristic can be improved as compared with the case where the p-type buried region is fixed to the emitter potential in the ON state as in Patent Document 3, for example.

Further, for example, when the p-type buried region is in a floating state when it is in the off state as in the above-mentioned Patent Document 3, the potential difference between the gate electrode and the p-type buried region becomes large depending on the potential state of the p-type buried region, and the deposition is increased. A high electric field may concentrate on the insulating layer. On the other hand, according to the first embodiment, in the off state, the p-type buried region is electrically connected to the p ⁻ -type base region by the p ^- type inversion layer and fixed at the emitter potential (eg, ground). As a result, even if a high voltage is applied to the collector electrode, the potential difference between the gate electrode and the p-type buried region (voltage applied to the deposited insulating layer) is about the gate voltage, so that the high electric field is not concentrated in the deposited insulating layer. .. Further, by fixing the p-type buried region to the emitter potential, the portion of the n ⁻ type drift layer along the gate insulating film is also kept at a potential close to the emitter potential, and the voltage applied to the gate insulating film is about the gate voltage. Becomes Therefore, the high electric field is not concentrated on the gate insulating film. Therefore, it is possible to improve the withstand voltage characteristic as compared with the related art, and it is possible to prevent malfunction or insulation breakdown. Further, since the high electric field is not concentrated on the gate oxide film, the allowable upper limit value of the collector voltage can be increased to the extent that an electric field close to the maximum electric field strength of the semiconductor material is generated. Thereby, for example, by using a wide bandgap semiconductor, it is possible to increase the breakdown voltage up to a state close to the characteristic limit of the wide bandgap semiconductor material.

Further, according to the first embodiment, a p-type inversion layer is formed inside the n ⁻ -type drift layer in the off-state, and the p ⁻ -type base region and the p-type buried region are formed by the p-type inversion layer. Therefore, it is not necessary to form a diffusion region for connecting the p ⁻ type base region and the p type buried region as in Patent Document 3, for example. Therefore, the manufacturing process can be simplified as compared with the related art.

(Embodiment 2)
Next, the structure of the semiconductor device according to the second embodiment will be described. FIG. 2 is a sectional view showing the structure of the semiconductor device according to the second embodiment. The semiconductor device differs from that according to the semiconductor device according to the first embodiment of the second embodiment, n ^- inside the type drift layer 2, n ^- -type drift layer 2 high n-type diffusion region impurity concentration than (or less , N-type blocking region (fifth semiconductor region) 13 is provided. The n-type blocking region 13 serves as a barrier against minority carriers (holes) inside the n ⁻ type drift layer 2 when in the on state, and has a function of enhancing the effect of accumulating minority carriers. As a result, the carrier density of the n ⁻ type drift layer 2 can be increased, so that the on-resistance can be reduced.

n-type blocking region 13, n ^- type drift layer 2, p ^- between type base region 3 and the p-type buried region 9, p ^- be provided apart -type base region 3 and the p-type buried region 9 Is preferred. The reason is as follows. The electric field strength near the pn junction 21 between the p ⁻ type base region 3 and the n ⁻ type drift layer 2 or the electric field strength near the bottom of the trench 5 (near the p type buried region 9 and the deposited insulating layer 6) is a breakdown voltage. Rate control. This is because it is preferable not to provide the n-type blocking region 13 so that the impurity concentration of the n ⁻ -type drift layer 2 does not become high in the portion that controls the breakdown voltage. That is, by providing the n-type blocking region 13 between the p ⁻ -type base region 3 and the p-type buried region 9, the electric field strength at the bottom of the trench 5 and the p-type buried region 9 is not substantially changed, and the n-type blocking region 13 is not changed. A blocking area 13 can be provided. As a result, low on-resistance can be achieved without lowering the breakdown voltage.

The impurity concentration of the n-type blocking region 13 is higher than the impurity concentration of the n ⁻ -type drift layer 2. Further, even if the impurity concentration of the n-type blocking region 13 is a high impurity concentration (for example, about 1×10 ¹⁷ /cm ³ ) so that the electric field strength on the collector side of the p-type buried region 9 does not exceed the withstand voltage limit value. Good. The thickness of the n-type blocking region 13 is, for example, about several μm. The n-type blocking region 13 may be an epitaxial layer or a diffusion region formed by ion implantation, for example. When forming the n-type blocking region 13 made of the epitaxial layer, for example, the p ⁺ -type starting substrate comprising the p ⁺ -type collector layer 1, n ^- after depositing a type drift layer 2 and the n-type blocking regions 13, again n ^- n by depositing the type drift layer 2 ^- may be adjusted thickness of the type drift layer 2. When forming the n-type blocking region 13 formed of the diffusion region by ion implantation, for example, the acceleration energy of the ion implantation is changed variously, and the n-type blocking region is formed at a predetermined depth from the first main surface of the n ⁻ type drift layer 2. 13 may be formed.

n-type blocking region 13, n ^- across the type drift layer 2, for example p ^- type base region 3 and the n ^- may be opposed to the pn junction 21 over the entire surface between the type drift layer 2. The n-type blocking region 13 may be provided on the collector side of the bottom of the trench 5. In this case, by appropriately setting the impurity concentration and the thickness of the n-type blocking region 13, it is possible to minimize the decrease in breakdown voltage.

As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained. Further, according to the second embodiment, by providing the n-type blocking region, the on-resistance characteristic can be further improved.

(Embodiment 3)
Next, the structure of the semiconductor device according to the third embodiment will be described. FIG. 3 is a sectional view showing the structure of the semiconductor device according to the third embodiment. The semiconductor device according to the third embodiment is different from the semiconductor device according to the second embodiment in that p-type buried region 9 is always in a floating state (both in the on state and the off state).

In the third embodiment, the off-state, n ^- inside the type drift layer 2, p ^- type base region 3 and n ^- depletion from the pn junction 21 between the type drift layer 2 (not shown) It spreads and the peak of the electric field intensity becomes near the pn junction 21. Further, n ^- in the interior of the type drift layer 2, p-type buried region 9 and the n ^- depletion layer from the pn junction 22 between the type drift layer 2 (not shown) is spread, in the vicinity of the pn junction 22 A peak of electric field strength is formed. That is, the peak of the electric field strength can be dispersed in two places inside the n ⁻ type drift layer 2, and the maximum peak value of the electric field strength can be reduced. Therefore, the breakdown voltage can be improved. Further, by providing the n-type blocking region 13 inside the n ⁻ -type drift layer 2, it is possible to improve the on-resistance characteristics as in the second embodiment.

As described above, according to the third embodiment, the same effect as that of the second embodiment can be obtained.

(Embodiment 4)
Next, the structure of the semiconductor device according to the fourth embodiment will be described. FIG. 4 is a sectional view showing the structure of the semiconductor device according to the fourth embodiment. The semiconductor device according to the fourth embodiment is different from the semiconductor device according to the third embodiment in that a portion sandwiched between adjacent trenches 5 is deeper than the trenches 5 and is always fixed to the emitter potential. Another p-type region (hereinafter, referred to as p-type column region (third semiconductor region)) 14 is provided. In the fourth embodiment, the p-type buried region is not provided. In addition, the n-type blocking region (fifth semiconductor region) 15 is a portion that controls the breakdown voltage (in the vicinity of the deposited insulating layer 6 and in the vicinity of the pn junction 23 between the p-type column region 14 and the n ⁻ -type drift layer 2 described later). ) Is provided closer to the collector side than the bottom of the trench 5 so that the impurity concentration of the n ⁻ type drift layer 2 in FIG.

The p-type column region 14 is provided between the adjacent trenches 5 and apart from the trench 5, and is electrically connected to the emitter electrode 10. The depth of the p-type column region 14 is deeper than the depth of the trench 5. For example, the p type column region 14 may penetrate the n ⁺ type emitter region 4 and the p ⁻ type base region 3 to reach the n type blocking region 15 provided inside the n ⁻ type drift layer 2. .. By providing the p-type column region 14 deeper than the trench 5, the electric field can be concentrated on the pn junction 23 between the p-type column region 14 and the n ⁻ -type drift layer 2, so that the vicinity of the deposited insulating layer 6 is formed. The electric field strength can be reduced. The impurity concentration of the p-type column region 14 can be variously changed according to design conditions, and may be high enough to prevent degeneration of the energy level.

As described above, according to the fourth embodiment, by providing the n-type blocking region inside the n ⁻ -type drift layer, the on-resistance characteristics can be improved as in the second embodiment.

(Embodiment 5)
Next, the structure of the semiconductor device according to the fifth embodiment will be described. FIG. 5 is a sectional view showing the structure of the semiconductor device according to the fifth embodiment. The semiconductor device according to the fifth embodiment is different from the semiconductor device according to the fourth embodiment in that the p ⁻ type base region 3 and the p type buried region (sixth semiconductor region) are formed by the p type column region (seventh semiconductor region) 16. ) 9 is connected. That is, similar to the p-type column region of the fourth embodiment, the p ⁻ -type base region 3, the p-type column region 16, and the p-type buried region 9 form a portion sandwiched between the adjacent trenches 5 from the trench 5. The p-type region is provided with a deep depth and is always fixed to the emitter potential. Specifically, the p-type column region 16 is formed on the gate insulating film 7 provided on the sidewall of the trench 5 between the p ⁻ -type base region 3 and the p-type buried region 9 of the n ⁻ -type drift layer 2. It is provided along. The structure of the n-type blocking region 15 is similar to that of the fourth embodiment.

As described above, according to the fifth embodiment, the same effect as that of the fourth embodiment can be obtained.

In the above, the present invention can be variously modified without departing from the spirit of the present invention, and in the above-described respective embodiments, for example, the dimensions of each part, the impurity concentration, etc. are variously set according to the required specifications and the like. Further, although the first conductivity type is the n-type and the second conductivity type is the p-type in each of the above-described embodiments, the present invention may have the first conductivity type as the p-type and the second conductivity type as the n-type. The same applies.

As described above, the semiconductor device according to the present invention is useful for a MOS semiconductor device having a trench gate structure having a high breakdown voltage.

1 p ⁺ type collector layer 2 n ⁻ type drift layer 3 p ⁻ type base region 4 n ⁺ type emitter region 5 trench 6 deposition insulating layer 7 gate insulating film 8 gate electrode 9 p type buried region 10 emitter electrode 11 collector electrode 12 p Inversion layer 13,15 n-type blocking region 14,16 p-type column region 21 p ^- type base region and n ^- type drift layer pn junction 22 p-type buried region and n ^- type drift layer Pn junction of a pn junction between a p-type column region and an n ⁻ type drift layer

Claims (7)

A second conductive type first semiconductor region provided on the first main surface side of the first conductive type semiconductor layer;
A second semiconductor region of a first conductivity type selectively provided inside the first semiconductor region;
A trench penetrating the second semiconductor region and the first semiconductor region to reach the semiconductor layer;
An insulating layer embedded in the bottom of the trench,
Inside the trench, a gate insulating film provided along the sidewall of the trench,
Inside the trench, inside the gate insulating film, and a gate electrode provided on the surface of the insulating layer,
A second conductive type third semiconductor region selectively provided inside the semiconductor layer so as to surround the bottom of the trench, and facing the gate electrode with the insulating layer interposed therebetween;
A fourth semiconductor region provided on the second main surface side of the semiconductor layer,
A first electrode electrically connected to the first semiconductor region and the second semiconductor region;
A second electrode electrically connected to the fourth semiconductor region;
Equipped with
When in the off state, a second conductivity type inversion layer is formed along the gate insulating film in a portion of the semiconductor layer sandwiched between the first semiconductor region and the third semiconductor region. The first semiconductor region and the third semiconductor region are electrically connected,
The third semiconductor region extends to the second semiconductor region side along the trench, is closer to the bottom of the trench than the interface between the insulating layer and the gate electrode, and is the interface of the gate insulating film from the interface. It is separated by more than the thickness,
The thickness of the gate insulating film is uniform along the sidewall of the trench,
The semiconductor device is characterized in that the thickness of the insulating layer is thicker than the thickness of the gate insulating film. The semiconductor layer further includes a fifth semiconductor region of the first conductivity type, which is selectively provided separately from the first semiconductor region and the third semiconductor region and has a higher impurity concentration than that of the semiconductor layer. The semiconductor device according to claim 1, wherein: The semiconductor device according to claim 2, wherein the fifth semiconductor region is provided in the semiconductor layer between the first semiconductor region and the third semiconductor region. The impurity concentration of the semiconductor layer and the thickness of the gate insulating film are set such that the inversion layer is generated in an off state. Semiconductor device. 5. The impurity concentration of the semiconductor layer, the thickness of the gate insulating film, and the work function of the gate electrode so that the inversion layer is generated in the off state are set. Semiconductor device. The semiconductor device according to claim 1, wherein the third semiconductor region is in a floating state when it is in an on state. The semiconductor device according to claim 1, further comprising the fourth semiconductor region of the second conductivity type.

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