JP6714390B2 - Electronic device and manufacturing method thereof - Google Patents

Description

The present invention relates to an electronic device and a manufacturing method thereof, for example, an electronic device having a two-dimensional active layer and a manufacturing method thereof.

Graphene is a carbon material in which a 6-membered ring formed by carbon is formed into a sheet. The electron mobility of graphene is very high. Therefore, a transistor using graphene as a channel is known (Patent Document 1). Further, two-dimensional conductive high _MoS, transition metal chalcogenides, such as MoS 2, MoSe or MoSe ₂ are known.

JP, 2011-192667, A

Even if an ohmic electrode is formed on the active layer of graphene or transition metal chalcogenite, the contact resistance between the ohmic electrode and the active layer is high.

The present invention has been made in view of the above problems, and an object thereof is to reduce the contact resistance between an ohmic electrode and an active layer.

The present invention provides a substrate, an active layer provided on the substrate, in which one or more atomic layers or molecular layers made of graphene or transition metal chalcogenite are laminated, and the active layer provided on the active layer. A plurality of ohmic electrodes electrically contacting each other, wherein the roughness of the upper surface of the substrate in the first region where the plurality of ohmic electrodes electrically contact the active layer is equal to the roughness between the plurality of ohmic electrodes. The electronic device is larger than the roughness of the upper surface of the substrate in the second region in which carriers travel in the active layer.

The invention of the present application comprises the step of making the upper surface of the substrate in the first region rougher than the upper surface of the substrate in the second region, and an atomic layer made of graphene or transition metal chalcogenite on the substrate in the first region and the second region, or Forming an active layer in which one or more molecular layers are laminated, and forming a plurality of ohmic electrodes on the active layer in electrical contact with the active layer in the first region; And a step of not forming the inside thereof, wherein the second region is a region in which carriers travel in the active layer between the plurality of ohmic electrodes.

According to the present invention, the contact resistance between the ohmic electrode and the active layer can be reduced.

FIG. 1 is a conceptual diagram showing a graphene layer and an ohmic electrode in a comparative example. FIG. 2 is a conceptual sectional view of the electronic device according to the first embodiment. FIG. 3 is a conceptual sectional view of the vicinity of the first region in the first embodiment. FIG. 4A is a TEM image (No. 1) of the graphene layer formed on the SiC substrate. FIG. 4B is a TEM image (part 2) of the graphene layer formed on the SiC substrate. FIG. 4C is a TEM image (No. 3) of the graphene layer formed on the SiC substrate. FIG. 5A is a cross-sectional view (1) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 5B is a cross-sectional view (2) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 5C is a cross-sectional view (3) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 6A is a cross-sectional view (4) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 6B is a cross-sectional view (5) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 6C is a cross-sectional view (6) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 6D is a cross-sectional view (7) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 7A is a cross-sectional view (8) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 7B is a cross-sectional view (9) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 7C is a cross-sectional view (10) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 7D is a cross-sectional view (11) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 8A is a cross-sectional view (12) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 8B is a cross-sectional view (13) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 8C is a cross-sectional view (14) illustrating the method for manufacturing the FET according to the second embodiment.

[Description of Embodiments of the Present Invention]
First, the contents of the embodiments of the present invention will be listed and described.
The present invention provides a substrate, an active layer provided on the substrate, in which one or more atomic layers or molecular layers made of graphene or transition metal chalcogenite are laminated, and the active layer provided on the active layer. A plurality of ohmic electrodes electrically contacting each other, wherein the roughness of the upper surface of the substrate in the first region where the plurality of ohmic electrodes electrically contact the active layer is equal to the roughness between the plurality of ohmic electrodes. The electronic device is larger than the roughness of the upper surface of the substrate in the second region in which carriers travel in the active layer. This makes it possible to reduce the contact resistance between the ohmic electrode and the active layer without lowering the carrier mobility of the active layer in the second region in which the carriers travel.

It is preferable that the substrate is a SiC substrate and the active layer is a graphene layer. This makes it possible to reduce the contact resistance between the ohmic electrode and the graphene layer without lowering the carrier mobility of the graphene layer in the second region in which the carriers travel.

It is preferable to provide a gate electrode provided on the active layer in the second region. Accordingly, it is possible to prevent the mobility of the graphene layer serving as a channel below the gate electrode from being lowered.

The present invention comprises the step of making the upper surface of the substrate in the first region rougher than the upper surface of the substrate in the second region, and an atomic layer of graphene or a transition metal chalcogenite on the substrate in the first region and the second region, or Forming an active layer in which one or more molecular layers are laminated, and forming a plurality of ohmic electrodes on the active layer in electrical contact with the active layer in the first region; And a step of not forming the inside thereof, wherein the second region is a region in which carriers travel in the active layer between the plurality of ohmic electrodes. This makes it possible to reduce the contact resistance between the ohmic electrode and the active layer without lowering the carrier mobility of the active layer in the second region in which carriers travel.

The substrate is a SiC substrate, and the step of forming the atomic layer or the active layer preferably includes a step of forming a graphene layer from carbon in the substrate by heat-treating the substrate. This makes it possible to reduce the contact resistance between the ohmic electrode and the graphene layer without lowering the carrier mobility of the graphene layer in the second region in which the carriers travel.

[Details of Embodiment of Present Invention]
Specific examples of the semiconductor device according to the embodiment of the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited to these exemplifications, and is shown by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope.

FIG. 1 is a conceptual diagram showing a graphene layer and an ohmic electrode in a comparative example. As shown in FIG. 1, in the electronic device according to Comparative Example 1, a graphene layer 12 is provided on a SiC substrate 10. The ohmic electrode 25 is provided on the graphene layer 12. In the graphene layer 12, one or more atomic layers 48 are stacked. The one-atom layer 48 is a layer having one carbon atom 40.

The reason why the contact resistance between the graphene layer 12 and the ohmic electrode 25 is high is not clear, but it can be considered as follows, for example. The carbon atoms of the atomic layer 48 are formed by σ bonds 44 formed by σ orbits 42. The σ bond 44 extends two-dimensionally in the plane direction. A ππ ^* orbit 46 which is a valence electron orbit exists substantially perpendicular to the σ bond 44. The wave functions of the ππ ^* orbit 46 are overlapped in the plane direction and are formed by the electron cloud 47. The two-dimensional carrier conduction in the graphene layer 12 is performed by the σ bond 44 and the electron cloud 47.

Ideally, the orbits of the carbon atoms 40 in the graphene layer 12 are all bonded between the carbon atoms. That is, the graphene layer 12 does not share an orbit with the ohmic electrode 25. The bond between the graphene layer 12 and the ohmic electrode 25 is only weak due to Van der Waals force. Therefore, when the bond between carbon atoms in the graphene layer 12 is in an ideal state, injection of electrons from the ohmic electrode 25 into the electron cloud 47 of the ππ ^* orbit 46 in the graphene layer 12 or extraction of electrons from the electron cloud 47 is performed. (Hole injection) is hard to occur.

In reality, the graphene layer 12 has defects. In addition, there is an end portion of the graphene layer 12. These cause the injection of carriers into the electron cloud 47. However, since the density of defects and edges is low, the contact resistance between the ohmic electrode 25 and the graphene layer 12 becomes high.

For example, in an FET (Field Effect Transistor), which the prototypes of the present inventors prototype, use the graphene layer 12 as a channel, the contact resistance with the ohmic electrode 25 is about 1×10 ⁻⁴ Ω·cm ² . When the gate length is 80 nm, the cutoff frequency is 400 GHz. In the device simulation, if the contact resistance between the channel and the ohmic electrode can be set to 1×10 10 ⁻⁶ Ω·cm ² that is equivalent to that of a GaN-based FET, the cutoff frequency can be set to 600 GHz.

FIG. 2 is a conceptual sectional view of the electronic device according to the first embodiment. As shown in FIG. 2, the graphene layer 12 is provided on the substrate 10. The graphene layer 12 includes one or a plurality of atomic layers 48. A source electrode 24 and a drain electrode 26 are provided as the ohmic electrode 25 on the graphene layer 12. The gate electrode 20 is provided between the source electrode 24 and the drain electrode 26 on the graphene layer 12 with the gate insulating film 14 interposed therebetween. The first region 60 is a region where the ohmic electrode 25 electrically contacts the graphene layer 12. The second region 62 is a region where carriers travel in the graphene layer 12 between the ohmic electrodes 25 (for example, between the source electrode 24 and the drain electrode 26). A recess 45 is formed on the upper surface of the first region 60. The upper surface of the second region 62 is flat. The substrate 10 is a SiC substrate, and the graphene layer 12 is formed by a thermal sublimation method. The ohmic electrode 25 is a nickel (Ni) layer.

FIG. 3 is a conceptual sectional view of the first region in the first embodiment. As shown in FIG. 3, a recess 45 is formed on the upper surface of the substrate 10 in the first region 60. The depth D from the upper surface 11 of the substrate 10 in the region other than the recess 45 to the bottom of the recess 45 is, for example, 1 nm to 100 nm, and the width W is, for example, several 100 nm to several 10 μm. In the recess 45, a larger number of atomic layers 48 are stacked than in the recess 45. The atomic layer 48a in the region where the recess 45 is not formed is two-dimensionally spread. On the other hand, the atomic layer 48b provided in the recess 45 has an end 49. In the thermal sublimation method, the atomic layer 48 is formed from the substrate 10 side of the graphene layer 12. Therefore, the plurality of atomic layers 48b in the recess 45 are formed between the upper atomic layer 48a and the substrate 10.

The graphene layer 12 was formed on the SiC substrate 10, and the number of atomic layers 48 in the graphene layer 12 inside and outside the recess 45 was observed. The method for producing the sample is as follows. A recess 45 having a depth D of about 16 nm, a width W of about 20 μm, and a depth D of 16 μm was formed on the upper surface 11 of the H-SiC substrate 10. The surface of the SiC substrate 10 is cleaned. The washing conditions are 5 minutes for acetone treatment, 5 minutes for ethanol treatment, and 5 minutes for water washing. Then, the graphene layer 12 is formed by using the thermal sublimation method. The graphene layer 12 is formed by heat-treating the SiC substrate 10 at 1600° C. in an Ar atmosphere. The heat treatment time was set longer than when manufacturing the FET described later so that the graphene layer 12 can be easily observed.

4A to 4C are TEM (Transmission Electron Microscope) images of the graphene layer formed on the SiC substrate. FIG. 4A is a cross-sectional TEM image of a portion other than the recess 45. FIG. 4B is a cross-sectional TEM image of a portion in the recess 45, which is not the deepest portion but has a depth from the upper surface 11 of about 9.5 nm. FIG. 4C is a cross-sectional TEM image of the deepest portion in the recess 45, where the depth D from the upper surface 11 is about 16 nm. The depth from the upper surface 11 was measured using an AFM (Atomic Force Microscope) method.

As shown in FIGS. 4A to 4C, the atomic layer stacked on the graphene layer 12 can be observed. In FIG. 4A, three to five atomic layers are stacked. In FIG. 4B, about 15 atomic layers are stacked. In FIG. 4C, about 30 atomic layers are stacked. One atomic layer in the graphene layer 12 is about 0.35 nm. Therefore, the graphene layer 12 having a thickness of about 30% to 60% of the depth from the upper surface 11 is formed in the recess 45. In this way, atomic layers are stacked in the recess 45 depending on the depth.

Returning to FIG. 3, for this reason, the end portion 49 of the atomic layer 48b exists in the region where the depth of the recess 45 changes. At the end portion 49, there is an unbonded orbital of carbon atom orbitals. Therefore, as indicated by the arrow 70, carriers are easily injected from the ohmic electrode 25 into the atomic layer 48b. The carriers injected into the atomic layer 48b move to the atomic layer 48a and propagate in the two-dimensional direction. Alternatively, the state of the electron cloud of the atomic layer 48a changes due to the influence of the end portion 49 of the atomic layer 48b. This facilitates the injection of carriers from the ohmic electrode 25 into the atomic layer 48a. These can reduce the contact resistance between the ohmic electrode 25 and the graphene layer 12.

When the recess 45 is formed in the substrate 10 and the number of stacked atomic layers 48 of the graphene layer 12 is modulated, the potential inside the graphene layer 12 is modulated. This reduces the carrier mobility in the graphene layer 12. Therefore, as shown in FIG. 2, the recess 45 is not provided in the substrate 10 in the second region 62. That is, the roughness of the upper surface of the substrate 10 in the second region 62 is made smaller than that in the second region 62. Accordingly, the contact resistance between the ohmic electrode 25 and the graphene layer 12 in the first region 60 can be reduced without lowering the carrier mobility of the graphene layer 12 in the second region 62.

The second embodiment is an example in which the first embodiment is applied to an FET (Field Effect Transistor). 5A to 8C are cross-sectional views showing the method for manufacturing the FET according to the second embodiment. As shown in FIG. 5A, the surface of the 6H—SiC substrate 10 is cleaned. The washing conditions are 5 minutes for acetone treatment, 5 minutes for ethanol treatment, and 5 minutes for water washing. As the cleaning of the substrate 10, for example, RCA processing may be performed. The substrate 10 may be a Si substrate on which a SiC layer is formed. When forming the graphene layer 12 using the SiC thermal sublimation method, the uppermost surface of the substrate 10 is the SiC layer. For example, when forming the graphene layer 12 using a CVD (Chemical Vapor Deposition) method, the uppermost surface of the substrate 10 may be a material layer other than SiC.

As shown in FIG. 5B, a mask layer 56 having an opening 58 is formed on the substrate 10. The mask layer 56 is, for example, photoresist. The opening 58 is provided in the first region 60 and is not provided in the second region 62 between the first regions 60.

As shown in FIG. 5C, a recess 45 is formed on the upper surface of the substrate 10 in the first region 60 using the mask layer 56 as a mask. The upper surface of the substrate 10 in the first region 60 may be less flat than the upper surface of the substrate 10 in the second region 62. As a method of forming the recess 45, a dry process and a wet process can be used. As a dry process, the surface of the substrate 10 in the first region 60 is exposed to CF ₄ plasma, for example. The conditions for plasma formation are, for example, a high frequency power of 800 W and a processing time of 3 minutes. As the wet treatment, the surface of the substrate 10 in the first region 60 is immersed in, for example, an HCl (hydrochloric acid) solution. The processing time is, for example, 5 minutes. Then, the mask layer 56 is removed. The surface of the substrate 10 of FIG. 5A may be cleaned after FIG. 5C and before FIG. 6A.

As shown in FIG. 6A, the graphene layer 12 is formed on the substrate 10 by the thermal sublimation method. The SiC substrate 10 is heat-treated at 1600° C. for 1 minute in Ar atmosphere. Thus, the graphene layer 12 having one atomic layer to two atomic layers and a thickness of 0.35 nm to 0.7 nm is formed on the substrate 10. As described above, by heat-treating the SiC, the Si atoms in the SiC substrate 10 are sublimated, and the C atoms are sp ₂ bonded to each other. As a result, the graphene layer 12 is formed of SiC.

The heat treatment atmosphere, heat treatment temperature, and heat treatment time in the thermal sublimation method can be appropriately set according to the film thickness and film quality of the graphene layer 12. For example, the heat treatment temperature can be set to 1600°C to 1800°C. Further, the heat treatment atmosphere may be a vacuum. In order to make the graphene layer 12 thin, heat treatment in an inert gas that slows the growth rate is preferable. For example, the CVD method can be used to form the graphene layer 12. In the first region 60, the atomic layers in the graphene layer 12 are stacked according to the depth of the recess 45. In the second region 62, the number of atomic layers in the graphene layer 12 is substantially constant.

As shown in FIG. 6B, an Al (aluminum) film 15 having a film thickness of 5 nm is formed on the graphene layer 12 by using a vapor deposition method. The Al film 15 can also be formed by using, for example, a sputtering method. As shown in FIG. 6C, the Al film 15 is exposed to the atmosphere for 24 hours, for example. As a result, the Al film 15 is naturally oxidized, and the aluminum oxide (Al ₂ O ₃ ) film 16 is formed on the graphene layer 12. As the film in contact with the graphene layer 12 of the gate insulating film 14, an aluminum oxide film obtained by oxidizing an Al film by a method other than natural oxidation, an aluminum oxide film formed by a method other than oxidation, or a film other than the aluminum oxide film is used. May be.

As shown in FIG. 6D, a photoresist 50 is applied on the aluminum oxide film 16. The photoresist 50 is exposed and developed. As a result, the photoresist 50 on the active region remains and the photoresist 50 on the non-active region is removed. For example, in the process of FIG. 6D, the aluminum oxide film 16 is removed by an alkaline developing solution used when developing the photoresist 50. Further, the graphene layer 12 is removed using the photoresist 50 as a mask. Oxygen plasma is used to remove the graphene layer 12. The conditions for removing the graphene layer 12 are a pressure of 4 Pa and a power of 200 W. Then, the photoresist 50 is removed.

As shown in FIG. 7A, a silicon oxide film 18 having a film thickness of 30 nm is formed on the substrate 10 by the CVD method so as to cover the aluminum oxide film 16. The silicon oxide film 18 is a film for thickening the gate insulating film 14. It is difficult to form a thick aluminum oxide film 16 having good film quality. On the other hand, the gate insulating film 14 is preferably thick in order to prevent the contact between the ohmic electrode 25 and the gate electrode 20. Therefore, the silicon oxide film 18 is formed on the aluminum oxide film 16. A film other than the silicon oxide film 18 may be used as such a film, but the silicon oxide film 18 is preferable as an insulating film having a small dielectric constant and easy to form.

As shown in FIG. 7B, the gate electrode 20 is formed on the silicon oxide film 18 by the vapor deposition method and the lift-off method. The gate electrode 20 is, for example, a Ti (titanium) film having a film thickness of 10 nm and a gold film having a film thickness of 100 nm from the gate insulating film 14 side. The gate electrode 20 may be formed by using, for example, a sputtering method. A film other than a gold film may be used as the gate electrode 20. From the viewpoint of suppressing the gate resistance, a material having a low resistivity is preferable.

As shown in FIG. 7C, the silicon oxide film 18 and the aluminum oxide film 16 are removed using a dry etching method. As a result, the gate insulating film 14 is formed from the aluminum oxide film 16 and the silicon oxide film 18.

As shown in FIG. 7D, the side surface of the silicon oxide film 18 is etched using a buffered hydrofluoric acid solution. At this time, the side surface of the aluminum oxide film 16 is also etched. As a result, the gate insulating film 14 becomes thinner than the gate electrode 20. In this way, the gate insulating film 14 and the gate electrode 20 have an eave shape. Thereby, when the ohmic electrode 25 including the source electrode 24 and the drain electrode 26 is formed, a short circuit between the ohmic electrode 25 and the gate electrode 20 can be suppressed.

As shown in FIG. 8A, a mask layer 52 is formed on the substrate 10. The mask layer 52 is, for example, a photoresist layer and has an opening 54 through which the surface of the graphene layer 12 is exposed.

As shown in FIG. 8B, an ohmic electrode 25 including a source electrode 24 and a drain electrode 26 is formed in a self-aligned manner with the gate electrode 20 by using a vapor deposition method. The ohmic electrode 25 is a nickel layer having a film thickness of 15 nm. The vapor deposition uses a planetary method. The mask layer 52 and the metal layer on the mask layer 52 are removed by a lift-off method. Accordingly, the ohmic electrode 25 can be formed so that the upper surface of the graphene layer 12 is not exposed from the space between the ohmic electrode 25 and the gate insulating film 14. The gate insulating film 14 is formed in an eave shape, and the gate insulating film 14 is thicker than the ohmic electrode 25. Thereby, the short circuit between the ohmic electrode 25 and the gate electrode 20 can be suppressed. The ohmic electrode 25 may include a gold layer on the nickel layer.

As shown in FIG. 8C, the pad 30 is formed on the source electrode 24 and the drain electrode 26 by using the vapor deposition method and the lift-off method. The pad 30 is a titanium film having a film thickness of 10 nm and a gold film having a film thickness of 100 nm from the source electrode 24 and drain electrode 26 sides. As a result, the FET of Example 1 is completed.

7B to 8C, the example in which the ohmic electrode 25 is formed after the gate electrode 20 is formed on the graphene layer 12 has been described. However, after the ohmic electrode 25 is formed on the graphene layer 12, the gate electrode 20 is formed. May be formed. Further, as in FIGS. 5B and 5C, the example in which the concave portion 45 is formed on the upper surface of the substrate 10 in the first region 60 has been described, but the convex portion may be formed in the first region 60. Moreover, you may form a convex part and a concave part in the 1st area|region 60.

According to Examples 1 and 2, the roughness of the upper surface of the substrate 10 in the first region 60 where the ohmic electrode 25 makes electrical contact with the graphene layer 12 (active layer) as shown in FIG. The roughness is larger than the roughness of the upper surface of the substrate 10 in the second region 62 in which the carriers travel in the graphene layer 12. As a result, as shown in FIG. 3, in the first region 60, the number of atomic layers 48 in the graphene layer 12 changes. This facilitates injection of carriers from the ohmic electrode 25 to the graphene layer 12. Therefore, the contact resistance between the ohmic electrode 25 and the graphene layer 12 can be reduced. On the other hand, when the number of atomic layers 48 changes in the second region 62 in which carriers travel, the state of the electron cloud of the atomic layers 48a changes. This reduces carrier mobility. Therefore, the upper surface of the substrate 10 in the second region 62 is flat. Accordingly, it is possible to suppress a decrease in carrier mobility of the graphene layer 12.

The roughness of the upper surface of the substrate 10 can be measured using, for example, the AFM method. As the roughness, for example, arithmetic mean roughness Ra can be used.

The value obtained by dividing the standard deviation of the number of stacked atomic layers in the graphene layer 12 in the first region 60 by the average value is the standard deviation of the number of stacked atomic layers in the graphene layer 12 in the second region 62 divided by the average value. It is larger than the value. That is, the first region 60 has a larger variation in the number of laminated atomic layers than the second region 62. Thereby, as described in FIG. 2, the contact resistance between the ohmic electrode 25 and the graphene layer 12 can be reduced. The number of atomic layers stacked in the graphene layer 12 can be measured by a TEM image, for example, as shown in FIGS. 4A to 4C.

Although the graphene layer 12 is described as an example of the active layer, the graphene layer 12 may be a transition metal chalcogenite layer. The transition metal chalcogenite is, for example, MoS, MoS ₂ , MoSe or MoSe ₂ . The transition metal chalcogenite layer has a structure in which one or more molecular layers are laminated, and has two-dimensional conductivity like the graphene layer. In the transition metal chalcogenite layer, the electron cloud also spreads in the plane direction, and it is difficult to inject and extract the electron from the ohmic electrode in the stacking direction to the transition metal chalcogenite layer. Similar to the graphene layer, if unevenness is present on the upper surface of the substrate 10, the state of the two-dimensionally spread electron cloud changes. Therefore, it becomes easy to inject and extract electrons from the ohmic electrode to the transition metal chalcogenite layer. This can reduce the contact resistance between the ohmic electrode and the transition metal chalcogenite layer.

When the active layer is the graphene layer 12, the arithmetic average roughness Ra of the upper surface of the substrate 10 in the first region 60 is preferably 1 nm or more. Thereby, the contact resistance between the ohmic electrode 25 and the graphene layer 12 can be reduced. The arithmetic average roughness Ra of the upper surface of the substrate 10 is preferably 2 nm or more, more preferably 3 nm or more. The arithmetic average roughness Ra of the upper surface of the substrate 10 in the second region 62 is preferably less than 1 nm. Thereby, the deterioration of the carrier mobility of the graphene layer 12 in the second region 62 can be suppressed. The arithmetic average roughness Ra of the upper surface of the substrate 10 is more preferably 0.1 nm or less, and further preferably 3 nm or more.

A value obtained by dividing the standard deviation of the number of stacked atomic layers in the graphene layer 12 in the first region 60 by the average value is 0.01 or less, and the standard deviation of the atomic layers in the graphene layer 12 in the second region 62 is less than or equal to 0.01. Is preferably 0.1 or more. Thereby, the contact resistance between the ohmic electrode 25 and the graphene layer 12 can be reduced, and the mobility of carriers in the graphene layer 12 in the second region 62 can be improved.

As shown in FIG. 8C, the gate electrode 20 is provided on the graphene layer 12 in the second region 62. This can suppress a decrease in carrier mobility of the graphene layer 12 below the gate electrode 20.

Further, as shown in FIG. 5C, the upper surface of the substrate 10 in the first region 60 is made rougher than the upper surface of the substrate 10 in the second region 62. As shown in FIG. 6A, an active layer in which one or more atomic layers or molecular layers made of graphene or transition metal chalcogenite are stacked is formed on the substrate 10 in the first region 60 and the second region 62. As illustrated in FIG. 8C, the ohmic electrode 25 that is in electrical contact with the graphene layer 12 is formed in the first region 60 and not in the second region 62 on the graphene layer 12. As a result, the electronic device according to the first embodiment can be manufactured.

The substrate is a SiC substrate, and it is preferable that the graphene layer 12 is formed from carbon in the substrate 10 by heat-treating the substrate 10 on the SiC substrate 10. In this way, when the graphene layer 12 is formed, the number of atomic layers of the graphene layer 12 in the recess 45 changes. Therefore, as described with reference to FIG. 3, the contact resistance between the ohmic electrode 25 and the graphene layer 12 can be reduced.

Even when the graphene layer or the transition metal chalcogenite layer is formed by a method other than the thermal sublimation method, the state of the electron cloud spreading two-dimensionally changes due to the unevenness of the surface of the substrate 10 in the first region 60. This facilitates injection and extraction of electrons from the ohmic electrode 25 to the electron cloud. Therefore, the contact resistance between the ohmic electrode 25 and the graphene layer or the transition metal chalcogenite layer can be reduced.

The film thickness of the graphene layer 12 in the second region 62 is preferably 0.35 nm or more in order to have a film thickness of one atomic layer or more, and is preferably 2 nm or less in order to shorten the film formation time. Since the thickness of the graphene layer 12 is 10 atomic layers or less, 3.5 nm or less is preferable. The thickness of the nickel layer of the ohmic electrode 25 is preferably 2 nm or more and 50 nm or less. Although the FET has been described as an example of the electronic device, the first embodiment can be used for other transistors or electronic devices.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined not by the meanings described above but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

(Appendix 1)
A substrate, an active layer provided on the substrate and having one or more atomic layers or molecular layers made of graphene or a transition metal chalcogenite laminated thereon, and an active layer provided on the active layer and electrically contacting the active layer. A plurality of ohmic electrodes that are provided, wherein the roughness of the upper surface of the substrate in the first region where the plurality of ohmic electrodes make electrical contact with the active layer is within the active layer between the plurality of ohmic electrodes. An electronic device that is larger than the roughness of the upper surface of the substrate in the second region in which the carrier travels.
(Appendix 2)
The electronic device according to Appendix 1, wherein the substrate is a SiC substrate and the active layer is a graphene layer.
(Appendix 3)
2. The electronic device according to appendix 1, further comprising a gate electrode provided on the active layer in the second region.
(Appendix 4)
A step of making the upper surface of the substrate in the first region rougher than the upper surface of the substrate in the second region; and an atomic layer or a molecular layer made of graphene or a transition metal chalcogenite on the substrate in the first region and the second region. Or a step of forming a plurality of stacked active layers, and forming a plurality of ohmic electrodes on the active layer in electrical contact with the active layer in the first region and not in the second region. And a second step, wherein the second region is a region in which carriers travel in the active layer between the plurality of ohmic electrodes.
(Appendix 5)
5. The electronic device according to appendix 4, wherein the substrate is a SiC substrate, and the step of forming the atomic layer or the active layer includes a step of forming a graphene layer from carbon in the substrate by heat treating the substrate. Production method.
(Appendix 6)
A value obtained by dividing a standard deviation of the number of stacked atomic layers or molecular layers in the active layer in the first region by an average value is equal to a number of stacked layers of the atomic or molecular layers in the active layer in the second region. The electronic device according to Appendix 1, which is larger than a value obtained by dividing the standard deviation by the average value.
(Appendix 7)
The electronic device according to Appendix 1, wherein the active layer is a transition metal chalcogenide layer.
(Appendix 8)
The electronic device according to Appendix 2, wherein the ohmic electrode is a nickel layer.
(Appendix 9)
The method of manufacturing an electronic device according to appendix 5, wherein the roughness of the upper surface of the substrate in the first region is larger than the roughness of the upper surface of the substrate in the second region between the plurality of ohmic electrodes.
(Appendix 10)
5. The method for manufacturing an electronic device according to Appendix 4, including a step of forming a gate electrode on the active layer in the second region.

10 substrate 11 upper surface 12 graphene layer 14 gate insulating film 15 Al film 16 aluminum oxide film 18 silicon oxide film 20 gate electrode 24 source electrode 25 ohmic electrode 26 drain electrode 30 pad 40 carbon atom 42 σ orbit 44 σ bond 45 recess 46 ππ ^* Orbital 47 Electron cloud 48, 48a, 48b Atomic layer 49 Edge 50 Photoresist 52, 56 Mask layer 54, 58 Opening 60 First region 62 Second region 70 Arrow

Claims (5)

A substrate having an upper surface ,
An active layer provided on the upper surface of the substrate , in which one or more atomic layers or molecular layers made of graphene or transition metal chalcogenite are stacked;
A plurality of ohmic electrodes provided on the active layer and in electrical contact with the active layer;
Equipped with,
It said top surface of said substrate has a Oite plurality of recesses in a first region where the plurality of ohmic electrodes is electrically in contact with the active layer,
The atomic layer or the molecular layer is formed in the first region and the second region between the first regions in parallel and flat with the upper surface of the substrate, and is formed from graphene or transition metal chalcogenite in the plurality of recesses. An electronic device , wherein a plurality of atomic layers or molecular layers are further formed . The electronic device according to claim 1, wherein the substrate is a SiC substrate, and the active layer is a graphene layer. The electronic device according to claim 1, further comprising a gate electrode provided on the active layer in the second region. Forming a plurality of recesses on the upper surface of the substrate in the first region;
A plurality of atomic layers or molecular layers made of graphene or a transition metal chalcogenite is formed in the plurality of recesses, and the substrate is formed on the upper surface of the substrate in the first region and a second region between the first regions . Forming an active layer in which one or more atomic layers or molecular layers made of graphene or a transition metal chalcogenite are laminated in parallel and in a plane with the upper surface ;
Forming a plurality of ohmic electrodes on the active layer in electrical contact with the active layer in the first region and not in the second region;
Including,
The method of manufacturing an electronic device, wherein the second region is a region where carriers travel in the active layer between the plurality of ohmic electrodes. The electronic device according to claim 4, wherein the substrate is a SiC substrate, and the step of forming the atomic layer or the active layer includes a step of forming a graphene layer from carbon in the substrate by heat-treating the substrate. Manufacturing method.

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