JP6704298B2 - DC/DC converter and its control circuit, control method, and electronic device - Google Patents

Description

The present invention relates to a DC/DC converter.

In various electronic devices, a DC/DC converter that converts a DC voltage having a certain voltage value into a DC voltage having another voltage value is used. A multi-phase DC/DC converter is used to suppress the ripple of the input current of the DC/DC converter. FIG. 1 is a circuit diagram of a multi-phase buck DC/DC converter (simply referred to as a DC/DC converter) 900. The DC/DC converter 900 receives the DC input voltage V _IN on the input line 902 and generates the stepped-down output voltage V _OUT on the output line 904. The DC/DC converter 900 is composed of M channels (M is an integer of 2 or more). The DC/DC converter 900 has a switching transistor M1, a synchronous rectification transistor M2, and an inductor L1 for each channel, and has an output capacitor C1 common to all M channels. In this specification, channel numbers are indicated by subscripts as necessary.

The controller 910 includes an error amplifier 912 common to M channels, pulse modulators 914_1 to 914_M provided for each channel, and drivers 922_1 to 922_M provided for each channel. Resistors R11, R12 are, divide the output voltage _{V OUT} minute, generates a feedback signal _{V FB} corresponding to the output voltage _{V OUT.} The error amplifier 912 amplifies an error between the feedback signal V _FB and the reference voltage V _REF which is its target value, and generates an error signal V _ERR according to the error. The error signal V _ERR is supplied to the pulse modulators 914_1 to 914_M of a plurality of channels.

The pulse modulator 914 of each channel generates a pulse signal S _PWM having a duty ratio according to the error signal V _ERR .

When the DC/DC converter 900 of FIG. 1 is operated in multi-phase, the pulse modulators 914_1 to 914_M of a plurality of channels operate in different phases. For example, when operating in the M phase, the phase difference between the pulse modulators 914_1 to 914_M is 360°/M.

JP, 2013-126335, A

In the DC/DC converter 900 that operates normally, the current flows evenly through each of the inductors L1 of the plurality of channels. However, if an abnormality occurs in any of the channels, the current is biased to a certain channel, which may increase the load on the circuit element of that channel. Alternatively, the bias of the current increases the ripple of the input current, and the advantage of multiphase is lost.

Such a problem may occur not only in the step-down DC/DC converter but also in the step-up (Boost) DC/DC converter or the buck-boost converter.

The present invention has been made in view of the above problems, and one of the exemplary objects of a certain aspect thereof is to provide a multi-phase DC/DC converter capable of self-diagnosing abnormality and a control circuit thereof.

One aspect of the present invention relates to a control circuit of a multi-phase DC/DC converter having a plurality of channels. The control circuit amplifies the error between the feedback signal according to the output voltage of the DC/DC converter and its target value to generate an error signal, and a pulse signal to generate a pulse signal of a plurality of channels based on the error signal. Corresponding to the modulator and multiple channels, multiple drivers that drive the corresponding switching transistors based on the corresponding pulse signals, and the integrated value or the average value of the gate signals of the switching transistors of each of the multiple channels. An abnormality detection unit that detects an abnormality based on the plurality of first detection signals.

In a normally operating multi-phase DC/DC converter, the switching transistors of each channel perform switching at substantially the same duty ratio while maintaining a predetermined phase difference. Therefore, in the normal state, the first detection signal, which is the integrated value or the average value of the gate signals of the respective switching transistors, becomes substantially equal. On the contrary, if an abnormality occurs in any of the channels, the first detection signal has a voltage level different from that of the other channels. According to this aspect, the abnormality can be self-diagnosed by comparing the first detection signals of a plurality of channels.

The abnormality detection unit corresponds to a plurality of channels, and each of the plurality of first detection signal generation units generates a first detection signal according to an integral value or an average value of the gate signals of the corresponding switching transistors, and a plurality of channels. And a comparison unit that compares a plurality of first detection signals obtained with respect to.

The first detection signal generation unit may include an analog integrator. The first detection signal generation unit may include an analog low pass filter.

The abnormality detection unit may compare each first detection signal with at least two other first detection signals. This makes it possible to identify the abnormal channel.

The abnormality detection unit may compare all two combinations selected from the plurality of first detection signals. This enables highly accurate abnormality detection.

The DC/DC converter may be a synchronous rectification type. The abnormality detection unit may determine the channel in which the abnormality has occurred by comparing a plurality of second detection signals indicating the integrated value or the average value of the gate signals of the synchronous rectification transistors of each of the plurality of channels.
By monitoring the switching state of the synchronous rectification transistor in addition to the switching transistor, the accuracy of abnormality detection can be improved.

The abnormality detection unit may further include a plurality of second detection signal generation units corresponding to a plurality of channels, each of which generates a second detection signal according to an integral value or an average value of the gate signals of the corresponding synchronous rectification transistors. Good.

When an abnormality is determined in a certain channel, the operation of the abnormal channel may be stopped and the remaining normal channels may be continuously operated. As a result, the load can be continuously driven even in an abnormal state.

The phase difference may be changed according to the number of remaining normal channels. This can increase the stability of the system.

The control circuit may further include a notification unit that notifies the outside when it is determined to be abnormal.

The control circuit may be integrated on one semiconductor substrate. "Integrated integration" includes the case where all the components of the circuit are formed on the semiconductor substrate and the case where the main components of the circuit are integrated, and some of them are used for adjusting the circuit constants. A resistor or a capacitor may be provided outside the semiconductor substrate.

Another aspect of the present invention relates to a DC/DC converter. The DC/DC converter includes any of the control circuits described above.

Another aspect of the present invention relates to an electronic device. The electronic device may include the DC/DC converter described above.

It should be noted that any combination of the above constituent elements and constituent elements and expressions of the present invention that are mutually replaced among methods, devices, systems, etc. are also effective as an aspect of the present invention.

According to an aspect of the present invention, it is possible to detect an abnormality in the multi-phase converter.

It is a circuit diagram of a multi-phase step-down DC/DC converter. 3 is a circuit diagram of a DC/DC converter including the control circuit according to the embodiment. FIG. 3 is an operation waveform diagram of the DC/DC converter of FIG. 2 in a normal state. FIG. FIG. 3 is an operation waveform diagram when the DC/DC converter of FIG. 2 is abnormal. FIG. 5A is a block diagram showing a configuration example of the abnormality detection unit, and FIG. 5B is a circuit diagram showing a configuration example of the first comparison unit. It is a figure which shows an example of the electronic device provided with the DC/DC converter which concerns on embodiment. It is a circuit diagram of the abnormality detection part according to the fourth modification.

Hereinafter, the present invention will be described based on preferred embodiments with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing are denoted by the same reference numerals, and duplicated description will be omitted as appropriate. Further, the embodiments are merely examples and do not limit the invention, and all the features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In the present specification, "a state in which the member A is connected to the member B" means that the member A and the member B are physically directly connected, or that the member A and the member B are electrically connected. It also includes the case of being indirectly connected via another member that does not affect the state or impairs the function.

Similarly, the "state in which the member C is provided between the member A and the member B" means that the member A and the member C are directly connected to each other or the member B and the member C are directly connected to each other. It also includes the case of being indirectly connected via another member that does not affect the connection state or impairs the function.

Further, "the signal A (voltage, current) corresponds to the signal B (voltage, current)" means that the signal A has a correlation with the signal B. Specifically, (i) the signal A Is a signal B, (ii) the signal A is proportional to the signal B, (iii) the signal A is obtained by level-shifting the signal B, and (iv) the signal A is obtained by amplifying the signal B. (V) signal A obtained by inverting signal B means (vi) or any combination thereof. It is understood by those skilled in the art that the range of “according to” depends on the types of the signals A and B and the application.

FIG. 2 is a circuit diagram of the DC/DC converter 100 including the control circuit 200 according to the embodiment. Similar to FIG. 1, the DC/DC converter 100 is a multi-channel, multi-phase step-down converter (Buck Converter), receives a DC input voltage V _IN on an input line 102, steps it down, and outputs a predetermined target voltage V _{OUT. A} stabilized output voltage V _OUT is generated at _(REF) and is supplied to a load (not shown) connected to the output line 104.

The DC/DC converter 100 is composed of M channels (M is an integer of 2 or more). The number of channels M is arbitrary and may be determined according to the application of the DC/DC converter 100, such as 2 channels, 3 channels, 4 channels, 6 channels, 8 channels, 12 channels, 16 channels. In this embodiment, M=4.

The DC/DC converter 100 includes an output circuit 110 and a control circuit 200. The output circuit 110 has a switching transistor M1, a synchronous rectification transistor M2, and an inductor L1 for each channel, and has an output capacitor C1 and resistors R11 and R12 common to the M channels. In the present embodiment, the switching transistor M1, the synchronous rectification transistor M2, and the resistors R11 and R12 are integrated in the control circuit 200, but an external discrete element or chip component may be used.

The control circuit 200 is a functional IC (Integrated Circuit) integrated on a single semiconductor substrate. The control circuit 200 is provided with an input (VIN) terminal, a switching (LX) terminal, and a ground (GND) terminal for each channel, and a feedback (FB) terminal common to all channels. A voltage corresponding to the output voltage V _OUT is fed back to the FB terminal. The control circuit 200 drives the switching transistor M1 and the synchronous rectification transistor M2 of the plurality of channels CH1 to CHM so that the feedback signal V _FB corresponding to the output voltage V _OUT approaches the target value V _REF .

The control circuit 200 includes an error amplifier 202, a pulse modulation circuit 203, drivers 206_1 to 206_M, a main logic 210, and an abnormality detection unit 220. The error amplifier 202 amplifies an error between the feedback signal V _FB corresponding to the output voltage V _OUT and its target value V _REF , and generates an error signal V _ERR .

The pulse modulation circuit 203 _generates pulse signals S _{PWM1 to} S _PWMM for the plurality of channels CH1 to CHM based on the error signal V _ERR . For example, the pulse modulation circuit 203 includes pulse modulators 204_1 to 204_M corresponding to the plurality of channels CH1 to CHM. The pulse modulator 204_i of each channel generates a pulse signal S _PWMi having a duty ratio (or frequency) according to the error signal V _ERR . The configuration and modulation method of the pulse modulator 204 are not particularly limited, but for example, a peak current mode pulse width modulator can be used.

The plurality of drivers 206 correspond to a plurality of channels. The driver 206_i of each channel drives the corresponding switching transistor M1 and synchronous rectification transistor M2 according to the corresponding pulse signal S _PWMi .

The main logic 210 is a logic circuit that controls the control circuit 200 in an integrated manner, and controls the start-up sequence and the phase difference of a plurality of channels.

Abnormality detecting unit 220 receives the gate signal _HG 1 _{~HG M} multiple channels CH1~CHM respective switching transistor M1. The abnormality detection unit 220 determines whether or not there is an abnormality in the DC/DC converter 100 by comparing the first detection signals according to the integrated value or the average value of the gate signals HG of the respective channels.

Abnormality detecting unit 220 further receives a gate signal _LG 1 _{~LG M} multiple channels CH1~CHM each of the synchronous rectification transistor M2. The abnormality detection unit 220 determines the channel in which the abnormality has occurred by comparing the second detection signal corresponding to the integrated value or the average value of the gate signals LG of the respective channels. When detecting the abnormality, the abnormality detection unit 220 asserts (for example, high level) the abnormality detection signal S11. The main logic 210 executes a predetermined protection process in response to the assertion of the abnormality detection signal S11. The notification unit 212 may notify the external circuit of the occurrence of the abnormality in response to the assertion of the abnormality detection signal S11. The notification unit 212 may be a serial interface circuit connected to a bus such as I ² C via the pin 214. Alternatively, the notification unit 212 may change the electrical state of the pin 214 depending on whether there is an abnormality.

The above is the configuration of the DC/DC converter 100. Next, the operation will be described. FIG. 3 is an operation waveform diagram of the DC/DC converter 100 of FIG. 2 in a normal state.

In the normally operating multi-phase DC/DC converter 100, the pulse signals S _{PWM1 to SPMW4} have substantially the same duty ratio and a phase difference of 360°/4=90°.

In a normal state, the high-side switching transistor M1 of each channel should switch while maintaining a predetermined phase difference (90 degrees) at substantially the same duty ratio, and the integrated value of the gate signals HG of a plurality of channels. Alternatively, the first detection signals SA _{1 to} SA ₄ , which are average values, are substantially equal.

Similarly, the low-side synchronous rectification transistor M2 of each channel should be switched while maintaining a predetermined phase difference (90 degrees) with substantially the same duty ratio, and the integrated value or average of the gate signals LG of a plurality of channels. The values of the second detection signals SB _{1 to} SB ₄ are substantially equal.

FIG. 4 is an operation waveform diagram when the DC/DC converter 100 of FIG. 2 is abnormal. Here, it is assumed that an abnormality has occurred in the high side driver that drives the switching transistor M1 of the fourth channel CH4, and the gate signal HG4 maintains a high level. That is, the switching transistor M1 remains off and does not switch.

At this time, the first detection signal SA ₄ of the fourth channel CH4 has a voltage level different from that of the first detection signals SA _{1 to} SA ₃ of the other normal channels CH1 to CH3. Therefore, the abnormality detection unit 220 can detect that an abnormality has occurred in the fourth channel CH4 by comparing the plurality of first detection signals SA _{1 to} SA ₄ .

The above is the operation of the DC/DC converter 100. According to the DC/DC converter 100, various abnormalities caused by a failure of the pulse modulator 204, a failure of the high side driver of the driver 206, a failure of the low side driver, a disconnection of an inductor, a ground fault of a wiring, a power fault, etc. It can be detected by self-diagnosis.

The present invention extends to various devices and circuits understood as the block diagram and circuit diagram of FIG. 2 or derived from the above description, and is not limited to a specific configuration. Hereinafter, more specific configuration examples and examples will be described in order to help understanding of the essence of the invention and circuit operation and to clarify them, not to narrow the scope of the invention.

FIG. 5A is a block diagram showing a configuration example of the abnormality detection unit 220. The abnormality detection unit 220 includes a plurality of first detection signal generation units 222, a plurality of second detection signal generation units 224, a first comparison unit 226, and a second comparison unit 228. The first detection signal generation unit 222 includes an integrator or a low pass filter that integrates the gate signal HG. The same applies to the second detection signal generator 224.

The first comparison unit 226 compares the plurality of first detection signals SA _{1 to} SA ₄ and generates the first abnormality detection signal S12. The second comparison unit 228 compares the plurality of second detection signals SB _{1 to} SB ₄ and generates the second abnormality detection signal S13. The logic gate 230 generates a logical sum of the abnormality detection signals S12 and S13.

FIG. 5B is a circuit diagram showing a configuration example of the first comparing section 226. The first comparison unit 226 compares each first detection signal SA _i with at least two other first detection signals SA _i−1 and SA _i+1 . In the case of the M channel, SA ₀ =SA _M and SA _M+1 =SA ₁ .

The first comparison unit 226 can be configured by an array of voltage comparators 232. The number of voltage comparators 232 may be equal to the number of channels M. Each voltage comparator 232 asserts its output (for example, high level) when the difference (absolute value) between the two inputs exceeds a predetermined threshold value. The logic gate 234 outputs the logical sum of the outputs SC _{1 to} SC ₄ of the plurality of voltage comparators 232 as the abnormality detection signal S12. The second comparison unit 228 is configured similarly to the first comparison unit 226. The logic gate 230 in FIG. 5A and the logic gate 234 in FIG. 5B can be integrated into one.

The first comparison unit 226 may include M or more comparators. For example, the first comparison unit 226 may compare all two combinations that can be selected from the plurality of first detection signals SA _{1 to} SA ₄ . For the M detection signals _SA 1 -SA _M, 2 pieces of combination, M × (M-1) / 2 ways exist. Therefore, the first comparison unit 226 may include M×(M−1)/2 comparators. When M=4, 6 comparators may be used.

The main logic 210, comparison results of the plurality of first detection signal _SA 1 -SA _M based on the _SC 1 to SC _M, may identify the abnormal channel CHj. As described above, when each first detection signal SA _i is compared with at least two other first detection signals SA _i-1 and SA _i+1 , it is possible to identify the abnormal channel. That is, when SC _j , which is the comparison result of SA _j and SA _j−1 , and SC _j+1, which is the comparison result of SA _j and SA _j+1 , are asserted and the other comparison results SC are negate, the j-th It can be determined that an abnormality has occurred in the channel. The main logic 210 may stop the operation of the abnormal channel CHj and continuously operate the remaining normal channels. As a result, the load can be continuously driven even in an abnormal state.

At this time, the phase difference may be changed according to the number of remaining normal channels. For example, in the configuration of M=4 channels, if an abnormality is recognized in one channel, the remaining three channels may be controlled with a phase difference of 360 degrees/3=120 degrees. This can increase the stability of the system.

(Use)
The DC/DC converter 100 can be mounted on a battery-driven electronic device such as a tablet terminal, a smart phone, a notebook PC, and a digital camera. FIG. 6 is a diagram showing an example of an electronic device 700 including the DC/DC converter 100 according to the embodiment. The electronic device 700 includes a housing 702, a battery 704, a microprocessor 706, and the DC/DC converter 100. The DC/DC converter 100 receives the battery voltage V _BAT (=V _IN ) from the battery 704 at its input terminal and supplies the output voltage V _OUT to the microprocessor 706 connected to the output terminal.

The present invention has been described above based on the embodiment. This embodiment is merely an example, and it will be understood by those skilled in the art that various modifications can be made to the combinations of their respective constituent elements and processing processes, and that such modifications are also within the scope of the present invention. is there. Hereinafter, such modified examples will be described.

(First modification)
The DC/DC converter 100 may be a diode rectification type. The invention is not limited to the step-down converter, and the present invention can be applied to a step-up type or a step-up/down type. The high-side transistor may be an N-channel MOSFET. Further, as the switching transistor M1 and the synchronous rectification transistor M2, an IGBT or a bipolar transistor may be used instead of the MOSFET.

(Second modified example)
When it is sufficient to simply detect the abnormality, the first detection signals SA ₁ and SA ₂ , SA ₃ and SA ₄ ,..., SA _M-1 and SA _M may be compared. The same applies to the second detection signal SB.

(Third modification)
Alternatively, the average value of the first detection signals SA _{1 to} SA ₄ of all channels may be obtained by calculation, and each first detection signal SA _i may be compared with the average value.

(Fourth modification)
In the embodiment, the first detection signal generation unit 222 and the second detection signal generation unit 224 are provided for each channel, but the present invention is not limited to this. FIG. 7 is a circuit diagram of the abnormality detection unit 220 according to the fourth modification. In this modification, the number of first detection signal generation units 222 provided is smaller than the number M of channels (for example, two). The multiplexer 240 selects one of the plurality of gate signals HG _{1 to} HG _M , HG _i , and outputs the selected one to the first detection signal generation unit 222_1. The multiplexer 240 selects _one of the plurality of gate signals HG _{1 to} HG _M HG _j (j≠i) and outputs the selected one to the first detection signal generation unit 222_2. According to this modification, by controlling the multiplexers 240 and 242, it is possible to compare an arbitrary combination of a plurality of gate signals with a small amount of hardware.

(Fifth Modification)
The method of generating the multi-phase pulse signals S _{PWM1 to} S _PWMM is not particularly limited. The pulse modulation circuit 230 may generate one PWM signal and phase-shift it to generate a plurality of pulse signals S _{PWM1 to} S _PWMM .

Although the present invention has been described by using specific words and phrases based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments are defined in the claims. Many modifications and changes in arrangement are possible without departing from the concept of the present invention.

100... DC/DC converter, 102... Input line, 104... Output line, 110... Output circuit, M1... Switching transistor, M2... Synchronous rectification transistor, L1... Inductor, C1... Output capacitor, 200... Control circuit, 202... Error Amplifier, 204... Pulse modulator, 206... Driver, 210... Main logic, 220... Abnormality detection section, 222... First detection signal generation section, 224... Second detection signal generation section, 226... First comparison section, 228... Second comparison unit.

Claims (15)

A control circuit for a multi-phase DC/DC converter having a plurality of channels, comprising:
An error amplifier that amplifies an error between the feedback signal according to the output voltage of the DC/DC converter and its target value to generate an error signal,
A pulse modulation circuit for generating pulse signals of a plurality of channels based on the error signal;
Corresponding to a plurality of channels, a plurality of drivers that drive the corresponding switching transistors based on the corresponding pulse signals,
An abnormality detection unit that detects an abnormality based on a plurality of first detection signals corresponding to the integrated value or the average value of the gate signals of the switching transistors of each of the plurality of channels;
A control circuit comprising: The abnormality detection unit,
A plurality of first detection signal generation units that correspond to a plurality of channels and that generate the first detection signals according to the integrated value or average value of the gate signals of the corresponding switching transistors;
A comparison unit that compares a plurality of first detection signals obtained for the plurality of channels;
The control circuit according to claim 1, further comprising: The control circuit according to claim 2, wherein the first detection signal generation unit includes an analog integrator. The control circuit according to claim 2, wherein the first detection signal generation unit includes an analog low-pass filter. The control circuit according to claim 1, wherein the abnormality detection unit compares each first detection signal with at least two other first detection signals. The control circuit according to claim 1, wherein the abnormality detection unit compares all two combinations selected from a plurality of first detection signals. The DC/DC converter is a synchronous rectification type,
The abnormality detection unit,
7. The abnormal channel is determined by comparing a plurality of second detection signals according to the integrated value or the average value of the gate signals of the synchronous rectification transistors of each of the plurality of channels. The control circuit according to any one of 1. The abnormality detection unit,
7. A plurality of second detection signal generators corresponding to a plurality of channels, each of which includes a plurality of second detection signal generators that generate a second detection signal corresponding to an integral value or an average value of the gate signals of the corresponding synchronous rectification transistors. 7. The control circuit according to 7. 9. The control circuit according to claim 1, wherein when an abnormality is determined in a certain channel, the operation of the abnormal channel is stopped and the remaining normal channels are continuously operated. 10. The control circuit according to claim 9, wherein the phase difference is changed according to the number of remaining normal channels. The control circuit according to any one of claims 1 to 10, further comprising a notification unit that notifies the outside when an abnormality is determined. The control circuit according to claim 1, wherein the control circuit is integrated on one semiconductor substrate. A DC/DC converter comprising the control circuit according to claim 1. An electronic device comprising the DC/DC converter according to claim 13. A method for controlling a multi-phase DC/DC converter having a plurality of channels, comprising:
Amplifying an error between the feedback signal according to the output voltage of the DC/DC converter and its target value to generate an error signal;
Generating a pulse signal in each channel based on the error signal,
Driving a corresponding switching transistor in each channel based on the corresponding pulse signal;
Generating a first detection signal according to an integrated value or an average value of the gate signals of the corresponding switching transistors in each channel,
Determining a channel in which an abnormality has occurred by comparing a plurality of first detection signals obtained for the plurality of channels,
A control method comprising:

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