JP6701881B2 - Imaging device, infrared detector, and dark current correction method for infrared detector - Google Patents

Description

  The present disclosure relates to an imaging device, an infrared detection device, and a dark current correction method for an infrared detector.

  In the quantum infrared detector, the light receiving element generates an amount of current according to the intensity of incident infrared light, the read circuit stores the current in the capacitor as electric charge, and the amplifier amplifies the voltage corresponding to the accumulated electric charge. Output. Quantum infrared detectors generally require cooling during operation because the upper limit of the detector operating temperature is limited by the signal to noise ratio (S/N ratio). Typical noises include dark current flowing in the light receiving element when incident infrared light is zero, shot noise which is a quantum fluctuation of current, reset noise of charge storage capacitor, fixed pattern noise of CMOS which constitutes a readout circuit, and There is random telegraph signal noise, etc. Cooling the detector to a low temperature can significantly reduce dark current and reset noise in particular.

  In order to cool to a low temperature, a large-scale and high-power-consumption refrigerator is required, and the price becomes expensive, which is a great disadvantage. In order to develop an infrared sensor system that includes a compact, low power consumption, and low-priced quantum infrared detector, the noise generated should not be reduced by lowering the temperature, but the generated noise should be removed by signal processing. Is preferred. As one of such noise removal methods, there is known Correlated Double Sampling (CDS) effective for removing reset noise that rapidly increases at high temperatures. In the CDS, first, the charge storage capacitor is reset, and then the read voltage corresponding to the voltage of the charge storage capacitor including reset noise is held in the first capacitor. After that, the charge storage capacitor is discharged by the current of the light receiving element, and then the read voltage corresponding to the voltage of the charge storage capacitor including the reset noise and the voltage change due to the discharge is held in the second capacitor. By taking the difference between the voltage of the first capacitor and the voltage of the second capacitor, the reset noise included in both voltages can be canceled and the current of the light receiving element can be detected. Further, by taking the difference by the CDS, it is possible to reduce the fixed pattern noise unique to each read circuit.

  When the temperature rises, the dark current of the light receiving element also sharply increases. In order to correct the dark current, it is necessary to collect data in which only the dark current is measured for each pixel. In order to create a state in which only a dark current flows through the light receiving element without the incidence of infrared rays, the pixel array of the light receiving element is blocked from the outside by a mechanical shutter that is sufficiently cooled.

  Conventionally, it is not easy to correct the dark current by the CDS, and it is common to correct the dark current after the CDS. This is because it is not easy to store the dark current for each pixel in a non-volatile manner by a simple mechanism in the circuit at the previous stage of the CDS. Therefore, in order to correct the dark current by the CDS, the infrared ray blocking operation by the shutter is performed. Is required to be executed for each video frame. However, if the dark current is acquired every frame, the dark current measurement requires the same amount of time as the photocurrent integration time, resulting in a decrease in operating speed. Further, it is not easy to maintain such a high-speed mechanical shutter opening/closing operation without problems for a long period of time, which leads to shortening the life of the infrared detector due to shutter failure.

  For the output signal of the pixel array of the infrared detector, it is necessary to perform processing for correcting variations in sensitivity and non-linearity of each light receiving element. When the dark current is corrected after CDS, the dark current In addition to the correction, these correction processes will be performed. If the pixel array has a high resolution and the number of pixels is large, and the configuration is such that the dark current correction is executed, the correction data and the amount of correction calculation required in a series of correction processes increase, resulting in a decrease in operating speed and system area. Will increase.

JP-A-6-86174 JP, 2010-278143, A JP-A-6-334165 JP-A-11-39858

  In view of the above, there is a demand for an imaging device that stores a dark current in a nonvolatile manner for each pixel and corrects the dark current by the CDS.

  The imaging device includes a pixel array including a light receiving element provided for each pixel for detecting infrared rays, and a bipolar resistance change type memory element provided for each pixel, and a dark current flowing through the light receiving element. An amount of which can be stored in the resistance change type memory element, and a first signal reflecting the amount of read current flowing in the resistance change type memory and a second signal reflecting the amount of current flowing in the light receiving element at the time of imaging. A read circuit for outputting and a difference circuit for obtaining a difference between the first signal and the second signal are included.

  According to at least one embodiment, the imaging device can non-volatilely store the dark current for each pixel and perform the dark current correction by the CDS.

It is a figure which shows an example of a structure of an infrared detection device. It is a figure which shows an example of the voltage-current characteristic which a bipolar resistance change type memory element shows. It is a figure which shows the outline|summary of the correction process in the infrared detection apparatus shown in FIG. It is a figure which shows an example of a structure of a pixel array and a read-out circuit. It is a figure which shows an example of a structure of a read-out circuit. 6 is a flowchart showing an example of operations of the infrared detection device shown in FIG. 1 and the circuit shown in FIG. 5. It is a figure which shows an example of a structure of a resistance change type memory element. It is a figure for demonstrating the circuit structure at the time of producing|generating the electric current of the magnitude|size 1 times the input current by a current mirror circuit. It is a figure for demonstrating the circuit structure at the time of producing|generating the electric current of the magnitude|size of the input current m times by a current mirror circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram showing an example of the configuration of an infrared detection device. The infrared detection device 10 shown in FIG. 1 includes an optical system 11, an infrared detector 12, a correction signal processing unit 13, a display recording unit 14, a cooler 15, a control unit 16, and a control unit 17. The infrared detector 12 includes a shutter 21, a pixel array 22, a readout circuit 23, and a temperature sensor 24.

  The optical system 11 forms incident light on the imaging surface. The pixel array 22 is provided on the image pickup surface and picks up an infrared image based on incident light. The shutter 21 is, for example, a mechanical shutter that can be opened and closed, and allows the incident light to pass when it is opened and blocks the incident light when it is blocked. The pixel array 22 includes a plurality of light receiving elements arranged in a matrix vertically and horizontally to detect infrared rays. The light receiving element has a characteristic that the electric resistance value changes according to the intensity of incident light (incident infrared light). By applying a bias voltage to the light receiving element irradiated with the incident light, an amount of current corresponding to the intensity of the incident light flows through the light receiving element. A plurality of light receiving elements are provided in a one-to-one correspondence with a plurality of pixels, and image pickup data by each light receiving element becomes pixel data of each pixel.

  The readout circuit 23 includes a plurality of pixel readout circuits provided in a one-to-one correspondence with the plurality of light receiving elements, and a CDS circuit provided for each column of the pixel array 22 (see FIG. 5). The pixel readout circuit converts a current flowing through the light receiving element into a voltage, amplifies the voltage, and outputs the amplified voltage to the CDS circuit. The CDS circuit performs correlated double sampling on the output voltage from the read circuit.

  The read circuit 23 further includes a bipolar resistance change memory element provided for each pixel. That is, each pixel readout circuit includes one resistance change type memory element. The resistance change type memory element includes a resistance change material, an upper metal electrode, and a lower metal electrode, and the resistance change material is arranged so as to be sandwiched between the upper metal electrode and the lower metal electrode. In the bipolar resistance change type memory element, transition metal oxides such as TaOx, HfOx, TiOx, WOx, CoOx and MoOx, those obtained by stacking these transition metal oxides, or the oxygen content of these transition metal oxides are What is changed in the film is used as the resistance change material.

  FIG. 2 is a diagram showing an example of voltage-current characteristics exhibited by a bipolar resistance change memory element. For explanation, a linear resistance is assumed. In FIG. 2, the horizontal axis represents the voltage applied to the resistance variable memory element, and the vertical axis represents the current flowing in the resistance variable memory element. The resistance change type memory element has a high resistance state SH and a low resistance state SL. The resistance change type memory element in the high resistance state SH exhibits a relatively high constant resistance value. The resistance change type memory element in the low resistance state SL exhibits a relatively low constant resistance value.

  When a voltage of the first predetermined voltage value V1 or more is applied to the resistance change type memory element in the high resistance state SH in the first direction, the resistance change type memory element causes the resistance change type memory element to show the state transition T1. Transition to the low resistance state SL. At this time, the amount of current I1 flowing through the resistance change type memory element when the state transition T1 is caused determines the resistance value of the low resistance state SL after the transition. Specifically, the resistance change type memory element is set to the low resistance state SL having a resistance value (=V1/I1) determined by the applied voltage V1 and the current amount I1 at the time of transition. The current amount I1 is called a compliance current, and can be set to an arbitrary value by adjusting the gate voltage of the selection transistor.

  When the voltage of the second predetermined voltage value V2 or more is applied to the resistance change type memory element in the low resistance state SL in the second direction opposite to the first direction, the resistance change type memory element becomes low. The resistance state SL transits to the high resistance state SH. The resistance change type memory element in the high resistance state SH does not transition to the low resistance state SL unless a voltage equal to or higher than the first predetermined voltage value V1 is applied in the first direction. Further, the resistance change type memory element in the low resistance state SL does not transition to the high resistance state SH unless a voltage of the second predetermined voltage value V2 or more is applied in the second direction.

  For the resistance change type memory element that is in the high resistance state SH as the reset state, a current of the amount of the current flowing through the light receiving element when the shutter 21 is closed is passed in the first direction. At this time, the SH resistance is set so that the voltage applied to the resistance change type memory exceeds the first predetermined voltage V1. As a result, the resistance change type memory element can be transited to the low resistance state SL, and the resistance change type memory element can store the dark current of the light receiving element. After that, when the first predetermined voltage V1 in the first direction is applied to the resistance change type memory element in the low resistance state SL, the same amount of stored dark current flows through the resistance change type memory element. It will be.

  Returning to FIG. 1, the pixel read circuit of the read circuit 23 causes the first signal reflecting the read current amount (stored dark current) flowing in the resistance change type memory and the current amount (dark region) flowing in the light receiving element when the shutter 21 is opened. The second signal reflecting the sum of the current and the photocurrent) is output. That is, the pixel readout circuit outputs a first signal including a dark current component and a second signal including a dark current component and a photocurrent component. Further, the CDS circuit of the read circuit 23 determines the difference between the first signal and the second signal. More specifically, the CDS circuit may perform correlated double sampling on the first signal and the second signal. This makes it possible to remove the influence of dark current from the pixel signal.

  The signal of each pixel obtained by the CDS circuit performing the correlated double sampling is supplied to the correction signal processing unit 13 as an output signal of the infrared detector 12. The correction signal processing unit 13 generates corrected image pickup data by performing a process of correcting variations in sensitivity and non-linearity of each light receiving element on the output signal of the infrared detector 12. The corrected imaging data output from the correction signal processing unit 13 is supplied to the display recording unit 14 and displayed as a captured image on the display unit of the display recording unit 14 or stored in the recording unit of the display recording unit 14. To do.

  The control unit 16 controls the optical system 11, the infrared detector 12, and the cooler 15. The control unit 16 opens and closes the shutter 21 at a predetermined timing to enable dark current measurement and imaging data measurement by the pixel array 22 and the readout circuit 23. The control unit 16 may operate to keep the temperature of the infrared detector 12 constant by controlling the operation of the cooler 15 based on the temperature detected by the temperature sensor 24. The control unit 16 controls the shutter 21, the pixel array 22, and the readout circuit 23 based on the temperature detected by the temperature sensor 24 to measure the dark current and change the resistance change type memory element when the temperature changes. May operate to store The temperature sensor 24 detects the temperature of the infrared detector 12, more preferably the temperature of the pixel array 22.

  FIG. 3 is a diagram showing an outline of correction processing in the infrared detection device 10 shown in FIG. The CDS processing 30 shown in FIG. 3 is executed by the CDS circuit of the read circuit 23. In order to correct the dark current by the CDS processing 30, as described above, the bipolar resistance change type memory element provided for each pixel of the infrared detector has a current amount flowing in the light receiving element when the shutter 21 is shut off. Is stored.

  The first signal 31 that is an input to the CDS processing 30 is a signal that reflects noise caused by the read circuit 23 and a dark current stored in the resistance change type memory element, that is, a noise component and a dark current component. Is a signal including. Here, the noise caused by the read circuit 23 includes reset noise and fixed pattern noise. The reset noise is a noise generated when the voltage of the charge storage capacitor of the pixel readout circuit is reset, and more specifically, a noise generated when the CMOS switch biased to the charge storage node is cut off. Charge injection, feedthrough, and switch thermal noise are the major sources of reset noise. The fixed pattern noise is noise generated due to variations in characteristics of various circuit elements and is a constant noise that does not change for each read operation by the read circuit 23.

  After the voltage of the charge storage capacitor is reset, a read current flowing in the resistance change type memory is caused to flow in the charge storage capacitor, so that the terminal voltage of the charge storage capacitor is changed according to the amount of the read current. A voltage corresponding to the inter-terminal voltage after the change is output as the first signal 31 from the pixel reading circuit of the reading circuit 23.

  The second signal 32 for the CDS processing 30 is a signal that reflects the noise caused by the readout circuit 23 and the imaging current (the sum of the dark current and the photocurrent) that flows in the light receiving element at the time of imaging, that is, the dark current component and the light. It is a signal including a current component. After the voltage of the charge storage capacitor is reset, the current at the time of imaging that flows in the light receiving element (that is, the current that flows in the light receiving element when the shutter 21 is opened) is made to flow in the charge storage capacitor. Change the voltage. A voltage according to the inter-terminal voltage after this change is output as the second signal 32 from the pixel readout circuit of the readout circuit 23.

  By taking the difference between the first signal 31 and the second signal 32 by the CDS processing 30, it is possible to generate an output signal from which reset noise, fixed pattern noise, and dark current components have been removed. That is, this output signal contains only the photocurrent component. Then, the sensitivity and non-linearity correction processing 33 is executed on the output signal. The sensitivity and nonlinearity correction processing 33 is executed by the correction signal processing unit 13 shown in FIG.

  FIG. 4 is a diagram showing an example of the configuration of the pixel array and the readout circuit. The pixel array circuit 41 includes a plurality of light receiving elements 43 arranged vertically and horizontally in a matrix. One light receiving element 43 corresponds to one pixel. The pixel array circuit 41 corresponds to the pixel array 22 of FIG.

  The pixel readout circuit array 42 and the CDS circuit 46 correspond to the readout circuit 23 in FIG. The pixel readout circuit array 42 includes a plurality of pixel readout circuits 44 arranged vertically and horizontally in a matrix. The plurality of pixel readout circuits 44 are provided in a one-to-one correspondence with the plurality of light receiving elements 43, and the corresponding pixel readout circuits 44 and the light receiving elements 43 are electrically connected to each other by the bump 45, which is representatively shown as one. It is connected to the. The bumps 45 are formed from two bumps per pixel in order to draw the upper and lower electrodes of the light receiving element 43 to the pixel readout circuit 44.

  The column of pixel readout circuits 44 arranged in the row direction (horizontal direction in the drawing) can be selected by asserting one of the plurality of row lines 48. The plurality of pixel readout circuits 44 in one selected row are electrically connected to the plurality of CDS circuits 46 in a one-to-one manner via a plurality of column lines 47 extending in the column direction (vertical direction in the drawing).

  The optical system 11 shown in FIG. 1 images incident infrared light on the surface of the pixel array circuit 41 on which the plurality of light receiving elements 43 are arranged. A current corresponding to the intensity of incident light flows through each light receiving element 43, and the current is supplied to the pixel readout circuit 44. The pixel readout circuit 44 converts the current from the light receiving element 43 into a voltage, further amplifies it, and supplies the amplified voltage to the CDS circuit 46 via the column line 47.

  FIG. 5 is a diagram showing an example of the configuration of the read circuit. As described above, the readout circuit 23 includes the pixel readout circuit and the CDS circuit. The pixel readout circuit 44 corresponding to one pixel shown in FIG. 5 includes MOS transistors 52 to 63, a resistance change type memory element 64, a charge storage capacitor 65, and switch circuits SW1 and SW2. The light receiving element 43 connected to the MOS transistor 52 is not a part of the pixel reading circuit 44, but is a part of the plurality of light receiving elements 43 (see FIG. 4) included in the pixel array 22. It is one corresponding light receiving element. The pixel read circuit 44 is connected to PMOS transistors 72 and 73, which are current mirror circuits for performing write current to the variable resistance memory element 64 and reading from the variable resistance memory element 64, and switch circuits SW3 and SW4. ing. Further, the pixel read circuit 44 is further connected to a write driver 71 for resetting the resistance change type memory element 64 to a high resistance state.

  The output signal of the pixel readout circuit 44 is supplied to the CDS circuit. In FIG. 5, the CDS circuit includes MOS transistors 82 and 83, capacitors 84 and 85, and a differential amplifier 86. The MOS transistor 81 is a load transistor and forms a source follower circuit for amplifying the output together with the MOS transistor 55.

  The control unit 16 shown in FIG. 1 controls the conduction/non-conduction state of each transistor and the conduction/non-conduction state of each switch circuit, whereby the dark current storing operation, the dark current reading operation, and the imaging current detection in the pixel reading circuit 44 are performed. Perform an action. By the dark current storage operation, the amount of dark current flowing through the light receiving element 43 is stored in the resistance change type memory element 64. By the dark current read operation, the charge storage capacitor 65 is discharged by causing the amount of read current flowing in the resistance change type memory element 64 to flow from the charge storage capacitor 65. Further, by the imaging current detection operation, the current flowing through the light receiving element 43 is caused to flow from the charge storage capacitor 65 to discharge the charge storage capacitor 65. Each operation will be described in more detail below.

  In any operation, the charge accumulation capacitor 65 may be reset to the reset voltage by first turning off the MOS transistors 52 and 53 and turning on the MOS transistor 54. The node between the channel end of the MOS transistor 54 and the channel end of the MOS transistor 55 is set to the reset potential. After that, the MOS transistor 54 is cut off, but at this time, the reset noise described above is generated, and the voltage stored in the charge storage capacitor 65 contains noise.

  In the dark current storage operation, the resistance change type memory element 64 is first reset to the high resistance state. In order to execute this reset operation, the MOS transistors 59 and 62 are rendered non-conductive, and the MOS transistors 61 and 63 are rendered conductive. In this state, the write driver 71 side is set to a sufficiently high potential and connected to the ground potential via the MOS transistor 61, whereby the resistance change type memory element 64 is reset to the high resistance state. After that, when the shutter 21 (see FIG. 1) is closed, the MOS transistors 52 and 53 are made conductive and non-conductive, respectively, and a dark current is caused to flow from the charge storage capacitor 65 via the light receiving element 43 and the MOS transistor 58.

  At this time, the switch circuits SW1 and SW2 are in a non-conducting state and a conducting state, respectively, as shown in the figure. Further, the switch circuits SW3 and SW4 are set in a non-conducting state and a conducting state, respectively, as shown in the figure. Further, the MOS transistors 59, 60, and 62 are made conductive, and the MOS transistors 61 and 63 are made nonconductive. Due to the function of the current mirror circuit, the same amount of current as the dark current flowing through the MOS transistor 58 flows through the MOS transistor 57, and further, the same amount of current as the current flowing through the MOS transistor 57 flows through the resistance change type memory element 64. At this time, a sufficient voltage is applied to the resistance change type memory element 64, and the resistance change type memory element 64 is set to a low resistance state for storing the amount of dark current.

  In the dark current read operation, the switch circuits SW1 and SW2 are set to the conducting state and the non-conducting state, respectively, contrary to the illustrated state. Further, the switch circuits SW3 and SW4 are set in a conductive state and a non-conductive state, respectively, opposite to the illustrated state. Further, the MOS transistors 59, 60, and 62 are made conductive, and the MOS transistors 61 and 63 are made nonconductive. Further, the MOS transistors 52 and 53 are made non-conductive and conductive, respectively. In this state, the voltage applied to the resistance change type memory element 64 becomes the same voltage as that at the time of writing, and the same amount of read current as the stored dark current flows through the resistance change type memory element 64.

  Due to the function of the current mirror circuit, the same amount of current as the read dark current flows through the MOS transistor 57, and further, the same amount of current that flows through the MOS transistor 57 flows through the MOS transistor 58. As a result, the same amount of current as the dark current flows from the charge storage capacitor 65 via the MOS transistors 53 and 58, and the voltage value of the charge storage capacitor 65 shows a voltage change according to the amount of dark current. By supplying a current for the same time as during image pickup, the voltage value of the charge storage capacitor 65 is set to a voltage value indicating the same voltage drop as the voltage drop due to the dark current during image pickup.

  After that, the row selection MOS transistor 56 is made conductive, and the MOS transistors 81, 82, and 83 are made conductive, conductive, and non-conductive, respectively, so that a voltage (amplified voltage) corresponding to the voltage of the charge storage capacitor 65 is obtained. It can be held in the capacitor 84.

  In the imaging current detection operation, the switch circuits SW1 and SW2 are in the non-conducting state and the conducting state as illustrated. Further, all the MOS transistors 59, 60, 61 and 63 are made non-conductive. Further, the MOS transistors 52 and 53 are made conductive and non-conductive, respectively. In this state, when the shutter 21 (see FIG. 1) is open, the imaging current (photocurrent+dark current) is passed from the charge storage capacitor 65 via the light receiving element 43 and the MOS transistor 58. As a result, the voltage value of the charge storage capacitor 65 shows a voltage change according to the amount of the imaging current. By supplying a current for a predetermined time, the voltage value of the charge storage capacitor 65 is set to a voltage value showing a voltage drop according to the magnitude of the imaging current.

  After that, the row selection MOS transistor 56 is made conductive, and the MOS transistors 81, 82, and 83 are made conductive, nonconductive, and conductive, respectively, so that a voltage (amplified voltage) corresponding to the voltage of the charge storage capacitor 65 is generated. It can be held in the capacitor 85. The differential amplifier 86 outputs a voltage according to the difference voltage between the voltage of the capacitor 84 and the voltage of the voltage capacitor 85. The output voltage of the differential amplifier 86 becomes an imaging pixel voltage in which the influence of dark current is removed, that is, the dark current is corrected. Further, this output voltage becomes an imaging pixel voltage from which the effects of fixed pattern noise and reset noise are removed.

  Since the reset noise also includes a random component, even if two reset noises generated by two different reset operations are input to the correlated double sampling, the reset noise cannot be completely canceled out for this random component. Can not. That is, if different reset operations are executed for the dark current read operation and the imaging current detection operation, the reset noise cannot be canceled out completely. In consideration of this, for example, the charge storage capacitor 65 is used as a pair of capacitors, and the same reset operation is executed for these two capacitors, and then the two capacitors are separated from each other, and the dark current is supplied to each capacitor. The read operation and the imaging current detection operation may be executed. After that, the same reset noise can be canceled by obtaining the difference between the voltages (amplified voltages) corresponding to the voltages of these two capacitors. However, in this case, different circuit elements (capacitors having the same specifications but physically different) are used, and thus fixed pattern noise may be included.

  By storing the dark current data in the non-volatile memory provided in the read circuit as described above, it is possible to remove the dark current in addition to the reset noise and the fixed pattern noise by correlated double sampling. . With this configuration, it is not necessary to hold the dark current data externally to perform data correction, the size and weight of the device can be reduced, and high sensitivity and high speed operation can both be achieved.

  By providing a current mirror circuit or the like for the dark current storing operation and the dark current reading operation, the number of transistors mounted in the reading circuit 23 increases. However, the pixel area of the infrared detection device is determined by the wavelength of infrared rays, and even if it is small, it is about 10 μm×10 μm to 20 μm×20 μm. Therefore, the area of the light receiving surface of the infrared detector hardly increases due to the increase in the number of transistors.

  FIG. 6 is a flow chart showing an example of the operation of the infrared detection device shown in FIG. 1 and the circuit shown in FIG. The steps shown in FIG. 6 may be executed by the control unit 16 shown in FIG. 1 by appropriately using the shutter 21, the pixel array 22, the readout circuit 23, and the like.

  In step S11, the infrared detector is powered on. In step S12, the control unit 16 uses the infrared detection device for the first time, has a temperature change of a predetermined temperature difference or more as compared with the temperature at the time of storing the dark current last time, or from the time of storing the dark current last time. It is determined whether any of the conditions that a certain time or more has elapsed is satisfied. Regarding the temperature change, the control unit 16 stores the temperature detection value indicated by the temperature sensor 24 at the time of storing the dark current, and compares the current temperature value indicated by the temperature sensor 24 with the stored temperature detection value. The control unit 16 may make the determination.

  If any of the conditions in step S12 is satisfied, the control unit 16 closes the shutter 21 in step S13. In step S14, the control unit 16 controls the read circuit 23 to execute the dark current storage operation described above, and stores the dark current of the light receiving element 43 of each pixel in the resistance change type memory element 64 of each pixel. To do. At this time, since the voltage of the charge storage capacitor 65 is a voltage reflecting the dark current, the amplified voltage corresponding to the voltage of the charge storage capacitor 65 obtained by the dark current storage operation is supplied to one of the CDS circuits. It may be held in a capacitor (eg capacitor 84 in FIG. 5).

  In step S15, the control unit 16 opens the shutter 21. Thereafter, in step S17, the control unit 16 executes the above-described imaging current detection operation, reflects the sum of the photocurrent and the dark current in the voltage of the charge storage capacitor 65, and outputs the amplified voltage corresponding to the voltage to the other side of the CDS circuit. Of the capacitor (for example, the capacitor 85 of FIG. 5). In step S18, the control unit 16 executes correlated double sampling using the CDS circuit.

  When none of the conditions in step S12 are satisfied, in step S16, the control unit 16 executes the dark current reading operation described above. That is, the control unit 16 reflects the dark current read from the resistance change type memory element 64 on the voltage of the charge storage capacitor 65, and the amplified voltage corresponding to the voltage is applied to the other capacitor of the CDS circuit (for example, the capacitor 85 of FIG. 5). ) Hold. After that, the imaging current detection operation of step S17 and the correlated double sampling operation of step S18 are executed.

  After performing the correlated double sampling in step S18, the control procedure returns to step S12 to capture the next video frame, and the subsequent processing is repeated. In step S19, a series of video data is output. Note that the data output timing in step S19 may be changed as appropriate, and if there is not a memory for storing a series of video data, the video data for each frame or the video data for each row is sequentially output. You can do it like this.

  As described above, the control unit 16 performs the operation of storing the amount of dark current flowing in the light receiving element 43 in the resistance change type memory element 64 once in a plurality of video frames, for example, one of the conditions in step S12 is satisfied. Sometimes it is executed intermittently. In the case of a cooled quantum infrared detector, the operating temperature is ideally constant, and dark current data may be acquired at a fixed operating temperature before shipment. However, in actuality, due to changes in the surrounding environment and changes in the refrigerator performance over time, the actual operating environment temperature changes slightly from moment to moment. The infrared detector 10 shown in FIG. 1 having the read circuit 23 shown in FIG. Therefore, it is possible to deal flexibly.

  FIG. 7 is a diagram showing an example of the configuration of the resistance change type memory element. FIG. 7 is a diagram schematically showing a part of a semiconductor device on which the read circuit 23 is mounted. A part of the semiconductor device shown in FIG. 7 includes a semiconductor substrate 101, a source region diffusion layer 102, a drain region diffusion layer 103, a gate electrode 104, and four metal wirings M1 to M4. In the infrared detector 12 disclosed in the present application, the resistance change type memory element 64 is mounted by being mixedly mounted on the read circuit 23. That is, the resistance change type memory element 64 is mounted so as to be embedded between the metal wiring layers of the read circuit 23.

  Specifically, in the part of the read circuit 23 shown in FIG. 7, the resistance change type memory element includes a resistance change material layer 105, an upper metal electrode 106, and a lower metal electrode 107. The upper metal electrode 106 is directly connected to, for example, the uppermost metal wiring M4, and the lower metal electrode 107 is connected to, for example, the metal wiring M3 via a dedicated via 108.

  The element area of the resistance change type memory element 64 is sufficiently smaller than the area of the light receiving element 43, and further, the resistance change type memory element 64 is mixedly mounted in the metal wiring of the semiconductor device of the read circuit 23 as described above. be able to. Therefore, by providing the resistance change type memory element 64 for each pixel, the pixel area of the infrared detector 12 hardly increases.

  FIG. 8 is a diagram for explaining the circuit configuration in the case where a current having a magnitude that is one time the input current is generated by the current mirror circuit. FIG. 8A shows a schematic plan view of a MOS transistor used in the current mirror circuit as seen from above. The MOS transistor includes a source region diffusion layer 111, a drain region diffusion layer 112, and a gate electrode 110. The transistor width of this MOS transistor is Tw.

  FIG. 8B shows an example of the structure of a current mirror circuit which generates a current having a magnitude one time the input current. The current mirror circuit shown in FIG. 8B includes MOS transistors 113 and 114 and a resistance change type memory element 115. Each of the MOS transistors 113 and 114 is a transistor of the same size as the MOS transistor shown in FIG. 8A and has the same transistor width Tw. By passing the current of the amount stored in the resistance change type memory element 115 through the MOS transistor 113, the same amount of current as that can be passed through the MOS transistor 114.

  FIG. 9 is a diagram for explaining a circuit configuration in the case where a current having a magnitude m times the input current is generated by the current mirror circuit. FIG. 9A is a schematic plan view of a MOS transistor used in a current mirror circuit as seen from above. This MOS transistor includes a plurality of source region diffusion layers 121, a plurality of drain region diffusion layers 122, and a plurality of gate electrodes 120. By connecting the source region diffusion layers to each other and connecting the drain diffusion layers to each other, it is possible to realize a circuit configuration in which a plurality of MOS transistors having the same transistor width are connected in parallel. It is assumed that the width of each of the plurality of MOS transistors connected in parallel with each other is Tw.

  FIG. 9B illustrates an example of a structure of a current mirror circuit which generates a current whose magnitude is m times the input current. The current mirror circuit shown in FIG. 9B includes MOS transistors 123 and 124 and a resistance change type memory element 125. The MOS transistor 123 is, for example, a transistor having the same size as the MOS transistor shown in FIG. 8A and has a transistor width Tw. The MOS transistor 124 is the MOS transistor shown in FIG. 9A, and a plurality of m MOS transistors each having a transistor width Tw are connected in parallel. Therefore, the MOS transistor 124 effectively has a transistor width of mTw. By supplying the current amount of the current stored in the resistance change type memory element 125 to the MOS transistor 123, it is possible to supply the MOS transistor 124 with a current amount that is m times the current amount.

  In the read circuit 23 shown in FIG. 5 described above, for example, the PMOS transistor 73 may be configured as shown in FIG. In the dark current storage operation, the transistor width of the PMOS transistor 73 is made equal to the transistor width of the PMOS transistor 72 by using only the outermost gate electrode of the gate electrodes 120 shown in FIG. 9A, for example. And On the other hand, in the dark current reading operation, by using all the gate electrodes, the transistor width of the PMOS transistor 73 can be made m times the transistor width of the PMOS transistor 72. As a result, the current mirror circuit generates a current that is a constant multiple of the read current that flows in the resistance change type memory element 64, and the voltage corresponding to the terminal voltage of the charge storage capacitor 65 that is changed by this constant multiple current is It is possible to output from the read circuit 44. The PMOS transistors 72 and 73 are provided outside the pixel readout circuit 44 corresponding to each pixel of the pixel array 22, and the pixel area is increased even if the configuration is switched as described above between storage and readout. There is no.

  Although the present invention has been described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the claims.

10 infrared detector 11 optical system 12 infrared detector 13 correction signal processor 14 display recorder 15 cooler 16 controller 17 controller 21 shutter 22 pixel array 23 readout circuit 24 temperature sensor

Claims (9)

A pixel array including a light-receiving element for detecting infrared rays provided for each pixel,
A bipolar resistance change memory element provided for each pixel is included, and the amount of dark current flowing through the light receiving element can be stored in the resistance change memory element, and read out flowing through the resistance change memory element. A read circuit that outputs a first signal that reflects the amount of current and a second signal that reflects the amount of current that flows in the light-receiving element during imaging.
A difference circuit for obtaining a difference between the first signal and the second signal;
An imaging device including.   The read circuit further includes a charge storage capacitor provided for each pixel, and between the terminals of the charge storage capacitor changed according to a read current flowing in the resistance change type memory element after resetting the voltage of the charge storage capacitor. A voltage corresponding to the voltage is output as the first signal, and a voltage corresponding to the terminal voltage of the charge storage capacitor, which is changed by the current at the time of imaging that flows in the light receiving element after the voltage of the charge storage capacitor is reset, The imaging device according to claim 1, wherein the imaging device outputs the second signal.   The differential circuit is a correlated double sampling circuit that performs correlated double sampling on the first signal and the second signal sequentially output from the read circuit. Imaging device.   The image pickup device according to claim 1, wherein the resistance change type memory element is mixedly mounted in a wiring layer of the read circuit.   The control circuit further includes a control circuit for controlling the operations of the pixel array and the readout circuit, wherein the control circuit stores an operation of storing the amount of dark current flowing in the light receiving element in the resistance change type memory element into a plurality of video frames. The image pickup apparatus according to claim 1, wherein the read circuit is executed intermittently once and the read circuit outputs the first signal and the second signal in each video frame. The read circuit applies a voltage to the resistance change type memory element in a first direction to increase the resistance, and then a second direction opposite to the first direction is applied to the resistance change type memory element. of by low resistance by applying a voltage in the direction, before SL imaging apparatus according to claim 1 to 5 any one claim storing the current amount of the dark current flowing to the light-receiving element to the resistance variable memory device.   The read circuit further includes a current mirror circuit that generates a current that is a constant multiple of the read current that flows in the resistance change type memory element, and a voltage that corresponds to the terminal voltage of the charge storage capacitor that is changed by the constant multiple current. The image pickup apparatus according to claim 2, wherein is output as the first signal. A cooler,
An optical system that forms incident light on the imaging surface,
A shutter that blocks the incident light,
A pixel array provided on the image pickup surface, including a light receiving element for detecting infrared rays provided for each pixel;
A bipolar variable resistance memory element provided for each pixel is included, and the amount of current flowing through the light receiving element when the shutter is shut off can be stored in the variable resistance memory element. A read circuit that outputs a first signal that reflects the amount of read current that flows and a second signal that reflects the amount of current that flows in the light receiving element when the shutter is opened;
A difference circuit for obtaining a difference between the first signal and the second signal;
Infrared detector including. A bipolar resistance change type memory element provided for each pixel of an infrared detector capable of blocking incident light by a shutter stores the amount of current flowing through the light receiving element when the shutter is blocked,
After resetting the voltage of the charge storage capacitor, the terminal voltage of the charge storage capacitor is changed according to the read current flowing in the resistance change type memory element to generate a first voltage,
After resetting the voltage of the charge storage capacitor, the inter-terminal voltage of the charge storage capacitor is changed by the current flowing in the light receiving element when the shutter is opened to generate the second voltage,
A method for correcting dark current of an infrared detector, comprising: each step of obtaining a difference between a voltage corresponding to the first voltage and a voltage corresponding to the second voltage.

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