JP6687837B2 - Data recording device and data recording method - Google Patents

Description

  The present invention relates to a data recording device and a data recording method.

  The data recording device collects data to be measured at the timing of a predetermined event and writes the collected data in a storage medium such as a memory. Then, the data in the memory is output at a predetermined timing, a predetermined analysis is performed on the output event data, and the event data is used for determining the state of the measurement target.

  Examples of the data recording device include a logic analyzer that traces and analyzes data output by a specific circuit in the integrated circuit device, and a data logger that continuously records sensor data in the IoT field.

  The data recording device is described in the following patent documents.

Japanese Patent Laid-Open No. 09-185531 JP, 10-40140, A JP, 2007-141072, A

  It is desirable for the data recording device to store a large amount of data in a small-capacity memory as little as possible. However, since the memory capacity is limited, the number of data that can be stored is limited. Although it is conceivable to compress and store the data, if the data to be measured changes at high speed, it will not be possible to store all the data if it takes time to compress the data.

  It is also possible to collect the measurement data in multiple times, but it is difficult to collect the data many times if the observed event rarely occurs. Furthermore, as the amount of collected data increases, it may be possible to dynamically execute memory management such as securing and freeing a memory area. However, if the event of memory management processing is not in time, , Can not be adopted.

  Therefore, an object of the first aspect of the embodiment is to provide a data recording device and a data recording method for recording event data in a memory having a limited capacity with as many bits as possible and as many as possible.

The first aspect of the present disclosure is
A memory for storing data,
An encoding unit that performs encoding to rearrange predetermined bits of event data to the first bit side of the most significant bit side or the least significant bit side to generate an event code,
In the first cycle, a plurality of first data having a bit string of a first bit width of the first bit side of the event code is sequentially written in the memory, and in a second cycle after the first cycle. , A plurality of second data having a bit string on the side of the first bit of the event code and having a bit width smaller than the first bit width of the plurality of first data already written in the memory. The data recording device has a memory controller that sequentially overwrites a storage area on the second bit side opposite to the first bit side.

  According to the first aspect, it is possible to record event data in a memory having a limited capacity with as many bits as possible.

It is a figure which shows the structure of the semiconductor device which has the data recording device of this Embodiment. It is a figure which shows an example of a measurement object circuit. It is a figure which shows the example of data recording by the data recording device in this implementation. It is a figure which shows the structure of the data recording device in this Embodiment. It is a figure which shows an example of the encoding of the event encoding part 14. It is a figure which shows the structure of a buffer memory. It is a flowchart figure which shows operation | movement of the counter unit 16. It is a figure which shows the structural example of a counter unit. It is a figure which shows the example of the address rewinding circuit of FIGS. It is a figure which shows the example of the address rewinding circuit of FIGS. FIG. 6 is a flowchart showing a writing process by the memory controller according to the first embodiment. FIG. 6 is a diagram showing a write process of cycles 0, 1, 2 in the first embodiment. FIG. 7 is a diagram showing a write process of cycle 3 in the first embodiment. FIG. 11 is a diagram showing a write process of cycle 4 in the first embodiment. FIG. 11 is a diagram showing a write process of cycle 4 in the first embodiment. It is a flowchart figure of the writing process of the event code | cord by the memory controller in 2nd Embodiment. It is a figure which shows the write-in process in the cycles 0, 1, 2 in 2nd Embodiment. It is a figure which shows the write-in process in the cycle 3 in 2nd Embodiment. It is a flowchart figure of the writing process of the event code | cord by the memory controller in 3rd Embodiment. It is a figure which shows the write-in process in the cycles 0, 1, 2 in 3rd Embodiment. It is a figure which shows the write-in process in the cycle 3 in 3rd Embodiment. It is a figure which shows the bit width of the event code memorize | stored in the buffer memory of 1st, 2nd, and 3rd embodiment, and the data number. It is a figure which shows the bit width of the event code memorize | stored in the buffer memory of 3rd Embodiment, and its data number. It is a flowchart figure of the program which produces | generates the map of a buffer memory. It is a flowchart figure of the program which produces | generates the map of a buffer memory. It is a figure which shows the data structure of a map.

  FIG. 1 is a diagram showing a configuration of a semiconductor device having the data recording device of the present embodiment. The semiconductor device 1 includes a measurement target circuit 2 and a data recording device 10 that records event data sequentially generated from the measurement target circuit. The data recording device 10 includes a data acquisition unit 11 that acquires event data sequentially generated from a measurement target circuit, a data buffer unit 12 that stores the acquired event data, and outputs the stored event data to the outside of the semiconductor device. It has a data output unit 13 for performing.

  The data output unit 13 outputs the event data to the receiving device 4 via the wired or wireless communication path 5. Then, the event data is analyzed. The data output unit 13 outputs event data by serial communication, for example.

  FIG. 2 is a diagram illustrating an example of the measurement target circuit. This example is an example of a microprocessor. The microprocessor has a processor (CPU) 6, a bus 7, a peripheral module 8, a memory 9 and the like. The processor 6 has a program counter PC, fetches an instruction corresponding to the address of the program counter PC from the memory 9, decodes the fetched instruction with a decoder (not shown), and an arithmetic circuit (not shown) executes the instruction. Alternatively, the arithmetic circuit causes the peripheral module 8 to execute a predetermined process.

  In such a microprocessor, the data recording device 10 collects the counter value (address) of the program counter and the data flowing on the bus as event data and stores it in the buffer memory, and the receiving device 4 stores the stored event data as data. It is extracted from the recording device 10 and used for analysis of operation.

  In the example of FIGS. 1 and 2, when the amount of data acquired from the measurement target circuit 2 is sufficiently larger than the communication band of the communication path 5, the data recording device 10 records the event data of the measurement target circuit and the reception device. It is difficult to output the event data to 4. As a result, if the capacity of the data buffer memory in the data buffer unit 12 is limited, it is expected that the data buffer memory will not be able to store all the event data and data will overflow.

  FIG. 3 is a diagram showing an example of data recording by the data recording device in the present embodiment. In the example of FIG. 3, the data recording device 10 is a data collection device in the IoT field. The data recording device 10 is, for example, a meteorological observation device or a road traffic survey device that acquires and records the observation target data. The data recording device 10 has a configuration similar to that of FIG. 1, and a data acquisition unit 11 that acquires event data output from an observation target, a data buffer unit 12 that stores event data, and outputs the event data. It has a data output unit 13. The data acquisition unit 11 has a sensor that detects event data of an observation target, and various event data is acquired via the sensor. The receiving device 4 and the communication medium 5 are the same as those in FIG.

  In the example of FIG. 3, the data recording device 10 continues to acquire and store the data of the monitoring target 3. However, if the capacity of the data buffer memory in the data buffer unit 12 is limited, if the bandwidth of the communication path 5 or the operation interval is limited, the data buffer memory cannot store all the event data and the data overflows. Will end up.

  As can be understood from the above example, the data recording device 10 is required to store all or as much event data as possible in the data buffer memory, and to store important data of each event data as much as possible.

  FIG. 4 is a diagram showing the configuration of the data recording device according to the present embodiment. The data recording apparatus of the present embodiment stores many bits of each event data in the memory when the buffer memory has a sufficient capacity, and sets the bits of each event data to a predetermined value as the cumulative number of event data increases. It is thinned according to the rule and stored in the memory with a short bit width. As a result, the data recording device stores more bits of each event data if the number of event data until the timing when the data output unit outputs the event data from the data buffer memory is small, and the data recording device stores the event data. If the number is large, the bit number of each event data is reduced and stored. As a result, it is possible to record the event data having the best effort bit width corresponding to the number of the event data.

  FIG. 4 shows the measurement target 3, the data recording device 10, the receiving device 4, and the communication path 5. As described above, the measurement target 3 is a measurement target circuit, weather conditions, traffic conditions, and the like.

  The data recording device 10 has a sampling unit 11 that collects various states of the measurement target 3. The sampling unit 11 corresponds to the data acquisition unit 11 of FIGS. The sampling unit 11 outputs the collected digital data as event data IV0-IV7 together with an event signal EVENT that notifies the occurrence of the event. The event data IV0 to IV7 are 8-bit data as an example. The sampling unit 11 is set with sampling timing conditions, such as sampling only when a specific signal value appears, or a sampling time zone or time interval, based on the sampling set value SP. The timing set value SP is externally input, for example.

  The data recording device 10 includes an event encoding unit 14 that encodes the event data IV0-IV7 input in synchronization with the event signal and outputs the encoded event code C0-C7. The event encoding unit 14 encodes the event data IV0-IV7 based on the encoding setting value CD and converts it into event codes C0-C7. Encoding means receiving n-bit input data, rearranging the data in bit units, and then outputting n-bit output data. The coding setting value CD is information that indicates a sorting rule. The coding setting value CD is set from the outside, for example. The encoding set value CD is set before the start of the data collection operation and is not changed during the data collection operation.

  FIG. 5 is a diagram showing an example of encoding of the event encoding unit 14. The event encoding unit 14 inputs the 8-bit event data IV0-IV7, and converts the lower bits IV3-IV0 of the event data into the upper bits C7-C4 of the event code based on the rearrangement rule of the encoding set value CD. , The upper bits IV7-IV4 of the event data are rearranged to the lower bits C3-C0 of the event code. Further, the event encoding unit 14 outputs an event signal EVENT.

  The event encoding unit 14 of FIG. 5 rearranges the bits of the event data IV0-IV7 having higher storage priority in the buffer memory 17 to the most significant bit (MSB) side. In response to such arrangement side rules, the memory controller 15 preferentially writes the MSB side bits of the event codes S0 to S7 in the buffer memory 17, as described later. That is, the memory controller 15 has a bit string on the MSB side of the event codes S0 to S7, and writes data of a smaller bit width in the buffer memory 17 correspondingly as the number of events increases. Therefore, as the number of events increases, the bit width of the event code written in the buffer memory becomes smaller, but the event recording can be continued.

  The event encoding unit 14 may rearrange bits of the event data having higher storage priority to the least significant bit (LSB) side. In that case, the memory controller 15 preferentially writes the LSB side bits of the event codes S0 to S7 into the buffer memory 17. The intention of the event encoding unit 14 is to rearrange bits according to priority, and the arrangement order may be ascending order, descending order, or another order rule, and is not limited to any one.

  In the following embodiment, an example will be described in which the event encoding unit 14 rearranges the bits of the event data having higher storage priority to the MSB side. Therefore, in the present embodiment, the coding setting value CD is a setting value indicating which bit of event data has a high storage priority, and the event coding unit 14 sets the bit specified by the coding setting value CD. To the MSB side.

  The data recording device 10 includes a buffer memory 17 that stores all bits or some bits of the event code, and a memory controller 15 that controls writing and reading to and from the buffer memory 17.

  Further, the data recording device 10 has a counter unit 16 for generating various control information indicating which bit of the event code is to be written in which bit position in the buffer memory 17 in the memory controller. In response to the event signal EVENT, the counter unit 16 generates control information as to which bit position of which address of the buffer memory 17 is to write a bit string of which bit width of the event code, and outputs the control information to the memory controller 15. The memory controller writes the event code in the buffer memory 17 based on the control information input from the counter unit.

  Then, the data recording device 10 has a data output unit 13 that reads out the event code written in the buffer memory 17 via the memory controller 15 and outputs the event code to the external receiving device 4.

  Next, the structure of the buffer memory 17 will be described, and then the operation and structure of the counter unit 16 and an example of the operation of writing the event code into the buffer memory by the memory controller 15 will be described.

  In the following description, the event data has a 1024 bit width (IV0-IV1023). Bits having a high storage priority in the event data are rearranged to the MSB side, and a bit string having a predetermined bit width on the MSB side of the event code is written in the buffer memory. Therefore, when the bit width of event data is 1024, the memory controller first writes all 1024 bits of the event code to the buffer memory, and as the value of the event ID increases, the upper half of the event code, A bit string with a bit width of 1/4 is written in the buffer memory.

  The bit width of the event data is constant during the data collection operation. Also, which data is being sampled is constant during operation. If you want to increase or decrease during operation, set the maximum length including all data you want to collect as the bit width. If it decreases during operation, it can be compensated with preset dummy data such as constants 0 and 1.

  FIG. 6 is a diagram showing the configuration of the buffer memory. Although the word width of the buffer memory is set to be the same as the number of bits of the event code (1024) for the sake of clarity, the present invention is not limited to this. When the word width of the actual memory (RAM: Random Access Memory) is smaller than the number of bits of the event code, RAM access may be performed in multiple times. The buffer memory stores 1024-bit wide data at addresses 0 to 63, respectively. In FIG. 6, bit positions obtained by dividing 1024 bits into 16 are shown in the horizontal direction, and 64 addresses 0 to 63 are shown in the vertical direction. The memory controller writes bit string data of a certain bit width on the MSB side of the event code into the buffer memory based on the address, the bit width of the event code to be written, and the start bit position to be written.

FIG. 7 is a flowchart showing the operation of the counter unit 16. The following constants are preset.
Bit width of buffer memory: RAM_WIDTH = 1024
Number of addresses (number of words): RAM_WORD = 64

Furthermore, the initial values of the counters and registers in the counter unit are the following values.
Number of divisions (or number of cycles): ndiv = 0
Number of events: nevent = 0
Number of rounds (number of laps): nround = 0
Address: addr = 0
Start bit position: sbit = 0
Bit width: width = RAM_WIDTH = 1024

  In FIG. 7, first, the counter unit is initialized (S10). That is, the division number ndiv, the event number nevent, the round number nround, the address addr, the start bit position sbit, and the bit width width in the counter unit are initialized to the above initial values. Then, if the stop determination condition is not satisfied (NO in S11), the processes S12-S21 subsequent thereto are performed. If the stop determination condition is satisfied (YES in S11), the process is stopped.

  Next, when the memory controller receives the event code from the event encoding unit (YES in S12), the counter unit 16 outputs the control value in the counter unit to the memory controller (S13). The control value is the above-mentioned address addr, the start bit position sbit, the bit width width and the like. As a result, the memory controller 15 writes the received event code in the buffer memory based on the control value from the counter unit. The counter unit also increments the event number nevent by +1 (S14).

  Then, the counter unit determines whether or not addr + 1 obtained by incrementing the address addr by +1 has reached the word number RAM_WORD of the memory (S15), and if not (NO in S15), increments the address addr by +1. (S16). The above is the processing performed when an event occurs in which one event code is input, and is repeated until addr + 1 reaches the word number RAM_WORD of the memory. Each time an event occurs, the memory controller 15 writes the MSB-side bit width width bit string of the received event code into the start bit position sbit of the storage area of the address addr in the memory buffer 17.

  Whether or not addr + 1 in step S15 has reached the word number RAM_WORD (= 64) is determined by whether or not an event code is written in the address addr from 0 to 63, that is, whether or not the round number nround is updated. It is a decision. Therefore, when addr + 1 reaches the word number RAM_WORD (YES in S15), the counter unit increments the round number nround by +1 (S17).

  Then, each time the round number is updated, the counter unit determines whether or not sbit + width obtained by adding the bit width width to the start bit position sbit has reached the bit width RAM_WIDTH (= 1024) of the buffer memory ( S18). This determination is whether or not the write cycle (division number ndiv) to the memory buffer memory is updated.

  In step S18, while sbit + width does not reach the bit width RAM_WIDTH (= 1024) of the buffer memory (NO in S18), the counter unit adds double the width * 2 to the start bit position sbit. Then, the round (round) of writing to the word area of the address addr = 0-63 is executed.

  In step S18, when sbit + width reaches the bit width RAM_WIDTH (= 1024) of the buffer memory (YES in S18), the counter unit updates the cycle (division number ndiv) (ndiv = ndiv + 1), Set the bit width to 1/2 (width = width / 2) and set the start bit position to the bit width (sbit = width) (S20).

  Then, regardless of which determination is made in step S18, the counter unit rewinds the address addr (S21) and returns to the stop determination S11. The rewinding of the address addr is, for example, a process of returning the address addr to the initial value 0. Alternatively, in the second and third embodiments described later, it is a process of returning the address addr to the initial value of each round, for example, 0, 1, 2 or the like, based on the number of events.

  FIG. 8 is a diagram showing a configuration example of the counter unit. The counter unit is, for example, a programmable reconfigurable device (FPGA (Field Programmable Gate Array), dedicated hardware circuit, for example, an application-specific integrated circuit (ASIC), SoC (System on Chip), or the like. In that case, the counter unit having the configuration shown in Fig. 8 is realized as a hardware circuit based on the hardware description language corresponding to the flowchart of Fig. 7. In Fig. 8, C is a counter and R is a counter. A register means a counter that counts up in response to an input signal, and a register stores the input signal .. It is preferable that the data recording device of FIG.

  The counter unit 16 of FIG. 8 has a stop determination circuit 25 that executes the stop determination of step S11 of FIG. In this example, the stop determination circuit 25 stops the operation and outputs a stop signal STOP to the memory controller when the bit width width reaches the minimum bit width width_nin. The condition determination used in the stop determination is not limited to this. The bit width is shortened as the number of data to be stored is increased, but if it is too short, the stored data is no longer meaningful, so it is reasonable to adopt the bit width. As another embodiment, a method of limiting the maximum number of events that can be recorded or a method of stopping when a predetermined signal is observed in the measurement target 3 can be considered.

  Next, regarding the step S12 in which the event code of FIG. 7 is generated, the counter unit detects it by receiving the event signal EVENT, for example. In response to the event signal EVENT, the counter unit outputs the respective values of the address counter C_addr, the start bit position register R_sbit, and the bit width register R_witdh as control values to the memory controller. The output wiring and the like corresponding to the output operation S13 are omitted in FIG.

  Then, in response to the event signal EVENT, the event number counter C_nevent counts up by +1. This operation corresponds to step S14.

  The first comparator CMP_1 is a circuit that determines update (or end) of the round of step S15. The first comparator CMP_1 operates in response to the event signal EVENT, and whether addr + 1 obtained by adding +1 to the address addr of the address counter C_addr is equal to or more than the word number RAM_WORD of the buffer memory (addr + 1 ≧ RAM_WORD) To judge. When the determination result is negative (addr <RAM_WORD), the first comparator CMP_1 sets the negative signal C1n to 1, and the address counter C_addr counts up the address addr. This corresponds to step S16.

  When the determination result is positive (addr + 1 = RAM_WORD), the first comparator CMP_1 sets the positive signal C1p to 1, increments the round number counter C_nround, and controls the second comparator CMP_2 to the operating state. To do. This operation corresponds to step S18.

  The second comparator CMP_2 is a determination circuit for updating (or terminating) the cycle of step S18. The second comparator CMP_2 determines whether sbit + width, which is the output of the adder 21, is equal to or larger than the memory bit width RAM_WIDTH (sbit_width ≧ RAM_WIDTH). When the determination result is negative, the second comparator sets the negation signal C2n to 1 and operates the doubling circuit 22, and the output sbit + width * 2 of the adder 23 is stored in the start bit register R_sbit. In this case, the positive signal C2p is 0, and the selector SEL selects the output of the adder 23. Further, the start bit register R_sbit may perform the storage operation in response to a signal obtained by delaying the negative signal C2n. The above corresponds to step S19.

  On the other hand, when the determination result is affirmative (sbit + width = RAM_WIDTH), the second comparator CMP_2 sets the affirmative signal C2p to 1, increments the division number counter C_ndiv, and sets the bit width register R_width to the bit width width. Is halved and stored, and the updated bit width width is stored in the register R_sbit at the start bit position. The register R_sbit at the start bit position is made to perform a storage operation with a signal obtained by delaying the positive signal C2p, for example.

  Finally, the address rewinding circuit 20 in the counter unit performs the rewinding operation of the address addr in response to the positive signal C1p of the first comparator CMP_1, and the address addr rewound to the address counter C_addr is reset to the reset value. Is set as.

  9 and 10 are diagrams showing an example of the address rewinding circuit of FIGS. As shown in FIG. 9, in the first embodiment, the address rewinding circuit rewinds the address addr to the initial value 0 (addr = 0). The second and third embodiments will be described later.

[First Embodiment]
FIG. 11 is a flowchart showing the write processing by the memory controller according to the first embodiment. FIG. 11 shows the number of cycles of write processing, CYC0 to CYC_K.

  FIG. 12 is a diagram showing the write processing of cycles 0, 1 and 2 in the first embodiment. FIG. 13 is a diagram showing a write process of cycle 3 in the first embodiment. 14 and 15 are diagrams showing the write processing of cycle 4 in the first embodiment. 12 to 15 show that the event code is written in the position shown in gray. Numerical values such as 0, 63, 64, 127, 128 and the like described only show the boundary portion of the serial numbers assigned to each event code. When the event code is sampled and output, serial numbers of 0, 1, 2, ... (Hereinafter, event ID (Identification)) are assigned to the event code for identification. Hereinafter, with reference to FIGS. 11 to 14, a process of writing the event code into the buffer memory 17 by the memory controller according to the first embodiment will be described.

[Cycle 0]
In FIG. 12, first, the memory controller performs writing of round (circulation) 0 in cycle 0 (CYC0). In the round (circulation) 0, the memory controller sequentially writes the event code having the bit width width = 1024 of the event ID 0-63 from the start bit position sbit = 0 at the address addr = 0-63 in the buffer memory 17. In this cycle 0, the event code is divided with a division ratio of 1/1 (that is, the 1024-bit event code is not divided and all bits are written). It is shown that the row of cycle 0 in FIG. 12 is written with an event code having a width of 1024 bits from address 0 to 63 from the start bit position 0.

[Cycle 1]
Next, the memory controller performs the writing of the round 1 in the cycle 1 (CYC1). In round 1, the memory controller sequentially writes the bit string of the MSB side bit width width = 512 of the event code of the event ID 64-127 from the start bit position sbit = 512 to the address addr = 0-63 in the buffer memory 17. . In this cycle 1, the event code is divided with a division ratio of 1/2. As shown in the row of cycle 1 in FIG. 12, the event code having a width of 512 bits is written from the start bit position 512 from the address 0 to 63.

  As a result, the low-order bit side of the event code written in cycle 0 and round 0 is overwritten with the MSB side 512-bit bit string of the new event code, and the buffer memory stores the MSB side of the cycle 0 and round 0 event code. Only 512 bits are left in the positions of bits 0-511 on the MSB side, and bits 512-1023 on the LSB side are replaced with 512 bits on the MSB side of the new event code. That is, at the end of cycle 1 and round 1, all the event codes stored in the buffer memory are only bit strings of the MSB side bit width width = RAM_WIDTH / 2 = 512 of the event code.

[Cycle 2]
Next, the memory controller performs writing in rounds (circulation) 2 and 3 in cycle 2 (CYC2). In round 2, the memory controller sequentially writes the bit string of the bit width width = 256 on the MSB side of the event code of the event ID 128-191 from the start bit position sbit = 256 to the address addr = 0-63 in the buffer memory 17. .

  Further, in the round 3, the memory controller starts from the start bit position sbit = 768 at the address addr = 0-63 in the buffer memory 17, and the bit string width = 256 on the MSB side of the event code of the event number 192-255. Are sequentially written. In this cycle 2, the event code is divided with a division ratio of 1/4.

  As a result, the MSB side 256-bit bit string of the new event code is overwritten on the lower bit side of the previously written event code. At the end of cycle 2, rounds 2 and 3, all the event codes stored in the buffer memory are only bit strings of the MSB side bit width width = RAM_WIDTH / 4 = 256 of the event code.

[Cycle 3]
In FIG. 13, the memory controller performs round 4-7 writing in cycle 3 (CYC3). In the round 4, the memory controller sequentially writes the bit string of the bit width width = 128 on the MSB side of the event code of the event ID 256-319 from the start bit position sbit = 128 to the address addr = 0-63 in the buffer memory 17. . Further, in round 5, the memory controller, at the address addr = 0-63 in the buffer memory 17, from the start bit position sbit = 384, the bit string width = 128 on the MSB side of the event code of the event ID 320-383. Write sequentially. In rounds 6 and 7, similarly, a bit string of 128-bit width on the MSB side of event codes of event IDs 384-447 and 448-511 is sequentially written from the start bit positions sbit = 640 and 869. In this cycle 3, the event code is divided with a division ratio of 1/8.

  As a result, the MSB side 128-bit bit string of the new event code is overwritten on the lower bit side of the previously written event code. At the end of cycle 3 and rounds 4-7, the event codes stored in the buffer memory are all bit strings of the MSB side bit width of the event code width = RAM_WIDTH / 8 = 128. The number of events is 64 × 8-1 = 511.

[Cycle 4]
In FIG. 14 and FIG. 15, the memory controller performs the writing of the round (circulation) 8-15 in the cycle 4 (CYC4). In the round 8, the memory controller sequentially writes the bit string of the bit width width = 64 on the MSB side of the event code of the event ID 512-575 at the address addr = 0-63 in the buffer memory 17 from the start bit position sbit = 64. . The same applies to Rounds 9-15.

  As a result, the MSB side 64-bit bit string of the new event code is overwritten on the lower bit side of the previously written event code. At the end of cycle 4 and rounds 8-15, all the event codes stored in the buffer memory have only the bit string width = RAM_WIDTH / 16 = 64 on the MSB side of the event code.

[Cycle 5]
FIG. 11 shows write processing (CYC5) of cycle 5, round (circulation) 16-31, and write processing (CYC6) of cycle 6, round (circulation) 2 ^5- (2 ⁶ -1). Further, as a generalization, the write processing (CYCK) of cycle K and round (circulation) 2 ^(K-1) -(2 ^K -1) is shown. The cycle K corresponds to the above-mentioned division number ndiv. Then, the cycle K is repeated while K = K + 1 until the stop condition is satisfied.

[Cycle K]
Generalizing, at cycle K (= ndiv), the memory controller, the address 0-63, start bit position ^{2 10-K, 2 10-} K + 2 * width, 2 10-K + 4 * width, 2 10 ^-K + 6 * width, ... 2 ¹⁰ -width From each, write MSB side 2 ^{10 -K} bit width bit sequence of event code.

  According to the first embodiment, the memory controller causes the bit width on the MSB side of the event code obtained by rearranging the bits having a high storage priority of the event data on the MSB side as the event number increases in accordance with its bit width width. While narrowing, overwrites the storage area on the LSB side of the event code previously written in the memory. As a result, while the number of stored events is small, the stored event code includes more bits including bits with a high storage priority. On the other hand, when the number of stored events increases, the stored event code retains at least all bits having a high storage priority or as many bits as possible. Partial bit data on the high priority side of all event codes is always included, and all bit data of the event code is not lost.

  Therefore, it has advantageous characteristics as a logic analyzer for LSI and a data logger for IoT. In particular, when recording the event data, if the timing of reading the stored event code from the buffer memory 17 is early, the event code having more bits can be read, and if the timing is late, it is suitable for the late timing. The event code having the best effort bit width can be read. Further, even when the event occurrence frequency is low or the event occurrence frequency varies, the best-effort effect can be provided.

[Second Embodiment]
In the first embodiment, the bit widths of all event codes are halved each time the cycle is updated. In this case, in the process of reading and analyzing the event code stored in the buffer memory, the read event code is in a state in which the bits on the LSB side are lost. Since the MSB side bit string of the event code remains, important bits can be extracted from the read event code. However, the lost bits on the LSB side of the read event code cannot be restored.

  Therefore, in the second embodiment, the memory controller controls the writing so that a part of the event code already written in the memory is not overwritten with a new event code. As a result, based on the bit string on the LSB side of some event codes remaining in the buffer memory, the lost bit string on the LSB side of the event code of another event can be estimated and restored while being complemented.

  For example, if a bit with a high transition probability in the bit value is rearranged on the MSB side as a bit with a high storage priority, the lost bit string on the LSB side has a low transition probability. It is possible to realize an auxiliary means by assuming that it is the same as the bit string on the LSB side of the code and directly adopting the bit string on the LSB side as the restored bits.

  FIG. 16 is a flowchart of the event code writing process performed by the memory controller according to the second embodiment. FIG. 16 shows write processing in cycles 0 (CYC0), 1 (CYC1), 2 (CYC2), 3 (CYC3).

  In addition, FIG. 17 is a diagram showing a write process in cycles 0, 1, and 2 in the second embodiment. Then, FIG. 18 is a diagram showing a writing process in the cycle 3 in the second embodiment.

  In the second embodiment, the memory controller, on the LSB side of the event code of the head address, among the plurality of event codes written in the lowest order side (that is, last) in the buffer memory 17 in the previous cycle, Do not overwrite the new event code. As a result, the event code of the leading address written in the lowermost side in the previous cycle is not lost in the lower bit side in the subsequent writing process. As a result, in the event codes with event IDs 0 and 64 in FIG. 17 and the event code with event ID 190 in FIG. 18, all the written bits are left in the buffer memory. Note that the event IDs, 64, 190, etc. are written and recorded with a bit number less than 1024 from the beginning, and even in the second and third embodiments, not all 1024-bit event codes are left. , Supplement.

  As a result, the value of the lower-order bit of the event code read from the buffer memory and output to the reception device 4 disappears due to overwriting, and the value of the lower-order bit of the event code left in the buffer memory is left unchanged. By extracting and applying the bits, the data can be restored as estimated data.

  The operation of writing the event code into the buffer memory by the memory controller according to the second embodiment will be described with reference to FIGS.

[Cycle 0]
First, in cycle 0 (CYC0) and round (circulation) 0, the memory controller starts from the start bit position sbit = 0 at the address addr = 0-63 in the buffer memory 17, and sets the bit width width = 1024 of the event ID 0-63. Event codes of are sequentially written.

[Cycle 1]
Next, in cycle 1 (CYC1) and round (circulation) 1, the memory controller starts from the start bit position sbit = 512 at the address addr = 1-63 in the buffer memory 17, and sets the bit width of the event ID 64-126 width = 512 event codes are written in sequence. As a result, of the event codes written in the last round (circulation) 0 of all cycles 0, the event code of 1024 bit width with the event ID 0 at the start address addr = 0 is stored in the buffer memory as it was when it was written. Left behind.

[Cycle 2]
Next, in cycle 2 and round 2 (CYC2_R2), the memory controller starts from the start bit position sbit = 256 at the address addr = 1-63 in the buffer memory 17, and determines the bit width width = event = 127-189. Write 256 event codes sequentially. Further, in cycle 2 and round 3 (CYC2_R3), the memory controller starts from the start bit position sbit = 768 at the address addr = 2-63 in the buffer memory 17, and sets the bit width width = 256 of the event ID 190-251. Event codes of are sequentially written. As a result, among the event codes written in the last round (circulation) 1 (CYC1) of the previous cycle 1, the 512-bit wide event code with the event ID of 64 at the start address addr = 1 is stored in the buffer at the time of writing. It is left in memory.

[Cycle 3]
As shown in FIG. 18, in cycle 3 and round (circulation) 4, in (CYC3_R4), the memory controller starts from the start bit position sbit = 128 at the address addr = 1-63 in the buffer memory 17, and outputs the event ID 252-314. Event codes with bit width of width = 128 are sequentially written. Similarly, in cycle 3 and round 5 (CYC3_R5), the memory controller starts from the start bit position sbit = 384 at the address addr = 1-63 in the buffer memory 17, and sets the bit width width of the event ID 315-377. Write event code of = 128 sequentially. In rounds 4 and 5, a new event code is overwritten at address addr = 1-63, so the event code with a 1024-bit width event ID of 0 in round 0 remains written in the buffer memory without being lost. Be done.

  Further, in cycle 3 and round 6 (CYC3_R6), in the memory controller, the memory controller starts from the start bit position sbit = 640 at the address addr = 2-63 in the buffer memory 17, and sets the bit width of the event ID 378-439 width = Write 128 event codes sequentially. According to this round 6, a new event code is not overwritten at the address addr = 1. Therefore, the event code with the event ID of 64 written in the last round 1 of cycle 1 remains as the data when written without being lost from the buffer memory.

  In cycle 3 and round 7 (CYC3_R7), the memory controller starts from the start bit position sbit = 896 at the address addr = 3-63 in the buffer memory 17, and sets the bit width width = event = 440-500. Write 128 event codes sequentially. According to this round 7, the address addr = 2 is not overwritten with a new event code. Therefore, the event code having the event ID 190 written in the last round 3 of the immediately preceding cycle 2 remains as the data when written without being erased from the buffer memory.

[Cycle K]
As described above, in the second embodiment, of the control values supplied from the counter unit, the bit width width and the start bit position sbit are the same as those in the first embodiment. However, the value when the address addr of the control value is reset in the loop processing, that is, the address addr reset by the address rewinding processing is different from that in the first embodiment.

  FIG. 9 shows an operation example of address rewinding according to the second embodiment. The address to be rewound is calculated by addr = F (sbit). Here, sbit = X and addr = F (X) are set, and as the start bit position sbit = X becomes larger, the reset address addr = F (X) gradually increases. In the example of round 7 of cycle 3 described above, the start bit position sbit = 896, so according to the operation example of FIG. 9, addr = F (X) = F (896) = 3, which is the same as the above description. Match.

  FIG. 10 shows another operation example of address rewinding in the second embodiment. In the example of FIG. 10, the calculation example of the address rewinding process is generalized and shown. According to this, when the start bit position sbit = X exceeds 0 and is W / 2 or less, the rewound address addr is F (X) = 1. As a result, in cycle 0, round 0, all event codes of 1024 bit width with event ID 0 written in address 0 are left in the buffer memory.

Similarly, when the start bit sbit = X exceeds W / 2 and W / 2 ² or less, the rewound address addr has F (X) = 2. As a result, all 512-bit wide event codes with the event ID of 64 written in address 1 in cycle 1 and round 1 are left in the buffer memory.

Thus, in the second embodiment, like the first embodiment, in the cycle K (= ndiv), the memory controller, the address 0-63, start bit position ^{2 10-K, 2 10-} K + 2 * width, 2 ^10-K + 4 * width, 2 ^10-K + 6 * width, ... 2 ¹⁰ -width The bit sequence of 2 ^10-K bit width of the MSB side of the event code is sequentially written from each. However, the address addr to be rewound is reset to the address F (X) corresponding to each condition of FIG. 10 according to the start bit position.

  In the second embodiment, when the event code is read from the buffer memory and the lower bits lost in the receiving device 4 are restored, the event code of event 1-63 shown in FIG. The bit string on the lower side of may be added. As a result, it is possible to restore the 1024-bit wide event code after supplementing it with the estimated value. Similarly, the lower-order bit string of the event ID 0 and the lower-order bit string of the event ID 64 may be added to the event codes of the event IDs 65 to 189. Similarly, the erased lower bits of the read event code can be restored after being supplemented with an estimated value by adding a lower bit string of the previously written and not erased event code.

[Third Embodiment]
Similar to the second embodiment, in the third embodiment, the memory controller writes a new event code on the LSB side of the event code of some events already written in the memory so as not to overwrite it. To control. As a result, by supplementing the bit string on the LSB side of the event code of some events left in the buffer memory as an estimated value, the lost bit string on the LSB side of the event code of another event is estimated and restored. be able to.

  FIG. 19 is a flowchart of the event code writing process by the memory controller according to the third embodiment. FIG. 19 shows the write processing in cycle 0 (CYC0), 1 (CYC1), 2 (CYC2), 3 (CYC3).

  Further, FIG. 20 is a diagram showing a write process in cycles 0, 1, and 2 in the third embodiment. Then, FIG. 21 is a diagram showing a writing process in the cycle 3 in the third embodiment.

  In the third embodiment, the memory controller creates a new event code on the LSB side of the event code of the head address among the plurality of event codes written in the buffer memory 17 in each round (circulation) of the previous cycle. Do not overwrite the event code. Therefore, in the event code of the leading address written in each round of the previous cycle, the lower bit side is not lost in the subsequent writing process. As a result, all the written bits of the event codes of events 0, 1, 64 in FIG. 20 and the event codes of events 2, 65, 127, 189 in FIG. 21 are left in the buffer memory.

  Therefore, as shown in FIG. 9, in the third embodiment, the address rewinding process resets the address addr to the address value of the cycle K (= ndiv). That is, reset to addr = ndiv.

  The operation of writing the event code into the buffer memory by the memory controller according to the third embodiment will be described with reference to FIGS.

  In cycle 0 and round (circulation) 0 shown in FIG. 19 (CYC0), the memory controller sets the address addr = 0-63, the start bit position sbit = 0, and the event code bit width of the event code 0-63. Write a 1024 bit string. This writing is the same as in the first and second embodiments.

[Cycle 1]
Next, in cycle 1 and round 1 (CYC1), since the start address addr is reset to addr = ndiv = 1, the memory controller sets the address addr = 1-63, the start bit position sbit = 512, and the event ID. Write a bit string with a bit width of 512 on the MSB side of the event code of 64-128. As a result, the event code whose event ID is 0 is not overwritten, and all the written bits are left.

[Cycle 2]
In cycle 2, rounds 2 and 3 (CYC2_R2, CYC2_R3), the start address addr is reset to addr = ndiv = 2. Then, the memory controller writes the bit string of the MSB side bit width 256 of the event code having the event ID of 127-188 and 189-250 at the address addr = 2-63 at the start bit position sbit = 256, 768, respectively. As a result, the event code with the event ID of 1,64 is not overwritten, and all the written bits are left.

[Cycle 3]
In cycle 3, round 4-7 (CYC3_R4, CYC3_R5, CYC3_R6, CYC3_R7), the start address addr is reset to addr = ndiv = 3. Then, the memory controller, at the address addr = 3-63, at the start bit position sbit = 128, 384, 640, 860 respectively, the event code of the event ID 251-131, 312-372, 373-433, 434-494 Write a bit string with a bit width of 128 on the MSB side. As a result, the event codes having the event IDs of 2,65, 127, and 189 are not overwritten, and all the written bits are left.

[Cycle K]
In cycle K, the memory controller starts at address addr = K-63, starting bit position 2 ^10-K , 2 ^10-K + 2 * width, 2 ^10-K + 4 * width, 2 ^10-K + 6 * width. , ... 2 ¹⁰ -width, the MSB side of the event code is sequentially written with a bit string of 210 ^-K bit width.

  In the third embodiment, the address rewinding process is addr = ndiv (= K), which is simpler than that in the second embodiment. Then, the event code of the head address of each previous cycle is not overwritten with the new event code, and all bits at the time of writing are left in the memory. As a result, the low-order bits of the event code that have been read from the buffer memory and that have disappeared are supplemented with the bits of the event code of the start address of the previous round that is close in time, and then the estimated data is added. You can restore it with.

[Comparison of Embodiments]
FIG. 22 is a diagram showing the bit width of the event code stored in the buffer memories of the first, second, and third embodiments and the number of data items thereof. The vertical axis represents the bit width of the event code in the buffer memory, and the horizontal axis represents the event ID number. The vertical axis is logarithmic, and the numerical value added in the graph is the value on the vertical axis at the plot point. It looks like a horizontal bar graph because the plot points are close, but it is actually a scatter plot. Each of the three graphs in FIG. 22 shows a state when about 8000 event codes are stored.

  At the time when the number of stored events reaches about 8000, in the first embodiment, only 8 bits on the MSB side remain in all event codes. On the other hand, in the second embodiment, the number of bits stored in the buffer memory differs depending on the event ID number. Although the event code stored in the memory has the largest number of bit widths of 8, the event codes having bit widths of 16, 32, 64, 256, 512, 1024 longer than that are also left one by one. .

  Then, in the third embodiment, the number of event codes stored in the memory that are left longer than the 8-bit width increases. In this example, one bit width 1024, two bit widths 512, and four bit widths 256 (hereinafter omitted) are left. For the purpose of compensating for the lost bit data, it can be expected that it is more likely that the guess will hit if more data having a large number of bits can be left. Therefore, in that respect, the third embodiment is better than the second embodiment. The embodiment is more effective. However, when storing the same number of data, comparing the second and third data, the second embodiment can leave the shortest bit width longer.

  FIG. 23 is a diagram showing the bit width of the event code stored in the buffer memory according to the third embodiment and the number of data items thereof. The vertical axis and the horizontal axis are the same as in FIG. The three graphs in FIG. 23 show the cases where the number of stored events (the number of data) is 2034, 1033, and 554, respectively.

  When the number of recorded events is as large as 2034, the bit width of the event code having the largest number of data is 32 bits. Considering that the event code was 1024 bits, it can be seen that considerable data is lost. . When the number of events is 1033, a large amount of 64-bit width data remains, and less data is lost than when 2034. When the number of events is 554, much 128-bit data remains. That is, FIG. 23 shows that if the number of events to be recorded is small, an event code having a longer bit width can be stored in the memory, and if the number of events increases, the event code in the memory has a shorter bit width. ing. The number of events recorded in the buffer memory depends on external factors such as when the contents of the buffer memory are transferred (this is related to the data transfer capability) and the frequency of occurrence of events. It can be seen from FIG. 23 that the best-effort adaptive data recording means can be provided.

[Decoding process of event code]
In the embodiment, the buffer memory 17 has the event code written or overwritten by the above-described writing method, and in addition, the counter unit 16 stores the number of events nevent currently written. .

  Then, the reception device 4 (or the analysis device that has acquired the event code from the reception device 4) receives the event code read from the buffer memory 17 and the event number nevent extracted from the counter unit. Next, the received data is used to determine the data format in the buffer memory. After that, the data in the buffer memory (the MSB side partial data of the event code) is read out in accordance with the data format, and the event code is restored while performing interpolation as necessary. Finally, the event code is subjected to decoding processing (bit rearrangement opposite to that at the time of encoding), data close to the original event data (at the time of event occurrence) is output, and the processing ends. When there is a bit overwritten and lost, it cannot be restored to the original event data, but the remaining bit can be used as accurate data.

  In the present embodiment, the receiving device or the analyzing device generates a map, which is a correspondence table between each bit in the buffer memory and the event ID, based on the number of events nevent. This map shows the data format in the buffer memory. Then, the receiving device or the analyzing device refers to the map and extracts the event code of each event ID from the bit string read from the buffer memory.

  24 and 25 are flowcharts of a procedure for generating a buffer memory map. The flowchart of FIG. 24 is similar to the flowchart of the counter unit of FIG. 24 has a step S10A of initializing parameters instead of the step S10 of initializing the counter of FIG. 7, and does not have the event code receiving step S12 of FIG. 7, and outputs the value of the counter of FIG. A map updating step S13A is provided instead of the step S13. FIG. 25 shows details of the map updating step S13A.

  The stop condition of the stop determination step S11 in FIG. 24 is when the event number nevent matches the event number nevent read from the buffer memory or extracted from the counter unit. This step is also different from FIG. 7.

Since the procedures of FIGS. 24 and 25 do not require high-speed operation, they can be implemented by software, but may be implemented as a hardware circuit. In one embodiment, the receiving device or the analyzing device has a processor that executes a program corresponding to the procedure of FIGS. 24 and 25, and the following constants are set before the processor executes the program.
Bit width of buffer memory: RAM_WIDTH = 1024
Number of addresses (number of words): RAM_WORD = 64

Then, the processor starts executing the program and first initializes the following parameters to initial values (S10).
Number of divisions (or number of cycles): ndiv = 0
Number of events: nevent = 0
Number of rounds (number of laps): nround = 0
Address: addr = 0
Start bit position: sbit = 0
Bit width: width = RAM_WIDTH = 1024

  When the processor executes the program of the flowchart, steps S13-S21 are repeatedly executed until the event number nevent reaches the event number nevent extracted from the counter unit. Then, every time the event number nevent is updated (S14), the map MAP is updated (S13).

  The other steps S14 to S21 are the same as the steps in FIG. That is, every time the number of events is incremented, the address addr to which the event code is written, the start bit position sbit, and the bit width width are generated.

  That is, according to the writing method based on the control signal of the counter unit, the data format in the buffer memory is updated every time the event number nevent is incremented. In the map update process S13A, the data format is updated by writing the event number nevent from the start bit position sbit of the address addr in the map to the bit width width.

  According to the map update process S13A in FIG. 25, the processor first obtains the parameter address addr, the start bit position sbit, the bit width width, and the current event number (equal to the event ID number) nevent ( S131), the variable i is initialized to 0 (S132), and while the variable i does not reach the bit width width (YES in S131), in the MAP memory of the address corresponding to the bit position sbit + i of the buffer memory and the address addr, The event number nevent is written (S134). Then, steps S133 and S134 are repeated while incrementing the variable i. In one embodiment, the MAP memory can be realized as a two-dimensional array variable like the programming language notation MAP [x, y] of S134, and the horizontal (x) size of the two-dimensional array variable is RAM_WIDTH, vertical (y) size is RAM_WORD. One element of the two-dimensional array variable needs a bit width sufficient to store the maximum value (non-negative integer) of nevent.

  FIG. 26 is a diagram showing a data structure of a map (two-dimensional array variable MAP [x, y]). The vertical y value of the map (corresponding to the address of the buffer memory 17) and the horizontal x index value (corresponding to the bit position of the buffer memory 17) correspond to those of FIGS. In FIG. 26, xr represents the index value at the rightmost position when the same value continues in the same row y. From the (xr + 1) column, another value is continuously stored in the right direction. That is, ... = MAP [xr-2, y] = MAP [xr-1, y] = MAP [xr, y], MAP [xr, y] ≠ MAP [xr + 1, y], MAP [xr + 1 , y] = MAP [xr + 2, y] = ... A plurality of xr having such a property may exist in the same row y, but the illustration is omitted in FIG.

  In the example of FIG. 26, it is shown that the event code having the event ID number 3 is written from the bit position 0 to the bit position xr of the address 3 in the buffer memory. In this way, the map indicates which event ID of the event code the words and bits of the buffer memory 17 shown in FIG. 12 correspond to, and thus the data format (data structure) of the buffer memory. .

  The reception device or the analysis device refers to the map generated as described above and extracts the event code read from the buffer memory for each event ID. Then, if necessary, based on the bit width of each event code, the lost lower-order bits are interpolated by referring to the lower-order bits of other event codes. Treat the position as an indeterminate value x). Furthermore, the receiving device or the analysis device decodes the restored event code based on the encoding setting value (relocation target bit) set in the event encoding unit, that is, restores the original configuration, and generates event data. To do. When there is a lost bit, the generated event data does not always match the data IVx output by the sampling unit 11 of FIG. 4, but the data set with a high priority can be correctly generated.

[Modification of Embodiment]
In the above-described embodiment, the event encoding rearranges the significant bits of the event data to the MSB side, and the memory controller selects the MSB side bit string when shortening the bit width of the event code. Write to the memory buffer.

  However, instead of the MSB side, it is also possible to rearrange the bits of high importance in event encoding to the LSB side, select the LSB side bit string, and write it to the memory buffer. In that case, a new event code is overwritten on the upper bit side of the already written event code.

  Furthermore, if it is more generalized, by introducing a new conversion rule for rereading the bit position, it is not limited to the MSB side and the LSB side, it is rearranged to another bit position and stored in the memory, and that bit position is stored. It may not be overwritten.

  In the second embodiment described above, the memory controller writes a new event code in the area of the event code written in the start address of the last round of the previous cycle without overwriting with a new event code in the next cycle. All the bits of the event code are left in memory. However, a new event code may not be overwritten in the next cycle in the area of the event code written in any address of any land in the previous cycle.

  As described above, according to the present embodiment, the event data acquired from the monitoring target or the measurement target is encoded so as to be rearranged in the order of high importance in bit units, and the encoded event code is stored in the buffer memory. Write in. Further, as the number of the event ID of the event data increases, the bit string of the event code written in the buffer memory is shortened, and overwriting is performed on the bit position of the less important side of the already recorded data. As a result, as many event codes as possible are written in the buffer memory. As a result, if the timing to read the event code from the buffer memory is early, the read event code contains more bits, and even if the timing is late, the bits with high importance are included. Data can be recorded with the best effort bit width. The degree of importance may be interpreted as the meaning of bit data that should be retained until the end as much as possible.

  The above embodiments are summarized as the following supplementary notes.

(Appendix 1)
A memory for storing data,
An encoding unit that performs encoding to rearrange predetermined bits of event data to the first bit side of the most significant bit side or the least significant bit side to generate an event code,
In the first cycle, a plurality of first data having a bit string of a first bit width on the first bit side of the event code is sequentially written in the memory, and in a second cycle after the first cycle. , A plurality of second data having a bit string on the side of the first bit of the event code and having a bit width smaller than the first bit width of the plurality of first data already written in the memory. A data recording device, comprising: a memory controller that sequentially overwrites a storage area on the second bit side opposite to the first bit side.

(Appendix 2)
In the first cycle, the memory controller sequentially writes a plurality of the event codes to the memory, and in a cycle subsequent to the first cycle, has a bit string on the first bit side of the event code, Note that a plurality of third data having a bit width smaller than the code is sequentially overwritten in a storage area on the second bit side opposite to the first bit side of the plurality of event codes already written in the memory. 1. The data recording device according to 1.

(Appendix 3)
The memory has a storage area having an N-bit width at each of M addresses,
Each cycle has a plurality of rounds of sequentially overwriting the data having a bit width smaller than the N bit width at the addresses 1 to M a plurality of times.
The data recording device according to attachment 1, wherein each of the cycles has twice as many rounds as the previous cycle.

(Appendix 4)
The memory controller is
In the second cycle, in the storage area on the second bit side of the plurality of data excluding a part of the plurality of data written in the memory in the cycle before the second cycle, 2. The data recording device according to attachment 1, which overwrites the data of 2.

(Appendix 5)
The memory has a storage area having an N-bit width at each of M addresses,
The memory controller is
In the first cycle, a plurality of the first data having a bit string on the first bit side of the event code and having a bit width of ½ of the data overwritten in the memory in the previous cycle, Sequentially overwriting the storage area on the second bit side of the plurality of data written at the plurality of addresses in the memory,
In the second cycle, a plurality of the plurality of the first codes having a bit string on the side of the first bit of the event code and having a bit width of ½ of the first data overwritten in the memory in the first cycle are provided. 2. The data recording device according to attachment 1, wherein the data of No. 2 is sequentially overwritten in the storage area on the second bit side of the plurality of data already written at the plurality of addresses in the memory.

(Appendix 6)
The memory controller is
In the second cycle, the storage area on the second bit side of the data excluding a part of the data written in the cycle before the second cycle is overwritten with the second data. The described data recording device.

(Appendix 7)
The second cycle has a round in which 1 to M addresses are sequentially overwritten with the plurality of pieces of second data, which is twice the number in which the first data is written in the N-bit width direction. ,
The memory controller, in the second cycle, in the storage area on the second bit side of data excluding a part of the data written in a part of the rounds of the cycle before the second cycle, 6. The data recording device according to attachment 5, which overwrites the second data.

(Appendix 8)
The data recording device according to appendix 1, wherein the memory controller repeats the overwrite in the second cycle until a predetermined condition is satisfied.

(Appendix 9)
2. The data recording device according to attachment 1, wherein the memory controller repeats the overwrite in the second cycle until the bit width of the second data reaches a reference value.

(Appendix 10)
The data recording device according to appendix 1, wherein the memory controller repeats the overwrite in the second cycle until the number of events of the event data reaches a reference number.

(Appendix 11)
further,
A data acquisition unit that acquires event data that sequentially occurs from the measurement target,
The data recording device according to appendix 1, further comprising: an output unit that outputs the event code stored in the memory.

(Appendix 12)
Encoding is performed by rearranging predetermined bits of event data sequentially generated from the measurement target to the first bit side of the most significant bit side or the least significant bit side to generate an event code,
In the first cycle, sequentially writing a plurality of first data having a bit string of a first bit width on the first bit side of the event code to a memory,
In a second cycle after the first cycle, a plurality of second data having a bit string on the side of the first bit of the event code and having a bit width smaller than the first bit width is stored in the memory. A data recording method of sequentially overwriting a storage area on the second bit side opposite to the first bit side of the plurality of first data that have been written to.

(Appendix 13)
further,
In the first cycle, a plurality of the event codes are sequentially written in the memory, and in the next cycle of the first cycle, the event code has a bit string on the first bit side and has a bit width smaller than the event code. 13. The data according to appendix 12, wherein the plurality of third data items of No. 3 are sequentially overwritten in the storage area on the second bit side opposite to the first bit side of the plurality of event codes already written in the memory. Recording method.

1: semiconductor device 2: measurement target circuit 3: observation target 4: receiving device 5: communication path 10: data recording device 11: data acquisition unit 12: data buffer unit 13: data output unit 14: event encoding unit
IV0-IV7: Event data
S0-S7: Event code 15: Memory controller 16: Counter unit 17: Buffer memory SP: Sampling set value CD: Encoding set value
RAM_WIDTH: Bit width of buffer memory
RAM_WORD: Number of addresses (number of words)
ndiv: Number of divisions (or number of cycles)
nevent: Number of events
nround: Number of rounds (number of laps)
addr: address in memory where the event code is written
sbit: Starting bit position in memory where the event code is written
width: Bit width of the event code written in memory

Claims (5)

A memory having a storage area having an N-bit width at each of the M addresses and storing data;
A coding unit that performs coding for rearranging the bit of event data having a higher storage priority in the memory to the first bit side of the most significant bit side or the least significant bit side to generate the event code having the N-bit width. When,
In the first 0th cycle, the N-bit wide event codes that are sequentially generated are sequentially written into the N-bit wide storage area of the M addresses of the memory,
In the K-th cycle (K is an integer of 1 or more), the partial data of N / 2 ^K- bit width on the side of the first bit of the event code of N-bit width that is successively generated is given to each address. Of the N bit width of the storage area divided into 2 ^K pieces of the N / 2 ^K bit width of the first partial area on the side of the first bit from the second partial area (J is Overwrites partial areas of 1 or more and 2 ^K-1 or less) sequentially, and executes the overwrite round while increasing J from 1 to 2 ^K-1 ,
A data recording device, comprising: a memory controller that repeats the overwrite processing in the Kth cycle while increasing the K sequentially from 1 . The memory controller is
In the Kth cycle, in at least a part of the overwrite rounds of the overwrite round, the second Jth partial area at each address except some of the M addresses is sequentially overwritten. Item 1. The data recording device according to item 1. The memory controller, the overwriting of cycles of the first K, repeated until a predetermined condition is satisfied, the data recording apparatus according to claim 1. The memory controller, the overwriting of cycles of the first K, repeated until the N / 2 ^K-bit width reaches the reference value, the data recording apparatus according to claim 1. A method of recording data in a memory having an N-bit width storage area at each of M addresses,
The event code having the N-bit width is coded by rearranging the bit having the higher storage priority of the event data sequentially generated from the measurement object in the memory into the most significant bit side or the least significant bit side to the first bit side. Produces
In the first 0th cycle, the N-bit wide event codes generated in sequence are sequentially written into the N-bit wide storage area of the M addresses of the memory,
In the K-th cycle (K is an integer of 1 or more), the partial data of the N / 2 ^K- bit width on the first bit side of the event code of the N-bit width, which is successively generated, is assigned to each address. the 2J-th (J counted from the first partial region of the first bit side of the partial area of the storage area 2 ^K number the divided N / 2 ^K-bit width of the N-bit width in the The integers of ^{1 to} 2 ^K-1 inclusive) are sequentially overwritten, and the overwriting round is executed while increasing J from 1 to 2 ^K-1 ,
A data recording method , wherein the Kth cycle is repeatedly incremented from 1 while repeating the Kth cycle overwrite process .

Images