JP6687406B2 - Motor control circuit, fan using it - Google Patents

Description

  The present invention relates to a motor control circuit.

  Known methods of driving a motor include rectangular wave drive, sine wave drive, and vector control. Of these, the vector control is a type of sine wave drive, in which the coil current of the motor is decomposed into the d-axis component and the q-axis component which are orthogonal to each other and each is controlled individually. Vector control has the advantage of high control efficiency, but it is complicated to control.

  The rectangular wave drive and the sine wave drive can be realized only by hardware such as an analog circuit or a digital circuit. On the other hand, in vector control, it is difficult to configure a control circuit only by hardware because of its complexity, and it is common to rely on software control by combining a processor (microcomputer) and a program.

  In order to drive the motor properly, information on the mechanical state of the motor (rotational speed and rotor position) is required. The mechanical state of the motor can be detected by a rotation sensor such as a rotary encoder or a resolver. Alternatively, in the sensorless system, it is necessary to estimate the mechanical state of the motor based on the electric state of the motor (coil current and / or coil voltage of the motor) and generate the drive control signal based on the estimated state. .

  FIG. 1 is a block diagram of a motor drive device 4R using software control. Here, sensorless drive is taken as an example. The motor 2 is a three-phase brushless motor. The drive device 4R mainly includes a three-phase inverter 6 and a motor control circuit 10R.

The motor control circuit 10R mainly includes an A / D converter module 12, a processor 14, and a pulse width modulator 16. The A / D converter module 12 converts the analog detection signal S1 according to the electrical state of the motor 2, that is, the coil current and the coil voltage into a digital detection signal S2. For example, the inverter 6, U-phase, V-phase, W-phase sense resistor _Rs U for detecting the _current, Rs _v, Rs _w is provided (referred to three-shunt configuration). A voltage drop occurs in the sense resistor Rs in proportion to the coil current of the corresponding phase. The voltage drop of the sense resistors Rs _{U to W} is input to the A / D converter module 12 via a plurality of analog ports. Other analog signals (not shown) can be input to the A / D converter module 12.

  The processor 14 generates a drive control signal (for example, a command value of a three-phase voltage) S3 for the motor 2 based on the digital detection signal S2 from the A / D converter module 12. The processor 14 is configured to execute the program 18 previously described by the user.

  The pulse width modulator 16 performs pulse width modulation (PWM) on the drive control signal S3 to generate a control signal S4 for the inverter 6. The inverter 6 switches according to the control signal S4 from the pulse width modulator 16.

JP-A-3-243193 JP-A-3-277194

Osamu Matsumoto, a professional teaches! Motor control that can be done so far with CortexTM-M microcomputer, [online], [January 7, 2016 search], Internet <URL: http://toshiba.semicon-storage.com/product/micro/pdf/armcortex- m_ws2012_2.pdf ＞

  The functions required of the motor control circuit 10R vary depending on the type of the motor 2 to be combined, the drive type, and the application. For example, as a method of current detection, in addition to the 3-shunt configuration shown in FIG. 1, there is a 1-shunt configuration in which one sense resistor is shared by three phases. The A / D converter processes three current detection signals in the former case, and processes one current detection signal in the latter case, and the appropriate timing of A / D conversion is different between the two.

  If the motor control circuit 10R can have versatility and flexibility that can be used in various applications, drive formats, and combinations with motors, the vendor of the motor control circuit 10R can reduce the number of types. It is advantageous from the viewpoint of development cost and inventory management. Also for the purchaser (user) of the motor control circuit 10R, the hardware (that is, the motor control circuit 10R) is common, and the software (that is, the program 18) is modified to support various applications, drive types, and motors. If so, the development period of various devices 1 equipped with the motor 2 can be shortened.

  As a result of examining the conventional motor control circuit 10R, the present inventor has come to recognize the following problems. That is, in the conventional motor control circuit 10R, the order and timing of A / D conversion by the A / D converter module 12 and the analog port that is the target of A / D conversion cannot be freely set and controlled by software. This has been one of the obstacles to increasing the versatility and flexibility of the motor control circuit 10R.

  The present invention has been made in view of the above problems, and one of the exemplary objects of a certain aspect thereof is to provide software control easiness and flexibility in a motor control circuit.

  One aspect of the present invention relates to a control circuit for a motor. The control circuit has a plurality of m (m is an integer of 2 or more) analog ports into which detection signals indicating the electric state of the motor can be input, and a multiplexer that receives the detection signals from the m analog ports. , A / D converter that converts the detection signal selected by the multiplexer into digital data, a processor that generates a motor drive command based on the digital data, and controls the operation of the A / D converter according to a control command from the processor And an interface circuit that transfers digital data to the processor. The interface circuit includes a run register (RUN) and a mode start register (MODE_START) that stores a value designating one of a software mode and a hardware mode. The interface circuit (i) uses the assertion of the run register as a trigger for the operation start of the A / D converter in the software mode, and (ii) in the hardware mode, at least one internal signal generated in the control circuit is A / D. This is the trigger to start the converter operation.

In this specification, "asserting a register" corresponds to writing a predetermined value (for example, 1) in the register.
In hardware mode, the A / D converter can be synchronized with the state of the control circuit. In the software mode, the A / D converter can be triggered by software control without depending on the hardware state.

  The interface circuit controls the A / D converter by using a timing signal generation circuit that generates a start timing signal based on a start event signal that is one of at least one internal signal, and the start timing signal as a trigger for starting the operation of the A / D converter. And an access control unit for controlling the access.

The interface circuit may further include an event selection register (EVENT_SEL) and an event selector that receives a plurality of internal signals, selects one according to a value stored in the event selection register, and outputs a start event signal. . The timing signal generation circuit may generate the start timing signal based on the start event signal.
This allows software control of the internal signal (ie, event) that triggers the operation start.

The interface circuit may further include a delay setting register (EVENT_DELAY_SEL, EVENT_DELAY_EN) that stores a setting value of the delay time from the assertion of the start event signal to the assertion of the start timing signal in the hardware mode. The timing signal generation circuit may include a delay circuit that delays the start event signal according to the set value of the delay setting register and outputs the start timing signal.
As used herein, "asserting a signal" corresponds to a transition of the signal to a predetermined level, and from another perspective, to the occurrence of a predetermined edge of the signal. As a result, the operation start timing can be finely controlled by software.

One control cycle of the A / D converter by the interface circuit may include k times (1 ≦ k ≦ n) A / D conversion that maximizes n (n is an integer of 2 or more). The interface circuit may further include a mode burst register (MODE_BURST) that stores a value designating one of the once conversion mode and the continuous conversion mode. The interface circuit (i) waits for the start of the next operation when the conversion process of one control cycle is completed in the single conversion mode, and (ii) when the conversion process of one control cycle is completed in the continuous conversion mode, The operation may be shifted to the next control cycle without waiting for the start of the operation.
The additional flexibility is provided by the ability to select between the single conversion mode and the continuous conversion mode.

The interface circuit may further include a register (BURST_SEL) that stores a value that specifies the number of conversions k included in one control cycle.
As a result, the minimum necessary conversion processing is performed, so that the load on the processor can be reduced.

One control cycle of the A / D converter by the interface circuit may include k times (1 ≦ k ≦ n) A / D conversion that maximizes n (n is an integer of 2 or more). The interface circuit further includes, for each A / D conversion, a timing signal generation circuit that generates a conversion timing signal based on a conversion event signal that is one of at least one internal signal, and a conversion timing signal for each A / D conversion. The A / D conversion trigger may include an access control unit that controls the A / D converter. In the sequential mode, the access control unit may execute each A / D conversion k times by using the corresponding conversion timing signal as a trigger.
As a result, the timing of A / D conversion can be controlled based on the state of hardware.

The interface circuit further includes n individual event selection registers (EVENT_SEL0 to EVENT_SELn-1) that store values that individually specify internal signals to be triggered for each maximum A / D conversion, and a plurality of internal events. An event that receives a signal and selects one of a plurality of internal signals corresponding to a value stored in a corresponding one of n individual event selection registers for each A / D conversion and outputs a conversion event signal And a selector may be included. The timing signal generation circuit may generate the conversion timing signal based on the conversion event signal for each A / D conversion in the sequential mode.
As a result, the trigger event can be set independently and individually for each conversion.

The interface circuit further includes delay setting registers (EVENT_DELAY_SEL0 to EVENT_DELAY_SELn-1, EVENT_DELAY_EN0 to EVENT_DELAY_ENn) that store setting values of the delay time from the assertion of the conversion event signal to the assertion of the conversion timing signal for each maximum A / D conversion. -1) may be included. The timing signal generation circuit may include a delay circuit that outputs a conversion timing signal by giving a delay corresponding to the setting value of the corresponding delay setting register to the corresponding conversion event signal for each A / D conversion.
As a result, the timing of A / D conversion can be finely controlled by software.

The interface circuit may further include a mode sequence register (MODE_SEQ) that stores a value designating one of the auto mode and the sequential mode. The interface circuit may automatically perform k A / D conversions in the auto mode.
In the auto mode, k times of A / D conversion can be performed at the timing automatically generated by the interface circuit, which is useful in a situation where the timing of A / D conversion is not so severe. In the sequential mode (manual mode), the timing of each A / D conversion can be manually specified individually, and strict timing control can be supported.

  The control circuit may include a plurality of A / D converter channels.

The control circuit may be integrated on one semiconductor substrate.
"Integrated integration" includes the case where all the components of the circuit are formed on the semiconductor substrate and the case where the main components of the circuit are integrated, and some of them are used for adjusting the circuit constants. A resistor or a capacitor may be provided outside the semiconductor substrate.

  Another aspect of the invention relates to a fan. The fan includes a fan motor and any one of the control circuits described above that drives the fan motor.

  It should be noted that any combination of the above constituent elements and constituent elements and expressions of the present invention that are mutually replaced among methods, devices, systems, etc. are also effective as an aspect of the present invention.

  According to an aspect of the present invention, ease and flexibility of software control can be provided.

It is a block diagram of the drive device of the motor using software control. 3 is a block diagram of a drive device including the control circuit according to the embodiment. FIG. FIG. 3 is a detailed block diagram of a part of the control circuit of FIG. 2. It is a figure explaining the interface of an ADC interface and an A / D converter. It is an operation waveform diagram of one control cycle of the A / D converter and the ADC interface. It is an operation waveform diagram of a pulse width modulator and a peak bottom pulse generator. It is a figure which shows an internal signal and an event. It is a figure which shows the structural example of an event selector and an interface unit. It is a figure which shows the control sequence of an A / D converter. FIG. 10A is a diagram for explaining the operation of the access control unit in the buffer mode, and FIG. 10B is a diagram for explaining the operation of the access control unit in the normal mode. It is a wave form diagram which shows the combination of a hardware mode and a sequential mode.

(overall structure)
FIG. 2 is a block diagram of the drive device 4 including the control circuit 10 according to the embodiment. The drive device 4 is used in the device 1 together with the motor 2. The type of the device 1 is not particularly limited, but it can be used in various fields such as home appliances, OA devices, industrial devices, vehicle-mounted devices, and portable electronic devices. In familiar places, the motor 2 is used for compressors such as air conditioners and refrigerators, and fans for cooling many devices. The drive device 4 includes an inverter 6 in addition to the control circuit 10. The inverter 6 includes U-phase, V-phase, and W-phase bridge circuits (drivers).

  In the present embodiment, the control target of the control circuit 10 is a three-phase brushless motor, and the inverter 6 is controlled by a sensorless method. The control circuit 10 outputs to the inverter 6 drive signals necessary for controlling the U-side, V-side, and W-phase high-side switches and low-side switches.

  The control circuit 10 is a functional IC (Integrated Circuit) integrated on one semiconductor substrate, monitors the electrical state of the motor 2, and generates a drive signal based on the result. The control circuit 10 is provided with a plurality of m (m is an integer of 2 or more) analog ports PORT-0 to PORT-m-1. In this embodiment, m = 8 and PORT-0 to PORT-7 are provided. A detection signal indicating the electrical state of the motor 2 can be input to each analog port. It should be noted that other electrical signals such as the output voltage of a temperature sensor such as a thermistor or the analog voltage indicating the rotation speed of the motor 2 may be input to each analog port.

A three-shunt configuration is shown in FIG. 2. A sense resistor (shunt resistor) R _S is provided for each of the U, V, and W phases, each sense resistor is assigned to one analog port, and each voltage drop occurs. Is input to the analog port assigned as the detection signal. In the case of the one-shunt configuration, the voltage drop of one shunt resistor is input to any analog port.

  The control circuit 10 mainly includes a digital arithmetic processing unit 30, an A / D converter 50, a memory 60, and a clock generator 70. Blocks not relevant to the present invention have been omitted. The A / D converter 50 has a multiplexer 52 on its input side that receives the detection signals of the m analog ports. The A / D converter 50 converts the detection signal selected by the multiplexer 52 into digital data (conversion data) DOUT. The control circuit 10 of FIG. 2 includes A / D converters 50 for three channels ch0 to ch2, but the number of channels is arbitrary. The configuration and system of the A / D converter 50 are not particularly limited, but for example, a successive approximation type A / D converter may be used.

  The digital arithmetic processing unit 30 receives the conversion data DOUT from the A / D converter 50 and outputs PWM signals (PWM_U, PWM_V, PWM_W and their inverted signals #PWM_U, #PWM_V, #PWM_W) for controlling the inverter 6. To generate. The system platform 32 of the digital arithmetic processing unit 30 is a so-called embedded processor, and may be configured using, for example, the ARM architecture provided by ARM Limited. In addition to the CPU core 34, the system platform 32 contains memory controllers 36, 38, a power management unit 40, a system controller 42, and the like.

  The memory 60 includes a non-volatile memory 62 such as a flash memory and a volatile memory 64 such as an SRAM. A program to be executed by the CPU core 34 is stored in the non-volatile memory 62. The volatile memory 64 is used as a main storage device.

  The motor control block 44 of the digital arithmetic processing unit 30 is a circuit block specific to the control of the motor 2. The ADC interface (interface circuit) 46 is an interface between the system platform 32 and the A / D converter 50, and transfers the conversion data from the A / D converter 50 to the CPU core 34. Further, as will be described later in detail, the operation of the A / D converter 50 can be software controlled by the CPU core 34. The ADC interface 46 controls the operation of the A / D converter 50 according to the control command from the CPU core 34. A control command from the CPU core 34 to the ADC interface 46 is issued by writing to a control register described later.

  The system platform 32 executes a program to generate a drive command for the motor 2 (for example, a three-phase voltage command value). The pulse width modulator 48 performs pulse width modulation on the drive command generated by the system platform 32, and generates U, V, W phase PWM signals and their inverted signals. The motor control method and algorithm are not particularly limited, and a known vector control technique can be used.

  Each block in the system platform 32 and each block in the motor control block 44 are connected to each other via a bus 31, and various data and control bits can be mutually referred to or written via a register. There is.

  The above is the overall configuration of the control circuit 10. Next, the ADC interface 46 will be described.

(ADC interface)
FIG. 3 is a detailed block diagram of part of the control circuit 10 of FIG. FIG. 3 shows the configuration of the ADC interface 46 in detail. The ADC interface 46 includes an ADC I / F register (hereinafter, simply referred to as a register) 80, interface units 82_1 to 82_3, and an event selector 84. The interface unit 82 is provided for each channel, and they are similarly configured.

  The ADC interface 46 operates in synchronization with the same system clock CLK_SYS (for example, 40 MHz) as the CPU core 34. On the other hand, the plurality of A / D converters 50 operate in synchronization with the clock CLK_IR in the conversion frequency operating range (for example, 16 MHz) of the A / D converter 50. The ADC interface 46 and the A / D converter 50 may be asynchronous.

  FIG. 4 is a diagram illustrating an interface between the ADC interface 46 and the A / D converter 50. FIG. 4 shows one conversion operation. The A / D converter 50 is, for example, a 12-bit successive approximation type and requires 12 cycles of the clock CLK_IR for one conversion. Prior to conversion, a port selection signal PORT_SEL [2: 0] designating an analog port is given from the ADC interface 46 to the A / D converter 50. When the conversion start signal CONV_IH is asserted, A / D conversion is started. When the conversion of 12 bits is completed after the lapse of 12 cycles, the conversion completion signal TRIG_OUT_OH is asserted and the 12-bit conversion data DOUT [11: 0] becomes valid. The number of bits of the A / D converter 50 is not particularly limited, and may be 10 bits or 8 bits, or the number of bits may be variable.

  Returning to FIG. The register 80 is accessible from the CPU core 34 via the bus 31. The register 80 includes a data register and a control register for each channel. The conversion data DOUT generated by the A / D converter 50 of the channel is stored in the data register of each channel. The CPU core 34 obtains the digital value of the detection signal input to the plurality of analog ports PORT-0 to PORT7 by accessing the data register. The operation of the A / D converter 50 of each channel is controlled based on the value written in the control register of the channel by the CPU core 34. Specifically, the ADC interface 46 controls the timing of the port selection signal PORT_SEL and the conversion start signal CONV_IH based on the value of the control register.

(Control cycle)
Next, the control cycle will be described. One control cycle of the A / D converter 50 by the ADC interface 46 includes k (1 ≦ k ≦ n) A / D conversions that maximizes n (n is an integer of 2 or more). In this embodiment, n = 8. Hereinafter, one channel will be described.

  The following control registers are provided to set the number of times k. It should be noted that the values of the control register shown in the present specification are examples, and other values may be assigned. The names of the registers are also for convenience.

・ Count register (BURST_SEL)
000: k = 1
001: k = 2
~
111: k = 8
A value designating the number of conversions k is stored in the register BURST_SEL. The maximum number of conversions k is equal to n. That is, 1 ≦ k ≦ n.

  That is, k / A conversion is performed during one control period, and thus k (maximum 8) conversion data DOUT0 to DOUTk-1 are generated. DOUTi-1 represents the i-th converted data and corresponds to DOUT [11: 0] in FIG. In order to store a maximum of n conversion data DOUT0 to DOUTn-1, n data registers are provided.

・ Data register (DATA0-DATAn-1)
The number of data registers DATA is equal to the maximum conversion number n. The n data registers (DATA0 to DATAn-1) store the converted data DOUT0 to DOUTn-1 for n times. The access control unit 92 described above stores the conversion data DOUT0 to DOUTn-1.

・ Port selection register (PORT_SEL0-PORT_SELn-1)
000: 1st port PORT-0
001: Second port PORT-1
010: 3rd port PORT-2
~
110: 7th port PORT-6
111: 8th port PORT-7
To control the multiplexer 52, n port selection registers are provided, which is equal to the maximum conversion count. The value Xi-1 of the i-th port selection register PORT_SELi specifies the analog port that the multiplexer 52 should select in the i-th A / D conversion. When the value X3 of the port selection register PORT_SEL3 is 0, the first analog port PORT-0 is selected in the fourth A / D conversion.

  FIG. 5 is an operation waveform diagram of the A / D converter 50 and the ADC interface 46 in one control cycle. First, prior to the first conversion, the value of the first port selection register PORT_SEL0 is set as the port selection signal PORT_SEL for the multiplexer 52. Subsequently, when the conversion start signal CONV_IH is asserted, the conversion starts, and when the conversion ends, the conversion end signal TRIG_OUT_OH is asserted and the first conversion data DOUT0 becomes valid. Then, prior to the second conversion, the value of the second port selection register PORT_SEL1 is set as the port selection signal PORT_SEL for the multiplexer 52. Subsequently, when the conversion start signal CONV_IH is asserted, the conversion starts, and when the conversion ends, the conversion end signal TRIG_OUT_OH is asserted and the second conversion data DOUT1 becomes valid. When the same process is repeated k times, one control cycle ends.

(Event)
Next, returning to FIG. 3, the event will be described. The control circuit 10 is configured to be controllable by using various events generated inside the control circuit 10 as a trigger. A signal that is generated inside the control circuit 10 and whose edge (or level) represents the occurrence of an event is called an internal signal.

In the present embodiment, the control circuit 10 can use at least one, and preferably a plurality of the following events.
・ U-phase turn-on event ・ U-phase turn-off event ・ V-phase turn-on event ・ V-phase turn-off event ・ W-phase turn-on event ・ W-phase turn-off event

  For example, when it is desired to use U-phase turn-on and turn-off events, the U-phase PWM signal PWM_U generated in the pulse width modulator 48 may be used as an internal signal, and the positive edge and the negative edge thereof are the U-phase turn-on and Corresponds to turn-off. Alternatively, the inverted signal #PWM_U may be used as an internal signal, and the negative edge and the positive edge thereof correspond to the U-phase turn-on and turn-off, respectively. In the present specification, # represents logical inversion.

  Similarly, when it is desired to use the V-phase turn-on and turn-off events, the V-phase PWM signal PWM_V (or its inverted signal #PWM_V) can be used as an internal signal. When the W-phase turn-on and turn-off events are used, The W-phase PWM signal PWM_W (or its inverted signal #PWM_W) may be used as the internal signal.

In the control circuit 10, the peak (peak) and the bottom (valley) of the triangular wave used in the pulse width modulator 48 can be used as events.
・ PWM triangular wave peak and bottom events

As an internal signal corresponding to the peak and the bottom, the peak _/ bottom detection signal S _{P / B} representing the peak and the bottom of the triangular wave is supplied from the pulse width modulator 48 to the ADC interface 46. For example, the peak-bottom detection signal SP _{/ B} is asserted (for example, high level) for one cycle of the system clock CLK_SYS at the peak and the bottom, respectively.

Peak bottom pulse generator 86 receives the peak-bottom detection signal S _{P / B,} peak, level of each bottom to generate a peak-bottom pulse P _{P / B} of transition.

FIG. 6 is an operation waveform diagram of the pulse width modulator 48 and the peak bottom pulse generator 86. In the pulse width modulator 48, the timer counter generates a triangular wave having a PWM cycle, and asserts a peak-bottom detection signal _{SP / B} (for example, high level) at each of the peak and the bottom. The peak-bottom pulse generator 86 changes the level of the peak-bottom pulse P _{P / B} every time the peak-bottom detection signal S _{P / B} is asserted. The peak-bottom pulse P _{P / B} generated in this way becomes a pulse signal having a PWM cycle, like the other internal signals (PWM_U to PWM_W), and they can be treated equally.

  Returning to FIG. The event selector 84 selects one of a plurality of internal signals for each channel and supplies it as an event signal EVT to the corresponding interface unit 82. The internal signal used for the event signal EVT can be individually selected for each channel according to the value of the control register of the register 80.

  In each channel, the interface unit 82 generates the timing signal TMG based on the event signal EVT from the event selector 84, and controls the operation of the A / D converter 50 according to the timing signal TMG. This is called hardware mode. As will be described later, it is possible to control the A / D converter 50 without depending on the event signal EVT, and this is called a software mode.

FIG. 7 is a diagram showing internal signals and events. As shown in FIG. 3, a plurality of internal signals PWM_U, PWM_V, PWM_W and a peak bottom pulse P _{P / B} are input to the ADC interface 46. Therefore, in each PWM cycle, eight events (i) to (viii) can be used for timing control (specifically, start state control and conversion timing described later). In the conventional technique described in Non-Patent Document 1, as described on page 17, the operation timing of A / D conversion is generated by a trigger generator (Trigger generator) configured as hardware. Software was not able to intervene in the timing control of the / D converter, which lacked flexibility. On the other hand, according to the present embodiment, the timing of the A / D converter 50 can be freely controlled using the internal signal (event). This contributes to increasing the degree of freedom of the program or the controllability of the motor.

(Event selector 84 and interface unit 82)
FIG. 8 is a diagram showing a configuration example of the event selector 84 and the interface unit 82. The event selector 84 includes selectors 88_1 to 88_3 provided for each channel. Each selector 88 selects an internal signal according to the value stored in the corresponding control register, generates an event signal EVT, and outputs the event signal EVT to the corresponding interface unit 82.

  Next, the configuration of the interface unit 82 will be described. Here, only the configuration of the third channel ch2 is shown, but the other channels are similarly configured. The interface unit 82 includes a timing signal generation circuit 90, an access control unit 92, a conversion data buffer 94, and an error detection unit 96.

  The timing signal generation circuit 90 generates the timing signal TMG according to the event signal EVT from the event selector 84. For example, the timing signal generation circuit 90 includes an edge selector 100, a delay circuit 102, a delay selector 104, and an asynchronous processing circuit 106.

  As described above, the event signal EVT output from the event selector 84 is a pulse signal having a PWM cycle. The edge selector 100 detects one of the positive edge and the negative edge of the event signal EVT according to the value of the corresponding control register, and cuts it out. That is, one event corresponding to each of the positive edge and the negative edge is selected. The delay circuit 102 is configured using a counter, and gives the cut edge signal a delay according to the value of the corresponding control register. Delay selector 104 selects one of a delayed and an undelayed signal, depending on its corresponding control register. The asynchronous processing circuit 106 synchronously processes the output of the delay selector 104 synchronized with the system clock CLK_SYS with the clock CLK_IR on the A / D converter side to generate the timing signal TMG.

  The access control unit 92 mainly has two functions. One is a function (access timing generation) of controlling the conversion timing of the A / D converter 50 by using the timing signal TMG as a trigger in the hardware mode. The other is a function (ADC control) of storing the conversion data DOUT obtained from the A / D converter 50 in the data register DATA of the register 80.

  The conversion data buffer 94 temporarily stores the digital value generated by the A / D converter 50. The error detection unit 96 determines whether there is an abnormality in the A / D converter 50 or the interface unit 82 based on the state of the access control unit 92. The error detection unit 96 detects the following errors, for example. When an error is detected, a predetermined value (for example, 1) may be written in the error notification register, and the CPU core 34 may be interrupted.

-Event error An event error is judged to have occurred when a new event that triggers the start of A / D conversion occurs during A / D conversion.

  Since high voltage needs to be handled in motor control, when unintended control is performed, it is necessary to detect it promptly and perform appropriate protection processing such as stopping the motor. By implementing an event error detection function in the error detection unit 96, it is possible to quickly detect at the hardware level that the relationship between events input to the ADC interface 46 is not properly controlled, and the circuit is protected. it can. Further, in the design stage of the device 1, detection of event error is very useful for debugging software or hardware design.

Next, the timing control of the A / D converter 50 will be described. In this embodiment, there are (1) operation start timing (2) k times A / D conversion timing as typical controllable timing of the control circuit 10.

  FIG. 9 is a diagram showing a control sequence of the A / D converter 50. The operation start corresponds to the start of one control cycle of the A / D converter 50 in a certain mode. When the start flag (START) is set in response to the start of the operation, the A / D converter 50 is in a state capable of executing k A / D conversions. In the control circuit 10 according to the embodiment, at least one of the operation start timing and the plurality of A / D conversion timings can be controlled by an event signal (timing signal) obtained from an internal signal.

  The control circuit 10 can switch between various modes. Hereinafter, modes of the control circuit 10 will be described. Since the three channels ch0 to ch2 are the same, only one channel will be described. The control register and the data register are provided for each channel.

<Buffer mode and normal mode>
The control circuit 10 according to the embodiment supports two modes of the buffer mode and the normal mode, and one of them can be designated by the value of the register MODE_BUF. In the two modes, the conversion data DOUT0 to DOUTn-1 are stored differently in the data registers DATA0 to DATAn-1.

-Mode buffer register (MODE_BUF)
Value 0: Normal mode Value 1: Buffer mode

  FIG. 10A is a diagram for explaining the operation of the access control unit 92 in the buffer mode. Port selection registers are also shown in FIG. In the buffer mode, the i-th (i = 1 to 8) conversion data DOUTi-1 is stored in the i-th data register (DATAi-1). In this buffer mode, data is stored in the n data registers in the order of conversion time series. In the buffer mode, the same analog port can be designated and the data can be acquired multiple times out of n times. The user may design the software with this in mind, which facilitates programming.

  FIG. 10B is a diagram for explaining the operation of the access control unit 92 in the normal mode. The value of the port selection register is the same as that in FIG. In the normal mode, the access control unit 92 refers to the port selection registers PORT_SEL0 to PORT_SEL7 to determine the storage destination of the conversion data DOUT to DOUT7. Specifically, the access control unit 92 stores the i-th conversion data DOUTi-1 in the data register DATAj corresponding to the corresponding port selection register PORT_SELi-1 value. For example, in FIG. 10B, attention is paid to the first conversion data DOUT0. Since the value of the corresponding port selection register PORT_SEL0 is 2, the conversion data DOUT0 is stored in the data register DATA2. Similarly, focusing on the second conversion data DOUT1, the value of the corresponding port selection register PORT_SEL1 is 4, so the conversion data DOUT1 is stored in the data register DATA4.

  That is, in the normal mode, the conversion data of the i-th analog port PORT-i is stored in the i-th data register DATAi-1. In the normal mode, the data of one analog port can be acquired only once per control cycle. The normal mode and the buffer mode can be selected according to the function required for the control circuit 10, and the flexibility of software control is provided.

<Hardware mode and software mode>
Regarding the operation start, the hardware mode and software mode described below are prepared. These modes can be specified by the value of the mode start register (MODE_START).

・ Mode start register (MODE_START)
0: Software mode 1: Hardware mode

In the software mode, the operation start is generated by software without depending on the state of hardware (that is, internal signal or event signal). A run register is provided to start the operation by software.
・ Run register (RUN)
Operation start by writing 1: 1 Specifically, when the CPU core 34 asserts the run register RUN (writes 1) based on software control, the operation of the A / D converter 50 is started by using it as a trigger. .

  In the hardware mode, after the run register RUN is asserted, the operation start is triggered by a predetermined state of the hardware. Specifically, when the start event signal EVT_START is input from the event selector 84 after 1 is written in the run register RUN, the operation of the A / D converter 50 is started by using that as a trigger. The start event signal EVT_START is one of the event signals output by the event selector 84.

  The following control registers are prepared for generating the start event signal EVT_START.

-Event selection register (EVENT_SEL)
0000: Select PWM_U 0001: Select PWM_V 0010: Select PWM_W 0011: Select #PWM_U 0100: Select #PWM_V 0101: Select #PWM_W 0110: Select P _{P / B} 0111: Select #P _{P / B} The internal signal to be the start event signal EVT_START is designated. It is used to control the event selector 84 of FIG. 3 (selector 88 of FIG. 8).

  The interface unit 82 generates the start timing signal TMG_START based on the start event signal EVT_START. The following control registers are prepared for generation of the start timing signal TMG_START.

-Edge selection register (EVENT_EDGE)
0: Positive edge 1: Negative edge Specifies whether the positive edge or the negative edge of the internal signal is used for generating the start event signal EVT_START. It is used to control the edge selector 100 of FIG.

  A combination of the event selection register EVENT_SEL and the edge selection register EVENT_EDGE specifies the event (start event) that triggers the operation start.

・ Delay setting register (EVENT_DELAY)
Specifies the delay time from the assertion of the start event signal EVT_START to the assertion of the start timing signal TMG_START. It is used to control the delay circuit 102 of FIG.

・ Delay enable register (EVENT_DELAY_EN)
The presence or absence of delay of the start timing signal TMG_START is designated. It is used to control the delay selector 104 of FIG.

A stop register (STOP) is provided to release the operation start.
・ Stop register (STOP)
1: Stops operation when 1 is written (start status is released)
The above is the description regarding the operation start.

<Auto mode and sequential mode>
Next, the conversion timing will be described. Two modes, that is, an auto mode and a sequential mode, are prepared in relation to the conversion timing, and the following control registers are prepared for the selection.

-Mode sequence register (MODE_SEQ)
0: Auto mode 1: Sequential mode

  The access control unit 92 automatically performs k / A conversions included in one control cycle in (i) auto mode. That is, the plurality of conversion timings CONV0 to CON7 are automatically generated by the access control unit 92 after the operation starts.

  In the (ii) sequential mode, the access control unit 92 executes k times of A / D conversion included in one control cycle each time an event occurs for each A / D conversion. Specifically, in the sequential mode, the event selector 84 of FIG. 8 sequentially generates the conversion event signals EVT0 to EVT7 following the start event signal EVT_START.

The following control registers are prepared for the conversion event signals EVT0 to EVT7.
-Individual event selection register (EVENT_SEL0-EVENT_SELn-1)
The respective internal signals to be the conversion event signals EVT0 to EVT7 are designated. The value is similar to EVENT_SEL and is used to control the event selector 84 in FIG. 3 (selector 88 in FIG. 8).

-Individual edge selection register (EVENT_EDGE0-EVENT_EDGE7)
0: Positive edge 1: Negative edge Specifies which of the positive edge and the negative edge of the internal signal is used to generate the conversion event signal EVT_CONV. It is used to control the edge selector 100 of FIG.

  A combination of the individual event selection register EVENT_SELi-1 and the individual edge selection register EVENT_EDGEi-1 specifies an event (conversion event) that triggers the i-th A / D conversion.

  The timing signal generation circuit 90 of FIG. 8 generates conversion timing signals TMG0 to TMG7 based on the conversion event signals EVT0 to EVT7 from the register 80. The following control registers are prepared for generation of the conversion timing signals TMG0 to TMG7.

・ Delay setting register (EVENT_DELAY0-EVENT_DELAY7)
Specify the delay time from the assertion of each conversion event signal EVTi to the assertion of the conversion timing signal TMGi. The value is similar to EVENT_DELAY and is used to control the delay circuit 102 in FIG.

・ Delay enable register (EVENT_DELAY_EN0-EVENT_DELAY_ENn-1)
The presence or absence of delay of each conversion event signal TMGi is designated. The value is similar to EVENT_DELAY_EN0 and is used to control the delay selector 104 in FIG.

  In the auto mode, A / D conversion can be performed n times automatically at the timing generated by the interface unit 82, which is useful in a situation where the A / D conversion timing is not so severe. In the sequential mode (manual mode), the timing (conversion timing) of each A / D conversion can be individually specified manually, and severe timing control can be supported.

<One time conversion mode and continuous conversion mode>
The access control unit 92 can select one-time conversion mode and continuous conversion mode described below. The following control registers are provided for switching between these modes.

・ Mode burst register (MODE_BURST)
0: Single conversion mode 1: Continuous conversion mode

  In the (i) single conversion mode, the access control unit 92 becomes the operation end when the conversion processing of k times is completed, the start flag (START) of FIG. 9 is negated once, and waits for the next operation start. In the software mode, the operation is started when the RUN register is written next. In the hardware mode, the operation is started by writing the RUN register and generating a start event.

  Further, in the (ii) continuous conversion mode, the access control unit 92 shifts to the next control cycle without waiting for the start of the next operation when the conversion processing of one control cycle is completed. That is, even after one control cycle ends, the state in which the start flag is set is maintained.

  In other words, in the single conversion mode, the operation start is requested every control cycle, whereas in the continuous conversion mode, the operation start is requested only for the first time. The additional flexibility is provided by the ability to select between the single conversion mode and the continuous conversion mode.

The above is the description of the modes supported by the control circuit 10. Subsequently, a specific operation of the control circuit 10 will be described. FIG. 11 is a waveform diagram showing a combination of the hardware mode and the sequential mode. When 1 is written to the RUN register at time t0, the circuit is enabled, but not in the hardware mode. Here, the bottom of PWM (the beginning of the PWM cycle) is designated as the start event. That is, the start timing signal TMG_START is generated based on the positive edge of the peak bottom pulse P _{P / B} , and the start state is reached at time t1. By selecting the bottom event, the control cycle of the A / D converter can be synchronized with the PWM operation.

  The first conversion is triggered by the negative edge event of the W-phase PWM signal, the second conversion is triggered by the negative edge event of the V-phase PWM signal, and the third conversion is triggered by the negative edge event of the U-phase PWM signal. Therefore, the conversion timing signals TMG_CONV1 to TMG_CONV3 are generated in response to each event. The same applies hereafter. When the set number of conversions (k times) have been completed, the start flag is negated and the non-start state is set. Then, when shifting to the next PWM cycle, a start timing signal is generated in response to the bottom event, and the start state is resumed.

  The present invention has been described above based on the embodiment. It should be understood by those skilled in the art that this embodiment is an exemplification, that various modifications can be made to the combinations of the respective constituent elements and the respective processing processes, and that such modifications are also within the scope of the present invention. is there. Hereinafter, such modified examples will be described.

  The number of phases of the motor is not particularly limited. The control circuit 10 can also be used in a system in which the mechanical state of the motor is directly monitored using a resolver or rotary encoder. In this case, the detection signal (speed signal or position signal) from the resolver may be input to any analog port.

2 ... Motor, 4 ... Driving device, 6 ... Inverter, 10 ... Control circuit, 12 ... A / D converter module, 14 ... Processor, 16 ... Pulse width modulator, 18 ... Program, 30 ... Digital arithmetic processing section, 31 ... Bus, 32 ... System platform, 34 ... CPU core, 36, 38 ... Memory controller, 40 ... Power management unit, 42 ... System controller, 44 ... Motor control block, 46 ... ADC interface, 48 ... Pulse width modulator, 50 ... A / D converter, 52 ... Multiplexer, 60 ... Memory, 62 ... Nonvolatile memory, 64 ... Volatile memory, 70 ... Clock generator, 80 ... Register, 82 ... Interface unit, 84 ... Event selector, 86 ... Peak bottom pulse Generator, 88 ... Selector, 90 ... Timin Signal generation circuit, 92 ... access control unit, 94 ... transform data buffer, 96 ... error detection section, 100 ... edge selector, 102 ... delay circuit, 104 ... delay selector, 106 ... asynchronous processing circuit.

Claims (13)

A motor control circuit,
A plurality of m (m is an integer of 2 or more) analog ports to which detection signals indicating the electric state of the motor can be input,
An A / D converter that has a multiplexer that receives a detection signal of each of the m analog ports, and that converts the detection signal selected by the multiplexer into digital data;
A processor capable of executing a software program and generating a drive command for the motor based on the digital data;
An interface circuit that controls the operation of the A / D converter in accordance with a control command from the processor and transfers the digital data to the processor;
Equipped with
One control cycle of the A / D converter by the interface circuit includes k (1 ≦ k ≦ n) A / D conversion in which n (n is an integer of 2 or more) is maximum.
The interface circuit is
A run register accessible to the processor ;
A mode start register which is accessible to the processor and which stores a value designating one of a software mode and a hardware mode;
N data registers accessible to the processor,
Of the n port selection registers accessible by the processor, the i-th (1 ≦ i ≦ n) port selection register selects the analog port to be selected by the multiplexer in the i-th A / D conversion. N port selection registers for storing the indicated values,
A mode buffer register which is accessible to the processor and which stores a value indicating one of a buffer mode and a normal mode;
Including,
The interface circuit is
(I) in the software mode, said processor asserts the run register, a trigger operation start of the A / D converter, (ii) in the hardware mode, at least one generated in the control circuit The internal signal of is used as a trigger to start the operation of the A / D converter, and in the buffer mode, the i-th digital data DOUT _i-1 is stored in the i-th data register, and in the normal mode, A control circuit for storing the i-th digital data DOUT _{i-1 in one} of the n data registers according to the value of a corresponding port selection register . The interface circuit is
Further comprising a timing signal generation circuit that generates a start timing signal based on a start event signal that is one of the at least one internal signal ,
Wherein in hardware mode, the start timing signal as a trigger for the operation start of the A / D converter, control circuit according to claim 1, wherein the benzalkonium controls the A / D converter. The interface circuit further comprises
An event selection register accessible to the processor ,
An event selector that receives a plurality of the internal signals, selects one according to a value stored in the event selection register, and outputs the start event signal,
Including,
The control circuit according to claim 2, wherein the timing signal generation circuit generates the start timing signal based on the start event signal. The interface circuit further comprises
A delay setting register that is accessible to the processor and stores a setting value of a delay time from the assertion of the start event signal to the assertion of the start timing signal in the hardware mode;
The timing signal generation circuit,
4. The control circuit according to claim 2, further comprising a delay circuit that delays the start event signal according to a set value of the delay setting register and outputs the start timing signal. One control cycle of the A / D converter by the interface circuit includes k (1 ≦ k ≦ n) A / D conversion in which n (n is an integer of 2 or more) is maximum.
The interface circuit further comprises
A mode burst register that is accessible to the processor and that stores a value designating one of a once conversion mode and a continuous conversion mode;
The interface circuit (i) waits for the start of the next operation when the conversion process of one control cycle is completed in the one-time conversion mode, and (ii) the conversion process of one control cycle is completed in the continuous conversion mode. Then, the control circuit according to any one of claims 1 to 4, wherein the control circuit shifts to the next control cycle without waiting for the start of the next operation. The interface circuit further comprises
The control circuit according to claim 5, further comprising a register that is accessible by the processor and that stores a value that specifies the number k of conversions included in the one control cycle. One control cycle of the A / D converter by the interface circuit includes k (1 ≦ k ≦ n) A / D conversion in which n (n is an integer of 2 or more) is maximum.
The interface circuit further comprises
A timing signal generation circuit for generating a conversion timing signal based on a conversion event signal, which is one of the at least one internal signal, for each A / D conversion;
An access control unit that controls the A / D converter by using the conversion timing signal for each A / D conversion as a trigger for the A / D conversion,
Including,
The control circuit according to claim 1, wherein the access control unit executes each of A / D conversions k times in the sequential mode by using a corresponding conversion timing signal as a trigger. The interface circuit further comprises
N individual event selection registers that are accessible to the processor and that store a value that individually specifies an internal signal to be a trigger for each of up to n A / D conversions;
A plurality of internal signals are received, and for each A / D conversion, one of the plurality of internal signals is selected according to a value stored in a corresponding one of the n individual event selection registers, and a conversion event is selected. An event selector that outputs a signal,
Including,
The control circuit according to claim 7, wherein the timing signal generation circuit generates the conversion timing signal based on the conversion event signal for each A / D conversion in the sequential mode. The interface circuit further comprises
A delay setting register that is accessible to the processor and stores a setting value of a delay time from the assertion of the conversion event signal to the assertion of the conversion timing signal for each of up to n A / D conversions;
The timing signal generation circuit,
A delay circuit for outputting the conversion timing signal by giving a delay corresponding to the set value of the corresponding delay setting register to the corresponding conversion event signal for each A / D conversion. 7. The control circuit according to 7 or 8. The interface circuit further comprises
A mode sequence register that is accessible to the processor and that stores a value that specifies one of auto mode and sequential mode;
10. The control circuit according to claim 7, wherein the interface circuit automatically executes k A / D conversions in the auto mode.   The control circuit according to claim 1, wherein the A / D converter includes a plurality of channels.   The control circuit according to claim 1, wherein the control circuit is integrated on one semiconductor substrate. A fan motor,
The control circuit according to claim 1, which drives the fan motor,
A fan characterized by comprising.

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