JP6686521B2 - Control system and control method - Google Patents

Description

  The present invention relates to a control system and a control method including a calculation module and an input module.

  A large-scale control system may employ a programmable controller in which necessary functions are distributed to a plurality of modules from the viewpoint of ease of system construction and maintenance. The programmable controller is composed of a plurality of types of modules such as an arithmetic module, a communication module, an input / output module (input module + output module), and a power supply module, and the number of each module can be changed according to the control target. , Maintenance and system extensibility are enhanced.

  In the programmable controller, for example, the communication module downloads the execution program for executing the application to the arithmetic module, the arithmetic module uses the downloaded execution program, and inputs the input data from the lower controlled device through the input / output module. The data is collected and arithmetic processing is executed, and the arithmetic result is transmitted to a lower controlled device through an input / output module (for example, Patent Document 1).

JP, 2014-120187, A

  As described above, in the programmable controller, the arithmetic module controls the other modules and the subordinate controlled devices by using the execution program. The processing of the arithmetic module based on such an execution program is roughly classified into an interrupt processing executed based on the satisfaction of an interrupt condition and a non-interrupt processing not subject to the time constraint of the interrupt processing. . The arithmetic module executes non-interrupt processing cyclically, and preferentially executes interrupt processing when the interrupt conditions are met, and effectively uses the extra time other than interrupt processing to perform non-interrupt processing. Was running.

  However, with the diversification of applications, the capacity of the execution program also increases, and the processing time of both interrupt processing and non-interrupt processing becomes long, making it difficult to complete within the expected processing time. . Here, if the cycle of the non-interruption process is simply lengthened, the frequency of updating the information also becomes low, resulting in deterioration of the control capability and resolution of the controlled device. In addition, since the processing result of the interrupt processing is also transmitted to the input / output module only periodically, the timing of transmitting the processing result of the interrupt processing is delayed as the cycle of the non-interrupt processing becomes longer.

  Therefore, in view of such a problem, the present invention provides a control system and a control method capable of preventing deterioration of control capability and resolution of a controlled device regardless of an increase in the capacity of an execution program. Has an aim.

In order to solve the above problems, the control system of the present invention includes an input module that inputs data from the outside, and an arithmetic module that is connected to the input module through a bus and performs an arithmetic operation based on the data received from the input module. Then, the program executed by the control system includes an interrupt program triggered by the satisfaction of the interrupt condition and a non-interrupt program excluding the interrupt program. A condition determination unit that determines whether the associated interrupt condition is satisfied, an interrupt program execution unit that executes the interrupt program when it is determined that the interrupt condition is satisfied, and an external comprising an AD converter for converting an analog signal into a digital signal, and AD control circuit for converting the control of the AD converter, the execution interrupt program When an arbitrary digital signal is required during the execution of the interrupt program, the AD control circuit executes the conversion control of the AD converter, and after the conversion of the AD converter is completed, normalizes only the arbitrary digital signal to obtain a normalized digital signal. Is generated and executes the interrupt program by the normalized digital signal, and the arithmetic module includes a non-interrupt program execution unit that refers to the execution result of the interrupt program execution unit and executes the non-interrupt program. And
The input module includes a DA converter that converts a digital signal into an analog signal and outputs the signal to the outside, and a DA control circuit that performs conversion control of the DA converter. The interrupt program execution unit is in the middle of executing the interrupt program. When an arbitrary digital signal is generated, only the arbitrary digital signal is denormalized to generate a denormalized digital signal, and the DA control circuit may be caused to execute the conversion control of the DA converter by the denormalized digital signal. .
In order to solve the above problems, the control system of the present invention includes an input module that inputs data from the outside, and an arithmetic module that is connected to the input module through a bus and performs an arithmetic operation based on the data received from the input module. Then, the program executed by the control system includes an interrupt program triggered by the satisfaction of the interrupt condition and a non-interrupt program excluding the interrupt program. A condition determination unit that determines whether the associated interrupt condition is satisfied, an interrupt program execution unit that executes the interrupt program when it is determined that the interrupt condition is satisfied, and an external The AD control circuit includes an AD converter that converts an analog signal into a digital signal, and an AD control circuit that controls conversion of the AD converter. The conversion control of the AD converter is executed in a cycle of, and the converted digital signal is held. The interrupt program execution unit holds the digital signal in the AD control circuit when an arbitrary digital signal is required during execution of the interrupt program. Generates a normalized digital signal by normalizing only an arbitrary digital signal, executes the interrupt program with the normalized digital signal, and the arithmetic module refers to the execution result of the interrupt program execution unit to execute the non-interrupt program. It is characterized by comprising a non-interruption program execution unit for executing.
The input module includes a DA converter that converts a digital signal into an analog signal and outputs the signal to the outside, and a DA control circuit that performs conversion control of the DA converter. The interrupt program execution unit is in the middle of executing the interrupt program. When an arbitrary digital signal is generated, only the arbitrary digital signal is denormalized to generate a denormalized digital signal, and the denormalized digital signal is held in the DA control circuit. The conversion control of the DA converter may be executed by the signal.

  A program duplication unit that duplicates the interrupt program in the input module may be further provided at a predetermined occasion.

  The predetermined trigger is when the arithmetic module and the input module are activated, and the program duplication unit may duplicate the interrupt program from the arithmetic module to the input module.

  The input module may further include a history notification unit that transmits information indicating that the interrupt processing is completed to the arithmetic module when the interrupt program execution unit completes the interrupt processing based on the interrupt program.

  The input module includes a first input module and a second input module, and the bus has a first bus connecting the arithmetic module and the first input module and a second bus connecting the arithmetic module and the second input module. The arithmetic module inputs data from the first input module through the first bus at every predetermined tact time, and the interrupt program execution unit of the second input module has a predetermined timing irrespective of the tact time. The data of the second input module may be input to the arithmetic module through the second bus.

  The arithmetic module outputs data to the first input module via the first bus at predetermined tact times and outputs data to the second input module via the second bus at a predetermined timing regardless of the tact time. May be.

  The first bus may be a serial transmission system and the second bus may be a parallel transmission system.

A book using a control system including an input module for inputting data from the outside to solve the above problem, and an arithmetic module connected to the input module through a bus and performing an arithmetic operation based on data received from the input module In the control method of the invention, the program executed by the control system includes an interrupt program triggered by the establishment of an interrupt condition and a non-interrupt program excluding the interrupt program, and the input module has: If it is determined whether the interrupt condition associated with the interrupt program is satisfied, and if it is determined that the interrupt condition is satisfied, the interrupt program is executed and any digital signal is executed during execution of the interrupt program. When a signal is required, the AD control circuit performs the conversion control of the AD converter that converts an external analog signal into a digital signal. To execute the conversion control data, after conversion completion of the AD converter to generate a normalized digital signal is normalized only arbitrary digital signals, executing an interrupt program by the normalized digital signals, computation module interrupt program The non-interruption program is executed by referring to the execution result of.
A book using a control system including an input module for inputting data from the outside to solve the above problem, and an arithmetic module connected to the input module through a bus and performing an arithmetic operation based on data received from the input module In the control method of the invention, the program executed by the control system includes an interrupt program triggered by the establishment of an interrupt condition and a non-interrupt program excluding the interrupt program, and the input module has: It is determined whether the interrupt condition associated with the interrupt program is satisfied. If it is determined that the interrupt condition is satisfied, the interrupt program is executed and the external analog signal is converted to a digital signal. An AD control circuit that performs conversion control of the AD converter executes conversion control of the AD converter at a predetermined cycle, and the converted digital signal When the input module holds an arbitrary digital signal during the execution of the interrupt program, the input module normalizes only the arbitrary digital signal held in the AD control circuit to generate a normalized digital signal. Is executed, the arithmetic module refers to the execution result of the interrupt program, and executes the non-interrupt program.

  According to the present invention, it is possible to prevent the control capability and resolution of the controlled device from deteriorating regardless of the increase in the capacity of the execution program.

It is an outline view showing a schematic connection relation of each device which constitutes a control system. It is an explanatory view showing a schematic structure of a control system. 6 is a timing chart for explaining the timing of processing based on an execution program. It is a figure which shows an example of the hardware constitutions of an arithmetic module. It is a figure which shows an example of the hardware constitutions of an input / output module. 6 is a timing chart illustrating a processing flow of the arithmetic module and the input / output module. It is an explanatory view for explaining processing of a program duplication part. It is an explanatory view for explaining a flow of processing of a non-interruption program execution part and an interruption program execution part. It is a block diagram showing a configuration of an input / output unit. 7 is a timing chart showing an example of processing of an interrupt program. 7 is a timing chart showing another example of the processing of the interrupt program. 9 is a timing chart showing still another example of the processing of the interrupt program. 6 is a timing chart for explaining an example of non-interruption processing. 9 is a timing chart for explaining another example of non-interrupt processing.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The dimensions, materials, and other specific numerical values shown in the embodiments are merely examples for facilitating the understanding of the invention, and do not limit the invention unless otherwise specified. In this specification and the drawings, elements having substantially the same function and configuration are denoted by the same reference numerals to omit redundant description, and elements not directly related to the present invention are omitted. To do.

(First embodiment: control system 100)
FIG. 1 is an external view showing a schematic connection relationship of each device constituting the control system 100, and FIG. 2 is an explanatory view showing a schematic configuration of the control system 100. The control system 100 includes a management device 110, a programmable controller 120, and a controlled device 130. The management device 110 and the programmable controller 120 are connected to each other by, for example, a network wiring 140 based on Ethernet (registered trademark) such as Giga (G) base. Further, the programmable controller 120 and the controlled device 130 are connected so as to be capable of communication and signal transmission through, for example, a dedicated connection wiring 142.

  The management device 110 collectively controls the plurality of programmable controllers 120 so that the entire control system 100 operates along the process defined by the application. For example, the management device 110 collects status information and control results from each programmable controller 120, and outputs various control commands to each programmable controller 120 according to the collected contents.

  The programmable controller 120 is also called a PLC (Programmable Logic Controller), and includes a plurality of modules such as a calculation module 122, a communication module 124, an input / output (I / O) module 126, and a power supply module 128 as shown in FIG. Composed of. In addition, each module is detachably fixed to the base board, and each module except the power supply module 128 is connected through a bus on the base board. As such a bus, for example, a first bus of a serial transmission system (not shown) and a second bus of a parallel transmission system (not shown) are prepared. In the present embodiment, the plurality of input / output modules 126 are connected to the arithmetic module 122 via either the first bus or the second bus.

  Here, the arithmetic module 122 downloads an execution program, which is a program divided for each programmable controller 120, from the management device 110 in order to realize an application defined in the control system 100, and executes the execution program. Alternatively, the operating status of the programmable controller 120 is displayed on a monitor (not shown). At that time, the controlled device 130 is controlled based on the control command received from the management device 110, the sensor detection result of the controlled device 130 input through the input / output module 126, and the like.

  The communication module 124 is connected to the management device 110, another programmable controller 120, and another module through the network wiring 140 of Ethernet (registered trademark), and can establish communication with each of them.

  The input / output module 126 is a module in which an input module that manages input from the controlled device 130 (external) and an output module that manages output to the controlled device 130 are combined. For example, when the controlled device 130 is a sensor, the sensor detection result is collected, and when the controlled device 130 is an electric motor, the control command represented by discrete is transmitted and the control result is collected. The power supply module 128 supplies power to each module such as the arithmetic module 122, the communication module 124, and the input / output module 126.

  The controlled device 130 is composed of, for example, a sensor that detects various states in FA (Factory Automation), an electric device that operates according to the detection result of the sensor, an electric device such as an encoder.

  Such a control system 100 can be applied to various controlled objects. For example, when the control system 100 is applied to a production execution system (MES), a motion control unit (Motion Control Unit), a center sealer unit (Center Sealer Unit), and a film unit as the controlled device 130. The programmable controller 120 is connected to a production device such as a (Film Unit). Then, the arithmetic module 122 of the programmable controller 120 takes in the operating state of the production equipment as input data from the input / output module 126, processes the input data using the execution program, and then issues a command to the production equipment through the input / output module 126. To do. Such an application is realized by the following execution program.

  FIG. 3 is a timing chart for explaining the timing of processing based on the execution program. In general, the processing of the arithmetic module 122 based on the execution program includes an interrupt processing executed based on the satisfaction of the interrupt condition in the input / output module 126 (processing triggered by the satisfaction of the interrupt condition). It is roughly divided into non-interrupt processing that is not subject to time restrictions due to interrupt processing. Here, a program used for interrupt processing is an interrupt program, and a program used for non-interrupt processing is a non-interrupt program. In the present embodiment, as the interrupt condition, a condition based on the input state (for example, the state of discrete signal or the count value) to the input / output module 126 will be described.

  The arithmetic module 122, for example, as shown in FIG. 3A, periodically executes non-interrupt processing using a non-interrupt program (for example, every tact time of 20 msec), and inputs data at the beginning of the cycle. Then, the processing result is output at the end of the cycle. Here, when the interrupt condition is satisfied in the input / output module 126, as shown in FIG. 3A, the arithmetic module 122 preferentially executes the interrupt process using the interrupt program, and executes the interrupt process other than the interrupt process. Non-interrupt processing is executed by effectively using the extra time. Specifically, when an interrupt process occurs, the non-interrupt process is suspended until the interrupt process ends, and the non-interrupt process is restarted after the interrupt process ends. Then, at the end of the cycle, the processing results of the interrupt processing and the non-interrupt processing are output.

  However, when the capacity of the execution program for realizing the application increases with the diversification of the application, as shown in FIG. 3B, the time spent for interrupt processing becomes long and the surplus time becomes short. On the other hand, similarly to the interrupt processing, the time spent for the non-interrupt processing becomes long, but the processing cannot be completed within the shortened dead time. Here, if the cycle of executing the non-interruption process is simply lengthened, the surplus time can be lengthened, but the frequency of updating information becomes low, and the controllability and resolution of the controlled device 130 deteriorate. . In particular, since the processing result of the interrupt processing is also transmitted to the input / output module 126 only periodically (only at the end of the cycle), an interrupt requiring an immediate reaction such as changing the control method when the predetermined upper and lower limit values are reached. Even in the case of processing, the reaction becomes slower as the cycle of non-interrupt processing becomes longer.

  Therefore, in the present embodiment, some or all of the interrupt processing is performed by another module (here, the input / output module 126), and the arithmetic module 122 mainly performs the non-interrupt processing (the remaining interrupt processing. Including distributed). For example, as shown in FIG. 3C, interrupt processing that occurs suddenly is completely executed in the input / output module 126, and in parallel, non-interrupt processing is periodically executed by the arithmetic module 122. . With this configuration, even if an interrupt process that requires an immediate response occurs, the interrupt process is executed quickly in the input / output module 126 without being affected by the cycle of the non-interrupt process in the arithmetic module 122, and Since the result can be reflected immediately, it is possible to prevent deterioration of the control capability and resolution of the controlled device 130, regardless of the increase in the capacity of the execution program.

  Further, in the present embodiment, an interrupt program for performing such an interrupt process is automatically arranged in the input / output module 126 at a predetermined timing such as at the time of starting. With such a configuration, it is possible to avoid a complicated installation work for each module, and it is possible to immediately start the interrupt process even when the input / output module 126 is newly installed or replaced. Hereinafter, the hardware configurations of the arithmetic module 122 and the input / output module 126 that achieve such an object will be described in detail.

(Operation module 122)
FIG. 4 is a diagram illustrating an example of the hardware configuration of the arithmetic module 122. The arithmetic module 122 shown in FIG. 4 includes an I / F unit 150, a non-volatile memory 152, a shared memory 154, a unique memory 156, and a control unit 158.

  The I / F unit 150 can establish communication with the communication module 124 and the input / output module 126 through the first bus and the second bus, and communicate with the management device 110 and other programmable controllers 120 through the communication module 124. it can.

  The non-volatile memory 152 is composed of a storage medium such as a ROM, an EEPROM, a flash memory, and an HDD, and holds a system program which is a basic program for operating a computer and an execution program (non-interruption program and interruption program). . The shared memory 154 is configured by a storage medium such as a RAM, and stores input data and output data updated by the control unit 158 executing the non-interruption program. The I / F unit 150, the non-volatile memory 152, and the shared memory 154 are connected via a common bus 160 so that they can be accessed. Therefore, the nonvolatile memory 152 and the shared memory 154 also accept access from other modules.

  For example, when a memory area that can be used as a shared work area is divided and assigned to each module, the shared memory 154 is associated with the assigned memory area. Therefore, the memory area allocated to the arithmetic module 122 does not have the memory of other modules, and when the memory area is accessed, only the shared memory 154 of the arithmetic module 122 can read or write data.

  Like the shared memory 154, the unique memory 156 is configured by a storage medium such as a RAM, and stores input data and internal data updated when the control unit 158 executes the non-interruption program. However, the unique memory 156 is not connected to the common bus 160 and can be accessed only from the control unit 158. Such access restriction to the memory can be realized by a decoder using an FPGA (Field-Programmable Gate Array) or the like.

  The control unit 158 is composed of a semiconductor integrated circuit including a central processing unit (CPU) and the like, reads a non-interruption program from the nonvolatile memory 152, expands it in the unique memory 156, and executes the non-interruption process. Then, the control unit 158 functions as a functional unit such as the program duplication unit 170, the non-interruption program execution unit 172, and the history management unit 174. The operation of such a functional unit will be described later in detail.

(I / O module 126)
FIG. 5 is a diagram showing an example of the hardware configuration of the input / output module 126. In this embodiment, a plurality of input / output modules 126 are prepared. Here, of the plurality of input / output modules 126, the input / output module 126 that operates at a relatively high speed will be described as an example. The input / output module 126 shown in FIG. 5 includes an I / F unit 180, a non-volatile memory 182, a shared memory 184, a unique memory 186, an input / output unit 188, and a control unit 190.

  The I / F unit 180 establishes communication with the arithmetic module 122, the communication module 124, and the input / output module 126 via the first bus and the second bus.

  The non-volatile memory 182 includes a storage medium such as a ROM, an EEPROM, a flash memory, and an HDD (Hard Disk Drive), and holds a system program. The shared memory 184 is configured by a storage medium such as a RAM, and stores an interrupt program that is a part of an execution program, input data, and output data updated by the control unit 190 executing the interrupt program. The I / F unit 180, the non-volatile memory 182, the shared memory 184, and the input / output unit 188 are connected by a common bus 192 so that they can be accessed. Therefore, the nonvolatile memory 182 and the shared memory 184 also accept access from other modules. However, it is preferable that each of the plurality of shared memories 184 is arranged in a module that frequently accesses the shared memory 184. For example, since the input / output module 126 has a high access frequency to the shared memory 184, the shared memory 184 is arranged in the input / output module 126.

  Like the shared memory 184, the unique memory 186 is configured by a storage medium such as a RAM, and stores input data and internal data updated by the control unit 190 executing an interrupt program. However, the unique memory 186 is not connected to the common bus 192 and can be accessed only from the control unit 190.

  The input / output unit 188 is connected to the controlled device 130 and performs communication and signal transmission with the controlled device 130. For example, the input / output unit 188 includes an FPGA, an AD converter, a DA converter, a photo coupler, a transistor, and the like, and inputs and outputs an analog signal, a digital signal, a rectangular wave (counter input), and the like. In particular, for analog signals, as described later, the FPGA performs individual conversion control for the AD converter and the DA converter, thereby achieving the distribution of the processing load.

  The control unit 190 is composed of a semiconductor integrated circuit including a central processing unit (CPU) or the like having the same specifications as the arithmetic module 122, reads an interrupt program from the shared memory 184, expands it in the unique memory 186, and executes the interrupt process. Run. Then, the control unit 190 also functions as functional units such as the condition determination unit 200, the interrupt program execution unit 202, and the history notification unit 204. The operation of such a functional unit will be described later in detail. Hereinafter, a flow of processing of the arithmetic module 122 and the input / output module 126 for performing the copying processing of the interrupt program to the input / output module 126 and the interrupt processing will be described.

(Program duplication processing S300)
FIG. 6 is a timing chart illustrating the flow of processing (control method) of the arithmetic module 122 and the input / output module 126. When the control system 100 is started and power supply to the arithmetic module 122 and the input / output module 126 is started, the control unit 158 of the arithmetic module 122 and the control unit 190 of the input / output module 126 each have a unique system program. Upon being activated, the program duplication unit 170 of the arithmetic module 122 duplicates the interrupt program of the execution programs stored in the non-volatile memory 152 to the input / output module 126 (S300). ). It should be noted that the interrupt program in the non-volatile memory 152 is not deleted by the duplication and is retained as it is.

  FIG. 7 is an explanatory diagram for explaining the processing of the program duplication unit 170. For example, the execution program in the control system 100 can be divided into six independent programs (not affected by other programs), the breakdown of which is three non-interruption programs and three interruption programs. Suppose However, at this point, the six programs have been compiled and are in the executable form. The program duplication unit 170 duplicates three of these interrupt programs to the input / output module 126 connected to the controlled device 130 controlled by the interrupt program.

  Here, each interrupt program is provided with a copy status, which is information about the interrupt process. Therefore, the program duplication unit 170 reads the duplication status attached to the interrupt program, and if the identifier of the I / O module 126 is registered as the duplication destination, the I / O module 126 specified by the identifier Duplicate the interrupt program associated with the duplication status. The input / output module 126 holds the interrupt program received from the arithmetic module 122 at a predetermined memory location in the shared memory 184. The duplication status includes an interrupt port number and an interrupt condition in addition to the identifier. Here, the interrupt port number indicates the number of the port (interrupt terminal) to be interrupted in the input / output unit 188, and the interrupt condition is a condition for generating an interrupt, such as an interrupt port number. It indicates a condition such as whether the generated discrete signal is TRUE or FALSE, or whether the count value obtained by counting the output signals of the servo or the like has reached a predetermined value.

  In the example of FIG. 7, since the identifiers of the interrupt program (1) and the interrupt program (2) are “1”, the program duplication unit 170 causes the interrupt program (1) and the interrupt program (2). Is copied to a predetermined memory location of the shared memory 184 of the input / output module (1) specified by the identifier “1”. Further, since the identifier of the interrupt program (3) is “2”, the program duplication unit 170 shares the interrupt program (3) with the input / output module (2) specified by the identifier “2”. Duplicate in memory 184.

  Subsequently, the program duplication unit 170 secures a memory area which is a work area of each interrupt program. Specifically, as shown in FIG. 7, the program duplication unit 170 duplicates the interrupt program (1) in the shared memory 184 of the input / output module (1) and determines the interrupt program (1) in advance. A memory area (1) having a large capacity is secured in the shared memory 184 of the input / output module (1). Similarly, the program duplication unit 170 secures a memory area (2) of a predetermined capacity for the interrupt program (2) in the shared memory 184 of the input / output module (1), and then the interrupt program (3). On the other hand, a memory area (3) having a predetermined capacity is secured in the shared memory 184 of the input / output module (2).

(Non-interruption program setting process S302)
FIG. 8 is an explanatory diagram for explaining the processing flow of the non-interruption program execution unit 172 and the interruption program execution unit 202. When the duplication of the interrupt program is completed as described above, the non-interrupt program execution unit 172 of the arithmetic module 122 prepares to execute the non-interrupt program. Specifically, the non-interruption program execution unit 172 reads out the non-interruption programs (1) to (3) from the non-volatile memory 152 and expands them in the unique memory 156, as shown in FIG.

(Interrupt program setting process S304)
Similarly, when the duplication of the interrupt program is completed as described above, the interrupt program execution unit 202 of the input / output module 126 prepares to execute the interrupt program. Specifically, as shown in FIG. 8, the interrupt program execution unit 202 of the input / output module (1) reads the interrupt programs (1) and (2) from the shared memory 184 and expands them in the unique memory 186. Similarly, the interrupt program execution unit 202 of the input / output module (2) reads the interrupt program (3) from the shared memory 184 and expands it in the unique memory 186.

(Non-interrupt program execution process S310)
Subsequently, the non-interruption program execution unit 172 executes the non-interruption program using the non-interruption program expanded in the unique memory 156. Here, the non-interruption program execution unit 172 refers to the execution result of the interrupt program execution unit 202 of the input / output module 126 described later (reads data from the shared memory 184) as necessary, and for example, every 20 msec. The execution result of the non-interruption program is derived.

(Condition determination processing S312)
The condition determination unit 200 determines whether or not the interrupt condition associated with the interrupt program is satisfied. Referring to the replication status in FIG. 7, in the present embodiment, the interrupt programs (1) to (3) are associated with interrupt conditions “1234”, “TRUE”, and “5678”, respectively. Therefore, the condition determination unit 200 of the input / output module (1) refers to the count value accumulated according to the operation of the servo or the like specified by the interrupt port number “1”, and the count value is “1234”. If it coincides with, it is determined that the interrupt condition of the interrupt program (1) is satisfied. Then, once it is determined that the interrupt condition is satisfied, the count value is reset to 0.

  Similarly, the condition determination unit 200 of the input / output module (1) refers to the discrete signal identified by the interrupt port number “3”, and if the discrete signal is TRUE, the interrupt determination of the interrupt program (2) is performed. It is determined that the inclusion condition is satisfied. The condition determination unit 200 of the input / output module (2) refers to the count value accumulated according to the operation of the servo or the like specified by the interrupt port number “1”, and the count value is “5678”. If it coincides with, it is determined that the interrupt condition of the interrupt program (3) is satisfied.

(Interrupt program execution process S314)
When the condition determination unit 200 determines that the predetermined interrupt condition is satisfied, the interrupt program execution unit 202 executes the interrupt program corresponding to the interrupt condition. For example, when the condition determination unit 200 of the input / output module (1) determines that the count value specified by the interrupt port number “1” has reached “1234”, the interrupt program execution unit 202 causes the interrupt program execution unit 202 to execute the interrupt program. Execute (1). Then, the interrupt program execution unit 202 stores the processing result of the interrupt processing based on the interrupt program (1) in the memory area (1) secured in the shared memory 184 by the program duplication unit 170. In this way, the non-interruption program execution unit 172 of the arithmetic module 122 can read the processing result from the shared memory 184 at an arbitrary timing.

  Here, the interrupt program execution unit 202 executes the interrupt program independently and with the highest priority without being restricted by the periodic processing by the non-interrupt program execution unit 172, and promptly reflects the processing result. be able to. Therefore, for example, for an interrupt process that requires an immediate reaction such that the control method is changed when a predetermined upper and lower limit value is reached, it is possible to shorten the reaction time. Further, since the non-interruption program execution unit 172 is not restricted (not affected by the cycle of non-interruption processing), the interrupt processing can be repeatedly executed in a time shorter than the cycle of non-interruption processing. It is also possible to implement interrupt processing with high frequency. In this way, it is possible to prevent the controllability and the resolution of the controlled device 130 from deteriorating despite the increase in the capacity of the execution program.

  Also, when an interrupt due to a discrete signal occurs in the input / output module 126, the input / output module 126 originally replaces the discrete signal with a bus signal and transmits the bus signal to the arithmetic module 122. When the interrupt process is performed after the determination, in the present embodiment, the process can be completed in the input / output module 126 without replacing with the bus signal, and therefore the time itself required for the interrupt process is shortened. be able to.

(History notification processing S316)
When the interrupt program execution unit 202 completes the interrupt process based on the interrupt program, the history notification unit 204 sends information indicating that the interrupt process is completed to the arithmetic module 122 accordingly. This is because the arithmetic module 122 manages whether or not the interrupt processing is performed as expected.

(History management process S318)
When the history management unit 174 receives the information indicating that the interrupt processing is completed from the history notification unit 204, the history management unit 174 manages the information as a history (log), and whether the number and timing of the interrupt processing fall within the expected range. If it is judged whether or not it deviates from the expected range, it is determined that an error has occurred in the interrupt process, and the error process is performed.

  In the control system 100 described above, the processing load of the calculation module 122 is increased by performing the distributed processing of the execution program by the calculation module 122 and the input / output module 126 even if the capacity of the execution program is increased. In addition, the interrupt process can be executed quickly at a timing independent of the non-interrupt process, and the control capability and resolution of the controlled device 130 can be prevented from deteriorating.

  In addition, since the interrupt program for performing such interrupt processing is automatically arranged in the input / output module 126 at the time of startup, it is possible to avoid complicated installation work for each module and to newly install the input / output module 126. Alternatively, even if the service is exchanged, the interrupt process can be started immediately. Therefore, even if the existing input / output module 126 is replaced with the shipping state input / output module 126 in which the execution program is not installed, the same state as the existing input / output module 126 can be quickly restored, thus improving maintainability. be able to.

(Second embodiment)
In this way, by distributing the processing that should originally be executed by the arithmetic module 122 to the input / output module 126, the processing load of the arithmetic module 122 itself can be reduced. However, on the other hand, the processing load of the input / output module 126 may increase by the processing load reduced by the arithmetic module 122. Therefore, the processing load of the input / output module 126, particularly the AD converter and the DA converter, is reduced, and the processing load of the input / output module 126 is reduced.

  FIG. 9 is a block diagram showing the configuration of the input / output unit 188. The input / output unit 188 of the input / output module 126 includes an AD converter 220, a DA converter 222, and an FPGA 224.

  The AD converter 220 converts an external analog signal into a digital signal. The DA converter 222 converts a digital signal into an analog signal and outputs it to the outside. The FPGA 224 also functions as an AD control circuit 224a that controls conversion of the AD converter 220 and a DA control circuit 224b that controls conversion of the DA converter. Further, the AD control circuit 224a is provided with a buffer for holding the digital signal converted by the AD converter 220, and the DA control circuit 224b is provided with a buffer for holding the digital signal to be converted by the DA converter 222. ing.

  FIG. 10 is a timing chart showing an example of the processing of the interrupt program. In the example of FIG. 10, the AD control circuit 224a and the DA control circuit 224b are mainly used, and AD conversion and DA conversion are repeated at a predetermined cycle (for example, 25 μsec), and the AD converter 220 generates a digital signal on the way. The interrupt program is executed at the trigger.

  Specifically, the AD control circuit 224a starts conversion control of the AD converter 220 at a time point (a) based on a predetermined cycle, holds the converted digital signal, and at the time point (b), the control unit 190. To normalize the digital signal to generate a normalized digital signal.

  Such normalization includes the following processes. That is, the AD control circuit 224a uses the control unit 190 to perform analog value adjustment processing for adjusting the offset and gain, which are the hardware characteristics of the AD converter 220, and the output value of the AD converter 220 (for example, 65536) in the use range of the interrupt program. Scale conversion processing for converting into (for example, 10000) and moving average processing showing an average of a plurality of past (for example, 8 or 16) digital values are performed.

  Since the AD converter 220 used here has a plurality of channels (for example, four channels) and it is not possible to know which channel's digital value is used by the interrupt program, normalization is applied to all the plurality of channels. However, the total time is increased by the number of channels.

  Then, when a series of processes for AD conversion is completed, the DA control circuit 224b denormalizes and denormalizes the digital signal held in the buffer of the DA control circuit 224b at the time point (c) through the control unit 190. A digital signal is generated, and conversion control of the DA converter 222 is executed by the denormalized digital signal. In this way, the DA converter 222 outputs an analog signal.

  Such denormalization includes the following processes. That is, the DA control circuit 224b is a scale conversion process for converting the use range (for example, 10000) of the interrupt program into the output value (for example, 65536) of the DA converter 222 through the control unit 190, and the hardware characteristic of the DA converter 222. Performs analog value adjustment processing to adjust offset and gain.

  Since the DA converter 222 used here has a plurality of (for example, four) channels and it is not possible to know which channel is required to be output by the interrupt program, denormalization is performed on all the plurality of channels. And the total time is extended by the number of channels.

  In this way, the AD control circuit 224a mainly operates the interrupt program while the AD conversion and the DA conversion are repeated at a predetermined cycle. Specifically, the AD control circuit 224a causes the control unit 190 to perform an interrupt process when the normalized digital signal is generated, and causes the interrupt program execution unit 202 to execute the interrupt program from time (d). Let Then, when the processing of the normalized digital signal is completed in the interrupt program, at the time point (e), the DA control circuit 224b holds the normalized digital signal, and the DA control circuit 224b displays the processing result of the interrupt program. It is reflected in the DA converter 222.

  However, in the control unit 190, since the AD converter 220 and the DA converter 222 are periodically performed at an accurate time, the normalization processing and the non-normalization processing for all channels of the digital signal are prioritized. Therefore, the asynchronous interrupt program is exclusively executed with the digital signal normalizing process and the non-normalizing process as indicated by hatching in FIG. 10, and as a result, the interrupt program is interrupted and restarted. Repeatedly, the time until the interrupt program is completed becomes long, and eventually the time when the processing result is reflected in the DA converter 222 is delayed.

  Therefore, in the present embodiment, the normalization process and the non-normalization process of the digital signal are kept to a necessary minimum, and even when the normalization process and the non-normalization process are executed, only the necessary channels are limited. This frees up time for the interrupt program.

  FIG. 11 is a timing chart showing another example of the processing of the interrupt program. In the example of FIG. 11, the interrupt program execution unit 202 of the control unit 190 serves as a main component, and performs minimum necessary AD conversion and DA conversion in response to a request from the interrupt program.

  Specifically, when the interrupt program execution unit 202 needs an arbitrary digital signal at the time (a) during execution of the interrupt program, the interrupt program execution unit 202 accesses, for example, the address of the analog signal connected to the AD converter 220. When AD is detected, the AD control circuit 224a is caused to execute the conversion control of the AD converter 220. Thus, the AD conversion is started from the time point (b).

  Then, when the conversion of the AD converter is completed, the AD control circuit 224a holds the converted digital signal at the time point (c) and normalizes the digital signal through the control unit 190 to generate a normalized digital signal. The normalization includes analog value adjustment processing, scale conversion processing, and moving average processing, as described with reference to FIG.

  However, here, of the plurality of channels provided in the AD converter 220, only the channel that requires a digital signal is normalized. Therefore, the processing time spent for the normalization processing is 1 / the number of channels (1/4 in this case) as compared with FIG. This is for the following reason. That is, as in the conventional case, when the interrupt processing is executed by the arithmetic module 122, the arithmetic module 122 cannot grasp which channel of the input / output module 126 the input / output requiring the digital signal corresponds to. In the example of 11, the interrupt processing is executed by the input / output module 126 itself, so that it is possible to grasp the correspondence between the input / output that requires the digital signal and the channel.

  Subsequently, the interrupt program execution unit 202 executes the interrupt program with the normalized digital signal, and at time (d), when an arbitrary digital signal is generated as a processing result, the arbitrary digital signal is denormalized. Then, a denormalized digital signal is generated and held in the buffer of the DA control circuit 224b. The denormalization includes scale conversion processing and analog value adjustment processing as described with reference to FIG.

  However, here, of the plurality of channels provided in the DA converter 222, only the channel for which the digital signal is output is denormalized. Therefore, the processing time spent for the denormalization processing is 1 / the number of channels (1/4 in this case) as compared with FIG.

  Finally, the interrupt program execution unit 202 causes the DA control circuit 224b to execute the conversion control of the DA converter 222 by the denormalized digital signal at the time point (e). In this way, the DA converter 222 outputs an analog signal.

  In the processing of FIG. 11, compared with the processing of FIG. 10, since AD conversion and DA conversion are not periodically performed, normalization processing and denormalization processing of digital signals accompanying the AD conversion and DA conversion are performed. I don't know. In addition, the control unit 190 takes the lead, executes normalization processing and denormalization processing only on necessary channels, and does not execute normalization processing and denormalization processing on other channels (the previous value is used as it is. ).

  Therefore, as shown by hatching in FIG. 11, it can be understood that the interrupt program is not interrupted by the normalization process or the non-normalization process, and the interrupt program ends in a shorter time than in FIG. 10. As described above, in the example of FIG. 11, it is possible to secure the execution time of the interrupt program and effectively use the resources.

  Also, in other processing, the normalization processing and the non-normalization processing of the digital signal are kept to a minimum, and even when the normalization processing and the non-normalization processing are executed, they are limited to only the necessary channels. As a result, the processing time can be released to the interrupt program.

  FIG. 12 is a timing chart showing still another example of the processing of the interrupt program. In the example of FIG. 12, the AD control circuit 224a and the DA control circuit 224b are the main components, and while the AD conversion and the DA conversion are repeated at a predetermined cycle (for example, 25 μsec), the interrupt program execution unit of the control unit 190 is in the middle thereof. The main unit 202 is to process digital signals in response to a request from the interrupt program.

  Specifically, the AD control circuit 224a starts conversion control of the AD converter 220 at a time point (a) based on a predetermined cycle, and holds the converted digital signal in a buffer. Further, the DA control circuit 224b controls the conversion of the DA converter 222 by the denormalized digital signal held in the buffer of the DA control circuit 224b at a time point (b) based on a predetermined cycle independent of the AD control circuit 224a. To execute. In this way, the DA converter 222 outputs an analog signal. Here, AD conversion and DA conversion excluding normalization processing and non-normalization processing are periodically performed.

  Then, the interrupt program execution unit 202 of the control unit 190, when an arbitrary digital signal is required at the time point (c) during the execution of the interrupt program, for example, with respect to the address of the analog signal connected to the AD converter 220, When the access is detected, the latest digital signal after conversion held in the AD control circuit 224a is read out at the time point (d), and the digital signal is normalized to generate a normalized digital signal. The normalization includes analog value adjustment processing, scale conversion processing, and moving average processing, as described with reference to FIG. Here, at the time point (d), the AD converter 220 has started the next conversion, but since the conversion result has not been generated, the previous conversion result is used.

  However, also here, of the plurality of channels provided in the AD converter 220, only the channel for which a digital signal is required is normalized. Therefore, the processing time spent for the normalization processing is 1 / the number of channels (1/4 in this case) as compared with FIG.

  Subsequently, the interrupt program execution unit 202 executes the interrupt program with the normalized digital signal, and when an arbitrary digital signal is generated as a processing result at the time point (e), the arbitrary digital signal is denormalized. Then, a denormalized digital signal is generated and held in the buffer of the DA control circuit 224b. The denormalization includes scale conversion processing and analog value adjustment processing as described with reference to FIG.

  However, also here, of the plurality of channels provided in the DA converter 222, only the channel for which the digital signal is output is denormalized. Therefore, the processing time spent for the denormalization processing is 1 / the number of channels (1/4 in this case) as compared with FIG.

  Then, the DA control circuit 224b executes the conversion control of the DA converter 222 by the denormalized digital signal held in the buffer.

  Even in the process of FIG. 12, the normalizing process and the denormalizing process of the digital signal are not periodically performed as compared with the process of FIG. Further, in AD conversion and DA conversion mainly performed by the control unit 190, normalization processing and denormalization processing are performed only on necessary channels, and normalization processing and denormalization processing are performed on other channels. Is not executed (the previous value is used as it is).

  Therefore, as shown by hatching in FIG. 12, the interrupt program is not interrupted by the normalization process or the non-normalization process, and the AD conversion is not waited. It can be understood that the processing is completed in a shorter time than in FIG. As described above, in the example of FIG. 12, the execution time of the interrupt program can be secured and the resources can be used more effectively.

  Moreover, since the load of the normalization process and the non-normalization process is minimized, the drive time of the control unit 190 is shortened, and heat generation and power consumption can be suppressed.

(Third Embodiment)
As described with reference to FIG. 3, the execution program is roughly divided into the interrupt program and the non-interrupt program, and the interrupt processing based on the interrupt program can be completely assigned to the input / output module 126. Then, the arithmetic module 122 can acquire the result of the interrupt processing from the input / output module 126 by the non-interrupt processing based on the non-interrupt program.

  FIG. 13 is a timing chart for explaining an example of non-interrupt processing. First, when the interrupt process occurs at the time point (a), the interrupt program execution unit 202 of the input / output module 126 executes arithmetic processing based on the interrupt program, and the processing result is obtained at the time point (b). It is held in the shared memory 184.

  Subsequently, the arithmetic module 122 periodically executes the non-interruption process based on the non-interruption program, and at the start time (c), acquires the input data from the shared memory 184 of the input / output module 126. Then, the input data is calculated at a time point (d) during the execution of the non-interruption program, and the output data as the calculation result is held in the shared memory 184 at the end time point (e) of the cycle. Finally, the interrupt program execution unit 202 of the input / output module 126 acquires output data from the shared memory 184 at an arbitrary time point (f).

  As described above, by periodically executing the non-interruption process, it becomes possible to accurately synchronize the input / output of data with the takt time. However, the input response time after the input data is generated and processed by the non-interrupt program, and the output response time after the non-interrupt program is processed until the output data is reflected become long. Such input response time and output response time are affected by the takt time. For example, if the number of input / output modules 126 or the number of input / outputs used by the input / output module 126 increases and the non-interrupt processing becomes longer accordingly, the takt time is inevitably lengthened. The time and output response time also become longer. Then, the control accuracy and responsiveness of the entire control system 100 may deteriorate.

  Here, when input / output responsiveness is required, the programmable controller 120 is separately provided, and in the independent programmable controller 120, arithmetic processing and the number of inputs / outputs are minimized to shorten the takt time. It is also conceivable to execute input / output processing at high speed and send / receive the result via the communication module 124. However, with this method, the control system 100 becomes large-scale.

  Therefore, in the programmable controller 120, a process that prioritizes synchronism over responsiveness and a process that prioritizes responsiveness over synchronism are separated, and a bus and an input / output module 126 are individually assigned to each. Specifically, as described above, a plurality of buses such as a serial transmission type first bus and a parallel transmission type second bus are prepared on the base board, and are connected to different input / output modules 126. Here, the serial transmission method is a method of sequentially transmitting information one bit at a time to a line having less than the number of bits of data, and the parallel transmission method is a method of transmitting all information to each line for at least a line having the number of bits of data. It is a method of transmitting data in parallel in parallel.

  For example, the arbitrary input / output module 126 (hereinafter, simply referred to as the first input / output module) is connected to the arithmetic module 122 through only the first bus, and any other input / output module 126 (hereinafter, simply referred to as the second input / output module). Is connected to the arithmetic module 122 through only the second bus. Then, the first input / output module (first input module) through the first bus is periodically processed as shown in FIG. 13, and the second input / output module (second input module) through the second bus is processed. As described below, high-speed processing is performed, and processing for prioritizing such synchronism and processing for prioritizing responsiveness are executed in parallel.

  FIG. 14 is a timing chart for explaining another example of the non-interrupt processing. Here, instead of the periodical processing described with reference to FIG. 13, an interrupt processing for starting the processing at the timing when the data is generated is performed. When the interrupt processing occurs at the time point (a), the interrupt program execution unit 202 of the input / output module 126 executes the arithmetic processing based on the interrupt program, and outputs the processing result to the shared memory at the time point (b). 184 is held and the operation module 122 is notified that the input data is ready (interrupt notification).

  Subsequently, the arithmetic module 122 executes the non-interrupt processing based on the non-interrupt program, and in response to the transmission from the input / output module 126, at the time point (c), the input data is input from the shared memory 184 of the input / output module 126. Is obtained, the input data is calculated, and the output data, which is the calculation result, is held in the shared memory 184 at the end point (d) of the cycle and the input / output module 126 is ready for the input data. Communicate (interrupt notification). Finally, the interrupt program execution unit 202 of the input / output module 126 acquires the output data from the shared memory 184 at the time point (e) in response to the transmission from the arithmetic module 122.

  Here, the interrupt notification is given at the timing when the data is generated, and the data is sent and received between the modules immediately after the data is generated, regardless of the tact time, so the input response time and output response time are shortened. It becomes possible to do.

  As described with reference to FIGS. 13 and 14, the following effects can be obtained by executing the processing that prioritizes synchronism over responsiveness and the processing that prioritizes responsiveness over synchronism in parallel. That is, the first input / output module via the first bus enables the input and output of data to be accurately synchronized with the tact time as in the conventional case. In addition, since the second input / output module through the second bus can reduce the input response time and the output response time, the number of input / output modules 126 and the number of input / outputs used by the input / output module 126 increase, and accordingly. Even if the non-interruption process becomes long and the takt time has to be lengthened, the control accuracy and responsiveness of the entire control system 100 can be improved.

  In this way, by adopting a plurality of transmission methods and utilizing the respective characteristics to distribute the input and output, it is possible to improve the processing efficiency and versatility of the control system 100 as a whole. In addition, both the synchronism and the responsiveness can be realized with a small number of modules by the small programmable controller 120.

  In addition, a program that causes a computer to function as the control system 100 and a computer-readable storage medium such as a computer-readable flexible disk, a magneto-optical disk, a ROM, a CD, a DVD, or a BD are also provided. Here, the program means a data processing unit described in an arbitrary language or a description method.

  The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but it goes without saying that the present invention is not limited to such embodiments. It is obvious to those skilled in the art that various changes or modifications can be conceived within the scope of the claims, and it should be understood that these also belong to the technical scope of the present invention. To be done.

  For example, in the above-described embodiment, for convenience of description, an example in which the input / output module 126 uses an interrupt program and the arithmetic module 122 uses a non-interrupt program excluding the interrupt program has been described. The interrupt program assigned to the output module 126 may be a part of all the interrupt programs included in the execution program, and the remaining interrupt programs can be used by the arithmetic module 122 itself. Therefore, the non-interruption program includes all programs except the interruption program assigned to the input / output module 126.

  Further, in the above-described embodiment, an example in which the program duplication unit 170 is provided in the arithmetic module 122 has been described, but the present invention is not limited to this case, and the input / output module 126, another module, or the management device 110 may be used. It may be equipped. Similarly, the example in which the interrupt program to be copied is held in the nonvolatile memory 152 of the arithmetic module 122 has been described, but the held memory may be any memory in the control system 100. Good. Further, in the above-described embodiment, an example in which the interrupt program is duplicated in the input / output module 126 has been described, but the non-interrupt program is held in any memory, and the non-interrupt program is triggered at a predetermined timing. May be duplicated in the computing module 122.

  Further, in the above-described embodiment, the case where the control system 100 is started has been described as the predetermined trigger for copying the interrupt program, but other arbitrary timings are not excluded, and various timings are selected. can do. In the above-described embodiment, an example in which the interrupt program is copied to the shared memory 184 of the input / output module 126 each time the control system 100 is activated has been described, but the input / output module 126 holds the interrupt program. If the memory to be executed is non-volatile, it may be determined whether or not the interrupt program has already been copied to the memory, and the interrupt program may be copied only when it has not been copied.

  In the above-described embodiment, the control system 100 has been described as an example, but it can be applied to various devices such as a distributed control device (DCS). Further, in the above-described embodiment, an example is given in which data is input from the outside through the input / output module 126 in which the input module and the output module are combined, but the output module is not an indispensable configuration, and at least the input module is required. For example, this embodiment can be applied.

  Further, in the above-described embodiment, an example in which the interrupt program of the execution programs is duplicated in the input / output module 126 and the interrupt processing is executed in the input / output module 126 has been described. When connected by two buses, a part of the interrupt processing can be further allocated to the arithmetic module 122 to distribute the interrupt processing.

  Further, in the above-described embodiments, the first bus of the serial transmission system and the second bus of the parallel transmission system have been described as the plurality of buses, but the present invention is not limited to such a case, and all the plurality of buses perform serial transmission. It may be a system or a parallel transmission system. Further, in the above-described embodiment, the example in which the input / output module 126 having the control unit 190 is connected to any of the buses has been described, but the input / output module 126 connected to the first bus that does not require responsiveness. May be an input / output module that manages input / output by an FPGA or the like that does not have the control unit 190.

  It should be noted that each step of the control method of the present specification does not necessarily have to be processed in time series in the order described as the timing chart, and may be processed in parallel or by a subroutine.

  INDUSTRIAL APPLICABILITY The present invention can be used for a control system and a control method including an arithmetic module and an input module.

100 control system 122 arithmetic module 126 input / output module (input module, first input module, second input module)
170 Program Duplication Unit 172 Non-Interrupt Program Execution Unit 174 History Management Unit 200 Condition Judgment Unit 202 Interrupt Program Execution Unit 204 History Notification Unit 220 AD Converter 222 DA Converter 224a AD Control Circuit 224b DA Control Circuit

Claims (12)

A control system comprising: an input module for inputting data from the outside; and an arithmetic module connected to the input module through a bus and performing an arithmetic operation based on data received from the input module,
The program executed by the control system includes an interrupt program triggered by the establishment of an interrupt condition and a non-interrupt program excluding the interrupt program,
The input module is
A condition determination unit that determines whether or not an interrupt condition associated with the interrupt program is satisfied,
When it is determined that the interrupt condition is satisfied, an interrupt program execution unit that executes the interrupt program,
An AD converter for converting an external analog signal into a digital signal,
An AD control circuit for controlling conversion of the AD converter;
Equipped with
The interrupt program execution unit,
When an arbitrary digital signal is required during execution of the interrupt program, the AD control circuit is caused to execute conversion control of the AD converter,
After the conversion of the AD converter is completed, only the arbitrary digital signal is normalized to generate a normalized digital signal,
Executing the interrupt program by the normalized digital signal,
The arithmetic module is
A control system comprising a non-interruption program execution unit for executing the non-interruption program with reference to the execution result of the interruption program execution unit. The input module includes a DA converter that converts a digital signal into an analog signal and outputs the analog signal to the outside, and a DA control circuit that performs conversion control of the DA converter.
The interrupt program execution unit,
When an arbitrary digital signal is generated during the execution of the interrupt program, only the arbitrary digital signal is denormalized to generate a denormalized digital signal,
The control system according to claim 1 , wherein the DA control circuit is caused to execute conversion control of the DA converter by the denormalized digital signal. A control system comprising: an input module for inputting data from the outside; and an arithmetic module connected to the input module through a bus and performing an arithmetic operation based on data received from the input module,
The program executed by the control system includes an interrupt program triggered by the establishment of an interrupt condition and a non-interrupt program excluding the interrupt program,
The input module is
A condition determination unit that determines whether or not an interrupt condition associated with the interrupt program is satisfied,
When it is determined that the interrupt condition is satisfied, an interrupt program execution unit that executes the interrupt program,
An AD converter for converting an external analog signal into a digital signal,
An AD control circuit for controlling conversion of the AD converter;
Equipped with
The AD control circuit is
The conversion control of the AD converter is executed at a predetermined cycle,
Hold the converted digital signal,
The interrupt program execution unit,
When an arbitrary digital signal is required during the execution of the interrupt program, only the arbitrary digital signal held in the AD control circuit is normalized to generate a normalized digital signal,
Executing the interrupt program by the normalized digital signal,
The arithmetic module is
A control system comprising a non-interruption program execution unit for executing the non-interruption program with reference to the execution result of the interruption program execution unit. The input module includes a DA converter that converts a digital signal into an analog signal and outputs the analog signal to the outside, and a DA control circuit that performs conversion control of the DA converter.
The interrupt program execution unit,
When an arbitrary digital signal is generated during the execution of the interrupt program, only the arbitrary digital signal is denormalized to generate a denormalized digital signal,
Holding the denormalized digital signal in the DA control circuit,
The DA control circuit is
The control system according to claim 3 , wherein conversion control of the DA converter is executed by the denormalized digital signal. The control system according to any one of claims 1 to 4, further comprising a program duplication unit that duplicates the interrupt program in the input module at a predetermined occasion. The predetermined trigger is when the arithmetic module and the input module are activated,
The control system according to claim 5 , wherein the program duplication unit duplicates the interrupt program from the arithmetic module to the input module. The input module further includes a history notification unit that transmits information indicating that the interrupt processing is completed to the arithmetic module when the interrupt program execution unit completes the interrupt processing based on the interrupt program. The control system according to any one of claims 1 to 6 . The input module includes a first input module and a second input module,
The bus includes a first bus connecting the arithmetic module and the first input module, and a second bus connecting the arithmetic module and the second input module,
The arithmetic module inputs data from the first input module through the first bus at every predetermined tact time,
The interrupt program execution unit of the second input module causes the data of the second input module to be input to the arithmetic module via the second bus at a predetermined timing irrelevant to the tact time. The control system according to any one of claims 1 to 7 . The arithmetic module is
Outputting data to the first input module through the first bus at every predetermined tact time,
9. The control system according to claim 8 , wherein data is output to the second input module through the second bus at a predetermined timing irrelevant to the takt time. The first bus is a serial transmission system,
Said second bus, the control system according to claim 8 or 9, characterized in that a parallel transmission scheme. A control method using a control system, comprising: an input module for inputting data from the outside; and an arithmetic module that is connected to the input module through a bus and performs an arithmetic operation based on data received from the input module.
The program executed by the control system includes an interrupt program triggered by the establishment of an interrupt condition and a non-interrupt program excluding the interrupt program,
The input module is
It is determined whether or not the interrupt condition associated with the interrupt program is satisfied,
If it is determined that the interrupt condition is satisfied, the interrupt program is executed,
When an arbitrary digital signal is required during the execution of the interrupt program, an AD control circuit that performs conversion control of an AD converter that converts an external analog signal into a digital signal is caused to execute conversion control of the AD converter.
After the conversion of the AD converter is completed, only the arbitrary digital signal is normalized to generate a normalized digital signal,
Executing the interrupt program by the normalized digital signal,
The arithmetic module is
A control method for executing the non-interruption program by referring to an execution result of the interruption program. A control method using a control system, comprising: an input module for inputting data from the outside; and an arithmetic module that is connected to the input module through a bus and performs an arithmetic operation based on data received from the input module.
The program executed by the control system includes an interrupt program triggered by the establishment of an interrupt condition and a non-interrupt program excluding the interrupt program,
The input module is
It is determined whether or not the interrupt condition associated with the interrupt program is satisfied,
If it is determined that the interrupt condition is satisfied, the interrupt program is executed,
An AD control circuit that performs conversion control of an AD converter that converts an external analog signal into a digital signal,
The conversion control of the AD converter is executed at a predetermined cycle,
Hold the converted digital signal,
The input module is
When an arbitrary digital signal is required during the execution of the interrupt program, only the arbitrary digital signal held in the AD control circuit is normalized to generate a normalized digital signal,
Executing the interrupt program by the normalized digital signal,
The arithmetic module is
A control method for executing the non-interruption program by referring to an execution result of the interruption program.

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