[go: up one dir, main page]

JP6677616B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

Info

Publication number
JP6677616B2
JP6677616B2 JP2016191663A JP2016191663A JP6677616B2 JP 6677616 B2 JP6677616 B2 JP 6677616B2 JP 2016191663 A JP2016191663 A JP 2016191663A JP 2016191663 A JP2016191663 A JP 2016191663A JP 6677616 B2 JP6677616 B2 JP 6677616B2
Authority
JP
Japan
Prior art keywords
frame
semiconductor device
manufacturing
sealing body
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2016191663A
Other languages
Japanese (ja)
Other versions
JP2018056369A (en
Inventor
清水　福美
福美 清水
晴彦 原田
晴彦 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2016191663A priority Critical patent/JP6677616B2/en
Priority to US15/660,294 priority patent/US9966329B2/en
Publication of JP2018056369A publication Critical patent/JP2018056369A/en
Application granted granted Critical
Publication of JP6677616B2 publication Critical patent/JP6677616B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67115—Apparatus for thermal treatment mainly by radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

本発明は、半導体装置の製造方法に関し、特に、半導体チップの下部に放熱板を内蔵した半導体装置の製造方法に適用して有効な技術に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a technique which is effective when applied to a method for manufacturing a semiconductor device having a built-in heat sink below a semiconductor chip.

特開２０１２−９４７０号公報（特許文献１）には、ダムバー切断前に、樹脂モールド工程におけるレジン未充填不良を検査する技術が開示されている。   Japanese Patent Application Laid-Open No. 2012-9470 (Patent Document 1) discloses a technique for inspecting a resin unfilling defect in a resin molding process before cutting a dam bar.

特開２０１０−５６３２５号公報（特許文献２）には、半導体チップの下部に、リードの先端部と重なる程度に広い放熱板を配置した半導体装置が開示されている。ただし、放熱板は、樹脂封止工程前に、リードフレームに連結されている。   Japanese Unexamined Patent Application Publication No. 2010-56325 (Patent Document 2) discloses a semiconductor device in which a heat radiating plate that is wide enough to overlap a tip end of a lead is arranged below a semiconductor chip. However, the heat sink is connected to the lead frame before the resin sealing step.

特開２０１２−９４７０号公報JP 2012-9470 A 特開２０１０−５６３２５号公報JP 2010-56325 A

特許文献１に記載されたように、ハロゲンフリー化の流れの中で、高流動性封止樹脂（たとえば、多環芳香族エポキシ樹脂の使用、可撓化剤の増量、シリカ等の充填材の微細化および球形化など）が多用される傾向にある。その場合、半導体チップの樹脂封止の際の溶融樹脂の流れが分散的となり、樹脂の未充填不良も特定の箇所に集中せず、様々な個所にばらばらに出現する傾向が高い。従って、封止体の全周（４辺）に渡って、未充填不良の検査をする必要がある。   As described in Patent Document 1, in a flow of halogen-free, a high-flowable sealing resin (for example, use of a polycyclic aromatic epoxy resin, an increase in the amount of a flexibilizing agent, and use of a filler such as silica, etc.) (Eg, miniaturization and spheroidization) tend to be frequently used. In this case, the flow of the molten resin at the time of resin sealing of the semiconductor chip becomes dispersive, and unfilling failure of the resin does not concentrate on a specific portion, but tends to appear in various places. Therefore, it is necessary to inspect for unfilled defects over the entire circumference (four sides) of the sealing body.

一方、半導体装置の高速化または高電力化を実現するために、放熱板を内蔵した半導体装置が使用されている。例えば、特許文献２のように、「かしめ技術」を用いて、樹脂封止工程前に放熱板をリードフレームに連結する方法が知られているが、この方法には、工程数が増加するため製造コストの増加、歩留りの低下という問題が内在している。   On the other hand, in order to realize higher speed or higher power of the semiconductor device, a semiconductor device having a built-in heat sink is used. For example, as in Patent Document 2, a method of connecting a heat sink to a lead frame before a resin sealing step using a “caulking technique” is known. However, this method increases the number of steps. There are inherent problems such as an increase in manufacturing cost and a decrease in yield.

そこで、本願発明者は、「かしめ技術」を用いることなく、複数のリードを保持するリードフレームと、放熱板を保持するフレーム（以下、「放熱フレーム」と呼ぶ）と、を重ねた状態で樹脂封止工程を実施する方法を検討している。しかしながら、このような製造方法では、放熱フレームの影響で、樹脂の未充填不良の検査を実施できず、半導体装置の信頼性が低下するという課題が明らかになった。   Therefore, the inventor of the present application has proposed a method in which a lead frame holding a plurality of leads and a frame holding a radiator plate (hereinafter, referred to as a “heat radiating frame”) are stacked on top of each other without using a caulking technique. A method for implementing the sealing step is being studied. However, in such a manufacturing method, the problem that the inspection of the resin unfilled defect cannot be performed due to the influence of the heat radiation frame and the reliability of the semiconductor device is reduced has become apparent.

つまり、放熱板を内蔵した半導体装置の信頼性の向上が求められている。   That is, there is a demand for improvement in reliability of a semiconductor device having a built-in heat sink.

その他の課題と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   Other problems and novel features will be apparent from the description of this specification and the accompanying drawings.

一実施の形態による半導体装置の製造方法は、半導体チップを搭載したリードフレームを準備する工程と、放熱板を有する放熱フレームを準備する工程と、リードフレームと放熱フレームとを積層した状態で、半導体チップおよび放熱板を樹脂封止する工程と、を有する。そして、放熱フレームの枠体を、封止体を有するリードフレームから分離する工程の後に、封止体を有するリードフレームに対して、樹脂の未充填領域有無の検査を実施する。   A method of manufacturing a semiconductor device according to one embodiment includes a step of preparing a lead frame on which a semiconductor chip is mounted, a step of preparing a heat radiating frame having a heat radiating plate, and a method of stacking the lead frame and the heat radiating frame. Sealing the chip and the heat sink with resin. Then, after the step of separating the frame of the heat dissipation frame from the lead frame having the sealing body, the lead frame having the sealing body is inspected for the presence or absence of a resin unfilled area.

一実施の形態によれば、放熱板を内蔵した半導体装置の信頼性を向上することができる。   According to one embodiment, the reliability of a semiconductor device having a built-in heat sink can be improved.

一実施の形態の半導体装置の平面図である。FIG. 1 is a plan view of a semiconductor device according to one embodiment. 図１のＡ−Ａ線における断面図である。It is sectional drawing in the AA line of FIG. 一実施の形態の半導体装置のプロセスフロー図である。FIG. 3 is a process flow chart of the semiconductor device of one embodiment. 図３に示すリードフレーム準備工程のリードフレームの平面図である。FIG. 4 is a plan view of the lead frame in a lead frame preparation step shown in FIG. 3. 図４のＢ−Ｂ線における断面図である。FIG. 5 is a sectional view taken along line BB of FIG. 4. 図４のＣ−Ｃ線における断面図である。FIG. 5 is a sectional view taken along line CC of FIG. 4. 図３に示す放熱フレーム準備工程の放熱フレームの平面図である。FIG. 4 is a plan view of a heat radiation frame in a heat radiation frame preparation step shown in FIG. 3. 図７のＤ−Ｄ線における断面図である。It is sectional drawing in the DD line of FIG. 図７のＥ−Ｅ線における断面図である。It is sectional drawing in the EE line of FIG. 図３に示す樹脂封止工程の断面図（図４のＢ−Ｂ線に対応）である。FIG. 4 is a cross-sectional view (corresponding to line BB in FIG. 4) of the resin sealing step shown in FIG. 3. 図３に示す樹脂封止工程の断面図（図４のＣ−Ｃ線に対応）である。FIG. 4 is a cross-sectional view (corresponding to line CC in FIG. 4) of the resin sealing step shown in FIG. 3. 図３に示す樹脂封止工程の平面図である。FIG. 4 is a plan view of a resin sealing step shown in FIG. 3. 図３に示す樹脂封止工程完了後の平面図である。FIG. 4 is a plan view after the resin sealing step shown in FIG. 3 is completed. 図１３のＨ−Ｈ線における断面図である。It is sectional drawing in the HH line of FIG. 図３に示すゲート部樹脂切断工程における断面図（図４のＣ−Ｃ線に対応）である。FIG. 4 is a cross-sectional view (corresponding to line CC in FIG. 4) of the gate portion resin cutting step shown in FIG. 3. 図３に示す放熱フレーム分離工程における断面図（図４のＣ−Ｃ線に対応）である。FIG. 4 is a cross-sectional view (corresponding to line CC in FIG. 4) in a heat-radiating frame separating step shown in FIG. 3. 図３に示す放熱フレーム分離工程における断面図（図４のＢ−Ｂ線に対応）である。FIG. 4 is a cross-sectional view (corresponding to line BB in FIG. 4) in a heat radiation frame separating step illustrated in FIG. 3. 図３に示す検査工程における断面図である。FIG. 4 is a sectional view in an inspection step shown in FIG. 3. 図３に示す検査工程における検査領域の一部拡大平面図である。FIG. 4 is a partially enlarged plan view of an inspection area in an inspection step shown in FIG. 3. 図３に示すダム部切断工程における平面図である。FIG. 4 is a plan view in a dam section cutting step shown in FIG. 3. 図３に示すリード形成工程における平面図である。FIG. 4 is a plan view in a lead forming step shown in FIG. 3.

以下の実施の形態においては便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明等の関係にある。   In the following embodiments, when necessary for the sake of convenience, the description will be made by dividing into a plurality of sections or embodiments, but unless otherwise specified, they are not irrelevant to each other, and one is the other. Of some or all of the above, details, supplementary explanations, and the like.

また、以下の実施の形態において、要素の数等（個数、数値、量、範囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でもよい。   Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), a case where it is particularly specified and a case where it is clearly limited to a specific number in principle, etc. Except, the number is not limited to the specific number, and may be more than or less than the specific number.

さらに、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。   Furthermore, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be essential in principle. Needless to say.

同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうではないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲についても同様である。   Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of the constituent elements, etc., unless otherwise specified, and in principle, it is considered that it is not clearly apparent in principle, etc. It shall include those that are similar or similar to the shape and the like. This is the same for the above numerical values and ranges.

また、実施の形態を説明するための全図において、同一の部材には原則として同一の符号を付し、その繰り返しの説明は省略する。なお、図面をわかりやすくするために平面図であってもハッチングを付す場合がある。   In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals in principle, and the repeated description thereof will be omitted. Note that hatching may be used even in a plan view so as to make the drawings easy to understand.

（実施の形態）
本実施の形態では、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）型半導体装置を例に説明する。 (Embodiment)
In this embodiment, a QFP (Quad Flat Package) type semiconductor device will be described as an example.

＜半導体装置＞
まず、本実施の形態の半導体装置ＳＤの構成について、図１および図２を用いて説明する。図１は本実施の形態の半導体装置の平面図である。 <Semiconductor device>
First, the configuration of the semiconductor device SD of the present embodiment will be described with reference to FIGS. FIG. 1 is a plan view of the semiconductor device of the present embodiment.

図１に示すように、本実施の形態の半導体装置ＳＤは、四角形の封止体１と複数本のリード１２とを有する。封止体１は、４つの辺を有し、各辺において、辺に直交する方向に延在するように複数本のリード１２が封止体１から突出している。   As shown in FIG. 1, the semiconductor device SD of the present embodiment has a rectangular sealing body 1 and a plurality of leads 12. The sealing body 1 has four sides, and in each side, a plurality of leads 12 project from the sealing body 1 so as to extend in a direction orthogonal to the sides.

図１では、封止体１で覆われた半導体チップ２、チップ搭載部１５および放熱板２２を破線で示している。封止体１の中央部分には、四角形の半導体チップ２が配置されている。後述するが、半導体チップ２は、四角形のチップ搭載部１５上に配置されており、チップ搭載部１５の下には、円形の放熱板２２が配置されている。   In FIG. 1, the semiconductor chip 2 covered with the sealing body 1, the chip mounting portion 15, and the heat sink 22 are indicated by broken lines. A square semiconductor chip 2 is arranged at the center of the sealing body 1. As will be described later, the semiconductor chip 2 is disposed on a square chip mounting portion 15, and a circular heat radiating plate 22 is disposed below the chip mounting portion 15.

平面視にて、Ｘ方向およびＹ方向において、四角形のチップ搭載部１５は、四角形の半導体チップ２より大きい。つまり、Ｘ方向およびＹ方向において、チップ搭載部１５の一辺は、半導体チップ２の一辺よりも大きい。そして、半導体チップ２は、チップ搭載部１５からはみ出すことなく、チップ搭載部１５の内側に配置されている。ここで、Ｘ方向とＹ方向は、互いに直交し、図１の紙面の横方向をＸ方向、縦方向をＹ方向とするが、他の図面でも同様とする。   In plan view, the square chip mounting portion 15 is larger than the square semiconductor chip 2 in the X direction and the Y direction. That is, one side of the chip mounting portion 15 is larger than one side of the semiconductor chip 2 in the X direction and the Y direction. The semiconductor chip 2 is arranged inside the chip mounting section 15 without protruding from the chip mounting section 15. Here, the X direction and the Y direction are orthogonal to each other, and the horizontal direction on the paper surface of FIG. 1 is the X direction and the vertical direction is the Y direction, but the same applies to other drawings.

また、Ｘ方向およびＹ方向において、円形の放熱板２２は、チップ搭載部１５より大きい。すなわち、放熱板２２の面積は、チップ搭載部１５の面積より大きい。つまり、Ｘ方向およびＹ方向において、放熱板２２の直径は、チップ搭載部１５の一辺よりも大きい。そして、チップ搭載部１５は、放熱板２２からはみ出すことなく、放熱板２２の内側に配置されている。   In the X direction and the Y direction, the circular heat sink 22 is larger than the chip mounting portion 15. That is, the area of the heat sink 22 is larger than the area of the chip mounting portion 15. That is, in the X direction and the Y direction, the diameter of the heat sink 22 is larger than one side of the chip mounting portion 15. The chip mounting portion 15 is disposed inside the heat sink 22 without protruding from the heat sink 22.

なお、四角形とは、略四角形も含み、例えば、四角形の角部が面取りされた形状も含む。また、放熱板２２は、円形に限定されず、四角形、８角形等の多角形でも良い。   In addition, the quadrangle includes a substantially quadrangle, and also includes, for example, a shape in which a corner of the quadrangle is chamfered. Further, the heat radiating plate 22 is not limited to a circle, but may be a polygon such as a quadrangle or an octagon.

この半導体装置ＳＤは、放熱板を内蔵したＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）型半導体装置である。   The semiconductor device SD is a QFP (Quad Flat Package) type semiconductor device having a built-in heat sink.

図２は、図１のＡ−Ａ線に沿った断面図である。半導体装置ＳＤは、半導体チップ２、複数本のリード１２、チップ搭載部（タブ）１５、放熱板２２および封止体１を有する。   FIG. 2 is a sectional view taken along line AA of FIG. The semiconductor device SD has a semiconductor chip 2, a plurality of leads 12, a chip mounting portion (tab) 15, a heat radiating plate 22, and a sealing body 1.

半導体チップ２は、例えば、シリコン（Ｓｉ）からなる半導体基板で構成され、複数の半導体素子、複数の配線、および、複数のパッド電極（端子、外部電極、外部引出電極）３を有する。半導体素子は、例えば、ＭＩＳＦＥＴ（Ｍｅｔａｌ Ｉｎｓｕｌａｔｏｒ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）であり、配線およびパッド電極３は、例えば、銅（Ｃｕ）またはアルミニウム（Ａｌ）を主成分とする金属膜からなる。半導体チップ２の主面２ａには、複数の半導体素子と複数のパッド電極３が形成されている。複数の半導体素子は、複数の配線（金属配線）により接続されて回路ブロックを構成し、回路ブロックは、配線を介してパッド電極３と電気的に接続されている。そして、複数のパッド電極３は、複数のリード１２と電気的に接続されている。パッド電極３は、例えば、金（Ａｕ）または銅（Ｃｕ）を主成分とするワイヤ（ボンディングワイヤ）４により、例えば、銅（Ｃｕ）を主成分とするリード１２に接続されている。   The semiconductor chip 2 is composed of, for example, a semiconductor substrate made of silicon (Si), and has a plurality of semiconductor elements, a plurality of wirings, and a plurality of pad electrodes (terminals, external electrodes, external lead electrodes) 3. The semiconductor element is, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor), and the wiring and the pad electrode 3 are made of, for example, a metal film mainly containing copper (Cu) or aluminum (Al). On the main surface 2a of the semiconductor chip 2, a plurality of semiconductor elements and a plurality of pad electrodes 3 are formed. The plurality of semiconductor elements are connected by a plurality of wires (metal wires) to form a circuit block, and the circuit block is electrically connected to the pad electrodes 3 via the wires. The pad electrodes 3 are electrically connected to the leads 12. The pad electrode 3 is connected to, for example, a lead 12 mainly containing copper (Cu) by a wire (bonding wire) 4 mainly containing gold (Au) or copper (Cu).

高流動性封止樹脂（例えば、多環芳香族エポキシ樹脂などのエポキシ樹脂）からなる封止体１は、半導体チップ２、ワイヤ４、リード１２、チップ搭載部１５、接着層５、および、放熱板２２を覆っている。半導体チップ２は、接着層５によりチップ搭載部１５に接着されている。封止体１は、平坦な主面１ａ、平坦な裏面１ｂ、および、主面１ａと裏面１ｂ間を繋ぐ側面１ｃを有している。半導体装置ＳＤを実装基板に実装した状態で、主面１ａおよび裏面１ｂは、実装面ＭＢに対して平行となる。なお、半導体装置ＳＤを実装基板に実装した状態で、実装面ＭＢに近い側を封止体１の裏面１ｂ、遠い側を封止体１の主面１ａと定義する。   A sealing body 1 made of a high fluidity sealing resin (for example, an epoxy resin such as a polycyclic aromatic epoxy resin) includes a semiconductor chip 2, wires 4, leads 12, a chip mounting portion 15, an adhesive layer 5, and heat radiation. The plate 22 is covered. The semiconductor chip 2 is adhered to the chip mounting portion 15 by the adhesive layer 5. The sealing body 1 has a flat main surface 1a, a flat back surface 1b, and a side surface 1c connecting the main surface 1a and the back surface 1b. With the semiconductor device SD mounted on the mounting board, the main surface 1a and the back surface 1b are parallel to the mounting surface MB. In a state where the semiconductor device SD is mounted on the mounting board, a side closer to the mounting surface MB is defined as a back surface 1b of the sealing body 1 and a side farther from the mounting surface MB is defined as a main surface 1a of the sealing body 1.

複数のリード１２は、半導体チップ２を取り囲むように配置されており、半導体チップ２を中心に放射状に延在している。複数のリード１２は、基材である銅（Ｃｕ）で構成されており、各々のリード１２は、封止体１の主面１ａ側である主面と、封止体１の裏面１ｂ側である裏面とを有する。リード１２は、封止体１の内部に位置するインナーリード部ＩＬとアウターリード部ＯＬとからなり、アウターリード部ＯＬの主面および裏面は、半田メッキ膜１２ｍで覆われている。   The plurality of leads 12 are arranged so as to surround the semiconductor chip 2, and extend radially around the semiconductor chip 2. The plurality of leads 12 are formed of copper (Cu) as a base material. Each of the leads 12 has a main surface that is a main surface 1a side of the sealing body 1 and a back surface 1b side of the sealing body 1. And a certain back surface. The lead 12 includes an inner lead portion IL and an outer lead portion OL located inside the sealing body 1, and a main surface and a back surface of the outer lead portion OL are covered with a solder plating film 12m.

また、アウターリード部ＯＬは、ガルウイング形状を有し、インナーリード部ＩＬから連続して、直線的に、封止体１の外部に突出する突出部Ｐ１と、突出部Ｐ１から実装面ＭＢに向かって延びる屈曲部Ｐ２と、実装面ＭＢに対してほぼ平行に屈曲部Ｐ２から延在し、実装半田を介して実装基板に接続される接続部Ｐ３とを有している。図２では、リード１２の裏面側を用いて突出部Ｐ１、屈曲部Ｐ２および接続部Ｐ３を定義しているが、主面側でも同様の定義となる。リード１２の裏面において、アウターリード部ＯＬは、突出部Ｐ１、屈曲部Ｐ２、および、接続部Ｐ３で構成されている。   Further, the outer lead portion OL has a gull wing shape, and continuously and linearly projects from the inner lead portion IL to the outside of the sealing body 1 and from the projection portion P1 toward the mounting surface MB. And a connecting portion P3 extending from the bending portion P2 substantially parallel to the mounting surface MB and connected to the mounting board via mounting solder. In FIG. 2, the protruding portion P1, the bent portion P2, and the connecting portion P3 are defined using the back surface side of the lead 12, but the same definition is applied to the main surface side. On the back surface of the lead 12, the outer lead portion OL includes a protruding portion P1, a bent portion P2, and a connection portion P3.

放熱板２２は、銅（Ｃｕ）を主成分とする板状部材であり、その主面は、チップ搭載部１５の裏面に接触して配置されている。放熱板２２およびチップ搭載部１５において、封止体１の主面１ａ側の面を主面と呼び、封止体１の裏面１ｂ側の面を裏面と呼ぶ。また、後述するリードフレームおよび放熱フレームでも、同様に、封止体１の主面１ａ側の面を主面と呼び、封止体１の裏面１ｂ側の面を裏面と呼ぶ。   The heat radiating plate 22 is a plate-shaped member mainly composed of copper (Cu), and its main surface is arranged in contact with the back surface of the chip mounting portion 15. In the heat radiating plate 22 and the chip mounting portion 15, the surface on the main surface 1a side of the sealing body 1 is called a main surface, and the surface on the back surface 1b side of the sealing body 1 is called a back surface. Similarly, in the lead frame and the heat dissipation frame described later, the surface on the main surface 1a side of the sealing body 1 is called the main surface, and the surface on the back surface 1b side of the sealing body 1 is called the back surface.

図２に示すように、放熱板２２は、リード１２のインナーリード部ＩＬの一部と重なっている。つまり、放熱板２２は、インナーリード部ＩＬの一部と重なる程度に、大きくしているが、封止体１の外形よりも小さく、放熱板２２の端部は封止体１の内部で終端している。また、放熱板２２の裏面は、封止体１で覆われているが、放熱板２２の裏面を封止体１の裏面１ｂから露出させた構造としても良い。   As shown in FIG. 2, the heat radiating plate 22 overlaps a part of the inner lead portion IL of the lead 12. That is, the heat radiating plate 22 is large enough to overlap a part of the inner lead portion IL, but smaller than the outer shape of the sealing body 1, and the end of the heat radiating plate 22 is terminated inside the sealing body 1. doing. Further, the back surface of the heat radiating plate 22 is covered with the sealing body 1, but may have a structure in which the back surface of the heat radiating plate 22 is exposed from the back surface 1 b of the sealing body 1.

＜半導体装置の製造方法＞
次に、本実施の形態の半導体装置ＳＤの製造方法を、図３を用いて説明する。図３は、半導体装置ＳＤのプロセスフロー図である。図４は、図３に示すリードフレーム準備工程のリードフレームの平面図である。図５は、図４のＢ−Ｂ線に沿う断面図である。図６は、図４のＣ−Ｃ線における断面図である。図７は、図３に示す放熱フレーム準備工程の放熱フレームの平面図である。図８は、図７のＤ−Ｄ線に沿う断面図である。図９は、図７のＥ−Ｅ線における断面図である。図１０は、図３に示す樹脂封止工程の断面図（図４のＢ−Ｂ線に対応）である。図１１は、図３に示す樹脂封止工程の断面図（図４のＣ−Ｃ線に対応）である。図１２は、図３に示す樹脂封止工程の平面図である。図１３は、図３に示す樹脂封止工程完了後の平面図である。図１４は、図１３のＨ−Ｈ線における断面図である。図１５は、図３に示すゲート部樹脂切断工程における断面図（図４のＣ−Ｃ線に対応）である。図１６は、図３に示す放熱フレーム分離工程における断面図（図４のＣ−Ｃ線に対応）である。図１７は、図３に示す放熱フレーム分離工程における断面図（図４のＢ−Ｂ線に対応）である。図１８は、図３に示す検査工程における断面図である。図１９は、図３に示す検査工程における検査領域の一部拡大平面図である。図２０は、図３に示すダム部切断工程における平面図である。図２１は、図３に示すリード成形工程における平面図である。 <Semiconductor device manufacturing method>
Next, a method for manufacturing the semiconductor device SD of the present embodiment will be described with reference to FIG. FIG. 3 is a process flow diagram of the semiconductor device SD. FIG. 4 is a plan view of the lead frame in the lead frame preparation step shown in FIG. FIG. 5 is a sectional view taken along line BB of FIG. FIG. 6 is a cross-sectional view taken along line CC of FIG. FIG. 7 is a plan view of the heat radiating frame in the heat radiating frame preparing step shown in FIG. FIG. 8 is a sectional view taken along the line DD of FIG. FIG. 9 is a sectional view taken along line EE of FIG. FIG. 10 is a sectional view (corresponding to line BB in FIG. 4) of the resin sealing step shown in FIG. FIG. 11 is a cross-sectional view (corresponding to the line CC in FIG. 4) of the resin sealing step shown in FIG. FIG. 12 is a plan view of the resin sealing step shown in FIG. FIG. 13 is a plan view after the resin sealing step shown in FIG. 3 is completed. FIG. 14 is a sectional view taken along line HH in FIG. FIG. 15 is a cross-sectional view (corresponding to line CC in FIG. 4) of the gate portion resin cutting step shown in FIG. FIG. 16 is a cross-sectional view (corresponding to the line CC in FIG. 4) in the heat radiation frame separating step shown in FIG. FIG. 17 is a cross-sectional view (corresponding to line BB in FIG. 4) in the heat radiation frame separating step shown in FIG. FIG. 18 is a cross-sectional view in the inspection step shown in FIG. FIG. 19 is a partially enlarged plan view of the inspection area in the inspection step shown in FIG. FIG. 20 is a plan view of the dam portion cutting step shown in FIG. FIG. 21 is a plan view of the lead forming step shown in FIG.

まず、図４〜図６に示すように、図３のプロセスフロー図のリードフレーム準備工程（ステップＳ１）を実施する。図４は、図３に示すリードフレーム準備工程のリードフレームの平面図である。   First, as shown in FIGS. 4 to 6, the lead frame preparation step (step S1) in the process flow diagram of FIG. 3 is performed. FIG. 4 is a plan view of the lead frame in the lead frame preparation step shown in FIG.

図４に示すように、リードフレーム１０には、複数のデバイス領域ＤＲが所定の間隔でＸ方向に配置されている。略４角形のデバイス領域ＤＲは、１つの半導体装置ＳＤを形成するための領域である。各デバイス領域ＤＲは、Ｘ方向に延在する２つの横枠１１ａと、Ｙ方向に延在する２つの縦枠１１ｂによって囲まれている。デバイス領域ＤＲ間の縦枠１１ｂには、Ｙ方向に延在するスリット１７が形成されている。そして、枠体１１は、Ｘ方向に延在する２つの横枠１１ａと、２つの横枠１１ａを連結し、スリット１７を有する複数の縦枠１１ｂと、横枠１１ａと縦枠１１ｂの交差部において、横枠１１ａおよび縦枠１１ｂからデバイス領域ＤＲの角部に突出する４つの凸部１１ｃと、で構成されている。   As shown in FIG. 4, the lead frame 10 has a plurality of device regions DR arranged at predetermined intervals in the X direction. The substantially quadrangular device region DR is a region for forming one semiconductor device SD. Each device region DR is surrounded by two horizontal frames 11a extending in the X direction and two vertical frames 11b extending in the Y direction. A slit 17 extending in the Y direction is formed in the vertical frame 11b between the device regions DR. The frame body 11 connects the two horizontal frames 11a extending in the X direction, connects the two horizontal frames 11a, and has a plurality of vertical frames 11b having slits 17, and intersections of the horizontal frames 11a and the vertical frames 11b. , Four projections 11c projecting from the horizontal frame 11a and the vertical frame 11b to the corners of the device region DR.

デバイス領域ＤＲの中央部には、四角形のチップ搭載部１５が配置されており、チップ搭載部１５の各角部は、吊りリード１４を介して枠体１１（具体的には、枠体１１の凸部１１ｃ）に接続されている。チップ搭載部１５の周囲には、複数のリード１２が放射状に配置され、リード１２の一端は、チップ搭載部１５の近傍で終端しており、リード１２の他端は、横枠１１ａまたは縦枠１１ｂに接続されている。   A square chip mounting portion 15 is arranged at the center of the device region DR, and each corner of the chip mounting portion 15 is connected to the frame 11 (specifically, the frame 11 It is connected to the projection 11c). A plurality of leads 12 are radially arranged around the chip mounting portion 15, one end of the lead 12 terminates near the chip mounting portion 15, and the other end of the lead 12 has a horizontal frame 11 a or a vertical frame. 11b.

ダム部１３は、複数のリード１２の延在方向と直交する方向に延在し、隣接するリード１２間、および、リード１２と凸部１１ｃ間、を接続している。ダム部１３は、Ｘ方向に延在する２つの横ダム１３ａと、Ｙ方向に延在する２つの縦ダム１３ｂを有する。対向する２つの縦ダム１３ｂ（チップ搭載部１５に近い側の辺）の間隔をＸ１、対向する２つの横ダム１３ａ（チップ搭載部１５に近い側の辺）の間隔をＹ１とする。   The dam portion 13 extends in a direction orthogonal to the direction in which the plurality of leads 12 extend, and connects the adjacent leads 12 and between the leads 12 and the protrusions 11c. The dam portion 13 has two horizontal dams 13a extending in the X direction and two vertical dams 13b extending in the Y direction. Let X1 be the distance between two opposing vertical dams 13b (the side closer to the chip mounting portion 15) and Y1 be the distance between two opposing horizontal dams 13a (the side closer to the chip mounting portion 15).

リードフレーム１０は、例えば、銅（Ｃｕ）を主成分とする１枚の金属板に、プレス加工又はエッチング加工を施して、所望のパターンを形成するため、枠体１１、リード１２、チップ搭載部１５、吊りリード１４、ダム部１３は、一体となっている。リードフレーム１０の膜厚は、例えば、およそ０．１５ｍｍである。   The lead frame 10 is formed, for example, by pressing or etching a single metal plate containing copper (Cu) as a main component to form a desired pattern. 15, the suspension lead 14, and the dam portion 13 are integrated. The thickness of the lead frame 10 is, for example, about 0.15 mm.

さらに、チップ搭載部１５上には、複数のパッド電極３を有する半導体チップ２が接着されており、パッド電極３は、ワイヤ４を介して、対応するリード１２に接続されている。   Further, a semiconductor chip 2 having a plurality of pad electrodes 3 is bonded on the chip mounting portion 15, and the pad electrodes 3 are connected to corresponding leads 12 via wires 4.

図５は、図４のＢ−Ｂ線に沿う断面図であり、図６は、図４のＣ−Ｃ線における断面図である。図６に示すように、段差部１６において、吊りリード１４に曲げ加工が施されており、チップ搭載部１５の裏面は、吊りリード１４の裏面より距離ｄだけ低くなっている。言い換えると、チップ搭載部１５の裏面は、吊りリード１４の裏面より距離ｄだけ、封止体１の裏面１ａに近い。   FIG. 5 is a sectional view taken along line BB of FIG. 4, and FIG. 6 is a sectional view taken along line CC of FIG. As shown in FIG. 6, the suspension lead 14 is bent in the step portion 16, and the back surface of the chip mounting portion 15 is lower than the back surface of the suspension lead 14 by a distance d. In other words, the back surface of the chip mounting portion 15 is closer to the back surface 1a of the sealing body 1 by a distance d than the back surface of the suspension lead 14.

また、図５に示すように、チップ搭載部１５の裏面は、リード１２の裏面より距離ｄだけ低くなっている。言い換えると、チップ搭載部１５の裏面は、リード１２の裏面より距離ｄだけ、封止体１の裏面１ａに近い。   Further, as shown in FIG. 5, the back surface of the chip mounting portion 15 is lower than the back surface of the lead 12 by a distance d. In other words, the back surface of the chip mounting portion 15 is closer to the back surface 1a of the sealing body 1 by the distance d than the back surface of the lead 12.

次に、図７〜図９に示すように、図３のプロセスフロー図の放熱フレーム準備工程（ステップＳ２）を実施する。図７は、図３に示す放熱フレーム準備工程の放熱フレームの平面図である。   Next, as shown in FIGS. 7 to 9, a heat radiation frame preparing step (step S <b> 2) of the process flow diagram of FIG. 3 is performed. FIG. 7 is a plan view of the heat radiating frame in the heat radiating frame preparing step shown in FIG.

図７に示すように、放熱フレーム（放熱リードフレーム）２０には、複数のデバイス領域ＤＲが所定の間隔でＸ方向に配置されている。図７に示すデバイス領域ＤＲは、図４に示すデバイス領域ＤＲに対応している。各デバイス領域ＤＲは、Ｘ方向に延在する２つの横枠２１ａと、Ｙ方向に延在する２つの縦枠２１ｂによって囲まれている。デバイス領域ＤＲ間の縦枠２１ｂには、Ｙ方向に延在するスリット２５が形成されている。そして、枠体２１は、Ｘ方向に延在する２つの横枠２１ａと、２つの横枠２１ａを連結し、スリット２５を有する複数の縦枠２１ｂと、で構成されている。放熱フレーム２０のＹ方向の幅は、前述のリードフレーム１０のＹ方向の幅と等しく、スリット１７および２５は、等しい形状を有し、対応する位置に配置されている。ただし、放熱リード２０の横枠２１ａおよび縦枠２１ｂの幅は、図４に示すリードフレーム１０の横枠１１ａおよび縦枠１１ｂの幅よりも広いため、図７に示すように、デバイス領域ＤＲは、横枠２１ａおよび縦枠２１ｂの一部を含んでいる。   As shown in FIG. 7, a plurality of device regions DR are arranged in the X direction at predetermined intervals on the heat radiation frame (heat radiation lead frame) 20. The device area DR illustrated in FIG. 7 corresponds to the device area DR illustrated in FIG. Each device region DR is surrounded by two horizontal frames 21a extending in the X direction and two vertical frames 21b extending in the Y direction. A slit 25 extending in the Y direction is formed in the vertical frame 21b between the device regions DR. The frame body 21 is composed of two horizontal frames 21a extending in the X direction and a plurality of vertical frames 21b having the slit 25 and connecting the two horizontal frames 21a. The width of the heat radiating frame 20 in the Y direction is equal to the width of the lead frame 10 in the Y direction, and the slits 17 and 25 have the same shape and are arranged at corresponding positions. However, since the widths of the horizontal frame 21a and the vertical frame 21b of the heat radiation lead 20 are wider than the widths of the horizontal frame 11a and the vertical frame 11b of the lead frame 10 shown in FIG. 4, as shown in FIG. , A part of the horizontal frame 21a and the vertical frame 21b.

デバイス領域ＤＲの中央部には、円形の放熱板２２が配置されており、放熱板２２は、４ヶ所で、吊りリード２３を介して枠体２１に接続されている。   A circular heat radiating plate 22 is disposed at the center of the device region DR. The heat radiating plates 22 are connected to the frame 21 via suspension leads 23 at four locations.

図７に示すように、Ｘ方向に延在する２つの横枠２１ａは、放熱板２２側に辺２１ｘを有し、Ｙ方向に延在する２つの縦枠２１ｂは、放熱板２２側に辺２１ｙを有する。そして、対向する辺２１ｙ間の間隔をＸ２、対向する辺２１ｘ間の間隔をＹ２とする。ここで、間隔Ｘ２は、前述の間隔Ｘ１よりも小であり（Ｘ２＜Ｘ１）、間隔Ｙ２は、前述の間隔Ｙ１よりも小である（Ｙ２＜Ｙ１）。従って、２つの辺２１ｘおよび２つの辺２１ｙに囲まれた領域の面積Ｓ２は、Ｓ２＝Ｘ２×Ｙ２と表せる。また、図４における、２つの横ダム１３ａと２つの縦ダム１３ｂに囲まれた領域の面積Ｓ１は、Ｓ１＝Ｘ１×Ｙ１と表せる。従って、面積Ｓ２は、面積Ｓ１よりも小である（Ｓ２＜Ｓ１）。   As shown in FIG. 7, two horizontal frames 21 a extending in the X direction have sides 21 x on the heat radiating plate 22 side, and two vertical frames 21 b extending in the Y direction are sides on the heat radiating plate 22 side. 21y. The distance between the opposing sides 21y is X2, and the distance between the opposing sides 21x is Y2. Here, the interval X2 is smaller than the above-described interval X1 (X2 <X1), and the interval Y2 is smaller than the above-described interval Y1 (Y2 <Y1). Therefore, the area S2 of the region surrounded by the two sides 21x and the two sides 21y can be expressed as S2 = X2 × Y2. In FIG. 4, an area S1 of a region surrounded by two horizontal dams 13a and two vertical dams 13b can be expressed as S1 = X1 × Y1. Therefore, the area S2 is smaller than the area S1 (S2 <S1).

図８は、図７のＤ−Ｄ線に沿う断面図であり、図９は、図７のＥ−Ｅ線における断面図である。図９に示すように、段差部２４において、吊りリード２３に曲げ加工が施されており、放熱板２２の裏面は、吊りリード２３の裏面より距離ｄだけ低くなっている。言い換えると、放熱板２２の裏面は、吊りリード２３の裏面より距離ｄだけ、封止体１の裏面１ａに近い。   FIG. 8 is a cross-sectional view taken along line DD of FIG. 7, and FIG. 9 is a cross-sectional view taken along line EE of FIG. As shown in FIG. 9, the suspension lead 23 is bent at the step portion 24, and the back surface of the heat sink 22 is lower than the back surface of the suspension lead 23 by a distance d. In other words, the back surface of the heat sink 22 is closer to the back surface 1a of the sealing body 1 by a distance d than the back surface of the suspension lead 23.

放熱フレーム２０は、例えば、銅（Ｃｕ）を主成分とする１枚の金属板に、プレス加工又はエッチング加工を施して、所望のパターンを形成するため、枠体２１、放熱板２２、および、吊りリード２３は、一体となっている。放熱フレーム２０の膜厚は、リードフレーム１０の膜厚よりも厚く、例えば、およそ０．２ｍｍである。   The heat radiating frame 20 is formed, for example, by pressing or etching a single metal plate containing copper (Cu) as a main component to form a desired pattern. The suspension leads 23 are integrated. The thickness of the heat dissipation frame 20 is greater than the thickness of the lead frame 10, for example, about 0.2 mm.

また、図８に示すように、放熱板２２の裏面は、枠体２１の裏面より距離ｄだけ低くなっている。言い換えると、放熱板２２の裏面は、枠体２１の裏面より距離ｄだけ、封止体１の裏面１ａに近い。   As shown in FIG. 8, the back surface of the heat sink 22 is lower than the back surface of the frame 21 by a distance d. In other words, the back surface of the heat sink 22 is closer to the back surface 1a of the sealing body 1 by the distance d than the back surface of the frame 21.

なお、図３のプロセスフロー図のリードフレーム準備工程（ステップＳ１）と放熱フレーム準備工程（ステップＳ２）の順序は、逆でも良く、また、両者を並行して実施しても良い。   Note that the order of the lead frame preparation step (step S1) and the heat radiation frame preparation step (step S2) in the process flow diagram of FIG. 3 may be reversed, or both may be performed in parallel.

次に、図１０〜図１４に示すように、図３のプロセスフロー図の樹脂封止工程（ステップＳ３）を実施する。図１０は、図３に示す樹脂封止工程の断面図（図４のＢ−Ｂ線に対応）である。図１１は、図３に示す樹脂封止工程の断面図（図４のＣ−Ｃ線に対応）である。   Next, as shown in FIGS. 10 to 14, the resin sealing step (step S3) in the process flow diagram of FIG. 3 is performed. FIG. 10 is a sectional view (corresponding to line BB in FIG. 4) of the resin sealing step shown in FIG. FIG. 11 is a cross-sectional view (corresponding to the line CC in FIG. 4) of the resin sealing step shown in FIG.

図１０および図１１に示すように、放熱フレーム２０の主面上にリードフレーム１０の裏面を重ねた状態で、両者を金型３０内に配置し、樹脂封止工程を実施する。   As shown in FIGS. 10 and 11, in a state where the back surface of the lead frame 10 is overlaid on the main surface of the heat radiation frame 20, both are arranged in the mold 30, and a resin sealing step is performed.

金型３０は、上型３１および下型３２を有する。図１０では、上型３１を上側に、下型３２を下側に配置した例を示すが、上型３１を下側に、下型３２を上側に配置しても良い。上型３１は、合せ面３１ｆ、底面３１ｂおよび側壁３１ｓを有し、下型３２は、合せ面３２ｆ、底面３２ｂおよび側壁３２ｓを有する。上型３１および下型３２を閉じた状態で、金型３０にはキャビティ３４と呼ばれる空間が形成されるが、このキャビティ３４は、上型３１の底面３１ｂおよび側壁３１ｓならびに下型３２の底面３２ｂおよび側壁３２ｓで囲まれた空間である。   The mold 30 has an upper mold 31 and a lower mold 32. FIG. 10 shows an example in which the upper mold 31 is arranged on the upper side and the lower mold 32 is arranged on the lower side. However, the upper mold 31 may be arranged on the lower side and the lower mold 32 may be arranged on the upper side. The upper die 31 has a mating surface 31f, a bottom surface 31b, and a side wall 31s, and the lower die 32 has a mating surface 32f, a bottom surface 32b, and a side wall 32s. When the upper mold 31 and the lower mold 32 are closed, a space called a cavity 34 is formed in the mold 30. The cavity 34 is formed by the bottom 31 b and the side wall 31 s of the upper mold 31 and the bottom 32 b of the lower mold 32. And a space surrounded by the side wall 32s.

リードフレーム１０の主面が、上型３１の合せ面３１ｆと接触し、放熱フレーム２０の裏面が、下型３２の合せ面３２ｆと接触するように、上型３１および下型３２を閉めると、半導体チップ２、リード１２の一部、ワイヤ４、チップ搭載部１５、および、放熱板２２は、キャビティ３４内に配置される。図１０に示すように、リードフレーム１０のリード１２の裏面は、放熱フレーム２０の枠体２１の主面に接触している。さらに、チップ搭載部１５の裏面は、放熱板２２の主面に接触しており、半導体チップ２で発生した熱を、チップ搭載部１５を介して放熱板２２に、容易に拡散、伝達させることができる。また、図１１に示すように、放熱フレーム２０の吊りリード２３に設けられた段差部２４は、リードフレーム１０の吊りリード１４に設けられた段差部１６よりも、半導体チップ２またはチップ搭載部１５から離れている。ただし、段差部２４は、キャビティ３４内に位置している。   When the upper die 31 and the lower die 32 are closed such that the main surface of the lead frame 10 contacts the mating surface 31f of the upper die 31 and the back surface of the heat radiation frame 20 contacts the mating surface 32f of the lower die 32, The semiconductor chip 2, a part of the lead 12, the wire 4, the chip mounting portion 15, and the heat radiating plate 22 are arranged in the cavity 34. As shown in FIG. 10, the back surface of the lead 12 of the lead frame 10 is in contact with the main surface of the frame 21 of the heat radiation frame 20. Further, the back surface of the chip mounting portion 15 is in contact with the main surface of the heat radiating plate 22, so that the heat generated in the semiconductor chip 2 is easily diffused and transmitted to the heat radiating plate 22 via the chip mounting portion 15. Can be. As shown in FIG. 11, the step portion 24 provided on the suspension lead 23 of the heat dissipation frame 20 is smaller than the step portion 16 provided on the suspension lead 14 of the lead frame 10. Away from However, the step portion 24 is located inside the cavity 34.

次に、例えば、下型３２に設けられたゲート部３３からキャビティ３４内に樹脂３５を注入し、前述の封止体１を形成する。ゲート部３３は、上型３１に設けても良く、また、下型３２および上型３１の両方に設けても良い。   Next, for example, a resin 35 is injected into the cavity 34 from the gate portion 33 provided in the lower mold 32 to form the above-described sealing body 1. The gate portion 33 may be provided on the upper mold 31 or may be provided on both the lower mold 32 and the upper mold 31.

図１２は、図３に示す樹脂封止工程の平面図であり、具体的には、リードフレーム１０の平面図であるが、金型３０および放熱フレーム２０は、図示していない。図１２の破線Ｆは、金型３０のキャビティ３４の領域を示しており、破線Ｆの内側がキャビティ３４である。言い換えると、破線Ｆは、図１０に示す上型３１の側壁３１ｓがリードフレーム１０の主面と接触した位置、または、下型３２の側壁３２ｓが放熱フレーム２０の裏面と接触した位置を表している。   FIG. 12 is a plan view of the resin sealing step shown in FIG. 3, specifically, a plan view of the lead frame 10, but the mold 30 and the heat radiation frame 20 are not shown. A broken line F in FIG. 12 indicates a region of the cavity 34 of the mold 30, and the inside of the broken line F is the cavity 34. In other words, the broken line F indicates the position where the side wall 31 s of the upper die 31 shown in FIG. 10 is in contact with the main surface of the lead frame 10, or the position where the side wall 32 s of the lower die 32 is in contact with the back surface of the heat radiation frame 20. I have.

また、図１２において、破線Ｇが破線Ｆと重なっている。破線Ｇは、樹脂封止工程（ステップＳ３）における、図７で説明した放熱板２２の辺２１ｘおよび２１ｙの位置を表している。破線Ｇの外側の領域（図１２にハッチングを付した領域）は、リードフレーム１０と、放熱フレーム２０の枠体２１とが重なった領域である。本実施の形態では、破線Ｇが破線Ｆと重なっているため、図１０に示すように、放熱フレーム２０の枠体２１の放熱板２２側の端部（辺２１ｙと示す）は、キャビティ３４に接触している。つまり、キャビティ３４内が樹脂３５で満たされ、封止体１が形成されると、枠体２１の放熱板２２側の端部（辺２１ｙと示す）は、封止体１の側面１ｃと接触することとなる。言い換えると、放熱フレーム２０の枠体２１の放熱板２２側の端部（辺２１ｙまたは辺２１ｘ）は、キャビティ３４を構成する金型３０の側壁３２ｓの位置と一致している。   In FIG. 12, the broken line G overlaps the broken line F. The broken line G indicates the positions of the sides 21x and 21y of the heat sink 22 described in FIG. 7 in the resin sealing step (step S3). The area outside the broken line G (the area hatched in FIG. 12) is an area where the lead frame 10 and the frame 21 of the heat radiation frame 20 overlap. In the present embodiment, since the broken line G overlaps with the broken line F, the end (shown as the side 21y) of the frame 21 of the heat dissipation frame 20 on the heat dissipation plate 22 side is formed in the cavity 34 as shown in FIG. In contact. In other words, when the inside of the cavity 34 is filled with the resin 35 and the sealing body 1 is formed, the end (shown as the side 21 y) of the frame 21 on the side of the heat radiating plate 22 contacts the side surface 1 c of the sealing body 1. Will be done. In other words, the end (side 21y or side 21x) of the frame 21 of the heat radiation frame 20 on the side of the heat radiation plate 22 coincides with the position of the side wall 32s of the mold 30 constituting the cavity 34.

なお、破線Ｇは、破線Ｆと重なるか、または、破線Ｆと、ダム１３との間に位置することが肝要である。つまり、図１０に示すように、縦ダム１３ｂ（および横ダム１３ａ）が、放熱フレーム２０の枠体２１と重なっていることが肝要である。   It is important that the broken line G overlaps the broken line F or is located between the broken line F and the dam 13. That is, as shown in FIG. 10, it is important that the vertical dam 13b (and the horizontal dam 13a) overlap the frame 21 of the heat radiation frame 20.

次に、図１３は、図３に示す樹脂封止工程完了後の平面図である。図１４は、図１３のＨ−Ｈ線における断面図である。図１３および図１４は、封止体１を金型３０から取り出した状態を示している。なお、図１３は、封止体１およびリードフレーム１０を、封止体１の主面１ａ側から見た図面であるが、放熱フレーム２０は、図示していない。図１３および図１４に示すように、封止体１の周囲に沿って、薄膜樹脂４０が形成されている。図１３および図１４から明らかなように、薄膜樹脂４０は、放熱フレーム２０の枠体２１上であって、封止体１と、隣接するリード１２と、ダム部１３と、で挟まれた領域に形成され、その膜厚は、リードフレーム１０の膜厚とほぼ等しい。薄膜樹脂４０の膜厚は、封止体１の厚さ（主面１ａと裏面１ｂ間の距離）よりも薄い。   Next, FIG. 13 is a plan view after the resin sealing step shown in FIG. 3 is completed. FIG. 14 is a sectional view taken along line HH in FIG. FIGS. 13 and 14 show a state where the sealing body 1 is taken out of the mold 30. FIG. 13 is a view of the sealing body 1 and the lead frame 10 as viewed from the main surface 1a side of the sealing body 1, but the heat radiation frame 20 is not shown. As shown in FIGS. 13 and 14, a thin film resin 40 is formed along the periphery of the sealing body 1. As is clear from FIGS. 13 and 14, the thin film resin 40 is located on the frame 21 of the heat radiation frame 20 and is sandwiched between the sealing body 1, the adjacent lead 12, and the dam portion 13. And the thickness thereof is substantially equal to the thickness of the lead frame 10. The thickness of the thin film resin 40 is smaller than the thickness of the sealing body 1 (the distance between the main surface 1a and the back surface 1b).

次に、図１５に示すように、図３のプロセスフロー図のゲート部樹脂切断工程（ステップＳ４）を実施する。   Next, as shown in FIG. 15, the gate resin cutting step (step S4) in the process flow diagram of FIG. 3 is performed.

図１５は、図３に示すゲート部樹脂切断工程における断面図（図４のＣ−Ｃ線に対応）である。図１５に示すように、破線で示したゲート部樹脂３３ｒを封止体１から分離する。   FIG. 15 is a cross-sectional view (corresponding to line CC in FIG. 4) of the gate portion resin cutting step shown in FIG. As shown in FIG. 15, the gate resin 33 r indicated by the broken line is separated from the sealing body 1.

次に、図１６および図１７に示すように、図３のプロセスフロー図の放熱フレーム分離工程（ステップＳ５）を実施する。図１６は、図３に示す放熱フレーム分離工程における断面図（図４のＣ−Ｃ線に対応）である。図１７は、図３に示す放熱フレーム分離工程における断面図（図４のＢ−Ｂ線に対応）である。   Next, as shown in FIGS. 16 and 17, the heat radiation frame separating step (step S5) in the process flow diagram of FIG. 3 is performed. FIG. 16 is a cross-sectional view (corresponding to the line CC in FIG. 4) in the heat radiation frame separating step shown in FIG. FIG. 17 is a cross-sectional view (corresponding to line BB in FIG. 4) in the heat radiation frame separating step shown in FIG.

図１６に示すように、放熱フレーム２０の吊りリード２３と枠体２１との境界部で、枠体２１を吊りリード２３から切断、分離する。これに伴い、図１７に示すように、封止体１の外部で、リード１２の裏面に接触していた放熱リード２０の枠体２１も分離される。   As shown in FIG. 16, the frame 21 is cut and separated from the suspension leads 23 at the boundary between the suspension leads 23 of the heat radiation frame 20 and the frame 21. Accordingly, as shown in FIG. 17, the frame 21 of the heat radiation lead 20 that has been in contact with the back surface of the lead 12 outside the sealing body 1 is also separated.

なお、ゲート部３３が、放熱フレーム２０側に位置する場合、ゲート部樹脂切断工程（ステップＳ４）と、放熱フレーム分離工程（ステップＳ５）と、を同時実施することができる。   When the gate portion 33 is located on the heat radiating frame 20 side, the gate portion resin cutting step (step S4) and the heat radiating frame separating step (step S5) can be performed simultaneously.

次に、図１８および図１９に示すように、図３のプロセスフロー図の検査工程（ステップＳ６）を実施する。図１８は、図３に示す検査工程における断面図である。図１９は、図３に示す検査工程における検査領域の一部（図１３の領域Ｉ）拡大平面図である。   Next, as shown in FIGS. 18 and 19, the inspection step (step S6) in the process flow diagram of FIG. 3 is performed. FIG. 18 is a cross-sectional view in the inspection step shown in FIG. FIG. 19 is an enlarged plan view of a part of the inspection region (region I in FIG. 13) in the inspection step shown in FIG.

図１８に示すように、検査対象である、封止体１を備えたリードフレーム１０に対して、封止体１の裏面１ｂ側に照明装置４１、封止体１の主面１ａ側にカメラ４２を配置して、樹脂封止工程（ステップＳ３）における樹脂の未充填検査を実施する。すなわち、照明装置４１とカメラ４２の間に封止体１が配置されている。照明装置４１は、例えば、複数の白色ＬＥＤがマトリックス配置された光源と、それらを覆う光拡散板と、からなる。カメラ４２は、例えば、ＣＣＤカメラからなる。   As shown in FIG. 18, with respect to the lead frame 10 having the sealing body 1 to be inspected, the lighting device 41 is provided on the back surface 1 b side of the sealing body 1, and the camera is provided on the main surface 1 a side of the sealing body 1. 42 is arranged, and an unfilled resin inspection is performed in the resin sealing step (step S3). That is, the sealing body 1 is arranged between the lighting device 41 and the camera 42. The lighting device 41 includes, for example, a light source in which a plurality of white LEDs are arranged in a matrix, and a light diffusion plate that covers the light sources. The camera 42 is, for example, a CCD camera.

図１９に示すように、封止体１と、ダム部１３ａまたは１３ｂと、隣接する複数のリード１２と、で囲まれた領域が、完全に薄膜樹脂４０で埋め込まれているかどうかを検査する。また、同様に、封止体１の角部においては、封止体１と、ダム部１３ａまたは１３ｂと、リード１２と、吊りリード１４または枠体１１と、で囲まれた領域が、完全に薄膜樹脂４０で埋め込まれているかどうかを検査する。つまり、樹脂の未充填領域が存在した場合、照明装置４１からの透過光をカメラ４２で検出することで未充填領域を検出する。この検査は、封止体１の全周に対して実施する。   As shown in FIG. 19, it is inspected whether a region surrounded by the sealing body 1, the dam portion 13a or 13b, and the plurality of adjacent leads 12 is completely buried with the thin film resin 40. Similarly, at the corners of the sealing body 1, the region surrounded by the sealing body 1, the dam portion 13 a or 13 b, the lead 12, and the suspension lead 14 or the frame 11 is completely It is inspected whether it is embedded with the thin film resin 40. That is, when there is an unfilled area of the resin, the unfilled area is detected by detecting the transmitted light from the illumination device 41 with the camera 42. This inspection is performed on the entire circumference of the sealing body 1.

薄膜樹脂４０は、前述のとおり、リードフレーム１０とほぼ等しい０．１５ｍｍの膜厚を有し、樹脂中にはシリカ等も含まれるため、照明装置４１からの白色光を、充分遮ることができる。   As described above, the thin-film resin 40 has a thickness of about 0.15 mm, which is substantially equal to that of the lead frame 10, and silica or the like is included in the resin, so that white light from the lighting device 41 can be sufficiently blocked. .

ここで、検査工程（ステップＳ６）の前に、放熱フレーム２０の枠体２１を、リードフレーム１０から分離、除去しているため、照明装置４１からの白色光が放熱フレーム２０の枠体２１で遮られることがなく、未充填領域の検出が可能となる。   Here, before the inspection step (step S6), the frame 21 of the heat dissipation frame 20 is separated and removed from the lead frame 10, so that white light from the lighting device 41 is applied to the frame 21 of the heat dissipation frame 20. The unfilled area can be detected without being blocked.

また、検査対象である封止体１を備えたリードフレーム１０の下側に照明装置４１、上側にカメラ４２を配置して検査することで、検査対象からのごみ（例えば、樹脂バリ）の落下、付着に起因するカメラ４２の検出画像の誤認識を低減することができる。   In addition, by arranging the illumination device 41 below the lead frame 10 having the sealing body 1 to be inspected and the camera 42 above and inspecting the same, dust (for example, resin burrs) from the inspection object falls. In addition, it is possible to reduce erroneous recognition of the detection image of the camera 42 due to the adhesion.

次に、図２０に示すように、図３のプロセスフロー図のダム部切断工程（ステップＳ７）を実施する。図２０は、図３に示すダム部切断工程における平面図である。   Next, as shown in FIG. 20, the dam portion cutting step (step S7) in the process flow diagram of FIG. 3 is performed. FIG. 20 is a plan view of the dam portion cutting step shown in FIG.

図２０に示すように、隣接リード１２間のダム部１３ａおよび１３ｂを、パンチ等の切断治具で、切断、除去し、隣接するリード１２間を分離する。ダム部切断工程（ステップＳ７）では、ダム部１３ａおよび１３ｂと同時に、薄膜樹脂４０も同時に除去する。   As shown in FIG. 20, the dam portions 13a and 13b between the adjacent leads 12 are cut and removed with a cutting jig such as a punch, and the adjacent leads 12 are separated. In the dam section cutting step (step S7), the thin film resin 40 is removed simultaneously with the dam sections 13a and 13b.

図３のプロセスフロー図の樹脂封止工程（ステップＳ３）において、リードフレーム１０のダム部１３と重なるように、放熱フレーム２０の枠体２１が配置されていることで、薄膜樹脂４０の膜厚を薄くすることができ、ダム部切断工程（ステップＳ７）において、封止体１の側面１ｃの欠けを低減することができる。   In the resin sealing step (step S3) of the process flow diagram of FIG. 3, the frame 21 of the heat radiation frame 20 is arranged so as to overlap the dam portion 13 of the lead frame 10, so that the thickness of the thin film resin 40 is reduced. Can be reduced, and chipping of the side surface 1c of the sealing body 1 can be reduced in the dam section cutting step (Step S7).

仮に、図１２に示した破線Ｆが、ダム部１３の外側（半導体チップ１またはチップ搭載部１５の反対側、つまり、枠体１３側）に位置していたら、図１４から推測できるように、薄膜樹脂４０の膜厚は、本実施の形態の２倍以上の膜厚となる。つまり、リードフレーム１０の膜厚０．１５ｍｍと放熱フレーム２０の膜厚０．２ｍｍの和である膜厚０．３５ｍｍとなる。そして、ダム部切断工程（ステップＳ７）において、ダム部１３と同時に、厚い薄膜樹脂４０を切断するため、封止体１の側面１ｃに欠け、または、クラックが発生し、不良の原因となる。   If the broken line F shown in FIG. 12 is located outside the dam portion 13 (the opposite side of the semiconductor chip 1 or the chip mounting portion 15, that is, the frame 13 side), as shown in FIG. The thickness of the thin film resin 40 is twice or more the thickness of the present embodiment. That is, the film thickness is 0.35 mm, which is the sum of the film thickness of the lead frame 10 and the heat dissipation frame 20. Then, in the dam section cutting step (step S7), since the thick thin film resin 40 is cut simultaneously with the dam section 13, the side face 1c of the sealing body 1 is chipped or cracked, which causes a defect.

次に、図３のプロセスフロー図のメッキ工程（ステップＳ８）を実施する。メッキ工程（ステップＳ８）では、封止体１の外部に位置するアウターリード部ＯＬの主面、裏面および側面に半田メッキを付着する。   Next, the plating step (step S8) in the process flow diagram of FIG. 3 is performed. In the plating step (Step S8), solder plating is applied to the main surface, the back surface, and the side surfaces of the outer lead portion OL located outside the sealing body 1.

次に、図２１および図２に示すように、図３のプロセスフロー図のリード形成工程（ステップＳ９）を実施する。図２１は、図３に示すリード形成工程における平面図である。   Next, as shown in FIGS. 21 and 2, the lead forming step (step S9) in the process flow diagram of FIG. 3 is performed. FIG. 21 is a plan view of the lead forming step shown in FIG.

まず、図２１に示すように、リード１２の他端をリードフレーム１０の枠体１１から切断、分離する。その後、図２に示す形状に、リード１２を成形する。   First, as shown in FIG. 21, the other end of the lead 12 is cut and separated from the frame 11 of the lead frame 10. Thereafter, the lead 12 is formed into the shape shown in FIG.

次に、図３のプロセスフロー図の個片化工程（ステップＳ１０）を実施する。図２１に示す吊りリード１４を、封止体１との境界部で切断することにより、図２にしめす半導体装置ＳＤが完成する。   Next, an individualizing step (step S10) in the process flow diagram of FIG. 3 is performed. The semiconductor device SD shown in FIG. 2 is completed by cutting the suspension leads 14 shown in FIG. 21 at the boundary with the sealing body 1.

＜本実施の形態の半導体装置の製造方法の主たる特徴と効果＞
半導体チップ２を搭載したリードフレーム１０と、放熱板２２を有する放熱フレーム２０と、を積層した状態で、半導体チップ２を樹脂封止して封止体１を形成する。そして、放熱フレーム２０の枠体２１を、封止体１を有するリードフレーム１０から分離した後に、封止体１を有するリードフレーム１０に対して、樹脂の未充填領域有無の検査を実施する。 <Main Features and Effects of Manufacturing Method of Semiconductor Device of Present Embodiment>
In a state where the lead frame 10 on which the semiconductor chip 2 is mounted and the heat radiating frame 20 having the heat radiating plate 22 are laminated, the semiconductor chip 2 is resin-sealed to form the sealing body 1. Then, after separating the frame body 21 of the heat radiation frame 20 from the lead frame 10 having the sealing body 1, the lead frame 10 having the sealing body 1 is inspected for the presence or absence of a resin unfilled area.

放熱フレーム２０の枠体２１で、検査領域が遮られることが無いため、透過光を用いて、樹脂の未充填領域を検出する検査が可能となる。   Since the inspection area is not obstructed by the frame body 21 of the heat radiation frame 20, the inspection for detecting the unfilled area of the resin using the transmitted light becomes possible.

透過光を用いた検査とすることで、樹脂の未充填領域の検出精度を向上することができる。例えば、反射光を用いた検査方法は、リード１２と樹脂との間で、充分なコントラストが得られず、検出精度を向上させるのが困難である。   By performing the inspection using transmitted light, it is possible to improve the detection accuracy of the unfilled region of the resin. For example, in the inspection method using reflected light, a sufficient contrast cannot be obtained between the lead 12 and the resin, and it is difficult to improve detection accuracy.

リードフレーム１０と、放熱板２２を有する放熱フレーム２０と、を積層した状態で、半導体チップ２を樹脂封止して封止体１を形成するため、封止工程前に放熱板をリードフレームに連結する製造方法を用いた場合に比べ、放熱板２２を内蔵した半導体装置ＳＤの製造コストの低減または製造歩留りを向上できる。   In a state where the lead frame 10 and the heat radiating frame 20 having the heat radiating plate 22 are laminated, the semiconductor chip 2 is resin-sealed to form the sealing body 1. The manufacturing cost of the semiconductor device SD having the built-in heat sink 22 can be reduced or the manufacturing yield can be improved, as compared with the case where the connecting manufacturing method is used.

また、封止体１の全周に沿って、樹脂の未充填領域を検出する検査を実施するため、ハロゲンフリーの高流動性樹脂を用いた場合でも、放熱板２２を内蔵した半導体装置ＳＤの信頼性を向上できる。   In addition, in order to perform an inspection for detecting an unfilled area of the resin along the entire circumference of the sealing body 1, even if a halogen-free high-fluidity resin is used, the semiconductor device SD having the built-in heat sink 22 can be used. Reliability can be improved.

また、検査工程において、被検査体の下側に照明装置４１を、被検査体の上側にカメラ４２を配置することで、被検査体から落下、付着するごみに起因するカメラ４２の誤認識を防止でき、検査精度を向上できる。   In the inspection process, the illumination device 41 is arranged below the object to be inspected, and the camera 42 is arranged above the object to be inspected. Can be prevented and inspection accuracy can be improved.

樹脂封止工程において、放熱フレーム２０の枠体２１の端部（辺２１ｘまたは２１ｙ）は、リードフレーム１０のダム部１３と放熱板２２との間に位置する。さらに具体的に言うと、放熱フレーム２０の枠体２１の端部（辺２１ｘまたは２１ｙ）は、リードフレーム１０のダム部１３と金型３０のキャビティ３４との間に位置しているので、ダム部切断工程において、薄膜樹脂４０の膜厚を薄くすることができ、封止体１の側面１ｃの欠けを低減することができる。さらに、図１０に示すように、放熱フレーム２０の枠体２１の端部（辺２１ｘまたは２１ｙ）は、合せ面３２ｆと側壁３２ｓの交点Ａ上に位置しているのが好ましい。すなわち、放熱フレーム２０の枠体２１の端部（辺２１ｘまたは２１ｙ）は、交点Ａに接している。また、放熱フレーム２０の枠体２１の端部（辺２１ｘまたは２１ｙ）は、ダム部１３ｂの、チップ搭載部１５側の端部よりも、金型３０のキャビティ３４側に位置しているのが好ましい。   In the resin sealing step, the end portion (side 21x or 21y) of the frame 21 of the heat radiation frame 20 is located between the dam portion 13 of the lead frame 10 and the heat radiation plate 22. More specifically, the end (side 21x or 21y) of the frame 21 of the heat radiation frame 20 is located between the dam portion 13 of the lead frame 10 and the cavity 34 of the mold 30, so that the dam In the part cutting step, the thickness of the thin film resin 40 can be reduced, and chipping of the side surface 1c of the sealing body 1 can be reduced. Furthermore, as shown in FIG. 10, the end (side 21x or 21y) of the frame 21 of the heat radiation frame 20 is preferably located on the intersection A between the mating surface 32f and the side wall 32s. That is, the end (side 21x or 21y) of the frame 21 of the heat dissipation frame 20 is in contact with the intersection A. Further, the end (side 21x or 21y) of the frame 21 of the heat radiation frame 20 is preferably located closer to the cavity 34 of the mold 30 than the end of the dam portion 13b on the chip mounting portion 15 side. preferable.

以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。   As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.

また、上記実施の形態では、ＱＦＰ型半導体装置を例に説明したが、ＳＯＰ（Ｓｍａｌｌ Ｏｕｔｌｉｎｅ Ｐａｃｋａｇｅ）型半導体装置への適用も可能である。   Further, in the above embodiment, a QFP type semiconductor device has been described as an example, but the present invention is also applicable to a SOP (Small Outline Package) type semiconductor device.

ＱＦＰ型半導体装置では、図１に示すように、リード１２が封止体１の４つの辺から突出しているが、ＳＯＰ型半導体装置の場合、平面視にて長方形の封止体の対向する２辺からリードが露出する点が異なるが、それ以外は、上記実施の形態と同様である。   In the QFP type semiconductor device, as shown in FIG. 1, the leads 12 protrude from the four sides of the sealing body 1. In the case of the SOP type semiconductor device, the opposite ends of the rectangular sealing body 2 in plan view. The difference is that the lead is exposed from the side, but the rest is the same as the above embodiment.

ＤＲ デバイス領域
ＩＬ インナーリード部
ＯＬ アウターリード部
ＭＢ 実装面
Ｐ１ 突出部
Ｐ２ 屈曲部
Ｐ３ 接続部
ＳＤ 半導体装置
１ 封止体
１ａ 主面
１ｂ 裏面
１ｃ 側面
２ 半導体チップ
２ａ 主面
２ｂ 裏面
３ パッド電極（端子、外部電極、外部引出電極）
４ ワイヤ（ボンディングワイヤ）
５ 接着層
１０ リードフレーム
１１ 枠体
１１ａ 横枠
１１ｂ 縦枠
１１ｃ 凸部
１２ リード
１２ｍ 半田メッキ膜
１３ ダム部
１３ａ 横ダム
１３ｂ 縦ダム
１４ 吊りリード
１５ チップ搭載部（タブ）
１６ 段差部
１７ スリット
２０ 放熱フレーム
２１ 枠体
２１ａ 横枠
２１ｂ 縦枠
２１ｘ、２１ｙ 辺
２２ 放熱板
２３ 吊りリード
２４ 段差部
２５ スリット
３０ 金型
３１ 上型
３１ｂ 底面
３１ｆ 合せ面
３１ｓ 側壁
３２ 下型
３２ｂ 底面
３２ｆ 合せ面
３２ｓ 側壁
３３ ゲート部
３３ｒ ゲート部樹脂
３４ キャビティ
３５ 樹脂（封止樹脂）
４０ 薄膜樹脂
４１ 照明装置
４２ カメラ DR device area IL inner lead part OL outer lead part MB mounting surface P1 protrusion P2 bent part P3 connection part SD semiconductor device 1 sealing body 1a main surface 1b back surface 1c side surface 2 semiconductor chip 2a main surface 2b back surface 3 pad electrode (terminal) , External electrode, external extraction electrode)
4 wire (bonding wire)
5 Adhesive layer 10 Lead frame 11 Frame 11a Horizontal frame 11b Vertical frame 11c Convex portion 12 Lead 12m Solder plating film 13 Dam portion 13a Horizontal dam 13b Vertical dam 14 Suspended lead 15 Chip mounting portion (tab)
Reference Signs List 16 stepped portion 17 slit 20 heat dissipation frame 21 frame 21a horizontal frame 21b vertical frame 21x, 21y side 22 heatsink 23 suspension lead 24 stepped portion 25 slit 30 mold 31 upper mold 31b bottom surface 31f mating surface 31s side wall 32 lower mold 32b bottom surface 32f mating surface 32s side wall 33 gate part 33r gate part resin 34 cavity 35 resin (sealing resin)
40 thin film resin 41 lighting device 42 camera

Claims (13)

以下の工程を含む半導体装置の製造方法、
（ａ）第１主面と、前記第１主面と反対側の第１裏面と、を有する第１リードフレームを準備する工程であって、前記第１リードフレームは、その前記第１主面上に半導体チップが搭載されたチップ搭載部と、前記チップ搭載部の周囲に配置され、一端と他端とを有する複数のリードと、前記複数のリードの前記他端が接続される第１枠体と、前記複数のリードの前記一端と前記第１枠体との間に位置し、前記複数のリードを互いに連結するダム部と、前記チップ搭載部を前記第１枠体に連結する第１吊りリードと、を有する、
（ｂ）第２主面と、前記第２主面と反対側の第２裏面と、を有する第２リードフレームを準備する工程であって、前記第２リードフレームは、その前記第２主面上に前記チップ搭載部が搭載される放熱板と、前記放熱板の周囲を囲む第２枠体と、前記放熱板を前記第２枠体に連結する第２吊りリードと、を有する、
（ｃ）前記第２主面と前記第１裏面とが向き合うように、前記第１リードフレームと前記第２リードフレームとを重ねた状態で、前記第１リードフレームと前記第２リードフレームとを、キャビティ部を有する金型に配置し、前記半導体チップと、前記チップ搭載部と、前記放熱板と、を樹脂で封止し、封止体を形成する工程であって、前記キャビティ部を構成する前記金型の側壁は、前記ダム部よりも前記チップ搭載部側に位置しており、前記第２枠体の前記放熱板側の第１辺は、前記ダム部と前記金型の前記側壁との間に位置しており、
（ｄ）前記封止体を前記金型から取り出し、前記第２枠体を前記封止体から切り離す工程、
（ｅ）前記（ｄ）工程後に、前記封止体、前記ダム部および前記複数のリードに囲まれた領域に、前記樹脂が充填されているかどうかを検査する工程、
を有する。 A method for manufacturing a semiconductor device, comprising:
(A) a step of preparing a first lead frame having a first main surface and a first back surface opposite to the first main surface, wherein the first lead frame has the first main surface. A chip mounting portion on which a semiconductor chip is mounted, a plurality of leads disposed around the chip mounting portion and having one end and the other end, and a first frame to which the other end of the plurality of leads is connected A body, a dam portion located between the one end of the plurality of leads and the first frame, and connecting the plurality of leads to each other; and a first portion connecting the chip mounting portion to the first frame. Having a suspension lead,
(B) preparing a second lead frame having a second main surface and a second back surface opposite to the second main surface, wherein the second lead frame has the second main surface; A heat sink on which the chip mounting portion is mounted, a second frame surrounding the heat sink, and a second suspension lead connecting the heat sink to the second frame;
(C) In a state where the first lead frame and the second lead frame are overlapped so that the second main surface and the first back surface face each other, the first lead frame and the second lead frame are placed together. Disposing in a mold having a cavity portion, sealing the semiconductor chip, the chip mounting portion, and the heat sink with a resin to form a sealed body, wherein the cavity portion is formed. The side wall of the mold is located closer to the chip mounting portion than the dam portion , and the first side of the second frame body on the heat sink side is the dam portion and the side wall of the mold. Is located between
(D) removing the sealing body from the mold and separating the second frame from the sealing body;
(E) after the step (d), inspecting whether the resin is filled in a region surrounded by the sealing body, the dam portion, and the plurality of leads;
Having. 請求項１に記載の半導体装置の製造方法において、
前記（ｅ）工程は、前記封止体の全周に渡って実施する、半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the step (e) is performed over the entire circumference of the sealing body. 請求項１に記載の半導体装置の製造方法において、
前記封止体は、前記第１主面側に位置する上面と、前記上面の反対側であり、かつ、前記第２裏面側に位置する下面と、前記上面と前記下面との間に位置する側面と、を有し、
前記（ｅ）工程において、前記封止体の前記下面に面するように照明を、前記封止体の前記上面に面するようにカメラを配置する、半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1,
The sealing body is located on the upper surface located on the first main surface side, on the opposite side of the upper surface, and on the lower surface located on the second back surface side, and is located between the upper surface and the lower surface. Having a side and
The method of manufacturing a semiconductor device, wherein in the step (e), illumination is arranged so as to face the lower surface of the sealing body, and a camera is arranged so as to face the upper surface of the sealing body. 請求項１に記載の半導体装置の製造方法において、
前記封止体は、照明とカメラの間に配置されている、半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the sealing body is disposed between a lighting and a camera. 請求項１に記載の半導体装置の製造方法において、
前記（ｅ）工程において、前記封止体は、照明とカメラの間に配置されている、半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1 ,
Prior Symbol (e) step, the sealing member is disposed between the illumination and the camera, a method of manufacturing a semiconductor device. 請求項５に記載の半導体装置の製造方法において、
前記（ｃ）工程において、前記ダム部は、前記第２枠体に重なっている、半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 5,
The method of manufacturing a semiconductor device, wherein in the step (c), the dam portion overlaps the second frame. 請求項６に記載の半導体装置の製造方法において、
前記ダム部は、平面視における第１方向にて、互いに対向する第１ダム部および第２ダム部を有し、
前記第２枠体は、前記第１方向にて、互いに対向する前記第１辺および第２辺を有し、
前記第１方向にて、前記第１辺と前記第２辺との第１間隔は、前記第１ダム部と前記第２ダム部との第２間隔よりも小さい、半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 6,
The dam portion has a first dam portion and a second dam portion facing each other in a first direction in plan view,
The second frame has the first side and the second side facing each other in the first direction,
The method of manufacturing a semiconductor device, wherein a first distance between the first side and the second side in the first direction is smaller than a second distance between the first dam portion and the second dam portion. 請求項５に記載の半導体装置の製造方法において、
前記第２枠体の前記放熱板側の第１辺は、前記金型の前記側壁が前記リードの前記第１主面と接触する位置と一致している、半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 5,
The first side of the heat radiating plate side of the second frame, the side walls of the mold coincides with the position in contact with said first major surface of the lead, a method of manufacturing a semiconductor device. 請求項１に記載の半導体装置の製造方法において、
前記（ｃ）工程において、前記金型は、前記キャビティ部に前記樹脂を注入するためのゲート部を有し、
前記（ｄ）工程では、前記封止体を前記金型から取り出した後、前記ゲート部の前記樹脂を、前記封止体から分離し、その後に、前記第２枠体を前記封止体から切り離す、半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1,
In the step (c), the mold has a gate portion for injecting the resin into the cavity portion,
In the step (d), after removing the sealing body from the mold, the resin of the gate portion is separated from the sealing body, and thereafter, the second frame is separated from the sealing body. A method for manufacturing a semiconductor device. 請求項１に記載の半導体装置の製造方法において、
前記（ｅ）工程の後に、さらに、
（ｆ）前記ダム部を切断し、前記複数のリード間を分離する工程、
を有する、半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1,
After the step (e),
(F) cutting the dam portion to separate the plurality of leads;
A method for manufacturing a semiconductor device, comprising: 請求項１０に記載の半導体装置の製造方法において、
前記（ｆ）工程の後に、さらに、
（ｇ）前記複数のリードの前記他端を前記第１枠体から切断した後、前記複数のリードを成形する工程、
を有する、半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 10,
After the step (f),
(G) forming the plurality of leads after cutting the other ends of the plurality of leads from the first frame;
A method for manufacturing a semiconductor device, comprising: 請求項１に記載の半導体装置の製造方法において、
平面視にて、前記放熱板の面積は、前記チップ搭載部の面積よりも広い、半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein an area of the heat sink is larger than an area of the chip mounting portion in a plan view. 請求項１に記載の半導体装置の製造方法において、
前記（ｄ）工程において、前記封止体の外側で、前記第２吊りリードを切断することにより、前記第２枠体を前記封止体から切り離す、半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein in the step (d), the second suspension body is cut off from the sealing body by cutting the second suspension lead outside the sealing body.
JP2016191663A 2016-09-29 2016-09-29 Method for manufacturing semiconductor device Active JP6677616B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2016191663A JP6677616B2 (en) 2016-09-29 2016-09-29 Method for manufacturing semiconductor device
US15/660,294 US9966329B2 (en) 2016-09-29 2017-07-26 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016191663A JP6677616B2 (en) 2016-09-29 2016-09-29 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JP2018056369A JP2018056369A (en) 2018-04-05
JP6677616B2 true JP6677616B2 (en) 2020-04-08

Family

ID=61685700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016191663A Active JP6677616B2 (en) 2016-09-29 2016-09-29 Method for manufacturing semiconductor device

Country Status (2)

Country Link
US (1) US9966329B2 (en)
JP (1) JP6677616B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10651109B2 (en) * 2018-07-16 2020-05-12 Infineon Technologies Ag Selective plating of semiconductor package leads
WO2020161937A1 (en) * 2019-02-05 2020-08-13 パナソニックＩｐマネジメント株式会社 Sensor device
US20210043466A1 (en) * 2019-08-06 2021-02-11 Texas Instruments Incorporated Universal semiconductor package molds
JP7196815B2 (en) * 2019-10-23 2022-12-27 三菱電機株式会社 Semiconductor module and power converter
CN110610884B (en) * 2019-10-28 2021-06-22 四川旭茂微科技有限公司 Coating film chip adhesion device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05243358A (en) * 1992-02-27 1993-09-21 Nec Kansai Ltd Lead frame for resin mold and resin molding apparatus
US5910010A (en) * 1994-04-26 1999-06-08 Hitachi, Ltd. Semiconductor integrated circuit device, and process and apparatus for manufacturing the same
US6159770A (en) * 1995-11-08 2000-12-12 Fujitsu Limited Method and apparatus for fabricating semiconductor device
JP3871486B2 (en) * 1999-02-17 2007-01-24 株式会社ルネサステクノロジ Semiconductor device
JP2003031736A (en) * 2001-07-13 2003-01-31 Hitachi Ltd Semiconductor device and its manufacturing method
KR100781149B1 (en) * 2001-12-21 2007-11-30 삼성테크윈 주식회사 Leadframe strip and method of manufacturing semiconductor package using same
JP5119092B2 (en) 2008-08-28 2013-01-16 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP5507344B2 (en) * 2010-06-08 2014-05-28 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP5701523B2 (en) 2010-06-22 2015-04-15 日東電工株式会社 Semiconductor light emitting device
JP2014007363A (en) * 2012-06-27 2014-01-16 Renesas Electronics Corp Method of manufacturing semiconductor device and semiconductor device

Also Published As

Publication number Publication date
US20180090423A1 (en) 2018-03-29
JP2018056369A (en) 2018-04-05
US9966329B2 (en) 2018-05-08

Similar Documents

Publication Publication Date Title
JP6677616B2 (en) Method for manufacturing semiconductor device
TW575955B (en) Leadframe and method of manufacturing a semiconductor device using the same
JP6260593B2 (en) Lead frame, package, light emitting device, and manufacturing method thereof
TWI505519B (en) Light-emitting diode light bar and manufacturing method thereof
KR20080027920A (en) Semiconductor devices
JP6394634B2 (en) Lead frame, package, light emitting device, and manufacturing method thereof
JP6337873B2 (en) Package, package intermediate, light emitting device, and manufacturing method thereof
US9184118B2 (en) Micro lead frame structure having reinforcing portions and method
JP2008140944A (en) Light emitting device and manufacturing method thereof
US9673122B2 (en) Micro lead frame structure having reinforcing portions and method
US10304759B2 (en) Electronic device and method of making same
US20080073763A1 (en) Semiconductor device and method of manufacturing the same
CN104979321B (en) Semiconductor die package with multiple installation configurations
TW201541566A (en) Flat no-lead package and manufacturing method thereof
JP2015510277A (en) Semiconductor laser chip package having encapsulated indentations molded on a substrate and method for forming the same
JP2005116937A (en) Semiconductor light emitting device and manufacturing method thereof
WO2013150890A1 (en) Semiconductor device
JP2010109255A (en) Semiconductor device
JP5147295B2 (en) Semiconductor device
US20220109282A1 (en) Method for obtaining electronic devices and electronic devices
KR20020093250A (en) ELP type leadframe and ELP using the same
JP2006229263A (en) Semiconductor device
JP2010050491A (en) Method of manufacturing semiconductor device
JP2005277434A (en) Semiconductor device
KR20150142916A (en) Semiconductor package and method for manufacturing the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190313

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20191114

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20191119

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200116

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200303

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200313

R150 Certificate of patent or registration of utility model

Ref document number: 6677616

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150