JP6672962B2 - Silicon carbide semiconductor substrate and method of manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor substrate and a method for manufacturing a semiconductor device.

  In a semiconductor device including a silicon carbide (SiC) layer as an operation layer, an insulating film made of silicon dioxide and an electrode made of a conductor such as a metal are arranged on the silicon carbide layer. In a semiconductor device, it is important to improve operation reliability. In this regard, there has been proposed a measure for improving the reliability of an insulating film when an electrode made of a specific material is employed (for example, see Patent Document 1).

JP 2014-38899 A

  As described above, in a semiconductor device, it is important to improve operation reliability. Therefore, it is an object to provide a silicon carbide semiconductor substrate that can be used for manufacturing a highly reliable semiconductor device and a method for manufacturing a semiconductor device that can manufacture a highly reliable semiconductor device. .

  A silicon carbide semiconductor substrate according to the present invention includes a 4H silicon carbide substrate having an off angle of more than 0 ° and less than 5 °, and an epi layer made of silicon carbide formed on the 4H silicon carbide substrate. A triangular concave portion and a protrusion made of silicon carbide are formed on the surface of the epi layer. When viewed from the surface side of the epi layer, the protrusion overlaps the recess.

  According to the silicon carbide semiconductor substrate, it is possible to provide a silicon carbide semiconductor substrate that can be used for manufacturing a highly reliable semiconductor device.

FIG. 3 is a schematic sectional view showing an example of the structure of the silicon carbide semiconductor substrate. FIG. 4 is a schematic plan view showing a structure of a concave portion and a projecting portion formed on a surface of an epi layer. It is a schematic sectional drawing which shows the structure of the recessed part and the protrusion part formed in the surface of an epi layer. 4 is a flowchart schematically showing an example of a method for manufacturing a silicon carbide semiconductor substrate and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). FIG. 3 is a schematic cross-sectional view for describing an example of a method for manufacturing a MOSFET. FIG. 3 is a schematic cross-sectional view for describing an example of a method for manufacturing a MOSFET. FIG. 4 is a schematic cross-sectional view showing a state of a concave portion in a sacrificial oxide film forming step. FIG. 3 is a schematic cross-sectional view for describing an example of a method for manufacturing a MOSFET. FIG. 9 is a schematic sectional view showing a state of a concave portion in a sacrificial oxide film removing step. FIG. 3 is a schematic cross-sectional view for describing an example of a method for manufacturing a MOSFET. FIG. 3 is a schematic cross-sectional view for describing an example of a method for manufacturing a MOSFET. FIG. 3 is a schematic cross-sectional view for describing an example of a method for manufacturing a MOSFET. FIG. 3 is a schematic cross-sectional view for describing an example of a method for manufacturing a MOSFET. FIG. 3 is a schematic cross-sectional view for describing an example of a method for manufacturing a MOSFET. FIG. 1 is a schematic cross-sectional view illustrating an example of a structure of a MOSFET.

[Description of Embodiment of the Present Invention]
First, embodiments of the present invention will be listed and described. The silicon carbide semiconductor substrate of the present application includes a 4H silicon carbide substrate having an off angle of more than 0 ° and less than 5 °, and an epi layer made of silicon carbide formed on the 4H silicon carbide substrate. A triangular concave portion and a protrusion made of silicon carbide are formed on the surface of the epi layer. When viewed from the surface side of the epi layer, the protrusion overlaps the recess.

  In a semiconductor device including a silicon carbide layer as an operation layer, a problem may occur in the reliability of the operation. The present inventor studied the cause and obtained the following knowledge to arrive at the present invention. According to the study of the present inventors, in a semiconductor device having a structure in which an oxide film (for example, a gate insulating film) is formed on the surface of an epilayer on a 4H silicon carbide substrate having an off angle of more than 0 ° and less than 5 ° In some cases, a plurality of pits having a hexagonal outer shape in plan view are formed on the surface of the epi layer in contact with the oxide film. In an oxide film formed so as to be in contact with the surface of the epi layer in which such pits are formed, electric field concentration occurs due to variations in the thickness of the oxide film, and the reliability of the oxide film decreases. As a result, the reliability of the operation of the semiconductor device decreases. By reducing the density of the pits on the surface of the epi layer, it is possible to suppress a decrease in operation reliability.

  A plurality of recesses having a triangular shape in a plan view are formed on the surface of the epi layer. The pits are formed, for example, by forming a region that is deeply oxidized when a sacrificial oxide film is formed as a pretreatment for forming an oxide film on the epilayer, and the sacrificial oxide film is removed. It is formed in the recess.

  In the silicon carbide semiconductor substrate of the present application, a projection made of silicon carbide is formed so as to overlap with the concave portion when viewed from the surface side of the epi layer. Therefore, for example, even if a deeply oxidized region is formed during the formation of the sacrificial oxide film, the formation of the pits is suppressed by forming the protruding portion in the region. Therefore, according to the silicon carbide semiconductor substrate of the present application, a silicon carbide semiconductor substrate that can be used for manufacturing a highly reliable semiconductor device can be provided.

  In the above-described silicon carbide semiconductor substrate, the center of gravity of the protruding portion may be in the recess when viewed from the surface side of the epi layer. This makes it possible to more reliably suppress the formation of the pits.

  In the above silicon carbide semiconductor substrate, a plurality of concave portions may be formed on the surface of the epi layer.

  In the silicon carbide semiconductor substrate, a plurality of protrusions may be formed on the surface of the epi layer. Projections may be formed in more than half of the recesses. This makes it possible to more reliably suppress the formation of the pits.

  In the above-described silicon carbide semiconductor substrate, one projection may be formed in each of the recesses. This makes it possible to more reliably suppress the formation of the pits.

  In the silicon carbide semiconductor substrate, the projection may be formed in the recess when viewed from the front side of the epi layer. This makes it possible to more reliably suppress the formation of the pits.

  The method for manufacturing a semiconductor device according to the present application includes the steps of preparing the silicon carbide semiconductor substrate of the present application, forming an oxide film by oxidizing the surface of the epi layer, and removing the oxide film. Is provided.

  As described above, in the method of manufacturing a semiconductor device including the step of forming the oxide film (sacrificial oxide film) on the surface of the epi layer and then removing the oxide film, the pits may be formed on the surface of the epi layer. There is. In the method of manufacturing a semiconductor device according to the present application, the formation of the pits is suppressed because the silicon carbide semiconductor substrate on which the protrusions are formed is prepared. As a result, according to the method for manufacturing a semiconductor device of the present application, a semiconductor device having high reliability can be manufactured.

[Details of the embodiment of the present invention]
Next, an embodiment of a silicon carbide semiconductor substrate according to the present invention will be described below with reference to the drawings. In the following drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

  Referring to FIG. 1, an epi-substrate which is a silicon carbide semiconductor substrate in the present embodiment will be described. Referring to FIG. 1, an epi substrate 10 includes a substrate 11 and an epi layer 12.

  Substrate 11 is made of 4H silicon carbide. Substrate 11 has an n-type conductivity by including an n-type impurity such as nitrogen (N). The substrate 11 has an off angle of more than 0 ° and less than 5 °. Epi layer 12 is made of silicon carbide. The epi layer 12 is a layer formed on the first main surface 11A of the substrate 11 by epitaxial growth. The epi layer 12 has an epi main surface 12 </ b> A which is a main surface on the opposite side to the substrate 11. The epi principal surface 12A is a surface (principal surface) of the epi substrate 10 having an off angle of 4 ° or less with respect to the c-plane.

  Referring to FIGS. 1 to 3, a plurality of concave portions 92 having a triangular shape are formed in epi main surface 12A. Projection 91 made of silicon carbide is formed so as to overlap with recess 92. The protruding portion 91 has a shape such as a polygonal pyramid shape, a truncated polygonal pyramid shape, a conical shape, and a truncated conical shape. In the present embodiment, the projecting portion 91 has a hexagonal pyramid shape. When viewed in plan, the protrusion 91 has a shape such as a polygon or a circle. In the present embodiment, the projecting portion 91 has a hexagonal shape. Referring to FIG. 2, the center of gravity A of protrusion 91 is located in recess 92 when viewed from the front side of epi layer 12. In the present embodiment, the protrusion 91 is formed in the recess 92. The center of gravity A of the protrusion 91 is located between the center of gravity G of the recess 92 and the apex P of the recess 92 when viewed from the surface side of the epi layer 12. When viewed from the surface side of the epi layer 12, the protrusion 91 is located between the center of gravity G and the vertex P of the recess 92. The center of gravity A of the protrusion 91 is located on the [-1-120] side when viewed from the center of gravity G of the concave portion 92. The presence of the protrusion 91 and the recess 92 can be confirmed by using, for example, an AFM (Atomic Force Microscope).

  Next, an example of a method for manufacturing a silicon carbide semiconductor substrate and a semiconductor device in the present embodiment will be described. Referring to FIG. 4, in the method of manufacturing epi substrate 10 which is a silicon carbide semiconductor substrate in the present embodiment, first, a substrate preparing step is performed as a step (S10). In this step (S10), referring to FIG. 1, substrate 11 is prepared, for example, by slicing an ingot made of 4H—SiC containing an n-type impurity at a desired concentration. The first main surface 11A of the substrate 11 is a surface having an off angle with respect to the c-plane of more than 0 ° and less than 5 ° (4 ° or less).

  Next, a first epitaxial growth step is performed as a step (S20). In this step (S20), referring to FIG. 1, epitaxial layer 12 made of silicon carbide is formed on first main surface 11A of substrate 11 prepared in step (S10) by epitaxial growth. The step flow in the epitaxial growth may be, for example, in the direction of [11-20]. Epi layer 12 is formed so as to include a desired n-type impurity to be included in drift region 13 described later.

The epitaxial layer 12 is grown by epitaxial growth by using, for example, a mixed gas containing silane (SiH ₄ ), propane (C ₃ H ₈ ), hydrogen (H ₂ ), and ammonia (NH ₃ ) on the first main surface 11A of the substrate 11. Can be carried out. Silane is a source gas of silicon constituting silicon carbide. Propane is a raw material gas of carbon constituting silicon carbide. Hydrogen functions as an etching gas for maintaining proper step flow growth during the growth of the epi layer 12. Ammonia is a source gas of nitrogen introduced as an impurity. Nitrogen (N ₂ ) may be used instead of ammonia. In the step (S20), the growth temperature can be constant. The growth temperature can be, for example, 1600 ° C. Here, threading dislocations are present in the substrate 11, and the threading dislocations extend into the epitaxial layer 12 formed by epitaxial growth. Referring to FIGS. 2 and 3, when epi layer 12 is formed while the step flow in the direction of [11-20] is maintained, epi main surface 12A extends into epi layer 12. A recess 92 having a triangular planar shape is formed so as to correspond to threading dislocation 99. At this stage, the projecting portion 91 has not been formed.

  Next, a second epitaxial growth step is performed as a step (S30). In this step (S30), the protrusion 91 is formed so as to overlap the recess 92. Step (S30) can be performed subsequently using the same apparatus as in step (S20). Specifically, in the step (S30), of the mixed gas used for growing the epitaxial layer 12 in the step (S20), the supply of hydrogen is stopped, and argon (Ar) is supplied instead of hydrogen. Here, referring to FIGS. 2 and 3, there are many dangling bonds in a region corresponding to threading dislocation 99. Therefore, the growth rate and etching rate of silicon carbide are higher than in other regions. In the step of supplying hydrogen as the etching gas (S20), the balance between the growth rate of silicon carbide and the etching rate is maintained. Therefore, in the region corresponding to threading dislocation 99, silicon carbide grows at the same speed as the other regions. However, when the supply of hydrogen is stopped in the step (S30), growth is superior to etching. Then, the growth rate of silicon carbide in the region corresponding to threading dislocation 99 is higher than in other regions. As a result, a protrusion 91 is formed in a region corresponding to the threading dislocation 99. The end of the threading dislocation 99 in the epi layer 12 is located in the recess 92. Therefore, the projecting portion 91 is formed so as to overlap the concave portion 92. In the present embodiment, the protrusion 91 is formed inside the recess 92. It is preferable that the thickness of the epitaxial layer 12 grown in the step (S30) be 10 nm or less. The growth rate of the epi layer 12 in the step (S30) can be, for example, 15 μm / h (about 4 nm / sec). That is, the growth time in the step (S30) is preferably within 12 seconds.

  Through the above steps, the epitaxial substrate 10 in which the projections 91 made of silicon carbide are formed so as to overlap the concave portions 92 when viewed from the surface side of the epitaxial layer 12 is completed. Subsequently, a method of manufacturing a MOSFET, which is an example of a method of manufacturing a semiconductor device performed using the epi substrate 10, will be described.

  Next, an ion implantation step is performed as a step (S40). In this step (S40), ion implantation is performed on the epi-substrate 10 prepared in the steps (S10) to (S30). Specifically, referring to FIG. 1 and FIG. 5, first, ions to be p-type impurities such as Al ions are implanted into a region including epi-main surface 12A of epi layer 12. Thereby, a plurality of body regions 14 are formed in the epi layer 12 at desired intervals. Next, ions to be n-type impurities such as P ions are implanted into a region shallower than the thickness of body region 14. As a result, a source region 15 is formed in each body region 14. Next, ions to be p-type impurities such as Al ions are implanted into the source region 15 so as to have a thickness equivalent to the thickness of the source region 15. As a result, a contact region 16 is formed in each source region 15. In the epi layer 12, a region where none of the body region 14, the source region 15, and the contact region 16 is formed becomes the drift region 13.

  Next, an activation annealing step is performed as a step (S50). In this step (S50), referring to FIG. 5, epi substrate 10 is heated to a predetermined temperature. Thereby, the impurities implanted in the step (S40) are activated, and desired carriers are generated in the regions into which the impurities have been implanted.

Next, referring to FIG. 4, a sacrificial oxide film forming step is performed as a step (S60). In this step (S60), referring to FIGS. 5 and 6, epi substrate 10 is heated, for example, in an atmosphere containing oxygen. As a result, a sacrificial oxide film 29, which is a thermal oxide film made of SiO _2, is formed so as to cover the epi main surface 12A of the epi layer 12. At this time, referring to FIGS. 3 and 7, the region corresponding to threading dislocation 99 has a higher oxidation rate than other regions. Therefore, the thickness of sacrificial oxide film 29 increases in a region corresponding to threading dislocation 99, that is, in a region corresponding to protrusion 91.

  Next, referring to FIG. 4, a sacrificial oxide film removing step is performed as a step (S70). In this step (S70), referring to FIGS. 6 and 8, sacrificial oxide film 29 formed in step (S60) is removed. The removal of the sacrificial oxide film 29 can be performed using, for example, hydrofluoric acid. Thereby, the abnormal layer and the like near the main epitaxial surface 12A formed on the epi substrate 10 in the previous step are removed. At this time, referring to FIGS. 7 and 9, since the thickness of sacrificial oxide film 29 in the region corresponding to protrusion 91 is larger than in other regions, protrusion 91 is flattened or removed.

Next, referring to FIG. 4, a gate insulating film forming step is performed as a step (S80). In this step (S80), referring to FIGS. 8 and 10, epi substrate 10 on which step (S70) has been performed is heated, for example, in an atmosphere containing oxygen. As a result, a gate insulating film 20, which is a thermal oxide film made of SiO _2, is formed so as to cover epi main surface 12A of epi layer 12.

  Next, a gate electrode forming step is performed as a step (S90). In this step (S90), referring to FIGS. 10 and 11, for example, by LPCVD (Low Pressure Chemical Vapor Deposition), gate electrode 30 made of polysilicon containing an appropriate amount of impurities contacts gate insulating film 20. It is formed.

Next, an interlayer insulating film forming step is performed as a step (S100). In this step (S100), referring to FIGS. 11 and 12, an interlayer insulating film 40 made of SiO ₂ is formed, for example, by LPCVD so as to cover gate electrode 30 and gate insulating film 20.

  Next, referring to FIG. 4, a contact hole forming step is performed as a step (S110). In this step (S110), referring to FIGS. 12 and 13, contact hole 40A penetrating through interlayer insulating film 40 and gate insulating film 20 is formed. Specifically, a contact hole 40A is formed by forming a mask layer having an opening in a region where the contact hole 40A is to be formed, and performing RIE (Reactive Ion Etching) using the mask layer as a mask. can do. The epi principal surface 12A of the epi layer 12 (more specifically, the surfaces of the source region 15 and the contact region 16) is exposed from the contact hole 40A.

  Next, referring to FIG. 4, a metal film forming step is performed as a step (S120). In this step (S120), referring to FIGS. 13 and 14, contact is made with epi major surface 12A (more specifically, surfaces of source region 15 and contact region 16) of epi layer 12 exposed from contact hole 40A. As described above, a metal film to be the source electrode 60 is formed. More specifically, for example, a Ti film, an Al film, and a Si film are formed so as to cover epi main surface 12A of epi layer 12 exposed from contact hole 40A and the side wall of contact hole 40A and extend over interlayer insulating film 40. Are formed in this order. Further, a metal film having a similar structure is formed so as to cover the second main surface 11B of the substrate 11. The metal film can be formed by, for example, sputtering.

  Next, referring to FIG. 4, an alloying annealing step is performed as a step (S130). In this step (S130), the metal film formed in step (S120) is heated and alloyed. Thus, a source electrode 60 in ohmic contact with the epi layer 12 and a drain electrode 70 in ohmic contact with the substrate 11 are obtained.

  Next, a wiring forming step is performed as a step (S140). In this step (S140), referring to FIGS. 14 and 15, a source wiring 80 made of a conductor such as Al is formed by, for example, an evaporation method so as to be in contact with source electrode 60. Through the above procedure, MOSFET 1 of the present embodiment can be manufactured.

  Referring to FIG. 15, MOSFET 1 includes an epi-substrate 10 including a substrate 11 and an epi-layer 12, a gate insulating film 20, a gate electrode 30, an interlayer insulating film 40, a source electrode 60, and a drain electrode 70. , Source wiring 80.

  The body region 14 is arranged so as to include the epi main surface 12A which is the main surface of the epi layer 12 opposite to the substrate 11. A plurality of body regions 14 are formed at a predetermined interval from each other along epi main surface 12A. Body region 14 has a p-type conductivity by including a p-type impurity such as aluminum (Al) or boron (B).

  Source region 15 is arranged so as to include epi main surface 12 </ b> A and be surrounded by each body region 14. Source region 15 has an n-type conductivity by including an n-type impurity such as phosphorus (P).

  Contact region 16 is arranged so as to include epi main surface 12A and be surrounded by source region 15. The contact region 16 has a p-type conductivity by containing a p-type impurity such as Al or B, for example.

  In the epi layer 12, a region other than the body region 14, the source region 15, and the contact region 16 is a drift region 13. Drift region 13 has an n-type conductivity by including an n-type impurity such as N, for example. Source region 15 has a higher n-type impurity concentration than drift region 13. Further, contact region 16 has a higher p-type impurity concentration than body region 14.

Gate insulating film 20 is an oxide film made of an oxide such as silicon dioxide (SiO ₂ ). Gate insulating film 20 is arranged in contact with epi main surface 12A. The gate insulating film 20 extends from above the source region 15 arranged and surrounded by one body region 14 to above the source region 15 arranged and surrounded by another body region 14 adjacent to the one body region 14. Extending.

  Gate electrode 30 is arranged in contact with gate insulating film 20. Gate electrode 30 is made of a conductor such as polysilicon to which an impurity is added. Gate electrode 30 extends from above source region 15 arranged and surrounded by one body region 14 to above source region 15 arranged and surrounded by another body region 14 adjacent to one body region 14. Are there.

The interlayer insulating film 40 is made of an insulator such as SiO ₂ . The interlayer insulating film 40 is formed on the gate insulating film 20 so as to surround the gate electrode 30. A contact hole 40A is formed so as to penetrate through the interlayer insulating film 40 and the gate insulating film 20 in the thickness direction. That is, the side wall surface of the contact hole 40A is constituted by the gate insulating film 20 and the interlayer insulating film 40. Source region 15 and contact region 16 are exposed from contact hole 40A.

  The source electrode 60 is an interlayer insulating film forming an epi principal surface 12A of the epi layer 12 exposed from the contact hole 40A (more specifically, surfaces of the source region 15 and the contact region 16) and a side wall surface defining the contact hole 40A. It is arranged so as to cover the surface of 40 and extend onto the interlayer insulating film 40. Source electrode 60 is made of a conductor. Specifically, source electrode 60 is a metal film containing, for example, Ti (titanium), Al and Si (silicon), and is made of, for example, a TiAlSi alloy.

  Drain electrode 70 is arranged in contact with second main surface 11B of substrate 11. The drain electrode 70 is made of a conductor. Specifically, drain electrode 70 is a metal film containing, for example, Ti, Al, and Si, and is made of, for example, a TiAlSi alloy.

  The source wiring 80 is formed so as to cover the source electrode 60 and the interlayer insulating film 40. Source wiring 80 is made of a conductor such as Al, for example. The source wiring 80 is electrically connected to the source region 15 via the source electrode 60.

  When the voltage applied to the gate electrode 30 of the MOSFET 1 is lower than the threshold voltage, that is, when the MOSFET 1 is off, even if a voltage is applied between the source electrode 60 and the drain electrode 70, the body region 14 and the drift region 13 Then, the pn junction formed by the above becomes reverse bias and becomes non-conductive. On the other hand, when a voltage equal to or higher than the threshold voltage is applied to gate electrode 30 and MOSFET 1 is turned on, a semi-transition layer is formed in a surface layer facing gate electrode 30 with gate insulating film 20 interposed in body region 14. . As a result, the source region 15 and the drift region 13 are electrically connected, and a current flows between the source electrode 60 and the drain electrode 70. As described above, the MOSFET 1 operates.

  Here, the region corresponding to the threading dislocation 99 in the concave portion 92 has a high oxidation rate as described above. Therefore, when no countermeasure is taken, the thickness of the oxide film in the region corresponding to the threading dislocation 99 in the concave portion 92 increases when the sacrificial oxide film 29 is formed in the step (S60). Then, when the sacrificial oxide film 29 is removed in the step (S70), a pit having a hexagonal outer shape in plan view is formed in a region corresponding to the threading dislocation 99 in the concave portion 92. Then, when the gate insulating film 20 is formed so as to be in contact with the epi principal surface 12A of the epi layer 12 in which the pits are formed in the step (S80), electric field concentration occurs due to a variation in the thickness of the gate insulating film 20. As a result, the reliability of the gate insulating film 20 decreases. As a result, the reliability of the operation of the MOSFET 1 decreases.

  On the other hand, in the method of manufacturing MOSFET 1 in the present embodiment, epi substrate 10 having projection 91 made of silicon carbide formed so as to overlap recess 92 is used. Therefore, even if the thickness of the oxide film in the region corresponding to the threading dislocation 99 in the concave portion 92 increases in the step (S60), the formation of the pits is suppressed by forming the projecting portion 91 in the region. Is done. As described above, epi substrate 10 of the present embodiment is a silicon carbide semiconductor substrate that can be used for manufacturing a highly reliable semiconductor device. Further, according to the method for manufacturing MOSFET 1 of the present embodiment, MOSFET 1 having high reliability can be manufactured.

  In the epi-substrate 10, it is preferable that the protrusion 91 is formed in more than half of the plurality of recesses 92. Thereby, the formation of the pits can be more reliably suppressed. It is more preferable that 80% or more of the plurality of concave portions 92 have the protruding portions 91 formed therein.

  It is preferable that one protrusion 91 is formed in each of the recesses 92. Thereby, the formation of the pits can be more reliably suppressed. Further, the height of the protruding portion 91 is preferably set to 10 nm or less.

  In the above embodiment, the MOSFET has been described as an example of the semiconductor device. However, the semiconductor device that can be manufactured by the manufacturing method of the present application is not limited to this. For example, a semiconductor device having another structure such as an IGBT (Insulated Gate Bipolar Transistor) is used. It may be.

  It should be understood that the embodiments disclosed this time are illustrative in all aspects and are not restrictive in any aspect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The method for manufacturing a silicon carbide semiconductor substrate and a semiconductor device of the present application can be particularly advantageously applied to the manufacture of a semiconductor device that requires improvement in operation reliability.

1 MOSFET
DESCRIPTION OF SYMBOLS 10 Epi-substrate 11 Substrate 11A, 11B Main surface 12 Epi-layer 12A Epi-main surface 13 Drift region 14 Body region 15 Source region 16 Contact region 20 Gate insulating film 29 Sacrificial oxide film 30 Gate electrode 40 Interlayer insulating film 40A Contact hole 60 Source electrode 70 Drain electrode 80 Source wiring 91 Projection 92 Depression 99 Threading dislocation

Claims (7)

A 4H silicon carbide substrate having an off angle of more than 0 ° and less than 5 °,
An epi layer made of silicon carbide formed on the 4H silicon carbide substrate,
A triangular recess and a protrusion made of silicon carbide are formed on the surface of the epi layer,
When viewed from the surface side of the epi layer, the protrusion overlaps the recess,
Silicon carbide semiconductor substrate. When viewed from the surface side of the epi layer, the center of gravity of the protrusion is in the recess.
The silicon carbide semiconductor substrate according to claim 1. On the surface of the epi layer, a plurality of the concave portions are formed,
The silicon carbide semiconductor substrate according to claim 1. A plurality of the protrusions are formed on the surface of the epi layer,
The protrusion is formed in at least half of the recesses,
The silicon carbide semiconductor substrate according to claim 3. In each of the recesses, the protrusion is formed one by one,
The silicon carbide semiconductor substrate according to claim 4. When viewed from the surface side of the epi layer, the protrusion is formed in the recess.
The silicon carbide semiconductor substrate according to claim 1. A step of preparing the silicon carbide semiconductor substrate according to any one of claims 1 to 5,
Forming an oxide film by oxidizing the surface of the epi layer;
Removing the oxide film.
A method for manufacturing a semiconductor device.

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