JP6669030B2 - Switching power supply - Google Patents

Description

  The present invention relates to a switching power supply used for a power supply for LED lighting and the like.

  The power supply for LED lighting such as base lighting and ceiling light is composed of AC power supply, electromagnetic wave noise elimination filter (EMI filter), power factor improvement circuit (PFC section), step-down chopper, LED, sub power supply, microcomputer, and drive circuit. Have been. The sub power supply supplies power to the PFC unit and the microcomputer. The microcomputer performs power control, dimming control, and initial illuminance correction. The drive circuit drives the PFC section and the step-down chopper under the control of the microcomputer.

  The PFC unit is often operated in a critical mode in which the switching element is turned on when the reactor current becomes zero in order to reduce noise. However, in many cases, the step-down chopper operates in a PWM (pulse width modulation) mode in which the oscillation frequency of the switching element is fixed in consideration of power supply operation stability at the time of dimming, that is, at a light load.

  As a conventional technique of this type, a load control device described in Patent Literature 1 is known. The load control device includes switching means for switching an operation mode of the power factor correction circuit between a critical mode and a discontinuous current mode according to a dimming signal.

Japanese Patent No. 5152501

  However, the critical mode has lower EMI and higher efficiency than the PWM mode, but the oscillation frequency of the switching element changes due to a change in load or input voltage. In particular, when the load is light (when dimming is low) or when the input voltage is high, the oscillation frequency increases as shown in FIG.

  At this time, the switching operation of the switching element becomes unstable because the switching loss increases and the ON width becomes extremely short. As a solution to this problem, there is a method of providing an upper limit (fmax) to the oscillation frequency irrespective of dimming and a change in input voltage, as shown in FIG. In this method, when the oscillation frequency reaches the frequency upper limit value fmax, a bottom skip operation is performed, and the number of skips increases or decreases according to the load. Therefore, an increase in the oscillation frequency is suppressed.

  In addition, in LED lighting, stable switch control that does not generate ripples in LED current is required even under a light load condition of 5% or less dimming so that flicker does not occur in light emission.

  An object of the present invention is to provide a switching power supply device capable of performing stable switch control and improving efficiency.

  A switching power supply device according to the present invention has a voltage detection circuit that detects an AC voltage of an AC power supply, operates in a critical mode, has a switching element, and switches an AC voltage of the AC power supply to a DC voltage by switching the switching element. A power factor improving circuit that converts the voltage into a voltage, a DC / DC converter that converts a DC voltage output from the power factor improving circuit into another DC voltage and supplies power to a load, and a control circuit that turns on and off the switching element And a maximum oscillation frequency limiting circuit that sets a maximum oscillation frequency of the switching element in proportion to the detection voltage based on the detection voltage detected by the voltage detection circuit.

  According to the present invention, the maximum oscillation frequency limiting circuit sets the maximum oscillation frequency of the switching element in proportion to the detection voltage based on the detection voltage detected by the voltage detection circuit, so that the lower the AC voltage, the lower the maximum oscillation frequency. By setting so that a wide ON width can be secured. Therefore, it is possible to provide a switching power supply device capable of performing stable switch control and improving efficiency.

FIG. 2 is a diagram illustrating a circuit configuration of the switching power supply device according to the first embodiment of the present invention. FIG. 2 is a configuration block diagram of a control circuit including a maximum oscillation frequency limiting circuit in the switching power supply device according to Embodiment 1 of the present invention. FIG. 3 is a detailed configuration diagram of a maximum oscillation frequency limiting circuit and an oscillator illustrated in FIG. 2. FIG. 3 is a detailed configuration diagram of a maximum oscillation frequency limiting unit in the maximum oscillation frequency limiting circuit. FIG. 3 is a diagram illustrating a configuration of a variable current source that varies a current according to an input voltage. 5 is a timing chart illustrating the operation of each unit in the maximum oscillation frequency limiting circuit. FIG. 7 is a diagram illustrating a state in which the maximum oscillation frequency of the switching element is limited according to the input voltage in the critical mode in the present invention. FIG. 7 is a diagram illustrating a change in an oscillation frequency of a switching element with respect to an input voltage and dimming in a critical mode. FIG. 4 is a diagram illustrating a limitation on a maximum oscillation frequency of a switching element with respect to an input voltage and dimming in a critical mode in a conventional circuit.

  Hereinafter, a switching power supply according to an embodiment of the present invention will be described in detail with reference to the drawings.

(Example 1)
FIG. 1 is a diagram illustrating a circuit configuration of a switching power supply device according to Embodiment 1 of the present invention. The switching power supply includes an AC power supply 1, a full-wave rectifier circuit 2, a voltage detection circuit 3, a PFC (power factor correction circuit) unit 4, a DC / DC converter 5, an LED 6, and a control circuit 7.

  The full-wave rectifier circuit 2 performs full-wave rectification on the AC voltage of the AC power supply 1 and outputs a rectified voltage to the PFC unit 4. The voltage detection circuit 3 detects an AC voltage of the AC power supply and outputs the detected voltage to the control circuit 7.

  The PFC section 4 operates in the critical mode, has a switching element Qo, and converts the rectified voltage from the full-wave rectifier circuit 2 into a DC voltage by turning on and off the switching element Qo.

  The PFC unit 4 includes a series circuit of a reactor Lo, a switching element Qo, and a current detection resistor Ro at both ends of the output of the full-wave rectifier circuit 2, a series circuit of a diode Do and a capacitor Co connected at both ends of the series circuit. Having.

  The DC / DC converter 5 converts a DC voltage output from the PFC unit 4 into another DC voltage and supplies power to the LED 6 as a load.

  The control circuit 7 turns on / off the switching element Qo of the PFC unit 1 and controls on / off of a switching element (not shown) in the DC / DC converter 5. The control circuit 7 includes a maximum oscillation frequency limiting circuit 11 that sets the maximum oscillation frequency of the switching element Qo in proportion to the detection voltage based on the detection voltage detected by the voltage detection circuit 3.

  FIG. 2 is a configuration block diagram of a control circuit including a maximum frequency limiting circuit in the switching power supply according to Embodiment 1 of the present invention. The control circuit 7 includes an FB terminal for inputting an output voltage from the capacitor Co as a feedback voltage, a COMP terminal as an output terminal of the error amplifier EAM, a CS terminal for inputting a source voltage of the switching element Qo, a power supply Vcc terminal, and a switching element. An OUT terminal for outputting a gate signal to be applied to the gate of Qo, a GND terminal, a ZCD terminal for inputting a zero current detection signal (ZCD signal) for detecting that the current flowing through the auxiliary winding Lc has become zero, and a voltage. It has a VSENSE terminal for inputting the voltage detected by the detection circuit 3.

  The error amplifier EAM amplifies an error voltage between the voltage from the FB terminal and the reference voltage Vref1, and outputs the amplified error voltage to the comparator CP1. The comparator CP1 generates a pulse signal by comparing the triangular wave signal from the oscillator OSC with the error voltage VCOMP from the error amplifier EAM, and outputs the pulse signal to the reset terminal R of the flip-flop circuit RS1 via the OR circuit OR1. The flip-flop circuit RS1 outputs a pulse signal to the gate of the switching element Qo via the buffer circuit BF1 and the OUT terminal. Thereby, the switching element Qo can be turned on and off.

  When the voltage from the FB terminal becomes equal to or higher than the reference voltage Vref3, the overvoltage protection comparator OVP outputs an H level to the OR circuit 1 to turn off the switching element Qo, thereby performing overvoltage protection. When the voltage from the FB terminal becomes equal to or lower than the reference voltage Vref2, the low-voltage protection comparator UVP outputs an H level to the OR circuit 1 to turn off the switching element Qo, thereby performing low-voltage protection.

  When the source voltage of the switching element Qo becomes equal to or higher than the reference voltage Vref5, the comparator OCP1 outputs an H level to the OR circuit 1 to turn off the switching element Qo, thereby protecting the switching element Qo from overcurrent. .

  The regulator REG connected to the Vcc terminal supplies power to each unit in the control circuit 7. The comparator UVLO stops the regulator REG when the voltage obtained by dividing the Vcc voltage by the resistors R1 and R2 becomes equal to or lower than the reference voltage Vref4.

  Further, the control circuit 7 includes a maximum oscillation frequency limiting circuit 11, an OR circuit OR2, and a restart timer TM. The maximum oscillation frequency limiting circuit 11 includes a comparator 12, a down edge detection circuit 13, and a maximum oscillation frequency limiting unit 14.

  The comparator 12 outputs an H-level pulse to the down-edge detection circuit 13 when the ZCD signal input from the ZCD terminal is equal to or higher than the reference voltage Vref6. The down-edge detection circuit 13 detects the fall of the H-level pulse from the comparator 12 and outputs a fall detection signal to the maximum oscillation frequency limiting unit 14.

  The maximum oscillation frequency limiter 14 sets the maximum oscillation frequency fmax of the switching element Qo in proportion to the detection voltage based on the detection voltage detected by the voltage detection circuit 3, and outputs the signal of the maximum oscillation frequency fmax to the OR circuit OR2 and the oscillator OSC. To the gate of the MOSFET Q1.

  FIG. 3 is a detailed configuration diagram of the maximum oscillation frequency limiting circuit 11 and the oscillator OSC shown in FIG. The oscillator OSC includes a constant current source I1, a MOSFET Q1 connected to the constant current source I1, a capacitor C1 connected to the constant current source I1, and a zener diode ZD connected to the constant current source I1.

  The capacitor C1 is charged by the current of the constant current source I1, and the voltage VC1 rises as shown. When the voltage VC1 of the capacitor C1 reaches a constant voltage, the voltage VC1 becomes a constant voltage due to breakdown of the Zener diode ZD. Further, when the signal of the maximum oscillation frequency from the maximum oscillation frequency limiter 14 is at the H level, the MOSFET Q1 is turned on, the capacitor C1 is discharged, and the voltage VC1 becomes zero. Therefore, the switching element Qo is turned on and off at the oscillation frequency f determined by the constant current source I1, the capacitor C1, and the MOSFET Q1.

  FIG. 4 is a detailed configuration diagram of the maximum oscillation frequency limiting unit 14 in the maximum oscillation frequency limiting circuit 11. The maximum oscillation frequency limiter 14 includes a variable current source I2, NOR circuits NOR1, NOR2, a MOSFET Q2, a capacitor C2, and a Zener diode ZD2.

  The variable current source I2 varies the current according to the input voltage V. As shown in FIG. 5, the resistors R3 and R4, the voltage follower VF, the resistor R5, the current mirror circuits Q3 and Q4, and the current mirror circuit Q5 , Q6.

  The input voltage VSENSE is divided by a resistor R3 and a resistor R4 and input to a voltage follower VF. A current corresponding to the input voltage VSENSE flows to the current mirror circuits Q3 and Q4 via the resistor R5, and the current flows to the current mirror circuits Q5 and Q6 to become a current of the variable current source I2. Therefore, the current flowing through the MOSFET Q6 increases when the input voltage VSENSE is high, and decreases when the input voltage VSENSE is low.

  That is, when the input voltage VSENSE is large, the current is large, so that the charging time of the capacitor C2 is short, and the maximum oscillation frequency fmax is high. When the input voltage VSENSE is small, the current is small, so that the charging time of the capacitor C2 becomes long, and the maximum oscillation frequency fmax becomes low.

  In FIG. 4, a NOR circuit NOR1 takes an OR of the inversion of the output of the down-edge detection circuit and the output of the comparator CP2, inverts the inversion of the OR with an inverter INV1, and outputs the OR to the gate of the MOSFET Q2 via the one-shot 1shot. I do. MOSFET Q2 is turned on for a pulse time of one shot 1shot.

  The comparator CP2 outputs the H level to the NOR circuits NOR1 and NOR2 when the voltage Vc2 of the capacitor C2 is lower than the voltage of the reference power supply Vref7, and outputs the L level when the voltage Vc2 is equal to or higher than the voltage of the reference power supply Vref7. The signal output from the comparator CP2 is a signal having the maximum oscillation frequency fmax. The NOR circuit NOR2 takes the OR of the inverted output of the down-edge detecting circuit and the output of the comparator CP2, and outputs the inverted OR as a signal of the maximum oscillation frequency fmax.

  The OR circuit OR2 outputs the maximum oscillation frequency signal from the maximum oscillation frequency limiter 14 to the set terminal S of the flip-flop circuit RS1. That is, the maximum oscillation frequency fmax is generated by the maximum oscillation frequency limiting circuit 11, and is output to the set terminal S of the flip-flop RS1.

  The cycle of the drain current Id and the voltage Vds of the switching element Qo provided in the PFC section 4, that is, the oscillation frequency of the switching element Qo is generated by the oscillator OSC and the comparator CP1, and output to the reset terminal R of the flip-flop RS1. You.

  Next, the operation of the maximum oscillating frequency limiting circuit 11 of the switching power supply of Embodiment 1 thus configured will be described in detail with reference to the timing chart shown in FIG.

  First, the capacitor C1 is charged by the current of the constant current source I1 from time t1, and until time t4 when the voltage Vc1 of the capacitor C1 becomes the output Vcomp of the error amplifier EMP, the output PWM of the comparator CP1 changes the L level to the flip-flop RS1. Output to

  Next, when the voltage Vc1 of the capacitor C1 becomes equal to or higher than the output Vcomp of the error amplifier EMP, the output PWM of the comparator CP1 outputs an H level to the flip-flop RS1 until time t6. Therefore, a pulse is output to the gate of the switching element Qo, so that the switching element Qo is turned on, and the drain current Id of the switching element Qo increases linearly.

  Further, at time t0, when the Lc winding voltage Vzcd proportional to the drain voltage of the switching element Qo drops sharply, the down edge detection circuit 13 detects the down edge of the Lc winding voltage Vzcd proportional to the drain voltage, An H level ZCD signal is output until time t1. From time t0 to time t1, the output of the down edge detection circuit 13 goes low, so that the output of the NOR circuit NOR1 of the maximum oscillation frequency limiting section 14 goes high.

  Since a one-shot one-shot pulse is included in the signal inverted by the inverter INV1, the MOSFET Q2 is turned on and the capacitor C2 is discharged, so that the voltage Vc2 of the capacitor C2 becomes zero. Therefore, the comparator CP2 outputs an H level, and the NOR circuit NOR2 outputs an L level.

  At time t2, the output of the one-shot 1shot becomes L level, and when the MOSFET Q2 is turned off, the capacitor C2 is charged by the current of the variable current source I2, and the voltage Vc2 increases.

  At time t3, when voltage Vc2 reaches reference voltage Vref7, comparator CP2 outputs an L level, and NOR circuit NOR2 outputs an L level. The operation from time t6 to t9 is the same as the operation from time t0 to t3.

  Next, when the input voltage VSENSE increases and the current of the variable current source I2 shown in FIG. 5 increases, the charging time of the capacitor C2 becomes shorter as shown at times t22 to t23 and t26 to t27. For this reason, the maximum oscillation frequency increases.

  On the other hand, when the input voltage VSENSE decreases and the current of the variable current source I2 decreases, the charging time of the capacitor C2 increases. For this reason, the maximum oscillation frequency decreases. FIG. 7 shows a state in which the maximum oscillation frequency of the switching element is limited according to the input voltage in the critical mode. FIG. 7 shows that the maximum oscillation frequency decreases when the input voltage VSENSE decreases.

  As described above, according to the switching power supply device of the first embodiment, the maximum oscillation frequency limiting circuit 11 sets the maximum oscillation frequency of the switching element Qo in proportion to the detection voltage based on the detection voltage detected by the voltage detection circuit 3. Therefore, by setting the maximum oscillation frequency to be smaller as the AC voltage (input voltage) is smaller, it is possible to secure a wide ON width. Therefore, it is possible to provide a switching power supply device capable of performing stable switch control and improving efficiency.

  At times t0 to t11 and times t20 to t27, the maximum oscillation frequency limiting circuit 11 operates in the critical mode when the oscillation frequency of the switching element Qo does not reach the maximum oscillation frequency fmax.

  From time t30 to t33, the load becomes light, and the Lc winding voltage Vzcd proportional to the voltage of the switching element Qo oscillates, and a bottom occurs. At this light load, after the oscillation frequency of the switching element Qo reaches the maximum oscillation frequency fmax, that is, the maximum oscillation frequency limiting circuit 11 operates in the bottom skip mode at an oscillation frequency equal to or lower than the maximum oscillation frequency.

  In this case, from time t30 to t31, the down edge circuit 13 detects the bottom of the voltage Vzcd. Since time t30 to t31 when the bottom is detected is within the ON time of the maximum oscillation frequency fmax, the NOR circuit NOR2 does not output the H level.

  Next, from time t32 to t33, the down-edge circuit 13 detects the bottom of the voltage Vzcd, and the time t32 to t33 when the bottom is detected exceeds the on-time of the maximum oscillation frequency fmax. Is output. That is, since the first bottom is skipped, the cycle of the maximum oscillation frequency fmax is extended.

  As described above, the switching loss of the switching element Qo can be reduced by lowering the maximum oscillation frequency fmax at a light load.

  In the first embodiment, the maximum oscillation frequency limiting circuit 11 is provided in the control circuit 7. However, for example, the maximum oscillation frequency limiting circuit 11 may be provided in the PFC unit 4.

DESCRIPTION OF SYMBOLS 1 AC power supply 2 Full-wave rectifier circuit 3 Voltage detection circuit 4 PFC part 5 DC / DC converter 6 LED
7 Control circuit 11 Maximum frequency limiting circuit 12 Comparator 13 Down edge detecting circuit 14 Maximum oscillation frequency limiting section OVP Overvoltage protection comparator UVP Low voltage protection comparator EAM Error amplifier Qo Switching elements CP1, CP2, OCP1 Comparator OSC Oscillator OR1, OR2 OR circuit NOR1 , NOR2 NOR circuit RS1 Flip-flop circuit BF1 Buffer circuit R1-R5 Resistance ZD Zener diode C1, C2 Capacitor INV1 Inverter 1 shot One shot

Claims (5)

A voltage detection circuit for detecting an AC voltage of the AC power supply;
A power factor improvement circuit that operates in a critical mode, has a switching element, and converts an AC voltage of the AC power supply into a DC voltage by switching the switching element;
A DC / DC converter that converts a DC voltage output from the power factor correction circuit into another DC voltage and supplies power to a load;
A control circuit for turning on and off the switching element;
A maximum oscillation frequency limiting circuit that sets a maximum oscillation frequency of the switching element in proportion to the detection voltage based on the detection voltage detected by the voltage detection circuit;
A switching power supply device comprising:   The maximum oscillation frequency limiting circuit operates in the critical mode when the oscillation frequency of the switching element does not reach the maximum oscillation frequency, and operates at the maximum after the oscillation frequency reaches the maximum oscillation frequency at light load. 2. The switching power supply according to claim 1, wherein the switching power supply operates in a PWM or bottom skip mode at an oscillation frequency equal to or lower than the oscillation frequency.   The switching power supply device according to claim 1, wherein the maximum oscillation frequency limiting circuit is provided in the control circuit.   3. The switching power supply device according to claim 1, wherein the maximum oscillation frequency limiting circuit is provided in the power factor improvement circuit.   The switching power supply according to any one of claims 1 to 4, wherein the load is an LED.

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