JP6666405B2 - Memory system and control method - Google Patents

Description

  Embodiments described herein relate generally to a technique for controlling a nonvolatile memory.

  2. Description of the Related Art In recent years, memory systems including a nonvolatile memory have become widespread.

  As one of such memory systems, a solid state drive (SSD) based on NAND flash technology is known.

  SSDs are used as main storages of various computers due to their features of low power consumption and high performance.

  Recently, attempts have been made to improve the performance of the SSD by control from the host.

International Publication No. WO2012 / 020544

  However, in order to improve the performance of the SSD, it is required to realize a new function for providing useful information for improving the performance to the host.

  The problem to be solved by the present invention is to provide a memory system and a control method that can provide a host with information on the frequency of updating data.

According to an embodiment, a memory system includes a nonvolatile memory and a controller configured to write data to the nonvolatile memory in response to a write command received from a host. The controller receives a first write command, which is a previous write command including a first logical address, from the host. After receiving the first write command, the controller receives, from the host, a second write command that is a current write command including the same logical address as the first logical address. Said controller, said after receiving the first of the total amount of data received from the host during the period from the reception of the write command until it receives the second write command or the first write command, A value related to an elapsed time until the second write command is received is obtained. The controller notifies the host of a total amount of the data or a value related to the elapsed time.

FIG. 1 is a block diagram illustrating a configuration example of a memory system according to an embodiment. FIG. 4 is an exemplary view for explaining a garbage collection number management operation and a garbage collection operation executed by the memory system of the embodiment. FIG. 4 is an exemplary view for explaining an example of a garbage collection (GC) count management list used in the memory system of the embodiment. FIG. 9 is an exemplary view for explaining a garbage collection target block selecting operation executed by the memory system of the embodiment based on a garbage collection count management list. FIG. 4 is an exemplary view for explaining a garbage collection operation executed by the memory system of the embodiment. FIG. 4 is an exemplary view for explaining an example of a plurality of types of data written in the memory system of the embodiment. The figure explaining the example of the relationship between the number of times of garbage collection, and the ratio of the data amount among several types of data. 9 is an exemplary flowchart illustrating the procedure of a garbage collection operation executed by the memory system of the embodiment. FIG. 4 is an exemplary view for explaining a garbage collection operation including a process of merging valid data of two blocks having different garbage collection times, which is executed by the memory system of the embodiment. 9 is an exemplary flowchart illustrating a procedure of a garbage collection operation including a process of merging valid data of two blocks having different garbage collection times, which is executed by the memory system of the embodiment. The figure explaining the operation | movement which permits a merge process only to the block group more than a specific garbage collection frequency. 9 is a flowchart illustrating a procedure of a garbage collection operation including an operation of permitting a merge process only for a block group having a specific garbage collection count or more. FIG. 4 is an exemplary view for explaining an operation executed by the memory system according to the embodiment to sequentially allocate free blocks for writing data from the host. FIG. 4 is an exemplary view for explaining an example of a block use order management list used by the memory system of the embodiment. FIG. 9 is a diagram for explaining an accumulated data write amount calculation operation executed by the memory system of the embodiment when a write to the same LBA is requested. FIG. 7 is an exemplary view for explaining a processing sequence of a cumulative data write amount response process executed by the memory system of the embodiment. 9 is an exemplary flowchart illustrating the procedure of a cumulative data write amount response process executed by the memory system of the embodiment. FIG. 9 is an exemplary view for explaining another processing sequence of the cumulative data writing amount response processing which is executed by the memory system of the embodiment. 9 is an exemplary flowchart for explaining another procedure of the accumulated data write amount response process executed by the memory system of the embodiment. FIG. 3 is an exemplary view for explaining an example of a lookup table used in the memory system of the embodiment. 9 is an exemplary flowchart for explaining a procedure of a time lapse response process executed by the memory system of the embodiment when a write to the same LBA is requested. 9 is an exemplary flowchart illustrating an example of a procedure of processing executed by the host based on the accumulated data write amount / time elapsed information received from the memory system of the embodiment. FIG. 2 is a block diagram illustrating a configuration example of a host. FIG. 3 is an exemplary view showing a configuration example of a computer including the memory system of the embodiment and a host.

Hereinafter, embodiments will be described with reference to the drawings.
First, a configuration of an information processing system 1 including a memory system according to an embodiment will be described with reference to FIG.

  This memory system is a semiconductor storage device configured to write data to a nonvolatile memory and read data from the nonvolatile memory. This memory system is implemented, for example, as a solid state drive (SSD) 3 based on NAND flash technology.

  The information processing system 1 includes a host (host device) 2 and an SSD 3. The host 2 is an information processing device such as a server or a personal computer.

  The SSD 3 can be used as a main storage of the information processing device functioning as the host 2. The SSD 3 may be built in the information processing device, or may be connected to the information processing device via a cable or a network.

  As an interface for interconnecting the host 2 and the SSD 3, SCSI, Serial Attached SCSI (SAS), ATA, Serial ATA (SATA), PCI Express (PCIe), Ethernet (registered trademark), Fiber channel, and the like are used. obtain.

  The SSD 3 includes a controller 4, a nonvolatile memory (NAND memory) 5, and a DRAM 6. The NAND memory 5 may include, but is not limited to, a plurality of NAND flash memory chips.

  The NAND memory 5 includes a large number of NAND blocks (blocks) B0 to Bm-1. The blocks B0 to Bm-1 function as an erasing unit. Blocks are sometimes referred to as “physical blocks” or “erase blocks”.

  The blocks B0 to Bm-1 include many pages (physical pages). That is, each of the blocks B0 to Bm-1 includes the pages P0 to Pn-1. In the NAND memory 5, data reading and data writing are performed in page units. Data erasure is performed in block units.

  The controller 4 is electrically connected to a NAND memory 5 which is a nonvolatile memory via a NAND interface 13 such as Toggle or ONFI. The controller 4 may function as a flash translation layer (FTL) configured to perform data management of the NAND memory 5 and block management of the NAND memory 5.

  Data management includes (1) management of mapping information indicating the correspondence between logical block addresses (LBAs) and physical addresses, and (2) concealment of read / write in page units and erasure operations in block units. , Etc. are included. The management of the mapping between the LBA and the physical address is executed using a look-up table (LUT) 33 functioning as a logical-physical address conversion table. The look-up table (LUT) 33 manages mapping between LBAs and physical addresses in predetermined management size units. Many of the write commands from the host 2 require writing of 4 Kbytes of data. Therefore, the look-up table (LUT) 33 may manage the mapping between the LBA and the physical address, for example, in units of 4 Kbytes. The physical address corresponding to a certain LBA indicates a physical storage position in the NAND memory 5 to which the data of this LBA has been written. The physical address includes a physical block address and a physical page address. Physical page addresses are assigned to all pages, and physical block addresses are assigned to all blocks.

  Data can be written to a page only once per erase cycle.

  Therefore, the controller 4 maps a write (overwrite) to the same LBA to another page in the NAND memory 5. That is, the controller 4 writes data to this other page. Then, the controller 4 updates the look-up table (LUT) 33 to associate this LBA with this another page, and invalidates the original page (that is, old data with which this LBA was associated).

  Block management includes management of bad blocks, wear leveling, garbage collection operations, and the like. Wear leveling is an operation for leveling the program / erase count of each physical block.

  The garbage collection operation is an operation for creating free space in the NAND memory 5. This garbage collection operation copies all valid data in some blocks in which valid data and invalid data are mixed to another block (copy destination free block) in order to increase the number of free blocks in the NAND memory 5. . Then, the garbage collection operation updates the look-up table (LUT) 33 and maps each LBA of the copied valid data to a correct physical address. When valid data is copied to another block, a block regarded as invalid data is released as a free block. This allows this block to be reused after erasure.

  The host 2 sends a write command to the SSD 3. This write command includes a logical address (start logical address) of write data (that is, data to be written) and a transfer length. In this embodiment, the LBA is used as a logical address, but in other embodiments, an object ID may be used as a logical address. The LBA is represented by a serial number given to a logical sector (logical block). Serial numbers start at zero. The size of the logical sector is, for example, 512 bytes.

  The controller 4 of the SSD 3 writes the write data specified by the start logical address and the transfer length in the write command to a page of a block in the NAND memory 5. Further, by updating the look-up table (LUT) 33, the controller 4 maps the LBA corresponding to the written data to a physical address indicating the physical storage location where the data has been written.

  More specifically, the controller 4 allocates one of the free blocks in the NAND memory 5 for writing data from the host 2. The allocated block is a write target block to which data from the host 2 is to be written, and is also referred to as a “write destination block” or an “input block”. While updating the look-up table (LUT) 33, the controller 4 sequentially writes the write data received from the host 2 to an available page of the write target block (write destination block). When there is no available page in the write destination block, the controller 4 allocates a new free block as the write destination block.

  Next, the configuration of the controller 4 will be described.

  The controller 4 includes a host interface 11, a CPU 12, a NAND interface 13, a DRAM interface 14, an SRAM 15, and the like. The CPU 12, NAND interface 13, DRAM interface 14, and SRAM 15 are interconnected via a bus 10.

  The host interface 11 receives various commands (write command, read command, unmap (UNMAP) command, etc.) from the host 2.

  The write command requests the SSD 3 to write the data specified by the write command. The write command includes the LBA (start LBA) of the first logical block to be written and the transfer length (the number of logical blocks). The read command requests the SSD 3 to read the data specified by the read command. The read command includes the LBA (start LBA) of the first logical block to be read and the transfer length (the number of logical blocks).

  The CPU 12 is a processor configured to control the host interface 11, the NAND interface 13, the DRAM interface 14, and the SRAM 15. The CPU 12 executes command processing for processing various commands from the host 2 in addition to the above-described FTL processing.

  For example, when the controller 4 receives a write command from the host 2, under the control of the CPU 12, the controller 4 executes the following write operation of writing write data specified by the write command to the NAND memory 5.

  That is, the controller 4 writes the write data to the physical storage location (available page) of the current write destination block, updates the look-up table (LUT) 33 to the LBA (start LBA) included in the write command. The physical address of this physical storage location is mapped.

  These FTL processing and command processing may be controlled by firmware executed by the CPU 12. This firmware causes the CPU 12 to function as a garbage collection (GC) number management unit 21, a garbage collection (GC) operation control unit 22, and an update frequency information response unit 23.

  Data written to the SSD 3 by the host 2 may have a data locality that a part of the data is frequently rewritten and the remaining part is not frequently rewritten. In this case, for example, if the GC operation is performed by a normal GC algorithm of selecting some upper blocks having a large amount of invalid data as the GC target blocks, the frequency of updating increases as the GC operation is repeated many times. Data and infrequently updated data tend to be mixed in the same block. A mixture of frequently updated data and infrequently updated data may cause an increase in SSD3 write amplification.

  This is because, in a block in which frequently updated data (hot data) and infrequently updated data (cold data) are mixed, only a part of the area in the block is invalidated at an early timing by updating the hot data. On the other hand, the remaining area (Cold data) in this block is maintained in the valid state for a long time.

  If a block is filled only with Hot data, there is a high possibility that all data in this block will be invalidated at relatively early timing by updating (rewriting) those data. Therefore, this block can be reused only by erasing the block without performing a garbage collection operation.

  On the other hand, if the block is filled only with Cold data, all data in this block will remain valid for a long time. Therefore, this block is likely not to be subject to garbage collection operations for a long time.

  Write amplification (WA) is defined as follows.

WA = "Total amount of data written to SSD" / "Total amount of data written from host to SSD"
The “total amount of data written to the SSD” corresponds to the sum of the total amount of data written to the SSD from the host and the total amount of data internally written to the SSD by a garbage collection operation or the like.

  An increase in the write amplification (WA) causes an increase in the number of rewrites (program / erase) of each block in the SSD 3. That is, as the write amplification (WA) is larger, the number of times of program / erase of the block is more likely to reach the upper limit value of the number of times of program / erase. As a result, the durability and the life of the SSD 3 are deteriorated.

  In the present embodiment, in order to be able to separate data with a high update frequency from data with a low update frequency, a “GC function considering the number of times of GC of the data in a block” and an “LBA-based update frequency notification function” ".

  The garbage collection (GC) number management unit 21 and the garbage collection (GC) operation control unit 22 execute a “GC function in consideration of the number of GCs of data in a block”. The “GC function in consideration of the number of GCs of data in a block” executes an improved garbage collection (GC) operation capable of suppressing an increase in SSD3 write amplification due to data locality.

  The garbage collection (GC) number management unit 21 manages the number of garbage collection (GC) times for each block including data written by the host 2. The GC count of a certain block indicates the number of times data in this block has been copied by a garbage collection (GC) operation. That is, the GC count of a certain block indicates how many times data in this block has been copied as valid data in the past.

  For a block immediately after data has been written by the host 2, that is, a block whose data has never been collected (copied) by GC, the GC count of this block is set to zero.

  If some blocks whose GC count is zero are selected as GC target blocks (copy source blocks) and valid data of these blocks is copied to the copy destination free block, the GC count management unit 21 performs this copy. The GC count of the first free block is set to 1. This is because the data in the copy destination free block is data copied once from the GC target block (copy source block) as valid data.

  Each block (copy source block) regarded as invalid data by copying valid data to the copy destination free block becomes a free block. Since the free block does not include data, it is not necessary to manage the number of times of GC of the free block.

  If some blocks (copy source blocks) whose GC count is 1 are selected as garbage collection (GC) target blocks and valid data of these blocks is copied to the copy destination free block, the GC count management unit 21 Sets the GC count of the free block at the copy destination to 2. This is because the data in the copy destination free block is data that has been copied twice in the past as valid data.

  In this way, the value of the number of GCs associated with a certain block is determined by how many times data in this block has been copied by past GC operations, that is, how many GC operations have been performed on data in this block in the past. Indicates whether it was executed.

  The GC operation control unit 22 selects some blocks associated with the same number of GCs as target blocks of the garbage collection (GC) operation, and extracts only valid data of the blocks associated with the same number of GCs into the same copy destination block. , An improved GC operation.

  For example, the GC operation control unit 22 selects some blocks as target blocks for GC from a block group associated with the same number of GCs (that is, a set of blocks having the same number of GCs). The GC operation control unit 22 copies valid data in these blocks selected as the GC target blocks to a copy destination free block. Then, a value obtained by adding 1 to the number of GCs of these blocks selected as the GC target block is set as the number of GCs of the copy destination free block by the GC number management unit 21.

  The “LBA-based update frequency notification function” notifies the host 2 of the frequency of writing to each LBA included in each write command, thereby efficiently separating the host 2 from Hot data / Cold data. It is a function to assist.

  The “LBA-based update frequency notification function” is executed by the update frequency information response unit 23.

  Upon receiving a write command including an LBA from the host 2, the update frequency information response unit 23 determines whether a value related to the time elapsed from the previous write to this LBA to the current write to this LBA, or the previous time to this LBA. The host 2 is notified of the cumulative amount of data written from this write to the current write to this LBA as a response to this write command. Accordingly, the host 2 can be notified of the actual update frequency (rewrite frequency) of the user data, so that the host 2 can update the user data with a plurality of types of data having different update frequencies, for example, frequently updating the user data. Data (Hot data), data of low update frequency (Cold data), and data of an update frequency intermediate between Hot data and Cold data (Warm data). As a result, for example, the host 2 can execute processing for distributing these different types of data to different SSDs as needed.

  Next, other components in the controller 4 will be described.

  The NAND interface 13 is a NAND controller configured to control the NAND memory 5 under the control of the CPU 12.

  The DRAM interface 14 is a DRAM controller configured to control the DRAM 6 under the control of the CPU 12.

  Part of the storage area of the DRAM 6 may be used as a write buffer (WB) 31 for temporarily storing data to be written to the NAND memory 5. The storage area of the DRAM 6 may be used as a GC buffer 32 for temporarily storing data moved during a garbage collection (GC) operation. Further, the storage area of the DRAM 6 may be used for storing the above-described lookup table 33.

  Further, the storage area of the DRAM 6 may be used as a GC count management list 34 and a block use order management list 35.

  The GC count management list 34 is a list for holding the GC count for each block including data written by the host 2. The GC count management list 34 may be a table showing the correspondence between the block ID (for example, physical block address) of each block and the GC count of the data in these blocks.

  Alternatively, the GC count management list 34 may be composed of a plurality of GC count lists for managing each block for each GC count (for example, GC count = 0 to GC count = n). Here, n is the upper limit of the number of times of GC to be managed. For example, the GC count list of GC count = 0 holds a list of block IDs (for example, physical block addresses) of the blocks associated with the GC count of 0. The GC count list of GC count = 1 holds a list of block IDs (for example, physical block addresses) of the blocks associated with one GC count.

  The block use order management list 35 holds an allocation number (sequential number) assigned to each of the blocks allocated for the write destination block. That is, the controller 4 assigns a number (assignment number) indicating the assignment order to each of the blocks assigned as the write target blocks. The number may be a sequential number starting from 1. For example, an allocation number = 1 is assigned to a block allocated first for a write destination block, an allocation number = 2 is allocated to a block allocated second for a write destination block, and a third Assigned number = 3 is assigned to the block assigned for the block. As a result, it is possible to manage a block use history indicating which blocks have been allocated as write destination blocks and in what order. As the assignment number, a value of a counter that is incremented each time a new free block is assigned for a write destination block can be used.

  The SSD 3 may hold various other management information. An example of such management information may include a page management table holding valid / invalid flags corresponding to each physical address. Each valid / invalid flag indicates whether the corresponding physical address (physical page) is valid or invalid. The validity of the physical page means that the data in the physical page is valid data. An invalid physical page means that data in the physical page is data that has been invalidated by updating (rewriting).

  Next, the configuration of the host 2 will be described.

  The host 2 is an information processing device that executes various programs. The programs executed by the information processing device include an application software layer 41, an operating system (OS) 42, and a file system 43.

  As is generally known, an operating system (OS) 42 manages the entire host 2, controls hardware in the host 2, and controls to enable an application to use the hardware and the SSD 3. Software.

  The file system 43 is used for controlling file operations (creation, storage, update, deletion, etc.). For example, ZFS, Btrfs, XFS, ext4, NTFS, etc. may be used as the file system 43. Alternatively, a file object system (for example, Ceph Object Storage Daemon) or a Key Value Store System (for example, Rocks DB) may be used as the file system 43.

  Various application software threads run on the application software layer 41. Examples of application software threads include client software, database software, virtual machines, and the like.

  When the application software layer 41 needs to send a request such as a read command or a write command to the SSD 3, the application software layer 41 sends the request to the OS. The OS 42 sends the request to the file system 43. The file system 43 translates the request into a command (read command, write command, etc.). The file system 43 sends the command to the SSD 3. When the response from the SSD 3 is received, the file system 43 sends the response to the OS 42. The OS 42 sends the response to the application software layer 41.

  Next, details of the “GC function in consideration of the number of times of GC of data in a block” will be described with reference to FIGS.

  FIG. 2 shows a GC count management operation and a GC operation executed by the SSD 3.

  The controller 4 of the SSD 3 allocates a certain free block as a block for writing data (write data) from the host 2 (write destination block), and can use the write data received from the host 2 in the write destination block. Write to pages sequentially. When all pages of the current write destination block are filled with data, the controller 4 manages the current write destination block as an active block (a block including data). Further, the controller 4 allocates another free block as a new write destination block. In this way, in the SSD 3, the data (write data) received from the host 2 is sequentially written from the first page to the last page of the current write destination block in the order of arrival.

  Blocks B11 to B17 in FIG. 2 are blocks immediately after data is written by the host 2, that is, blocks in which data in the block has never been copied by a garbage collection (GC) operation. The number of GCs corresponding to these blocks B11 to B17 is zero.

  As time passes, a part of the data in each of the blocks B11 to B17 may be invalidated by the rewriting. Thus, valid data and invalid data may be mixed in each of the blocks B11 to B17.

  When the number of free blocks falls below the threshold number, the controller 4 starts a GC operation for creating free blocks from several blocks in which valid data and invalid data are mixed.

  First, the controller 4 selects some blocks in which valid data and invalid data coexist as GC target blocks. In the selection of the GC target block, the controller 4 selects a block group associated with the same GC count as the GC target block, as described above. This block group may be, for example, a block group to which the block with the largest amount of invalid data belongs, that is, a set of blocks having the same GC count as the GC count of the block with the largest invalid data amount. In this case, first, the controller 4 may select a block having the largest amount of invalid data from blocks including data written by the host 2. Next, the controller 4 divides the block having the largest invalid data amount and one or more blocks associated with the same GC count as the GC count of the block having the largest invalid data amount into the blocks to be subjected to the garbage collection (GC) operation. May be selected.

  The controller 4 copies valid data in some selected GC target blocks (several blocks associated with the same GC count) to a copy destination free block, and adds 1 to the GC count of these GC target blocks. The value is set as the GC count of the copy destination free block. As a result, the value obtained by adding 1 to the number of GCs of the GC target block is inherited by the copy destination free block. It is possible to correctly indicate whether or not it has been copied.

  For example, if two blocks B11 and B12 associated with the same GC count are selected as GC target blocks, and valid data of these blocks B11 and B12 is copied to the copy destination free block B21, the copy destination free block B21 Is set to a value (here, 1) obtained by adding 1 to the number of GCs (here, 0) of the blocks B11 and B12.

  Similarly, if three blocks B13, B14, and B15 associated with the same GC count are selected as GC target blocks, and valid data of these blocks B13, B14, and B15 are copied to the copy destination free block B22, The number of GCs of the copy destination free block B22 is set to a value (here, 1) obtained by adding 1 to the number of GCs (here, 0) of the blocks B13, B14, and B15.

  Similarly, if two blocks B16 and B17 associated with the same GC count are selected as GC target blocks, and the valid data of these blocks B16 and B17 is copied to the copy destination free block B23, the copy destination free block The GC count of B23 is set to a value (here, 1) obtained by adding 1 to the GC count (here, 0) of the blocks B16 and B17.

  As time passes, a part of the data in each of the blocks B21, B22, and B23 may be invalidated by the rewriting. As a result, valid data and invalid data may be mixed in each of the blocks B21, B22, and B23.

  If two blocks B21 and B22 associated with the same GC count are selected as GC target blocks and valid data of these blocks B21 and B22 is copied to the copy destination free block B31, the GC of this copy destination free block B31 The number of times is set to a value (here, 2) obtained by adding 1 to the number of GCs (here, 1) of the blocks B21 and B22.

  As described above, in the present embodiment, the number of GCs managed for each block indicates the number of times data in the block has been copied by a past GC operation. In order to correctly manage the number of times of GC, a value obtained by adding 1 to the number of times of GC of the GC target block is taken over by data in the copy destination free block.

  FIG. 3 shows an example of the GC count management list 34.

  When the upper limit value n of the number of times of GC to be managed is 10, for example, the number-of-GCs management list 34 may be composed of eleven GC number lists respectively corresponding to the number of GCs = 0 to the number of GCs = 10.

  The GC count list of GC count = 0 indicates a list of block IDs (for example, physical block addresses) of the blocks associated with GC count = 0. The GC count list of GC count = 1 indicates a list of block IDs (for example, physical block addresses) of the blocks associated with GC count = 1. Similarly, the GC count list of GC count = 10 indicates a list of block IDs (for example, physical block addresses) of the blocks associated with GC count = 10. Each GC count list is not limited, but may include only blocks in which valid data and invalid data are mixed.

  FIG. 4 shows a GC target block selection operation executed by the controller 4.

  In the process of selecting a GC target block, the garbage collection operation control unit 22 of the controller 4 firstly selects a GC target block group from a plurality of block groups (a plurality of GC count lists) respectively associated with different GC counts. May be selected. In FIG. 4, a block group with the number of GC = 5 (block B2, block B5, block B11, block B21) is selected as a block group to be subjected to GC. The case where a target block is selected is illustrated.

  In the process of selecting a GC target block, for example, first, a block that meets a predetermined condition may be selected as the first GC candidate. The block that satisfies the predetermined condition may be a block having the largest amount of invalid data among the active blocks (blocks including data written by the host 2). In another embodiment, the block that meets the predetermined condition may be the oldest block among the active blocks. In the following, it is assumed that the block having the largest amount of invalid data is selected as the first GC candidate.

  If the block with the largest invalid data amount is the block B5, the controller 4 specifies a GC count list including the block B5 (here, a GC count list of 5 GC counts), A block group (block B2, block B5, block B11, block B21) indicated by the count list is selected as a GC target block group, and some GC target blocks are selected from the GC target block group. For example, among the blocks B2, B5, B11, and B21, some upper blocks having a large invalid data amount may be selected as the GC target blocks. In this case, for example, the block B5 and one or more upper blocks having the largest invalid data amount among the blocks B2, B11, and B21 may be selected as the GC target blocks.

  FIG. 5 shows a GC operation performed by the controller 4.

  The controller 4 manages a free block pool (free block list) 60 including all free blocks. The controller 4 selects one free block from these free blocks. The controller 4 allocates the selected free block as the copy destination free block B1000. The controller 4 copies all valid data from the GC target blocks (here, blocks B2, B5, and B11) having the same GC count to the copy destination free block B1000. Then, the controller 4 updates the lookup table 33 and maps each LBA of the valid data to each physical address of the copy destination free block B1000.

  The GC count of the copy destination free block B1000 is set to the GC count (= 5) +1 of the blocks B2, B5, and B11. Block B1000 is added to the GC count list of GC count = 6. Blocks B2, B5, and B11 are free blocks that do not include valid data. The blocks B2, B5, and B11 that have become free blocks are discarded from the GC count list where the GC count is 5.

  FIG. 6 shows an example of a plurality of types of data written to the SSD 3.

  FIG. 6 assumes that three types of data (data A, data B, and data C) having different update frequencies are written to the SSD 3. The data storage area (LBA space) of the SSD 3 includes three spaces corresponding to LBA groups A, B, and C.

  The data A written to the LBA group A is data with a low update frequency, and the amount of the data A is the largest among the data A, B, and C. That is, LBA group A has the largest LBA range.

  The data C written to the LBA group C is frequently updated data, and the amount of the data C is the smallest among the data A, B, and C. That is, LBA group C has the smallest LBA range.

  The data B written to the LBA group B has an intermediate update frequency between the data A and the data C, and the amount of the data B is intermediate between the amount of the data A and the amount of the data C.

  The ratio of the amount of data A to the total user capacity of SSD 3 may be, for example, 50%. The ratio of the amount of data B to the total user capacity of SSD 3 may be, for example, 30%. The ratio of the amount of the data C to the total user capacity of the SSD 3 may be, for example, 20%.

  The update frequency of the data A, that is, the frequency of writing to the LBA group A may be, for example, 20%. The update frequency of the data B, that is, the frequency of writing to the LBA group B may be, for example, 30%. The update frequency of the data C, that is, the frequency of writing to the LBA group C may be, for example, 50%.

  In this case, for example, after the SSD 3 is filled with the data A, the data B, and the data C, a write command requesting a write to the data C (LBA group C) is issued once every two write commands. The host 2 issues a write command requesting a write to the data A (LBA group A) from the host 2 to the SSD 3 at a rate of once every five write commands. For example, the data C is updated at a high frequency of one time (50%) for two write commands.

  When data written to the SSD 3 has data locality as shown in FIG. 6, data A, data B, and data C are mixed in each write destination block, as shown in the lower part of FIG.

  In one write destination block, the ratio of the amount of data C to the block capacity is 50%, the ratio of the amount of data B to the block capacity is 30%, and the ratio of the amount of data A to the block capacity is 20%. .

  As described above, since the amount of the data C is smaller than the data A and the data B and the update frequency of the data C is higher than the data A and the data B, most of the data C in each block is at a faster timing. The probability of being invalidated is high. On the other hand, the data A and the data B, especially the data A, are likely to be maintained in the valid state for a long time.

  Each block in which the amount of invalid data has increased due to the update (rewrite) of the data C eventually becomes a GC target block, and valid data is copied from these blocks to a copy destination free block. In each GC target block, there is a high probability that most of the data C is invalidated and most of the data A and data B are maintained as valid data. For this reason, in the copy destination block, the amount of data A and the amount of data B increase as compared with the GC target block, and instead, the amount of data C decreases as compared with the GC target block.

  In the present embodiment, since the valid data in several blocks having the same GC count is copied to the copy destination free block, the valid data in the block with the small GC count and the valid data in the block with the large GC count are determined by the GC. The operation does not copy to the same copy destination free block. Therefore, the ratio of the amount of data A to the capacity of the block can be increased for a block having a larger number of GCs, whereby data A (Cold data) can be separated from data C (hot data).

  FIG. 7 shows an example of the relationship between the number of GCs and the ratio of the data amount among the data A, B, and C in each block.

  In each block where the GC count = 0, the ratio of the amount of data C to the block capacity is 50%, the ratio of the amount of data B to the block capacity is 30%, and the ratio of the amount of data A to the block capacity is 20. %.

  The ratio of the amount of data C to the capacity of the block is rapidly reduced by one or two GC operations. As the number of GC increases, the ratio of the amount of data B to the capacity of the block also gradually decreases.

  As described above, in the present embodiment, since the valid data in the block with a small number of GC times and the valid data in the block with a large number of GC times are not copied to the same copy destination free block, (1) a group containing almost only data A (for example, about 7 to 10 times of GC); (2) a group containing data A and data B and containing almost no data C (for example, about 3 to 6 times of GC). ), (3) It can be classified into a group including data A, data B and data C (for example, about 0 to 2 times of GC).

  In other words, in the present embodiment, the blocks having the same number of GC times can have the same ratio of the amounts of data A, B, and C included in the blocks.

  Therefore, the improved GC operation of the present embodiment in which valid data in several blocks having the same GC count is copied to the same copy destination free block is performed even when data written in the SSD 3 has high data locality. Even if there is, a group of blocks including only data A, a group of blocks including data A and data B and hardly including data C, and a group of blocks including data A, data B and data C are included. The Hot data and the Cold data can be gradually separated from each other. As a result, an increase in the write amplification of the SSD 3 can be suppressed.

  The flowchart of FIG. 8 shows a procedure of the GC operation executed by the controller 4.

  The controller 4 checks the number of remaining free blocks (step S11), and determines whether the number of remaining free blocks is equal to or smaller than the threshold th1 (step S12). This check may be performed periodically. For example, the number of remaining free blocks may be checked when a new free block is to be assigned as a write destination block.

  If the number of remaining free blocks is equal to or smaller than the threshold th1 (YES in step S12), the controller 4 first selects the first GC candidate from all active blocks. The first GC candidate may be a block with the maximum invalid data amount. In this case, the block with the maximum invalid data amount is selected as the first GC candidate from all the active blocks (step S13). The controller 4 refers to the GC count management list 34, and a block group (first block group) associated with the same GC count as the GC count of the first GC candidate (here, for example, the block having the maximum invalid data amount). Is selected, and some GC target blocks are selected from the first block group (step S14). In step S14, a block group (first block group) indicated by the GC count list including the first GC candidate (for example, the block with the maximum invalid data amount) is selected, and several blocks are selected from the first block group. Is selected. In this case, the first GC candidate (for example, the block with the maximum invalid data amount) and another one or more blocks included in the GC count list may be selected as the GC target blocks.

  The controller 4 copies all the valid data in the selected GC target block to the copy destination free block (Step S15). In step S15, valid data is read from each of the valid pages in the selected GC target block, and the read valid data is written to each available page of the copy destination free block. In step S15, the controller 4 further updates the look-up table (LUT) 33 to associate the LBA of the copied valid data with the physical address of the copy destination free block, and updates the page management table, The original page in the GC target block (that is, the old data associated with this LBA) is invalidated. In this case, the controller 4 may first obtain the physical address of the original page in which the copied valid data is stored by referring to the lookup table (LUT) 33. May be updated, and the valid / invalid flag corresponding to this physical address may be set to a value indicating invalid.

  Thereafter, the controller 4 sets the GC count of the selected GC target block + 1, that is, a value obtained by adding 1 to the GC count of the first block group as the GC count of the copy destination free block (step S16).

  FIG. 9 shows a GC operation including a process of merging valid data of two block groups having different GC counts.

  For example, when the amount of valid data included in the block group (GC target block group) associated with the same GC count as the GC count of the block with the maximum invalid data amount is smaller than the threshold, the controller 4 has a different GC count. A process of merging valid data of two block groups is executed. In this case, the controller 4 may select another block group having a GC count as close as possible to the GC count of the GC target block group.

  For example, it is assumed that the block having the maximum invalid data amount is the block B300, and the number of times of GC of the block B300 is 10. In this case, the controller 4 checks the total valid data amount of the block group included in the GC count management list with the GC count = 10. For example, when the block included in the GC count management list with the GC count of 10 is only the block B300, or when about 2 or 3 blocks are included in the GC count management list with the GC count of 10, Is very small, the controller 4 selects a block group on which the GC operation is to be executed together with the block group of GC count = 10.

  In this case, the controller 4 determines that all the blocks having the number of GCs that are at least one less than the number of GCs of the block B300 having the maximum invalid data amount (here, the block group having the number of GCs 9; the block group having the number of GCs 8; A block group having the maximum number of garbage collections may be selected from among the block group having the number of times 7 and the block group having the number of times GC is 0.

  First, the controller 4 refers to the GC count management list with the GC count = 9, and determines whether or not there is a block with the GC count = 9. If the block with the number of GC = 9 does not exist, the controller 4 refers to the GC number management list with the number of GC = 8 to determine whether or not there is a block with the number of GC = 8.

  If there is no block with the number of GCs = 9 and there is a block with the number of GCs = 8, the controller 4 selects a block group with the number of GCs = 8 (for example, blocks B41, B42, and B43). Then, the controller 4 copies the valid data of the block B300 and the valid data of the block group with the GC count = 8 to the copy destination free block. In this case, not all the valid data in the blocks B41, B42, and B43 need be used, and valid data in at least one of the blocks B41, B42, and B43 may be used.

  The flowchart of FIG. 10 shows a procedure of a GC operation including a process of merging valid data of two block groups having different numbers of times of GC.

  The controller 4 checks the number of remaining free blocks (step S21), and determines whether the number of remaining free blocks is equal to or smaller than the threshold th1 (step S22). As mentioned above, this check may be performed periodically.

  If the number of remaining free blocks is equal to or smaller than the threshold th1 (YES in step S22), the controller 4 first selects the first GC candidate from all active blocks. The first GC candidate may be a block with the maximum invalid data amount. In this case, the block with the maximum invalid data amount is selected as the first GC candidate from all the active blocks (step S23). The controller 4 refers to the GC count management list 34, and a block group (first block group) associated with the same GC count as the GC count of the first GC candidate (here, for example, the block having the maximum invalid data amount). Is determined, and it is determined whether or not the total amount of valid data of this block group (first block group) is equal to or smaller than a threshold th2 (step S24).

  The value of the threshold th2 may be fixed or may be a value that can be changed as needed. As the value of the threshold th2 is larger, the execution of the above-described merge processing is more easily permitted.

  For example, the threshold th2 may be set in advance to a value indicating the capacity of one block in the SSD3. Thus, the execution of the merge process can be permitted only when the GC operation cannot be executed only in the block group associated with the same GC count as the GC count of the first GC candidate. Alternatively, the threshold value th2 may be set to a value that is an integral multiple of the capacity of one block in the SSD 3, for example, a value that is twice as large.

  If the total amount of valid data in the first block group is not equal to or smaller than the threshold th2 (NO in step S24), the controller 4 selects some GC target blocks from the first block group (step S25). In step S25, these GC target blocks are selected from the first block group indicated by the GC count list including the first GC candidate (for example, the block with the maximum invalid data amount). In this case, the first GC candidate (for example, the block with the maximum invalid data amount) and another block included in the GC count list may be selected as the GC target block.

  In step S25, the controller 4 copies all the valid data in the selected GC target block to the copy destination free block. In step S25, the controller 4 further updates the look-up table (LUT) 33 to associate the LBA of the copied valid data with the physical address of the free block at the copy destination and to change the original page in each GC target block. Disable.

  Thereafter, the controller 4 sets the GC count of the selected GC target block + 1, that is, a value obtained by adding 1 to the GC count of the first block group, as the GC count of the copy destination free block (step S26). .

  On the other hand, if the total amount of valid data in the first block group is equal to or smaller than the threshold th2 (YES in step S24), the controller 4 is associated with the number of GC times smaller than the number of GC times in the first block group by one or more times. A block group (second block group) associated with the maximum number of GCs is selected from all the block groups (step S27).

  The controller 4 copies the valid data of the first block group and the valid data of the second block group to the copy destination free block (Step S28). In step S28, the controller 4 further updates the look-up table (LUT) 33 to associate the LBA of the copied valid data with the physical address of the free block at the copy destination and to change the original page in each GC target block. Disable.

  The controller 4 sets the GC count +1 of the second block group as the GC count of the copy destination free block, or sets the GC count +1 of the first block group +1 as the GC count of the copy destination free block (step S29). Alternatively, when the number of GC target blocks in the second block group is larger than the number of GC target blocks in the first block group, the number of GC times of the second block group + 1 is set as the number of GC times of the copy destination free block. Alternatively, if the number of GC target blocks in the first block group is larger than the number of GC target blocks in the second block group, the number of GCs of the first block group + 1 plus the GC of the copy destination free block It may be set as the number of times.

  FIG. 11 shows an operation of permitting the merging process only for a block group having a specific GC count or more.

  The valid data included in a block having a large number of GC times is likely to be data (data A) with a low update frequency. However, since the data A is also rewritten at a rate of 20%, a block having a large number of GC times, for example, a block having a GC number of 10 may have a large invalid data amount. Valid data in a block having a large number of GCs is data that has never been updated (rewritten), that is, data that has been maintained in a valid state for a long time. Therefore, there is a high probability that this valid data will not be updated.

  On the other hand, a block having a small number of times of GC is likely to include data B or data C. Regarding such a block, even if the GC operation of the block is not immediately executed, all data in the block may be invalidated with the passage of time management.

  Accordingly, by permitting only the blocks having the number of GCs equal to or greater than the merge permission threshold th3 to permit the group of blocks to be permitted to perform the merging process, it is possible to prevent the occurrence of useless copying and to increase the efficiency of GC. it can.

  FIG. 11 illustrates a case where the merge permission threshold th3 is set to 8 GC times.

  In this case, if the GC count of the block group (first block group) associated with the same GC count as the GC count of the first GC candidate is 8 or more, the merging process of the first block group with another block group Is allowed.

  For example, merge processing of a block group with GC count = 10 and another block group and merge processing of a block group with GC count = 9 and another block group are permitted. On the other hand, for example, merging of a block group with the number of GC = 7 and another block group is prohibited.

  The flowchart of FIG. 12 shows a procedure of a GC operation including an operation of permitting a merge process only for a block group having a specific number of GC times or more.

  In the GC operation shown in the flowchart of FIG. 12, the processes of steps S30 to S33 are added in addition to the processes described in FIG. Hereinafter, the processing of steps S30 to S33 will be mainly described.

  If the total amount of valid data in the first block group is equal to or smaller than the threshold th2 (YES in step S24), the process of the controller 4 proceeds to step S30. In step S30, the controller 4 determines whether or not the GC count of the first block group is equal to or larger than the merge permission threshold th3.

  If the GC count of the first block group is equal to or greater than the merge permission threshold th3 (YES in step S30), the controller 4 executes the merge processing in steps S27 to S29 described with reference to FIG.

  On the other hand, if the GC count of the first block group (the GC count of the first GC candidate block) is smaller than the merge permission threshold th3 (NO in step S30), the controller 4 executes the merge processing in steps S27 to S29. Are prohibited, and the processing of steps S31 to S33 is executed instead.

  In step S31, the controller 4 selects another block group different from the first block group as the GC target block group. For example, the controller 4 selects a block having the largest amount of invalid data next to the block of the first GC candidate as a new GC candidate, and selects a block group indicated by the GC count list including the new GC candidate as a GC. It may be selected as a target block group.

  Next, the controller 4 copies the valid data of the selected GC target block group to the copy destination free block (step S32), and adds 1 to the GC count of the copy destination free block and the GC count of the GC target block group. A value is set (step S33).

  If the first GC candidate block is associated with a GC count smaller than the merge permission threshold th3, it is highly possible that the first GC candidate block contains frequently updated data. For this reason, the controller 4 may wait until all the valid data of this block is invalidated without executing the GC for the first GC candidate block.

  Next, the details of the "LBA-based update frequency notification function" will be described with reference to FIGS.

  FIG. 13 shows an operation of sequentially allocating free blocks for writing data from the host 2.

  The controller 4 allocates one of the free blocks indicated by the free block list 60 as the write destination block 62. In this case, the controller 4 updates the block use order management list 35 and sets the allocation number (sequential number) of the block initially allocated as the write destination block 62 to 1. As shown in FIG. 14, the block use order management list 35 holds an allocation number (sequential number) corresponding to each block address. These allocation numbers indicate the order relation of the blocks allocated to the write destination block 62. That is, the controller 4 assigns an assignment number indicating the assignment order to each of the blocks assigned as the write target blocks, and manages these assignment numbers using the block use order management list 35.

  The controller 4 writes the write data received from the host 2 to the write buffer 31. Thereafter, the controller 4 sequentially writes the write data in the write buffer 31 from the first page to the last page of the write destination block 62 while updating the look-up table (LUT) 33.

  When there are no more available pages in the write destination block 62, the controller 4 moves the write destination block 62 to the active block list 61, and allocates a free block in the free block list 60 as a new write destination block 62. In this case, the controller 4 updates the block use order management list 35 and sets the assignment number (sequential number) of this block assigned as the new write destination block 62 to 2.

  If all data in any block in the active block list 61 has been invalidated by the update, this block is moved to the free block list 60.

  If the number of free blocks in the free block list 60 falls below the threshold th1, the above-described GC operation for creating free blocks is performed.

  FIG. 15 shows a cumulative data write amount calculation operation executed when a write to the same LBA is requested.

  When receiving a write command including a certain LBA from the host 2, the controller 4 notifies the host 2 of a cumulative data write amount from the previous write to the LBA as a response to the write command. The accumulated data write amount indicates the total amount of data written to the NAND memory 5 by the host 2 from the previous write to the same LBA as the received write command LBA to the current write to the write command LBA. .

  The cumulative data writing amount can be calculated from the following value, for example.

(1) Capacity per block (2) Number of pages included in block (3) First physical storage location (old physical address) in NAND memory 5 to which data was written by the previous write to the same LBA
(4) Second physical storage location (new physical address) in the NAND memory 5 to which data is to be written by the current write
(5) Allocated for writing data from the host 2 between the allocation of the block including the first physical storage location (old physical address) and the allocation of the block including the second physical storage location (new physical address). The number of blocks (1) to (4) is ordinary management information in the SSD 3 and is not prepared exclusively for calculating the accumulated data writing amount. For example, by referring to the look-up table (LUT) 33, the controller 4 can easily acquire the physical address mapped to the LBA in the received write command as the first physical storage location.

  The “number of blocks” in (5) can be easily calculated from, for example, the assignment number assigned to the block including the first physical storage location and the assignment number assigned to the block including the second physical storage location. it can.

  The allocation numbers (sequential numbers) are managed by the block use order management list 35 in FIG. Since the management unit of these allocation numbers (sequential numbers) is a block unit, the capacity required to hold these allocation numbers is small. Therefore, the accumulated data writing amount can be obtained at a low cost with almost no use of dedicated management information for the calculation.

  FIG. 15 shows an operation of calculating the accumulated data write amount executed when a write command including the LBA 10 is received.

  Here, it is assumed that data has already been written to page Px of block B51 by the previous write to LBA10, and that data should be written to page Py of the current write destination block B62 by this write to LBA10. Have been. If the allocation number of the block B51 is 10 and the allocation number of the block B51 is 13, it is understood that two write destination blocks (for example, blocks B52 and B61) have been allocated between the block 51 and the block B62. .

  The cumulative data writing amount is given by d1 + d2 + d2 + d3.

  Here, d1 indicates the number of pages in the block B51 following the page Px, or the capacity corresponding to the number of pages. d2 indicates the number of pages in one block or the capacity of one block. d3 indicates the number of pages in the block B62 preceding the page Py, or the capacity corresponding to the number of pages.

  The larger the number of write commands received from the host 2 between the reception of the previous write command including the LBA 10 and the reception of the current write command including the LBA 10, the larger the accumulated data write amount. Therefore, the above-described cumulative data write amount can represent the update frequency of data specified by the LBA 10, that is, the frequency of writing to the LBA 10.

  When receiving the write command, the controller 4 may acquire (calculate) the accumulated data write amount in the following procedure.

  First, the controller 4 acquires the old physical address (here, PA1) mapped to the LBA (here, LBA10) included in the write command with reference to the look-up table (LUT) 33. Then, the controller 4 refers to the block use order management list 35 and assigns the block assignment number (here, 10) specified by the old physical address and the block assignment number specified by the new physical address (here, PA2). And a number (here, 13). The controller 4 obtains d1 from the number of pages included in the block and the old physical address (PA1), and obtains d3 from the number of pages included in the block and the new physical address (PA2). Further, the controller 4 calculates the difference between the assignment of the block designated by the old physical address and the assignment of the block designated by the new physical address from the difference between the assignment numbers (13) and (10). The total number of blocks (here, 2) allocated as the write destination block is obtained. As a result, the accumulated data write amount (= d1 + d2 + d2 + d3) can be obtained (calculated).

  FIG. 16 shows a processing sequence of the cumulative data writing amount response processing.

  Here, it is assumed that this processing sequence is applied to an NCQ (Native Command Quing) system in which a write command and write data are divided.

  The host 2 sends a write command including a start LBA indicating a certain LBA (= LBAx) to the SSD 3. In response to the reception of the write command, the controller 4 of the SSD 3 calculates the cumulative data write amount from the previous write to LBAx to the current write to LBAx (step S41), and calculates the calculated cumulative data write amount. Is transmitted to the host 2. The command permission response is a permission response indicating an acknowledgment (permission of execution of the write command) for the received write command. When the SSD 3 transmits a permission response to the host 2, transfer of the write data specified by the write command is started. The permission response may include a value for identifying a write command to be permitted to be executed. The accumulated data write amount may be represented by, for example, bytes or the number of logical blocks (logical sectors).

  In response to receiving the command permission response, the host 2 sends the write data to the SSD 3. The controller 4 of the SSD 3 writes the write data to the write buffer 31, writes the write data of the write buffer 31 to the write destination block (step S42), and transmits a command completion response (response) to the host 2. A command completion response may be transmitted to the host 2 when the write data is written to the write buffer 31.

  The host 2 can grasp the actual update frequency of LBAx data (frequency of writing to LBAx) based on the accumulated data write amount included in the command permission response received from the SSD 3.

  If the actual update frequency of the LBAx data is different from the update frequency of the LBAx data expected by the host 2, for example, the actual update frequency of the LBAx data is expected by the host 2. If the update frequency is higher than the update frequency, the host 2 may send an abort command to the SSD 3 to abort the sent write command as necessary. In this case, the writing of the data specified by the write command is not executed.

  The flowchart of FIG. 17 shows the procedure of the cumulative data writing amount response process executed by the controller 4.

  The controller 4 receives a write command including LBAx as the start LBA from the host 2 (Step S51). The controller 4 includes an old physical address mapped to the LBAx, a new physical address to be mapped to the LBAx, an allocation number given to a block including a physical storage location specified by the old physical address, and a new physical address. The accumulated data write amount from the previous write to the LBAx to the current write to the LBAx is calculated based on the assignment number assigned to the block (current write destination block) including the physical storage location specified by It is calculated (step S52). The controller 4 returns a permission response including the accumulated data write amount to the host 2 (Step S53).

  The controller 4 determines whether write data corresponding to the write command or an abort command for aborting the write command is received from the host 2 (step S54).

  If the write data has been received, the controller 4 proceeds to step S55. In step S55, the controller 4 writes the write data into the write buffer 31, writes the write data in the write buffer 31 into the current write destination block, updates the look-up table (LUT) 33, and stores the new physical address in LBAx. And updates the page management table to invalidate the old physical address (old data).

  Thereafter, the controller 4 returns a command completion response to the host 2 (step S56).

  As described above, a command completion response may be transmitted to the host 2 when the write data is written to the write buffer 31.

  On the other hand, if the abort command has been received, the controller 4 discards the write command (step S57).

  FIG. 18 shows another processing sequence of the cumulative data writing amount response processing.

  The host 2 sends a write command including a certain LBA (= LBAx) as a start LBA to the SSD 3. In response to receiving the write command, the controller 4 of the SSD 3 transmits a command permission response to the host 2. In response to receiving the command permission response, the host 2 sends the write data to the SSD 3. The write data is written to the write buffer 31. The controller 4 of the SSD 3 calculates the accumulated data write amount (Step S58). The process of calculating the accumulated data write amount may be started in response to receiving a write command.

  Thereafter, the controller 4 writes the write data to the write destination block (step S59), and transmits a command completion response including the calculated accumulated data write amount to the host 2.

  As described above, a command completion response including the accumulated data write amount may be transmitted to the host 2 when the write data is written to the write buffer 31.

  The flowchart of FIG. 19 shows another procedure of the cumulative data write amount response processing.

  The controller 4 receives a write command including LBAx as the start LBA from the host 2 (Step S61). The controller 4 returns a permission response to the host 2 (Step S62). The controller 4 receives the write data from the host 2 (Step S63). The write data is written to the write buffer 31.

  The controller 4 includes an old physical address mapped to the LBAx, a new physical address to be mapped to the LBAx, an allocation number given to a block including a physical storage location specified by the old physical address, and a new physical address. Is calculated from the last write to LBAx to the current write to LBAx based on the assignment number and the like assigned to the block (current write destination block) including the physical storage location specified by (Step S64). The controller 4 proceeds to Step S65.

  In step S65, the controller 4 writes the write data in the write buffer 31 to the current write destination block, updates the lookup table (LUT) 33, maps the new physical address to LBAx, and updates the page management table. To invalidate the old physical address (old data).

  Thereafter, the controller 4 returns a command completion response including the accumulated data write amount to the host 2 (step S66).

  As described above, a command completion response may be transmitted to the host 2 when the write data is written to the write buffer 31.

  Next, with reference to FIGS. 20 to 23, a description will be given of a process of notifying the host 2 of a time elapsed value from the previous write to the same LBA instead of the accumulated data write amount.

  The elapsed time value is information on the elapsed time from the previous write to the same LBA, and the example of the elapsed time value may be the time of the previous write to the same LBA or the previous write to the same LBA. It may be a time interval between the time of the write and the time of the current write to this same LBA.

  FIG. 20 shows an example of a look-up table (LUT) 33 configured to manage the correspondence between the LBA, the physical address, and the last write time in a predetermined management unit such as 4 Kbytes. Show.

  The look-up table (LUT) 33 includes a physical address storage area 33A and a time storage area 33B for each LBA. Each time storage area 33B is used to hold a value indicating a time at which writing to the corresponding LBA has occurred, that is, a value indicating a time at which data of the corresponding LBA has been written. The time held in each time storage area 33B may be, for example, hours, minutes, and seconds.

  When a write command including a certain LBA is received, the controller 4 registers the physical address in the physical address area 33A corresponding to this LBA, and stores the data specified by the write command in the time area 33B corresponding to this LBA. The time at which (write data) was written is registered. The physical address indicates the physical address of the physical storage location where the data specified by the write command is written. The write time may be the time at which the write command was received, the time at which the data specified by the write command was written to the write buffer 31, or the data specified by the write command. May be the time at which was written to the write destination block of the NAND memory 5.

  The flowchart of FIG. 21 shows the procedure of the time lapse response process executed by the controller 4.

  Here, it is assumed that a command permission response including the elapsed time value is transmitted to the host 2.

  The controller 4 receives a write command including LBAx as the start LBA from the host 2 (Step S71). The controller 4 refers to the look-up table (LUT) 33 and acquires the time of the previous write to LBAx, that is, the time at which data was written by the previous write command including LBAx (step S72). The controller 4 returns a permission response including a time elapsed value indicating the time of the previous write to the LBAx to the host 2 (Step S73). As described above, the elapsed time value is the time interval between the time of the previous write to LBAx and the time of the current write of LBAx, that is, the current time (time of the current write to LBAx) to LBAx. It may be a value obtained by subtracting the time of the previous write.

  The controller 4 determines whether the write data corresponding to the write command or the abort command for aborting the write command is received from the host 2 (step S74).

  If the write data has been received, the controller 4 proceeds to Step S75. In step S75, the controller 4 writes the write data to the write buffer 31, writes the write data in the write buffer 31 to the current write destination block, updates the look-up table (LUT) 33, and stores the new physical address in LBAx. And the new write time, and updates the page management table to invalidate the old physical address (old data).

  Thereafter, the controller 4 returns a command completion response to the host 2 (step S76).

  As described above, a command completion response may be transmitted to the host 2 when the write data is written to the write buffer 31.

  On the other hand, if the abort command has been received, the controller 4 discards the write command (step S77).

  In the flowchart of FIG. 21, the case where the command permission response including the elapsed time value is transmitted to the host 2 has been described. However, the command completion response including the elapsed time value may be transmitted to the host 2. The transmission of the command completion response including the elapsed time value can be executed in the same procedure as in FIGS.

  The flowchart of FIG. 22 shows a procedure of processing executed by the host 2 based on the accumulated data writing amount / time elapsed value notified from the SSD 3.

  The host 2 may classify the data into a plurality of types of data groups having different update frequencies based on the cumulative data write amount / time elapsed value notified from the SSD 3. For example, the file system 43 of the host 2 includes a data management unit. The data management unit classifies data into a plurality of types of data groups, and includes a data group (hot data) in which data is frequently updated and a frequency. It may be separated into a data group (Cold data) that is not updated. If the update frequency of the data written to the SSD 3 is equal to or greater than a certain threshold, the data management unit can recognize that the data is Hot data.

  The data management unit may move data recognized as hot data from the SSD 3 to another storage device in order to make the update frequency of each LBA range in the same SSD as uniform as possible.

  Alternatively, if the SSD 3 is realized as a high-priced SSD having high durability, the Hot data may be left in the SSD 3 and the Cold data may be moved from the SSD 3 to another storage device. Examples of high endurance high cost SSDs include SLC-SSDs that store one bit of information per memory cell.

  One of the indexes indicating the durability of SSD is DWPD (Drive Write Per Day). For example, DWPD = 10 means that for an SSD having a total capacity of 1 Tbyte, writing of 10 Tbytes per day (= 10 × 1 Tbyte) of data can be executed every day for 5 years.

  Hereinafter, an example of the procedure of the former process will be described.

  The host 2 transmits a write command including LBAx to the SSD 3 (step S81), and receives a response (permission response, command completion response) including the accumulated data write amount or the elapsed time value from the SSD 3 (step S82).

  The host 2 determines whether the frequency of updating the LBAx data (the frequency of writing to the LBAx) is equal to or higher than a predetermined upper limit frequency (threshold value th4) based on the accumulated data write amount or the elapsed time value (step S83). ). For example, in a case where the cumulative data writing amount is notified from the SSD 3, the host 2 may determine whether the cumulative data writing amount is equal to or larger than the threshold data amount indicated by the threshold th4. In the case where the time elapsed value (time of the previous write to the same LBA) is notified from the SSD 3, the host 2 calculates a time interval by subtracting the time of the previous write from the current time, and this time interval is , May be determined to be equal to or longer than the threshold time interval indicated by the threshold th4. Alternatively, the host 2 converts the accumulated data write amount or the elapsed time value into a ratio [percent] indicating the number of write accesses to the LBAx at one time, and this time interval is It may be determined whether or not it is equal to or longer than the threshold time interval indicated by the threshold th4.

  If the update frequency of the LBAx data (the frequency of writing to the LBAx) is equal to or greater than the threshold th4 (YES in step S83), the host 2 classifies the LBAx data into a high update frequency data group (Hot data) ( In step S84, the data of LBAx is moved from the SSD 3 to another storage device (step S85).

  In step S84, if the response including the accumulated data write amount or the elapsed time value is a permission response to the write command, the host 2 may execute a process of aborting the write command.

  FIG. 23 illustrates a hardware configuration example of an information processing apparatus that functions as the host 2.

  This information processing device is realized as a server computer or a personal computer. The information processing apparatus includes a processor (CPU) 101, a main memory 102, a BIOS-ROM 103, a network controller 105, a peripheral interface controller 106, a controller 107, an embedded controller (EC) 108, and the like.

  The processor 101 is a CPU configured to control the operation of each component of the information processing device. The processor 101 executes various programs loaded from any one of the plurality of SSDs 3 into the main memory 102. The main memory 102 is composed of a random access memory such as a DRAM. The program executed by the processor 101 includes the above-described application software layer 41, OS 42, and file system 43.

  The processor 101 also executes a basic input / output system (BIOS) stored in the BIOS-ROM 103, which is a nonvolatile memory. BIOS is a system program for hardware control.

  The network controller 105 is a communication device such as a wired LAN controller or a wireless LAN controller. The peripheral interface controller 106 is configured to execute communication with a peripheral device such as a USB device.

  The controller 107 is configured to execute communication with devices respectively connected to the plurality of connectors 107A. In the present embodiment, a plurality of SSDs 3 are connected to a plurality of connectors 107A, respectively. The controller 107 is a SAS expander, a PCIe switch, a PCIe expander, a flash array controller, a RAID controller, or the like.

  The EC 108 functions as a system controller configured to execute power management of the information processing device. The EC 108 powers on and off the information processing device in response to a user's operation of a power switch. The EC 108 is realized as a processing circuit such as a one-chip microcontroller. The EC 108 may include a keyboard controller that controls an input device such as a keyboard (KB).

  The processing described in FIG. 22 is executed by the processor 101 under the control of the file system 43.

  FIG. 24 illustrates a configuration example of an information processing apparatus including a plurality of SSDs 3 and a host 2.

  This information processing apparatus includes a thin box-shaped housing 201 that can be housed in a rack. A number of SSDs 3 may be arranged in the housing 201. In this case, each SSD 3 may be removably inserted into a slot provided on the front surface 201A of the housing 201.

  A system board (motherboard) 202 is arranged in the housing 201. Various electronic components including the CPU 101, the memory 102, the network controller 105, and the controller 107 are mounted on the system board (motherboard) 202. These electronic components function as the host 2.

  As described above, according to the “LBA-based update frequency notification function” of the present embodiment, when a write command including an LBA is received from the host 2, the last write to this LBA is performed this time to this LBA. The total amount of data written to the NAND memory 5 by the host 2 until the writing of the LBA, or a value related to the time elapsed from the previous writing to this LBA to the current writing to this LBA is obtained. Then, the host 2 is notified of the total amount of data or the value relating to the passage of time as a response to the received write command. Therefore, the data update frequency can be provided to the host 2 in units of LBA included in each write command.

  In the present embodiment, a NAND memory has been exemplified as the nonvolatile memory. However, the functions of the present embodiment include, for example, MRAM (Magnetoresistive Random Access Memory), PRAM (Phase change Random Access Memory), ReRAM (Resistive Random Access Memory, and Random Access Random Access Memory). It can be applied to various nonvolatile memories.

  Although several embodiments of the present invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in other various forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and their equivalents.

  2 host, 3 SSD, 4 controller, 5 NAND memory, 21 garbage collection number management unit, 22 garbage collection operation control unit, 23 update frequency information response unit.

Claims (8)

A non-volatile memory;
Anda controller configured to write data into the nonvolatile memory in response to a write command received from the host,
The controller is
Receiving from the host a first write command that is a previous write command including a first logical address;
After receiving the first write command, receiving from the host a second write command that is a current write command including the same logical address as the first logical address;
The total amount of data received from the host between the time when the first write command is received and the time when the second write command is received, or the time when the second write command is received after the first write command is received. Get the value about the elapsed time until receiving the command,
A memory system configured to notify the host of a total amount of the data or a value related to the elapsed time. The controller is
A first physical storage position of the first light the non-volatile memory in which data is written by the command, and the second physical storage location of the second write the nonvolatile memory where data is to be written by the command, A number of blocks allocated for writing data from the host between an allocation of a first block including the first physical storage location and an allocation of a second block including the second physical storage location. To obtain the total amount of the data,
2. The memory system according to claim 1, wherein the memory is configured to notify the host of the total amount of the acquired data.   The controller refers to a logical-physical address conversion table that manages mapping between a logical address and a physical address, and sets a physical address mapped to the first logical address as the first physical storage location. 3. The memory system of claim 2, wherein the memory system is configured to acquire. The controller is
Allocating one of the free blocks in the nonvolatile memory as a write target block to which data from the host is to be written,
Write write data received from the host to a writable page of the write target block,
When there is no writable page in the write target block, a new free block is allocated as the write target block,
A number indicating the order of assignment is assigned to each of the blocks assigned as the write target block,
Based on the number assigned to the first block including the first physical storage location and the number assigned to the second block including the second physical storage location, the assignment of the first block to the second block 3. The memory system according to claim 2, wherein the memory system is configured to acquire a number of the blocks allocated for writing data from the host before the allocation. A non-volatile memory;
Anda controller configured to write data into the nonvolatile memory in response to a write command received from the host,
The controller is
Receiving a first write command, which is a previous write command including a first logical address, from the host;
After receiving the first write command, receiving from the host a second write command that is a current write command including the same logical address as the first logical address;
A first physical storage position of the first light the non-volatile memory in which data is written by the command, and the second physical storage location of the second write the nonvolatile memory where data is to be written by the command, A number of blocks allocated for writing data from the host between an allocation of a first block including the first physical storage location and an allocation of a second block including the second physical storage location. Obtaining a total amount of data received from the host from the reception of the first write command to the reception of the second write command;
A memory system configured to notify the host of the total amount of the acquired data. A control method for controlling a nonvolatile memory and writing data to the nonvolatile memory according to a write command received from a host,
Receiving from the host a first write command that is a previous write command including a first logical address;
Writing data to the non-volatile memory in response to the first write command;
Receiving, from the host, a second write command that is a current write command including the same logical address as the first logical address after receiving the first write command;
The total amount of data received from the host between the time when the first write command is received and the time when the second write command is received, or the time when the second write command is received after the first write command is received. Obtaining a value for the elapsed time before receiving the command;
Notifying the host of a value relating to the total amount of data or the elapsed time to the host. The obtaining may include a first physical storage location in the nonvolatile memory to which data is written by the first write command, and a second physical storage location in the nonvolatile memory to which data is to be written by the second write command. 2 physical storage locations and allocated for writing data from the host between the allocation of the first block including the first physical storage location and the allocation of the second block including the second physical storage location. Obtaining the total amount of the data based on the number of blocks and
The control method according to claim 6, wherein the notifying includes notifying the host of the total amount of the acquired data. A non-volatile memory;
Anda controller for controlling the nonvolatile memory,
The controller is
After receiving a first write command, which is a previous write command including a first logical address, from a host , a second write command, which is a current write command including the same logical address as the first logical address , is described above. A memory system configured to notify the host of a value relating to an elapsed time until reception from the host.

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