JP6641913B2 - Delay circuit with temperature compensation - Google Patents

Description

  The present invention relates to a delay circuit used for a time adjustment function when generating a dead time of a semiconductor switch, a protection blanking time of a drive circuit, a pulse width of an alarm signal, and the like.

In a drive circuit of a semiconductor switch represented by an IGBT (Insulated Gate Bipolar Transistor), for example, a delay circuit may be used for the following applications.
(1) A period (dead time) for simultaneously turning off the IGBTs on the high voltage side and the low voltage side is generated so that a short-circuit current does not flow when the IGBTs on the high voltage side and the low voltage side are simultaneously turned on.
(2) Generate a blanking time for preventing malfunction due to noise in protection circuits (power supply voltage drop protection, short-circuit protection, etc.).
(3) When communicating the alarm type at the time of the protection operation, a pulse width is set when the type is represented by a different pulse width.

As a delay circuit applicable to the above (1) to (3), for example, a delay circuit described in Patent Document 1 has been proposed.
In this delay circuit, two MOS field-effect transistors are connected in series between a high potential side and a low potential side, and a connection point of both MOS field-effect transistors is connected to an output terminal via a logic circuit. A capacitor is connected between the connection point of the transistor and the connection point of the logic circuit and the low potential side. This delay circuit charges the capacitor through the high-potential-side MOS field-effect transistor and discharges the capacitor through the low-potential-side MOS field-effect transistor.

Patent Document 1 discloses an off-delay configuration in which a high-potential-side MOS field effect transistor is DC-biased by a current mirror circuit to delay the fall, and a low-potential-side MOS field-effect transistor is DC-biased by a current mirror circuit. A case where an on-delay configuration in which a rise is delayed by biasing is disclosed.
Patent Document 2 proposes an application of a DC bias by an operational amplifier that performs differential amplification instead of a DC bias by a current mirror circuit.

JP-A-3-2955311 JP-A-3-104412

  In the conventional example described in Patent Document 1 described above, a case is considered in which a DC bias is applied to the gate of the MOS field-effect transistor on the high potential side by a current mirror circuit. The current flowing through the capacitor has a positive temperature characteristic with respect to temperature rise. Specifically, as shown in FIG. 5, the horizontal axis represents temperature, and the vertical axis represents bias current Ib2. Then, for example, in the range of −40 ° C. to 150 ° C., when the temperature is −40 ° C., the bias current Ib2 becomes a value Ib2min close to 0A. Then, the characteristic line L31 rises to the right where the bias current Ib2 increases as the temperature rises.

Further, the delay time td1 generated by the delay circuit is as follows, assuming that the capacitance of the capacitor is C1 and the high potential is Vinm1.
td1 = C1 · Vinm1 / Ib2
It is represented by Therefore, the delay time td1 has a negative temperature characteristic. Specifically, as shown in FIG. 6, the horizontal axis represents the temperature, and the vertical axis represents the delay time td1. In this figure, when the temperature is −40 ° C., the delay time td1 has a relatively large value td1max. Then, the characteristic line L41 becomes lower right, in which the delay time td1 decreases as the temperature rises.

On the other hand, in the conventional example described in Patent Literature 2, a case will be examined in which a DC bias to the gate of the MOS field-effect transistor on the high potential side is performed by an operational amplifier. FIG. 8 shows a temperature characteristic of the current Ic2 flowing through the capacitor as an example. As shown in this figure, contrary to the conventional example described in Patent Document 1, the current decreases as the temperature increases. That is, the current Ic2 flowing through the capacitor has a negative temperature characteristic represented by a characteristic line L32 falling to the right.
The temperature characteristics of the delay time td2 are as follows, assuming that the capacitance of the capacitor is C1 and the high potential is Vinm1.
td2 = C1 · Vinm1 / Ic2
Becomes Therefore, as shown in FIG. 9, there is a positive temperature characteristic represented by a characteristic line L42 rising to the right where the delay time td2 increases as the temperature increases.

Therefore, in the conventional examples described in Patent Documents 1 and 2, there is a problem that the fluctuation range of the delay time with respect to the temperature change becomes large.
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the conventional example, and has as its object to provide a temperature-compensated delay circuit that can reduce a fluctuation width of a delay time due to a temperature change.

  In order to achieve the above object, an embodiment of a delay circuit with temperature compensation according to the present invention includes a capacitor for generating a delay time, a high-potential-side semiconductor switch to which an input signal is input, and a parallel connection with the capacitor. A low-potential-side semiconductor switch connected in series with the high-potential-side semiconductor switch; a current control circuit for controlling a current passing through the high-potential-side semiconductor switch; and a voltage between terminals of the capacitor element is equal to or higher than a set voltage. And an output circuit for outputting an output signal. In particular, the current control circuit includes a first current control circuit including a current mirror circuit and a second current control circuit including an operational amplifier.

  According to one embodiment of the present invention, it is possible to provide a temperature-compensated delay circuit that can reduce a variation width of a delay time with respect to a temperature change.

FIG. 2 is a circuit diagram showing an embodiment of a delay circuit with temperature compensation according to the present invention. FIG. 3 is a characteristic diagram illustrating a temperature characteristic of a charging current flowing through a capacitance element of the delay circuit with temperature compensation of FIG. 2. FIG. 2 is a characteristic diagram illustrating a temperature characteristic of a delay time of the delay circuit with temperature compensation of FIG. 1. FIG. 3 is a circuit diagram omitting a second current control circuit used for describing an operation of the present invention. FIG. 5 is a characteristic diagram illustrating temperature characteristics of a charging current flowing through the capacitance element in FIG. 4. FIG. 5 is a characteristic diagram illustrating a temperature characteristic of a delay time in FIG. 4. FIG. 9 is a circuit diagram showing a modification in which an operational amplifier is applied instead of the current mirror circuit of FIG. FIG. 8 is a characteristic diagram illustrating temperature characteristics of a charging current flowing through the capacitance element in FIG. 7. FIG. 8 is a characteristic diagram illustrating a temperature characteristic of the delay time in FIG. 7. It is a circuit diagram which shows the modification of the delay circuit with temperature compensation which concerns on this invention.

Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar portions as those of the conventional example are denoted by the same or similar reference numerals.
Further, the embodiments described below exemplify an apparatus and a method for embodying the technical idea of the present invention, and the technical idea of the present invention is based on the material, shape, structure, The arrangement is not specified below. The technical concept of the present invention can be variously modified within the technical scope defined by the claims described in the claims.
First, a delay circuit with temperature compensation used for a time adjustment function in generating a dead time time of a semiconductor switch, a protection blanking time of a drive circuit, a pulse width of an alarm signal, and the like, which represents an embodiment of the present invention, is described. An embodiment will be described.

As shown in FIG. 1, the delay circuit with temperature compensation according to one embodiment of the present invention includes a capacitance element 1 for generating a delay time, an input circuit 2, a charge / discharge circuit 3, a first current control circuit 4, , A second current control circuit 5 and an output circuit 6.
The input circuit 2 includes an input terminal IN to which a pulse signal to be delayed is input, and an inverter 21 connected to the input terminal IN for logically inverting the input pulse signal. The output signal of the inverter 21 is output to the control terminals of the high-potential-side semiconductor switch 31 and the low-potential-side semiconductor switch 32 of the charge / discharge circuit 3.

The charging / discharging circuit 3 is connected between a first power supply line L1 connected to the power supply terminal VS and a second power supply line L2 connected to the ground terminal GND. The output signal of the inverter 21 of the input circuit 2 is input to the charge / discharge circuit 3. The charge / discharge circuit 3 has a high-potential-side semiconductor switch 31 and a low-potential-side semiconductor switch 32 connected in series. Further, the capacitive element 1 is connected to the low-potential-side semiconductor switch 32 in parallel.
Here, the high-potential-side semiconductor switch 31 is composed of, for example, a P-channel MOSFET. The low-potential-side semiconductor switch 32 is constituted by an N-channel MOSFET. The high-potential-side semiconductor switch 31 has a gate serving as a control terminal connected to the output side of the inverter 21 of the input circuit 2. The source of the high-potential-side semiconductor switch 31 is connected to a first power supply line L1 via a first current mirror circuit 41 described later. The drain of the high-potential semiconductor switch 31 is connected to the capacitor 1 and the drain of the low-potential-side semiconductor switch 32 via the first resistor R1.

The low-potential-side semiconductor switch 32 has a gate serving as a control terminal connected to the output side of the inverter 21 of the input circuit 2. The drain of the low-potential-side semiconductor switch 32 is connected to the capacitor 1 and to the drain of the high-potential-side semiconductor switch 31 via the first resistor R1. The source of the low-potential-side semiconductor switch 32 is connected to the second power supply line L2.
The first current control circuit 4 includes a first current mirror circuit 41 connected between the first power supply line L1 and the high-potential-side semiconductor switch 31 of the charge / discharge circuit 3, and a bias current of the first current mirror circuit 41. And a second current mirror circuit 42 for controlling the current.

The first current mirror circuit 41 has a first transistor 41a and a second transistor 41b each formed of, for example, a P-channel MOSFET. The first transistor 41a has a gate and a drain connected to the second current mirror circuit 42, and also connected to the gate of the second transistor 41b. The source of the first transistor 41a is connected to the first power line L1.
The gate of the second transistor 41b is connected to the gate and the drain of the first transistor 41a. The source of the second transistor 41b is connected to the first power line L1. The drain of the second transistor 41 b is connected to the source of the high-potential-side semiconductor switch 31 of the charge / discharge circuit 3.

Here, the gate length of the first transistor 41a is Lg1, the gate width is Wg1, and the gate length of the second transistor 41b is Lg2, and the gate width is Wg2. Then, the ratio a = (Wg2 / Lg2) / (Wg1 / Lg1) is defined. The bias current Ib2 is multiplied by a by the bias current Ib1 flowing through the first transistor 41a. That is, the bias current Ib2 = a × Ib1 is output from the second transistor 41b.
The second current mirror circuit 42 includes two current mirror circuits 43 and 44 connected in parallel.
The current mirror circuit 43 includes, for example, a third transistor 43a and a fourth transistor 43b each configured by an N-channel MOSFET.

The third transistor 43a has a gate and a drain connected to a bias current terminal BIAS to which a bias current is input, and also connected to a gate of the fourth transistor 43b. The source of the third transistor 43a is connected to the current mirror circuit 44.
The fourth transistor 43b has a gate connected to the gate and drain of the third transistor 43a and the bias current terminal BIAS. The drain of the fourth transistor 43b is connected to the drain of the first transistor 41a of the first current mirror circuit 41. The source of the fourth transistor 43b is connected to the current mirror circuit 44.
The current mirror circuit 44 includes, for example, a fifth transistor 44a and a sixth transistor 44b each configured by an N-channel MOSFET.

The fifth transistor 44a has a gate and a drain connected to the source of the third transistor and the gate of the sixth transistor 44b. The source of the fifth transistor 44a is connected to the second power line L2. The sixth transistor 44b has a gate connected to the gate and the drain of the fifth transistor 44a. The drain of the sixth transistor 44b is connected to the source of the fourth transistor 43b. The source of the sixth transistor 44b is connected to the second power supply line L2.
Here, the third transistor 43a and the fifth transistor 44a have the same gate length Lg3 and the same gate width Wg3, and the fourth transistor 43b and the sixth transistor 44b have the same gate length Lg4 and the same gate width Wg4. Then, the ratio b = (Wg4 / Lg4) / (Wg3 / Lg3) is defined. In the second current mirror circuit 44, the bias current Ib0 input to the bias current terminal BIAS is multiplied by b and the bias current Ib1 flows. That is, the second current mirror circuit 44 generates the bias current Ib1 = b × Ib0 in which the bias current Ib0 is amplified by the ratio b. This bias current Ib1 flows through the third transistor 43b and the fifth transistor 44b.

The second current control circuit 5 has an operational amplifier 51. The non-inverting input terminal of the operational amplifier 51 is connected to a connection point between the first resistor R1 inserted in the charge / discharge circuit 3 and the high-potential-side semiconductor switch 31. The inverting input terminal of the operational amplifier 51 is connected via a voltage source 52 to a connection point between the first resistor R1 and the low-potential-side semiconductor switch 32 and the connection point between the capacitor 1 and the capacitor.
The second current control circuit 5 includes a seventh transistor 53 composed of, for example, an N-channel MOSFET connected in series between a connection point between the high-potential-side semiconductor switch 31 and the first resistor R1 and the second power supply line L2. And a second resistor R2. The seventh transistor 53 has a gate connected to the output terminal of the operational amplifier 51. The drain of the seventh transistor 53 is connected to a connection point between the high-potential-side semiconductor switch 31 and the first resistor R1. The source of the seventh transistor 53 is connected to the second resistor R2.

  Therefore, in the second current control circuit 5, when the voltage at the connection point between the high-potential-side semiconductor switch 31 and the first resistor R1 is lower than the voltage Vref of the voltage source 52, a low-level output signal is output from the operational amplifier 51. This output signal is input to the gate of the seventh transistor 53, and the seventh transistor 53 is turned off. Conversely, when the voltage at the connection point is equal to or higher than the voltage Vref of the voltage source 52, the operational amplifier 51 outputs a high-level output signal. This output signal is input to the gate of the seventh transistor 53, and the seventh transistor 53 is turned on.

  The output circuit 6 has a voltage dividing circuit 61, a comparator 62, a NAND circuit 63, an inverter 64, and an output terminal OUT. The voltage dividing circuit 61 has a third resistor R3 and a fourth resistor R4 connected in series between the first power line L1 and the second power line L2. The non-inverting input terminal of the comparator 62 is connected to a connection point between the first resistor R <b> 1 and the low-potential-side semiconductor switch 32 and the connection point of the capacitive element 1. An inverting input terminal of the comparator 62 is connected to a connection point of the third resistor R3 and the fourth resistor R4 of the voltage dividing circuit 61. When the terminal voltage Vc1 of the capacitor 1 is lower than the divided voltage Vdin of the voltage dividing circuit 61, the comparator 62 outputs a low-level comparison signal to the NAND circuit 63. On the other hand, when the terminal voltage Vc1 is equal to or higher than the divided voltage Vdin, the comparator 62 outputs a high-level comparison signal to the NAND circuit 63.

The comparison signal of the comparator 62 and the input pulse signal input to the input terminal IN are input to the NAND circuit 63. The NAND circuit 63 outputs a low-level output signal to the inverter 64 when the comparison signal and the input pulse signal are at a high level. On the other hand, the NAND circuit 63 outputs a high-level output signal to the inverter 64 when either the comparison signal or the input pulse signal is at a low level.
The inverter 64 logically inverts the input of the NAND circuit 63 and outputs the inverted output to the output terminal OUT.

Next, the operation of the temperature compensated delay circuit having the above configuration will be described.
Now, it is assumed that the pulse signal SP input to the input terminal IN is at a low level. At this time, in the input circuit 2, the output signal output from the inverter 21 becomes high level. This high-level output signal is output to the gates of the high-potential-side semiconductor switch 31 and the low-potential-side semiconductor switch 32 of the charge / discharge circuit 3. Therefore, the high-potential-side semiconductor switch 31 is turned off, and the low-potential-side semiconductor switch 32 is turned on. Then, the charging voltage charged in the capacitor 1 is discharged to the ground terminal GND via the low-potential-side semiconductor switch 32 and the second power supply line L2.

Therefore, the comparison signal output from the comparator 62 of the output circuit 6 has a low level. At this time, since the input pulse signal SP is also at a low level, the output signal of the NAND circuit 63 is at a high level. This is inverted by the inverter 64, and a low-level output signal is output from the output terminal OUT.
From this state, when the input pulse signal SP is inverted to a high level, the output signal of the inverter 21 of the input circuit 2 is inverted to a low level. In response, the high-potential-side semiconductor switch 31 of the charge / discharge circuit 3 is turned on. Therefore, the low-potential-side semiconductor switch 32 is turned off, and a charging path to the capacitor 1 is formed.

  At this time, the current flowing through the high potential side semiconductor switch 31 is controlled by the first current control circuit 4 and the second current control circuit 5. That is, the bias current Ib0 input to the bias current terminal BIAS flows through the third transistor 43a and the fifth transistor 44a of the second current mirror circuit 42. A bias current Ib1 corresponding to the bias current Ib0 is supplied from the first power supply line L1 to the second power supply line via the first transistor 41a of the first current mirror circuit 41, the fourth transistor 43b and the fifth transistor 44b of the second current mirror circuit 42. Flow to L2.

  Therefore, the charging current Ib2 corresponding to the bias current Ib1 flows through the second transistor 41b of the first current mirror circuit 41. This current is supplied to the capacitor 1 via the high-potential-side semiconductor switch 31 and the first resistor R1, and the capacitor 1 is charged. At this time, while the inter-terminal voltage Vc of the capacitive element 1 does not reach the set voltage Vinm set by the voltage dividing circuit 61, the output voltage of the comparator 62 is at a low level, and the input pulse signal SP is at a high level. On the other hand, since the output signal of the NAND circuit 63 is at a high level, it is inverted by the inverter 64 and a low-level output signal is output to the output terminal OUT.

Thereafter, when the charging of the capacitive element 1 proceeds and the terminal-to-terminal voltage Vc becomes equal to or higher than the set voltage Vinm, the comparison signal output from the comparator 62 becomes high level. In response, the output signal of the NAND circuit 63 is inverted to a low level, and a high-level output signal is output from the inverter 64 as a delay signal via the output terminal OUT.
It should be noted that the first current mirror circuit 41 and the second current mirror circuit 42 constituting the first current control circuit 4 each have a positive temperature characteristic. In examining this temperature characteristic specifically, the configuration shown in FIG. 4 is obtained by removing the second current control circuit 5 from the configuration shown in FIG. For example, as shown in FIG. 5, consider a characteristic diagram in which the horizontal axis represents temperature and the vertical axis represents charging current Ic. If the temperature range is −40 ° C. to 150 ° C., the voltage Ib2min is close to zero when the temperature is −40 ° C., and is represented by a rightward rising characteristic line L31 in which the charging current Ib2 increases as the temperature increases. You. The characteristic line L31 keeps a straight upward trend until the temperature reaches 150 ° C. Therefore, the bias current Ib2 flowing through the second transistor 41b of the first current mirror circuit 41 has a positive temperature characteristic.

  Therefore, the delay time td1 by the first current control circuit 4 is represented by td1 = C1 · Vinm / Ib2, where C1 is the capacitance of the capacitive element 1 and Vinm is the intermediate voltage of the voltage dividing circuit 61. That is, the delay time td1 is inversely proportional to the bias current Ib2. Therefore, it is shown that the delay time td1 has a negative temperature characteristic as shown in FIG. That is, when the temperature is −40 ° C., the maximum value is td1max, and thereafter, the characteristic line L41 is a rightward slope in which the delay time td1 decreases as the temperature increases. This decreasing trend continues until the temperature reaches 150 ° C.

  On the other hand, the case where the second current control circuit 5 is applied instead of the first current control circuit 4 in the configuration of FIG. In this case, as shown in FIG. 7, an eighth transistor 71 composed of, for example, a P-channel MOSFET is connected to the first power supply line L1 via the first resistor R1. Then, the gate of the eighth transistor 71 is connected to the output terminal of the operational amplifier 72. The source of the eighth transistor 71 is connected to the first resistor R1 and the drain is connected to the high-potential-side semiconductor switch 31. Then, the non-inverting input terminal of the operational amplifier is connected to the first power supply line L1 via the voltage source 73. Further, the inverting input terminal of the operational amplifier is connected to a connection point between the first resistor R1 and the source of the eighth transistor 71.

With such a configuration, the current Ic2 flowing through the capacitor 1 has a negative temperature characteristic. That is, as shown in FIG. 8, when the temperature is plotted on the horizontal axis and the current Ic2 is plotted on the vertical axis, the temperature characteristic shows that when the temperature is −40 ° C., the current Ic2 has a maximum value Ic2max. The current Ic2 decreases as the temperature increases.
The delay time td2 is expressed as td2 = C1 · Vinm / Ic2, where C1 is the capacitance of the capacitor 1, Ic2 is the current flowing through the capacitor 1, and Vinm is the intermediate voltage of the voltage divider 61. Is done. That is, the delay time td2 is inversely proportional to the current Ic2. Therefore, the temperature characteristic of the delay time td2 is a positive temperature characteristic. That is, as shown in FIG. 9, when the temperature is plotted on the horizontal axis and the delay time td2 is plotted on the vertical axis, the minimum value is td2min when the temperature is −40 ° C. As the temperature rises from this state, the delay time td2 increases and becomes a characteristic line L42 that rises to the right.

Thus, in the first current control circuit 4, the delay time td1 has a negative temperature characteristic, and in the second current control circuit 5, the delay time td2 has a positive temperature characteristic.
For this reason, in the circuit configuration of FIG. 1, when the second current control circuit 5 is not operating, the charging current Ib2 supplied from the first power supply line L1 to the first resistor R1 via the high-potential-side semiconductor switch 31 is , The first current control circuit 4. Although the first current control circuit 4 is a constant current circuit using a current mirror circuit, as shown in FIGS. 4 to 6, the charging current Ib2 has a positive temperature characteristic.

  When the temperature reaches a set temperature Ta around -40 ° C. to 150 ° C., for example, around 55 ° C., which is an intermediate temperature, the voltage Vr at the connection point between the high-potential-side semiconductor switch 31 and the first resistor R1 becomes the second voltage. The voltage of the voltage source 52 is set so as to reach the reference voltage Vref supplied to the inverting input terminal of the operational amplifier 51 of the current control circuit 5. With this setting, when the temperature is lower than Ta, the output signal of the operational amplifier 51 of the second current control circuit 5 becomes low. Therefore, the seventh transistor 53 maintains the off state, and the bypass current Ibp does not flow. When the temperature becomes equal to or higher than Ta, the output signal of the operational amplifier 51 of the second current control circuit 5 goes high. Therefore, the seventh transistor 53 is turned on, and the bypass current Ibp flows through the second resistor R2.

The second transistor 41b of the first current mirror circuit 41 of the first current control circuit 4 and the seventh transistor 53 of the second current control circuit 4 are connected in series between the first power line L1 and the second power line L2. Will be connected.
Therefore, the charging current Ic1 flowing through the capacitive element 1 depends on the magnitude relationship between the bias current Ib2 flowing through the second transistor 41b of the first current mirror circuit 41 and the bypass current Ibp that can be controlled by the operational amplifier 51. The smaller of the bypass current Ibp becomes dominant.

From the above, when the temperature is between −40 ° C. and the set temperature Ta, the charging current Ic1 is determined by the bias current ib2 of the first current control circuit 4, and the charging current Ic1 has a positive temperature characteristic. Become. On the other hand, when the temperature becomes equal to or higher than the set temperature Ta, the charging current Ic1 is determined by the bypass current Ibp of the second current control circuit 4, and the temperature switches to a negative temperature characteristic.
Therefore, when the temperature is in the range from −40 ° C. to the set temperature Ta, the charging current Ic1 increases as the temperature rises, as indicated by the characteristic line L31 in FIG. On the other hand, when the temperature is in the range of 150 ° C. from the set temperature Ta, the charging current Ic1 decreases as the temperature rises, as indicated by the characteristic line L32 in FIG.

For this reason, the temperature characteristic of the delay time td is such that when the temperature is in the range from −40 ° C. to the set temperature Ta, the delay time td decreases as the temperature rises as shown by the characteristic line L41 in FIG. In the range from to 150 ° C., the delay time Td increases due to the temperature rise, as indicated by the characteristic line L42 in FIG.
Therefore, when the temperature is in the range of −40 ° C. to 150 ° C., the variation width of the delay time td due to the temperature change is half that in the case where either the first current control circuit 4 or the second current control circuit 5 is used alone. Can be reduced to

As described above, in the embodiment, the first current control circuit 4 having the current mirror circuit and the second current control circuit 5 having the operational amplifier are connected in series between the first power supply line L1 and the second power supply line L2. The charging current Ic1 is supplied to the capacitive element 1 from the connection point of the two circuits via the first resistor R1. For this reason, in the above embodiment, it is possible to perform the temperature compensation by reducing the fluctuation width of the delay time td due to the temperature characteristic to half of the conventional example, and to provide a temperature-compensated delay circuit less affected by a temperature change. .
In the above embodiment, the bias current Id1 of the first current mirror circuit 41 of the first current control circuit 4 is generated by the second current mirror circuit 42 from the bias Ib0. For this reason, in the above-described embodiment, the first current mirror circuit 41 is obtained from the input bias current Ib0 only by adjusting the gate length and the gate width of the third transistor 43a to the sixth transistor 44b constituting the second current mirror circuit 42. , A bias current Ib1 serving as a reference current can be generated. That is, the above embodiment can generate a bias current without using a resistance element.

  In the above embodiment, the case where the operational amplifier 51 of the second current control circuit 5 drives the seventh transistor 53 by comparing the set voltage Vref with the terminal voltage of the first resistor R1 has been described. However, the present invention is not limited to this. For example, a temperature sensor 81 for detecting the temperature of the delay circuit with temperature compensation and outputting a voltage signal is provided, and a voltage signal corresponding to the temperature detected by the temperature sensor 81 is supplied to a non-inverting input terminal of a comparator 82 composed of an operational amplifier. , And a reference power supply 83 that outputs a reference voltage Vref1 corresponding to the set temperature Ta is connected to the inverting input terminal of the comparator 82 so that the comparison signal output from the comparator 82 is supplied to the seventh transistor 53. Good.

In this case, since the temperature characteristics of the charging current Ic1 and the delay time td can be accurately switched at the set temperature Ta, the fluctuation width due to the temperature conversion can be set accurately.
In the above embodiment, the channel types of the transistors constituting the charge / discharge circuit 3, the transistors constituting the first current control circuit 4, and the transistors constituting the second current control circuit can be set arbitrarily. In addition, other voltage-controlled semiconductor elements such as IGBTs can be applied without being limited to MOSFETs.

  DESCRIPTION OF SYMBOLS 1 ... Capacitance element, 2 ... Input circuit, 3 ... Charge / discharge circuit, 4 ... First current control circuit, 5 ... Second current control circuit, 6 ... Output circuit, 31 ... High potential side semiconductor switch, 32 ... Low potential side Semiconductor switch, 41: first current mirror circuit, 41a: first transistor, 41b: second transistor, 42: second current mirror circuit, 43: current mirror circuit, 43a: third transistor, 43b: fourth transistor, 44 ... current mirror circuit, 44a ... fifth transistor, 44b ... sixth transistor, 51 ... operational amplifier, 52 ... voltage source, 53 ... seventh transistor, 61 ... voltage divider circuit, 62 ... comparator, 63 ... AND circuit, 64 ... inverter 81, temperature sensor, 82, reference voltage source, 83, comparator (operational amplifier)

Claims (7)

A capacitive element for generating a delay time;
A high-potential-side semiconductor switch to which an input signal is input;
A low-potential-side semiconductor switch connected in parallel with the capacitive element, and connected in series with the high-potential-side semiconductor switch;
A current control circuit for controlling a current flowing through the high potential side semiconductor switch;
An output circuit that outputs an output signal when a voltage between terminals of the capacitive element is equal to or higher than a set voltage,
A first current control circuit including a current mirror circuit;
A delay circuit with temperature compensation, comprising: a second current control circuit having an operational amplifier.   The first current control circuit includes a first current mirror circuit connected between the high-potential-side semiconductor switch and a first power supply line, and a second current mirror circuit that controls a bias current of the first current mirror circuit. The delay circuit with temperature compensation according to claim 1, further comprising: The first current mirror circuit has a gate and a drain connected to the second current mirror circuit, a source connected to a first power supply line, and a gate connected to a gate and a drain of the first transistor. 3. The delay circuit with temperature compensation according to claim 2, further comprising: a second transistor having a source connected to the first power supply line and a drain connected to the high-potential-side semiconductor switch.   The second current mirror circuit includes a third transistor having a gate and a drain connected to a bias current source, a gate connected to a gate and a drain of the third transistor, and a drain connected to the first current mirror circuit. A fourth transistor, a fifth transistor having a gate and a drain connected to the source of the third transistor, a source connected to the second power supply line, a gate connected to the gate and the drain of the fifth transistor, and a drain connected to the fifth transistor. The delay circuit with temperature compensation according to claim 2, further comprising: a sixth transistor connected to a source of the fourth transistor, and a source connected to the second power supply line. The second current control circuit includes a first resistor connected between the high-potential-side semiconductor switch and the capacitor, a connection point between the high-potential-side semiconductor switch and the resistor, and a second power supply line. A series circuit of a seventh transistor and a second resistor connected in series between the first and second transistors, wherein the non-inverting input terminal has a high-potential-side terminal of the seventh transistor, the high-potential-side semiconductor switch, and the first Connected to a connection point of a resistor, an inverting input terminal is connected to the first resistor side of the capacitive element via a voltage source, and an output terminal is connected to a control terminal of the seventh transistor. The delay circuit with temperature compensation according to claim 4 . The said output circuit is provided with the comparator which compares the voltage between terminals of the said capacitance element, and the divided voltage of the said 1st power supply line and the said 2nd power supply line, The Claims 4 or 5 characterized by the above-mentioned. Delay circuit with temperature compensation.   The output circuit includes a NAND circuit to which a comparison signal output from the comparator and the input signal are input, an inverter that inverts an output of the NAND circuit, and an output terminal to which an output signal of the inverter is input. 7. The delay circuit with temperature compensation according to claim 6, further comprising:

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